Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate has a plurality of pixel regions. The display substrate comprises: a base; a first light-shielding layer disposed on the base, wherein the first light-shielding layer has a plurality of pixel openings, and each of the pixel openings corresponds to one of the pixel regions; a plurality of light-emitting devices, wherein each light-emitting device comprises a first light-emitting unit and a second light-emitting unit sequentially arranged in a direction away from the base and electrically connected to each other, the first light-emitting unit is located in the pixel opening, and the distance from a light-emitting surface of the first light-emitting unit to the base is less than the distance from the surface of the first light-shielding layer away from the base to the base; and a plurality of pixel driving circuits located on the side of the plurality of light-emitting devices close to the base, wherein the pixel driving circuits are electrically connected to the light-emitting devices, and are configured to, in a privacy mode, drive the first light-emitting units to emit light and control the second light-emitting units to be turned off, and, in a sharing mode, drive at least the second light-emitting units to emit light.

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular to a display substrate and a display device. BACKGROUND

[0002] With the increasing application of display technology, people will like to share information with others, but in special cases, they also hope to have privacy. For example, some display products have a privacy mode and a sharing mode. In the privacy mode, only the user in a small viewing angle position can see the display screen; in the sharing mode, users in a large viewing angle range can see the display screen.

[0003] SUMMARY

[0004] The present disclosure provides a display substrate and a display device.

[0005] In a first aspect, the present disclosure provides a display substrate having a plurality of pixel regions, wherein the display substrate comprises:

[0006] a substrate;

[0007] a first light shielding layer disposed on the substrate, the first light shielding layer having a plurality of pixel openings, each of the pixel openings corresponding to one of the pixel regions;

[0008] a plurality of light emitting devices, the light emitting device comprising a first light emitting unit and a second light emitting unit disposed in sequence and electrically connected in a direction away from the substrate; the first light emitting unit is located in the pixel opening, and the distance from the light emitting surface of the first light emitting unit to the substrate is less than the distance from the surface of the first light shielding layer away from the substrate to the substrate;

[0009] a plurality of pixel driving circuits located on the side of the plurality of light emitting devices close to the substrate, the pixel driving circuit is electrically connected with the light emitting device, and is configured to drive the first light emitting unit to emit light in the privacy mode, and control the second light emitting unit to be turned off; and drive at least the second light emitting unit to emit light in the sharing mode.

[0010] In some embodiments, the light emitting device further comprises a first electrode, a connecting electrode and a second electrode, the first electrode is located on the side of the first light emitting unit close to the substrate, the connecting electrode is located between the first light emitting unit and the second light emitting unit, and is made of a light-transmitting material, and the second electrode is located on the side of the second light emitting unit away from the substrate;

[0011] The pixel driving circuit comprises:

[0012] a driving sub-circuit electrically connected with the first electrode and configured to provide a corresponding driving current for the first electrode according to a driving signal;

[0013] a first switch sub-circuit having a first end electrically connected with the second electrode and a second end electrically connected with the connection electrode, the first switch sub-circuit being configured to, in the privacy mode, connect the first end and the second end, and in the sharing mode, disconnect the first end and the second end.

[0014] In some embodiments, the first switch sub-circuit comprises:

[0015] a first switch transistor having a gate electrically connected with a first control line, a first pole electrically connected with the connection electrode, and a second pole electrically connected with the second electrode.

[0016] In some embodiments, the pixel driving circuit further comprises:

[0017] a second switch sub-circuit having a first end electrically connected with the connection electrode and a second end electrically connected with the first electrode, the second switch sub-circuit being configured to, in the privacy mode, disconnect the first end and the second end, and in the sharing mode, connect or disconnect the first end and the second end.

[0018] In some embodiments, the second switch sub-circuit comprises:

[0019] a second switch transistor having a gate electrically connected with a second control line, a first pole electrically connected with the first electrode, and a second pole electrically connected with the connection electrode.

[0020] In some embodiments, the driving sub-circuit comprises a driving transistor, a capacitor, a reset module, a data writing module, a compensation module, and a light emitting control module, wherein,

[0021] the reset module is configured to, in response to a reset signal on a reset line, connect a first power line with a first end of the capacitor and connect an initialization signal line with a second end of the capacitor;

[0022] a gate of the driving transistor is electrically connected with the second end of the capacitor, and a first pole of the driving transistor is electrically connected with a first power line;

[0023] the data writing module is configured to, in response to a scanning signal on a scanning line, transmit a data voltage signal on a data line to the first end of the capacitor;

[0024] The compensation module is configured to, in response to the scanning signal, turn on the gate of the driving transistor and the second pole to write the voltage of the first power supply line and the threshold voltage of the driving transistor into the capacitor;

[0025] The light-emitting control module is configured to, in response to a light-emitting control signal on a light-emitting control line, turn on the reference voltage line and the first end of the capacitor, and turn on the second pole of the driving transistor and the first electrode.

[0026] In some embodiments, the connection electrode includes a first connection part, a second connection part and a third connection part, the first connection part is located on a side of the first light-emitting unit away from the substrate, the second connection part is located on a side of the first light-shielding layer facing the substrate, and the third connection part is connected between the first connection part and the second connection part, and the pixel driving circuit is electrically connected to the second connection part.

[0027] In some embodiments, the first light-emitting unit includes a bottom surface facing the substrate, a top surface facing away from the substrate, and a side surface connecting the bottom surface and the top surface.

[0028] The third connection part is electrically connected to an edge of the second connection part and in contact with the side surface of the first light-emitting unit, and a projection of the third connection part on the substrate overlaps a projection of the first light-shielding layer on the substrate.

[0029] In some embodiments, the first light-emitting unit and the second light-emitting unit have projections on the substrate, and the projections are located within a projection range of the first connection part on the substrate.

[0030] In some embodiments, the display substrate further includes:

[0031] An insulating layer between the first electrode and the second connection part, a height difference between a surface of the insulating layer away from the substrate and a surface of the first electrode away from the substrate is less than a thickness of the first electrode.

[0032] The surface of the first light-emitting unit facing the substrate is in contact with the surface of the insulating layer away from the substrate.

[0033] In some embodiments, a projection of the first electrode on the substrate and a projection of the insulating layer on the substrate form a first projection pattern, and a projection of the first light-emitting unit on the substrate is located within the first projection pattern.

[0034] In some embodiments, the first electrode includes oppositely arranged first and second edges, the insulating layer is in contact with the first edge, and there is no gap between the second edge and the first light shielding layer.

[0035] In some embodiments, a height difference between the surface of the substrate and the light exit surface of the second light emitting unit is less than 0.5 times the thickness of the second light emitting unit.

[0036] In some embodiments, the display substrate further includes:

[0037] An encapsulation structure is located on a side of the plurality of light emitting devices away from the substrate, and is configured to encapsulate the plurality of light emitting devices;

[0038] At least one second light shielding layer is located on a side of the encapsulation structure away from the substrate, and the second light shielding layer has a plurality of light transmission openings, and a projection of each of the light emitting devices on the substrate overlaps a projection of the light transmission opening on the substrate.

[0039] A color filter layer is located on a side of the encapsulation structure away from the substrate, and the color filter layer includes a plurality of color filter portions, at least part of the color filter portions being located in the light transmission opening.

[0040] In a second aspect, the present disclosure provides a display device including the display substrate described above. BRIEF DESCRIPTION OF DRAWINGS

[0041] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, and are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation of the present disclosure. In the drawings:

[0042] FIG. 1 is a schematic diagram of a distribution of a plurality of pixel regions of a display substrate provided in some embodiments.

[0043] FIG. 2 is a cross-sectional view along lines A-A’ and B-B’ in FIG. 1.

[0044] FIG. 3 is a schematic diagram of a distribution of a plurality of pixel regions of a display substrate provided in some embodiments of the present disclosure.

[0045] FIG. 4 is a cross-sectional view along line C-C’ in FIG. 3 provided in some embodiments of the present disclosure.

[0046] FIG. 5 is a schematic diagram of a pixel driving circuit provided in some embodiments of the present disclosure.

[0047] FIG. 6 is a schematic diagram of a pixel driving circuit provided in some other embodiments of the present disclosure.

[0048] FIG. 7 is a schematic diagram of a specific structure of a pixel driving circuit provided in some embodiments of the present disclosure.

[0049] FIG. 8 is a schematic diagram of a specific structure of a pixel driving circuit provided in some embodiments of the present disclosure.

[0050] FIG. 9 is a timing diagram of a pixel driving circuit provided in some embodiments of the present disclosure.

[0051] FIG. 10 is a schematic diagram of a connection between a light emitting device and a pixel driving circuit provided in some embodiments of the present disclosure.

[0052] FIG. 11 is a sectional view along line C-C' in FIG. 3 provided in some embodiments of the present disclosure.

[0053] FIG. 12 is a sectional view along line C-C' in FIG. 3 provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0054] The specific embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to illustrate and explain the present disclosure, and are not intended to limit the present disclosure.

[0055] To make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present disclosure.

[0056] Unless otherwise defined, technical terms or scientific terms used in the embodiments of the present disclosure should be understood as the common meanings thereof by a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like are only used to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0057] As used herein, "parallel," "perpendicular" include the recited condition and conditions that are approximately the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art taking into account the measurements at issue and the error associated with the particular measurement (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and approximately parallel, where the acceptable range of deviation for approximately parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and approximately perpendicular, where the acceptable range of deviation for approximately perpendicular can also be, for example, within 5°.

[0058] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0059] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the layer and regions are shown in the drawings with the same dimensions. For example, the thickness of layers and regions can be exaggerated in the drawings. Thus, the exemplary embodiments should not be construed as limited to the shapes of regions illustrated in the drawings, which are schematic, but include shapes that result from, for example, manufacturing. The regions illustrated in the drawings are schematic and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the exemplary embodiments in terms of the scope of shapes.

[0060] FIG. 1 is a schematic diagram of a distribution of a plurality of pixel regions of a display substrate provided in some embodiments, and FIG. 2 is a cross-sectional view along lines A-A' and B-B' in FIG. 1, the display substrate having a plurality of pixel regions P, only three of which are schematically illustrated in FIG. 1, each of which is configured to emit light of one color; in one example, as shown in FIG. 1, the plurality of pixel regions P form a plurality of pixel units, each of which includes a plurality of pixel regions P, for example, a red pixel region Pr, a green pixel region Pg, and a blue pixel region Pb, the red pixel region Pr and the green pixel region Pg being arranged along a first direction, and the blue pixel region Pb being located on one side of the red pixel region Pr and the green pixel region Pg along a second direction, the first direction being perpendicular to the second direction. It is noted that the arrangement of the pixel regions P in FIG. 1 is merely illustrative, and in other examples, the pixel regions P can be arranged in other manners, for example, the plurality of pixel regions P in the same pixel unit can be arranged in sequence along the first direction or the second direction.

[0061] As shown in FIG. 1 and FIG. 2, each pixel region P includes a shared sub-pixel region S-P and a privacy sub-pixel region D-P, and the light-emitting colors of the shared sub-pixel region S-P and the privacy sub-pixel region D-P are the same in the same pixel region P. The privacy sub-pixel region D-P can include one or more privacy pixel portions D-P1. FIG. 1 and FIG. 2 take an example in which the privacy sub-pixel region D-P includes one privacy pixel portion D-P1, and when the privacy sub-pixel region D-P includes multiple privacy pixel portions D-P1, the multiple privacy pixel portions D-P1 can be arranged along the first direction, or arranged along the second direction, or arranged in an array. The orthographic projection shape of the privacy pixel portion D-P1 on the substrate SUB can be a rectangle, a square, a rhombus, a circle, an ellipse, or other shapes.

[0062] As shown in FIG. 2, the display substrate includes a substrate SUB and a plurality of pixel driving circuits 30, a plurality of light-emitting devices 50, and a pixel definition layer PDL disposed on the substrate SUB. The shared sub-pixel region S-P and the privacy sub-pixel region D-P are both provided with the light-emitting device 50. The pixel definition layer PDL has a plurality of pixel openings, and each pixel opening corresponds to one light-emitting device 50. The light-emitting device 50 is disposed in each privacy pixel portion D-P1. When one privacy sub-pixel region D-P includes multiple privacy pixel portions D-P1, the multiple light-emitting devices 50 in the same privacy sub-pixel region D-P can be controlled to emit light by the same pixel driving circuit 30, so that in the same privacy sub-pixel region D-P, the first electrodes 51 of the multiple light-emitting devices 50 of the multiple privacy pixel portions D-P1 can be connected as an integral structure; in addition, in the same privacy sub-pixel region D-P, the light-emitting layers of the multiple light-emitting devices 50 of the multiple privacy pixel portions D-P1 are also connected as an integral structure, so as to reduce the precision requirement in the manufacturing of the first electrode 51 and the light-emitting layer. The first electrodes 51 of the light-emitting devices 50 in the privacy sub-pixel region D-P and the first electrodes 51 of the light-emitting devices 50 in the shared sub-pixel region S-P are spaced apart from each other.

[0063] It should be noted that for other embodiments, when the privacy sub-pixel region D-P includes multiple privacy pixel portions D-P1, in the same privacy sub-pixel region D-P, the first electrodes 51 of the multiple light-emitting devices 50 of the multiple privacy pixel portions D-P1 can also be independent of each other, and the light-emitting layers of the multiple light-emitting devices 50 of the multiple privacy pixel portions D-P1 can also be independent of each other.

[0064] The display substrate further comprises an encapsulation structure and a light-blocking layer BM. The encapsulation structure is located on a side of the plurality of light-emitting devices 50 away from the substrate SUB, and is configured to encapsulate the plurality of light-emitting devices 50 to prevent water vapor and / or oxygen in the external environment from corroding the light-emitting devices 50. For example, the encapsulation structure comprises a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 arranged in sequence in a direction away from the substrate SUB. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 can each be made of an inorganic material with high compactness, such as silicon oxynitride (SiON), silicon oxide (SiOx), or silicon nitride (SiNx). The organic encapsulation layer IJP can be made of a high polymer material containing a desiccant, or a high polymer material capable of blocking water vapor. For example, a high polymer resin is used, so that the stress of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 can be relieved, and a desiccant or other hygroscopic material can also be included to absorb water, oxygen, and other substances that enter the interior. The organic encapsulation layer IJP is formed after the organic material is solidified, and the organic material has a certain fluidity during the manufacturing process. Therefore, the surface of the organic encapsulation layer IJP away from the substrate SUB is a substantially flat surface.

[0065] The light-blocking layer BM is located on a side of the encapsulation structure away from the substrate SUB, and has a plurality of light transmission openings V. The orthographic projection of each light-emitting device 50 on the substrate SUB overlaps with the orthographic projection of a light transmission opening V on the substrate SUB. For example, the light-emitting devices 50 in different shared sub-pixel regions S-P can correspond to different light transmission openings V, and the light-emitting devices 50 in different privacy pixel regions D-P1 also correspond to different light transmission openings V.

[0066] In one example, the light transmission openings V corresponding to the shared sub-pixel regions S-P have a larger area than the light transmission openings V corresponding to the privacy sub-pixel regions D-P. When the display substrate is in the shared mode, the light-emitting devices 50 in the shared sub-pixel regions S-P and the privacy sub-pixel regions D-P all emit light, or only the light-emitting devices 50 in the shared sub-pixel regions S-P emit light. Since the light transmission openings V corresponding to the shared sub-pixel regions S-P all have a larger area, at least part of the large-angle light emitted by the light-emitting devices 50 can exit from the light transmission openings V. When the display substrate is in the privacy mode, the light-emitting devices 50 in the shared sub-pixel regions S-P do not emit light, and the light-emitting devices 50 in the privacy sub-pixel regions D-P emit light. The large-angle light emitted by the light-emitting devices 50 is blocked by the light-blocking layer BM.

[0067] It should be noted that in FIG. 2, the number of light shielding layers BM is taken as one layer for illustration. In other embodiments, the display substrate can include two layers of light shielding layers BM, the first layer of light shielding layers is located on the side of the encapsulation structure away from the substrate SUB, each of the anti-peep pixel portions D-P1 corresponds to a light transmission port V of the first layer of light shielding layers BM, different anti-peep pixel portions D-P1 correspond to different light transmission ports V, and the orthographic projection of each anti-peep pixel portion D-P1 on the substrate SUB overlaps with the orthographic projection of the corresponding light transmission port V of the first layer of light shielding layers BM on the substrate SUB. The spacing region between the adjacent two shared sub-pixel areas S-P arranged along the first direction does not overlap with the orthographic projection of the first layer of light shielding layers BM on the substrate SUB. The second layer of light shielding layers is located on the side of the first layer of light shielding layers away from the substrate SUB. A spacing layer is arranged between the two layers of light shielding layers BM. In this case, the size relationship between the area of the light transmission port corresponding to the anti-peep pixel portion D-P1 and the area of the light transmission port corresponding to the shared sub-pixel area S-P can not be limited. In this case, when the display substrate is in the sharing mode, the light emitting devices 50 in the shared sub-pixel area S-P and the anti-peep sub-pixel area D-P all emit light, or only the light emitting devices 50 in the shared sub-pixel area S-P emit light, and the light emitting devices 50 in the shared sub-pixel area S-P emit light at a large angle to the left and right sides, which will not be blocked by the first layer of light shielding layers. When the display substrate is in the anti-peep display mode, the light emitting devices 50 in the anti-peep sub-pixel area D-P emit light, and the two layers of light shielding layers shield the light emitting devices 50 at a large angle, thereby improving the anti-peep effect.

[0068] For the display substrate shown in FIGS. 1 and 2, since each pixel area P is divided into a shared sub-pixel area S-P and an anti-peep sub-pixel area D-P, and the spacing region between the shared sub-pixel area S-P and the anti-peep sub-pixel area D-P is shielded by the light shielding layer BM, when displaying, the actual light emitting area is smaller than the area of the pixel area P, that is, the aperture ratio is small, thereby affecting the display effect.

[0069] FIG. 3 is a schematic diagram of a distribution of a plurality of pixel regions P of a display substrate provided in some embodiments of the present disclosure, and FIG. 4 is a cross-sectional view along line C-C' in FIG. 3 of the display substrate provided in some embodiments of the present disclosure, the display substrate having a plurality of pixel regions P, only three pixel regions P are schematically shown in FIG. 3, each of the pixel regions P is configured to emit light of one color; in one example, the plurality of pixel regions P of the display substrate form a plurality of pixel units, each of the pixel units includes a plurality of pixel regions P, for example, a red pixel region Pr, a green pixel region Pg, and a blue pixel region Pb, the red pixel region Pr and the green pixel region Pg are arranged along a first direction, and the blue pixel region Pb is located on one side of the red pixel region Pr and the green pixel region Pg along a second direction, the first direction is perpendicular to the second direction. It should be noted that the arrangement of the pixel regions P in FIG. 3 is only exemplary, and in other examples, the pixel regions P can be arranged in other manners, for example, the plurality of pixel regions P in the same pixel unit can be arranged in sequence along the first direction or the second direction.

[0070] As shown in FIGS. 3 and 4, the display substrate includes a substrate SUB, and a first light shielding layer 20, a plurality of light emitting devices 50, and a plurality of pixel driving circuits 30 disposed on the substrate SUB. The first light shielding layer 20 has a plurality of pixel openings, each of the pixel openings corresponds to one of the pixel regions P. For example, the first light shielding layer 20 can be made of black insulating material. The light emitting device 50 includes a first light emitting unit 54 and a second light emitting unit 55 disposed in sequence and electrically connected in a direction away from the substrate SUB, for example, a connecting electrode can be disposed between the first light emitting unit 54 and the second light emitting unit 55 to electrically connect the two. The first light emitting unit 54 is located in the pixel opening, and a distance from an outlight surface of the first light emitting unit 54 to the substrate SUB is less than a distance from a surface of the first light shielding layer 20 away from the substrate SUB to the substrate SUB.

[0071] The plurality of pixel driving circuits 30 are located on a side of the plurality of light emitting devices 50 close to the substrate SUB, each of the pixel driving circuits 30 can correspond to one of the light emitting devices 50, and the pixel driving circuit 30 is configured to drive the first light emitting unit 54 to emit light in a privacy mode and control the second light emitting unit 55 to be turned off, and drive at least the second light emitting unit 55 to emit light in a sharing mode. For example, in the sharing mode, the pixel driving circuit 30 can only drive the second light emitting unit 55 to emit light, or drive both the first light emitting unit 54 and the second light emitting unit 55 to emit light.

[0072] In the embodiments of the present disclosure, when the display substrate is in the privacy mode, the pixel driving circuit 30 drives the first light emitting unit 54 to emit light, and the second light emitting unit 55 does not emit light; at this time, since the surface of the first light shielding layer 20 away from the substrate SUB is higher than the light emitting surface of the first light emitting unit 54, the first light shielding layer 20 has a certain shielding effect on the large-angle light emitted by the first light emitting unit 54, thereby realizing the privacy effect; when the display substrate is in the sharing mode, the pixel driving circuit 30 at least drives the second light emitting unit 55 to emit light, since the second light emitting unit 55 is farther away from the substrate SUB than the first light emitting unit 54, the first light shielding layer 20 has less or no limiting effect on the light emitted by the second light emitting unit 55, thereby realizing the sharing effect.

[0073] In addition, in the embodiments of the present disclosure, the first light emitting unit 54 and the second light emitting unit 55 are stacked, and compared with FIG. 1, the display substrate of the present disclosure has a larger area of actual light emitting region than the area of the pixel region P when performing privacy display or sharing display, thereby improving the display effect; and compared with FIG. 1, the embodiments of the present disclosure do not need to further divide the pixel region, thereby simplifying the design difficulty and process difficulty of the first light shielding layer 20.

[0074] In one example, the display substrate of the present disclosure can be used in a vehicle display device, in the sharing mode, the users of the main driver and the copilot can see the display picture; in the privacy mode, the user of the copilot can see the display picture, and the user of the main driver position will not be disturbed by the display picture, ensuring the driving safety.

[0075] In some embodiments, the light emitting device 50 can further include a first electrode 51, a connecting electrode 56 and a second electrode 52, the first electrode 51 is located on the side of the first light emitting unit 54 close to the substrate SUB, the connecting electrode 56 is located between the first light emitting unit 54 and the second light emitting unit 55, and is made of a light-transmitting material; for example, the light-transmitting material includes indium tin oxide (ITO), indium zinc oxide (IZO), etc. At least part of the second electrode 52 is located on the side of the second light emitting unit 55 away from the substrate SUB.

[0076] The first light emitting unit 54 and the second light emitting unit 55 can each include a light emitting layer, which can include small-molecule organic material or polymer molecular organic material, and can be a fluorescent light emitting material or a phosphorescent light emitting material, and can emit red light, green light, blue light, or white light. In addition, the first light emitting unit 54 and the second light emitting unit 55 can each further include a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer. For example, the first electrode 51 is an anode, and the second electrode 52 is a cathode, and in this case, the hole injection layer and the hole transport layer are located between the light emitting layer and the first electrode 51, and the electron injection layer and the electron transport layer are located between the light emitting layer and the second electrode 52. The second electrodes 52 of the plurality of light emitting devices 50 can be connected as an electrode layer.

[0077] The first electrode 51, the first light emitting unit 54, and the connecting electrode 56 constitute a first light emitting diode, which is an OLED (Organic Light Emitting Diode); the connecting electrode 56, the second light emitting unit 55, and the second electrode 52 constitute a second light emitting diode, which is also an OLED. The connecting electrode 56 can be used as a cathode of the first light emitting diode and is reused as an anode of the second light emitting diode. When a current path is formed between the first electrode 51, the first light emitting unit 54, and the connecting electrode 56, the first light emitting unit 54 emits light; when a current path is formed between the connecting electrode 56, the second light emitting unit 55, and the second electrode 52, the second light emitting unit 55 emits light. For example, the second electrode 52 is electrically connected to the second power line, and a driving current is provided to the first electrode 51, and in the privacy mode, the first light emitting unit 54 emits light and the second light emitting unit 55 does not emit light by short-circuiting the second electrode 52 and the connecting electrode 56, thereby achieving the privacy effect; in the sharing mode, the second light emitting unit 55 emits light and the first light emitting unit 54 does not emit light by short-circuiting the first electrode 51 and the connecting electrode 56; or, the first electrode 51 and the connecting electrode 56 are kept at different voltages (i.e., not short-circuited), and the second electrode 52 and the connecting electrode 56 are kept at different voltages (i.e., not short-circuited), so that the first light emitting unit 54 and the second light emitting unit 55 emit light at the same time.

[0078] In the embodiments of the present disclosure, each pixel region corresponds to one light emitting device 50, and one light emitting device 50 includes two light emitting units (i.e., the first light emitting unit 54 and the second light emitting unit 55 described above), each of which corresponds to one light emitting diode. In other examples, the light emitting device 50 can include M light emitting diodes arranged in sequence away from the substrate SUB, M > 2, wherein m1 light emitting diodes constitute the first light emitting unit 54, m2 light emitting diodes constitute the second light emitting unit 55, and m1 + m2 = M; the first electrode 51 is integrated with the anode of the light emitting diode closest to the substrate SUB; the second electrode 52 is integrated with the cathode of the light emitting diode farthest from the substrate SUB; the cathode of the m1th light emitting diode and the anode of the (m1 + 1)th light emitting diode are integrated and serve as the connecting electrode 56.

[0079] FIG. 5 is a schematic diagram of a pixel driving circuit 30 provided in some embodiments of the present disclosure. In some embodiments, as shown in FIG. 5, the pixel driving circuit 30 can include a driving sub-circuit 31 and a first switching sub-circuit 32. The driving sub-circuit 31 is electrically connected to the first electrode 51 and is configured to provide a corresponding driving current for the first electrode 51 according to a driving signal. The second electrode 52 of the light emitting device 50 is electrically connected to a second power supply line VSS. The first switching sub-circuit 32 has a first end electrically connected to the connecting electrode 56 and a second end electrically connected to the second electrode 52. The first switching sub-circuit 32 is configured to be conductive between the first end and the second end in the privacy mode, and to be disconnected between the first end and the second end in the sharing mode.

[0080] In one example, as shown in FIG. 5, the pixel driving circuit 30 includes the driving sub-circuit 31 and the first switching sub-circuit 32, and no other switching sub-circuit is arranged between the first electrode 51 and the connecting electrode 56. In this case, in the privacy mode, the first switching sub-circuit 32 is conductive between the first end and the second end, which is equivalent to short-circuiting the connecting electrode 56 and the second electrode 52, so that the second light emitting unit 55 no longer emits light. In the sharing mode, the first switching sub-circuit 32 is disconnected between the first end and the second end, and the driving current provided by the driving sub-circuit 31 can flow through the second light emitting unit 55 to make the second light emitting unit 55 emit light. Since no other switching sub-circuit is arranged between the first electrode 51 and the connecting electrode 56, the driving current can flow through the first light emitting unit 54, so that the first light emitting unit 54 and the second light emitting unit 55 emit light at the same time, thereby increasing the front brightness of the display substrate.

[0081] Figure 6 is a schematic diagram of the pixel driving circuit 30 provided in some embodiments of the present disclosure. As shown in Figure 6, in another example, the pixel driving circuit 30 can further include a second switch sub-circuit 33 in addition to the driving sub-circuit 31 and the first switch sub-circuit 32. The first end of the second switch sub-circuit 33 is electrically connected to the first electrode 51, and the second end is electrically connected to the connection electrode 56. The second switch sub-circuit 33 is configured to be disconnected between the first end and the second end in the privacy mode, so as not to affect the light emission of the first light emitting unit 54; and to be connected or disconnected between the first end and the second end in the sharing mode. For the pixel driving circuit shown in Figure 6, in the privacy mode, the first end and the second end of the first switch sub-circuit 32 are connected, which is equivalent to shorting the connection electrode 56 and the second electrode 52, so that the second light emitting unit 55 no longer emits light; and the first end and the second end of the second switch sub-circuit 33 are disconnected, which does not affect the light emission of the first light emitting unit 54. In the sharing mode, the first end and the second end of the first switch sub-circuit 32 are disconnected, and the driving current provided by the driving sub-circuit 31 can flow through the second light emitting unit 55 to make the second light emitting unit 55 emit light; at the same time, the first end and the second end of the second switch sub-circuit 33 are connected, so that the first light emitting unit 54 is short-circuited and no longer emits light; or, the first end and the second end of the second switch sub-circuit 33 are disconnected in the sharing mode, so that the driving current can flow through the first light emitting unit 54. At this time, the first light emitting unit 54 emits light and the second light emitting unit 55 emits light at the same time, thereby increasing the front brightness of the display substrate in the sharing mode.

[0082] Figure 7 is a schematic diagram of the specific structure of the pixel driving circuit 30 provided in some embodiments of the present disclosure, which is a specific implementation manner of Figure 5; and Figure 8 is a schematic diagram of the specific structure of the pixel driving circuit 30 provided in some embodiments of the present disclosure, which is a specific implementation manner of Figure 6.

[0083] As shown in FIGS. 7 and 8, the driving sub-circuit 31 comprises a driving transistor DTFT, a capacitor C, a reset module 311, a data writing module 312, a compensation module 313, and a light-emitting control module 314. The reset module 311 is configured to connect the reference voltage line VREF to the first end of the capacitor C and connect the initialization signal line VINIT to the second end of the capacitor C in response to a reset signal on the reset line RST. The gate of the driving transistor DTFT is electrically connected to the second end of the capacitor C, and the first electrode of the driving transistor DTFT is electrically connected to the first power supply line VDD. The data writing module 312 is configured to transmit a data voltage signal on the data line DL to the first end of the capacitor C in response to a scanning signal on the scanning line GL. The compensation module 313 is configured to connect the gate and the second electrode of the driving transistor DTFT in response to a scanning signal, so as to write the threshold voltage of the driving transistor DTFT into the capacitor C. The light-emitting control module 314 is configured to connect the reference voltage line VREF to the first end of the capacitor C and connect the second electrode of the driving transistor DTFT to the first electrode 51 in response to a light-emitting control signal on the light-emitting control line EM.

[0084] The working process of the pixel driving circuit 30 comprises a reset stage, a data writing stage, and a light-emitting stage. Specifically, in the reset stage, the reset module 311 transmits the voltage signal Vdd of the first power supply line VDD to the first end (i.e., the N2 node) of the capacitor C and transmits the initial voltage signal of the initial voltage line VINIT to the second end (i.e., the N1 node) of the capacitor C under the control of the reset signal on the reset line RST. Therefore, in the reset stage, the N2 node voltage is Vdd, the N1 node voltage is Vinit, Vref is the voltage of the reference voltage end VREF, and Vinit is the voltage of the initial voltage end VINIT.

[0085] In the data writing stage, the data writing module 312 transmits the voltage signal Vdata of the data line DL to the N2 node under the control of the scanning line GL, and the compensation module 313 connects the gate and the second electrode of the driving transistor DTFT. At this time, the driving transistor DTFT is equivalent to a diode structure, and the voltage of the N1 node reaches Vdd+Vth, so as to write the threshold voltage Vth of the driving transistor DTFT into the capacitor.

[0086] In the light emitting stage, under the control of the light emitting control line EM, the light emitting control module 314 transmits the voltage of the reference voltage line VREF to the N2 node. From the data writing stage to the light emitting stage, the voltage variation of the N2 node is Vref-Vdata, and due to the voltage stabilization of the capacitor C, the voltage of the N1 node will change from Vdd+Vth of the last stage to Vdd+Vth+Vref-Vdata. Therefore, in this stage, the gate voltage Vg of the driving transistor DTFT remains Vdd+Vth+Vref-Vdata, the source voltage Vs is the voltage Vdd of the first power supply line VDD, and the driving transistor DTFT is in a saturated state. According to the saturated state current characteristic, the driving current Ioled provided to the light emitting device 50 satisfies: Ioled=K(Vgs-Vth) 2 =K(Vdd+Vth+Vref-Vdata-Vdd-Vth) 2 =K(Vref-Vdata) 2

[0087] wherein K is a parameter related to the structural characteristics of the driving transistor DTFT, which can be regarded as a constant. As can be seen from the formula, the driving current provided to the light emitting device 50 is irrelevant to both the threshold voltage and the voltage of the first power supply line VDD, thereby preventing the threshold drift of the driving transistor DTFT and the IR Drop of the first power supply line VDD from affecting the driving current.

[0088] Further, as shown in FIG. 7 and FIG. 8, in some embodiments, the reset module 311 includes a first reset transistor T7 and a second reset transistor T1, wherein the gate of the first reset transistor T7 is electrically connected with the reset line RST, the first electrode is electrically connected with the first power supply line VDD, and the second electrode is electrically connected with the first end of the capacitor C. The gate of the second reset transistor T1 is electrically connected with the reset line RST, the first electrode is electrically connected with the initialization signal line VINIT, and the second electrode is electrically connected with the second end of the capacitor C. When the reset signal of the reset line RST is at the working level, the first reset transistor T7 turns on the first power supply line VDD and the first end of the capacitor C, and the second reset transistor T1 turns on the initialization signal line VINIT and the second end of the capacitor C. The data writing module 312 includes a writing transistor T2, the gate of the writing transistor T2 is electrically connected with the scanning line GL, the first electrode is electrically connected with the data line DL, and the second electrode is electrically connected with the first end of the capacitor C. When the scanning signal on the scanning line GL is at the working level, the writing transistor T2 turns on the data line DL and the first end of the capacitor C. The compensation module 313 includes a compensation transistor T2, the gate of the compensation transistor T2 is electrically connected with the scanning line GL, the first electrode of the compensation transistor T2 is electrically connected with the gate of the driving transistor DTFT, and the second electrode of the compensation transistor T2 is electrically connected with the second electrode of the driving transistor DTFT. When the scanning signal on the scanning line GL is at the working level, the compensation transistor T2 turns on the gate and the second electrode of the driving transistor DTFT. The light-emitting control module 314 includes a first light-emitting control transistor T5 and a second light-emitting control transistor T6, wherein the gate of the first light-emitting control transistor T5 is electrically connected with the light-emitting control line EM, the first electrode is electrically connected with the reference voltage line VREF, and the second electrode is electrically connected with the first end of the capacitor C. The gate of the second light-emitting control transistor T6 is electrically connected with the light-emitting control line EM, the first electrode of the second light-emitting control transistor T6 is electrically connected with the second electrode of the driving transistor DTFT, and the second electrode is electrically connected with the first electrode 51. When the light-emitting control signal on the light-emitting control line EM is at the working level, the first light-emitting control transistor T5 turns on the reference voltage line VREF and the first end of the capacitor C, and the second light-emitting control transistor T6 turns on the second electrode of the driving transistor DTFT and the first electrode 51 of the light-emitting device 50.

[0089] The transistor adopted in the embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other same devices with other characteristics. Since the source and drain of the adopted transistor are symmetrical, the source and drain thereof are not distinguished. In the embodiments of the present disclosure, in order to distinguish the source and drain of the transistor, one of the poles is referred to as a first pole and the other pole is referred to as a second pole. In addition, the transistor can be divided into N-type and P-type according to the characteristics of the transistor. In the following embodiments, a P-type transistor is taken as an example for description. When the P-type transistor is adopted, the source and drain are turned on when a low level is input to the gate. When the N-type transistor is adopted, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the source and drain are turned on when a high level is input to the gate. It is conceivable that the N-type transistor is adopted to be easily thought of by those skilled in the art without creative labor, and thus is also within the protection scope of the embodiments of the present disclosure.

[0090] When the transistors are all P-type transistors, the working level signal is a low level signal and the non-working level signal is a high level signal.

[0091] In some embodiments, as shown in FIGS. 7 and 8, the first switch sub-circuit 32 includes a first switch transistor T8, the gate of the first switch transistor T8 is electrically connected with the first control line CT1, the first pole of the first switch transistor T8 is the first end of the first switch sub-circuit 32, that is, the first pole of the first switch transistor T8 is electrically connected with the second electrode 52, and the second pole of the first switch transistor T8 is the second end of the first switch sub-circuit 32, that is, the second pole of the first switch transistor T8 is electrically connected with the connecting electrode 56.

[0092] In some embodiments, as shown in FIG. 8, the second switch sub-circuit 33 includes a second switch transistor T9, the gate of the second switch transistor T9 is electrically connected with the second control line CT2, the first pole of the second switch transistor T9 is the first end of the second switch sub-circuit 33, that is, the first pole of the second switch transistor T9 is electrically connected with the first electrode 51, and the second pole of the second switch transistor T9 is the second end of the second switch sub-circuit 33, that is, the second pole of the second switch transistor T9 is electrically connected with the connecting electrode 56.

[0093] FIG. 9 is a timing diagram of the pixel driving circuit 30 provided in some embodiments of the present disclosure. The working process of the pixel driving circuit 30 is introduced below in combination with FIGS. 8 and 9, wherein the P-type transistor is taken as an example for description.

[0094] In the reset stage t1, the reset line RST provides a low level signal, the scan line GL and the light emitting control line EM both provide high level signals, at this time, the first reset transistor T7 and the second reset transistor T1 are turned on, so that the voltage of the N2 node reaches the voltage Vdd of the first power supply line VDD, and the voltage of the N1 node reaches the voltage Vinit of the initialization signal line VINIT.

[0095] In the data writing stage t2, the scan line GL provides a low level signal, the reset line RST and the light emitting control line EM both provide high level signals, at this time, the writing transistor T4 is turned on, the voltage signal of the data line DL is transmitted to the N2 node, so that the voltage of the N2 node reaches Vdata; at the same time, the compensation transistor T2 turns on the gate and the second electrode of the driving transistor DTFT, and the voltage of the N1 node reaches Vdd+Vth.

[0096] In the light emitting stage, the light emitting control line EM provides a low level signal, the reset line RST and the scan line GL both provide high level signals, at this time, the first light emitting control transistor T5 is turned on, so as to transmit the voltage signal of the reference voltage line VREF to the N2 node, and the voltage of the N2 node changes from Vdate in the last stage to Vref. Under the voltage stabilizing action of the capacitor, the voltage of the N1 node changes from Vdd+Vth in the last stage to Vdd+Vth+Vref-Vdata. At the same time, the second light emitting control transistor T6 is turned on, and the driving current of the driving transistor DTFTT3 is transmitted to the light emitting device 50. Wherein, the driving current Ioled satisfies: Ioled=K(Vgs-Vth) 2 =K(Vdd+Vth+Vref-Vdata-Vdd-Vth) 2 =K(Vref-Vdata) 2 .

[0097] Wherein, the display substrate can further include a mode control circuit, for providing control signals to the first control line CT1 and the second control line CT2 according to the display mode (peep-proof mode or sharing mode) of the display substrate, to control the on-off state of the first switch transistor T8 and the second switch transistor T9.

[0098] In one example, the pixel regions P are arranged in multiple rows, a first switch transistor T8 in each row of pixel regions P is connected to a first control line CT1, a second switch transistor T9 in each row of pixel regions P is connected to a second control line CT2, and the mode control circuit can include a master control circuit, a first shift register, and a second shift register. The master control circuit is configured to provide an enable signal to the first shift register and a disable signal to the second shift register when the display substrate is in the privacy mode. The first shift register is configured to provide a low-level signal to the first control line CT1 connected to each row of pixel regions P in sequence according to the enable signal, to control the first switch transistor T8 to turn on, so that the second light emitting unit 55 does not emit light. The second shift register is configured to provide a high-level signal to the second control line CT2 connected to each row of pixel regions P in sequence according to the disable signal, to control the second switch transistor T9 to turn off, so that the first light emitting unit 54 can emit light. The master control circuit is further configured to provide a disable signal to the first shift register and an enable signal to the second shift register when the display substrate is in the sharing mode. The first shift register provides a high-level signal to the first control line CT1 connected to each row of pixel regions P in sequence according to the disable signal, to control the first switch transistor T8 to turn off, so that the second light emitting unit 55 can emit light. The second shift register provides a low-level signal to the second control line CT2 connected to each row of pixel regions P in sequence according to the enable signal, to control the second switch transistor T9 to turn on, so that the first light emitting unit 54 does not emit light. Alternatively, the master control circuit provides a disable signal to both the first shift register and the second shift register when the display substrate is in the sharing mode, so that both the first light emitting unit 54 and the second light emitting unit 55 in each pixel region P emit light.

[0099] FIG. 10 is a schematic diagram of the connection between the light emitting device 50 and the pixel driving circuit 30 according to some embodiments of the present disclosure. In FIG. 10, only two transistors and one capacitor C in the pixel driving circuit 30 are shown.

[0100] In some embodiments, the semiconductor layer is provided on a substrate SUB. The substrate SUB can be a rigid substrate, or a flexible substrate, where the rigid substrate can be a glass substrate, and the flexible substrate can be made of a flexible organic material. For example, the organic material is a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. The material of the semiconductor layer can include, for example, an inorganic semiconductor material (e.g., polysilicon, amorphous silicon, etc.), an organic semiconductor material, and an oxide semiconductor material. The semiconductor layer includes an active layer of each transistor (e.g., an active layer T6-a of the second light-emitting control transistor T6 and an active layer T8-a of the first switching transistor T8), which includes a channel portion and a source connection portion and a drain connection portion on both sides of the channel portion, the source connection portion being connected to the source of the transistor, and the drain connection portion being connected to the drain of the transistor. The source connection portion and the drain connection portion can each be doped with an impurity (e.g., an N-type impurity or a P-type impurity) having a higher impurity concentration than the channel portion. The channel portion is directly opposite the gate of the transistor, and when a voltage signal applied to the gate reaches a certain value, a carrier path is formed in the channel portion, which causes the source and the drain of the transistor to be turned on.

[0101] In one example, to prevent or reduce diffusion of metal atoms and / or impurities from the substrate SUB into the active layer of the transistor, a buffer layer BFL can be provided between the semiconductor layer and the substrate SUB.

[0102] In some embodiments, a first gate insulating layer GI1 is provided on the semiconductor layer, and the material of the first gate insulating layer GI1 can include a silicon compound. For example, the material of the first gate insulating layer GI1 includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbon nitride (SiCxNy), etc. In addition, the first gate insulating layer GI1 can be a single layer or multiple layers.

[0103] In some embodiments, a first gate electrode layer is disposed on the first gate insulating layer GI1. The first gate electrode layer can include the gate of each transistor (e.g., the gate T6-g of the second light emitting control transistor T6 and the gate T8-g of the first switch transistor T8), the first electrode plate C1 of the capacitor C. The material of the first gate electrode layer can include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first gate electrode layer can include gold (Au), an alloy of gold, silver (Ag), an alloy of silver, aluminum (Al), an alloy of aluminum, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), an alloy of copper, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), an alloy of molybdenum, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate electrode layer can have a single layer or multiple layers.

[0104] In some embodiments, as shown in FIG. 10, a second gate insulating layer GI2 is disposed on the first gate electrode layer, and the material of the second gate insulating layer GI2 can be selected from the materials of the first gate insulating layer GI1 listed above. The second gate insulating layer GI2 can be formed as a single layer or multiple layers.

[0105] In some embodiments, as shown in FIG. 10, a second gate electrode layer is disposed on the second gate insulating layer GI2. The second gate electrode layer can include the second electrode plate C2 of the capacitor C. The material of the second gate electrode layer is selected from the materials of the first gate electrode layer listed above. The second gate electrode layer can have a single layer or multiple layers.

[0106] In some embodiments, as shown in FIG. 10, an interlayer insulating layer ILD is disposed on the second gate electrode layer, and the material of the interlayer insulating layer ILD can include, for example, a silicon compound, a metal oxide, etc. The silicon compound and the metal oxide listed above can be specifically selected, which will not be repeated here.

[0107] In some embodiments, as shown in FIG. 10, the source-drain conductive layer is disposed on the interlayer insulating layer ILD. The source-drain conductive layer can include the source (e.g., the source T6-s of the second light-emitting control transistor T6 and the source T8-s of the first switch transistor T8) and the drain (e.g., the drain T6-d of the second light-emitting control transistor T6 and the drain T8-d of the first switch transistor T8) of each transistor, the source being electrically connected with the source connection portion, and the drain being electrically connected with the drain connection portion. The source-drain conductive layer can include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the source-drain conductive layer can be a single layer or multiple layers of metal, such as Mo / Al / Mo or Ti / Al / Ti.

[0108] In some embodiments, as shown in FIG. 10, the passivation layer PVX is disposed on the first source-drain conductive layer. The material of the passivation layer PVX can include a silicon compound, such as silicon oxide, silicon nitride, or silicon oxynitride.

[0109] In some embodiments, as shown in FIG. 10, the planarization layer PLN is disposed on the side of the passivation layer PVX away from the substrate SUB, and the surface of the planarization layer PLN away from the substrate SUB is substantially planar. The planarization layer PLN is made of an organic insulating material, such as a resin material including polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone, etc. For example, the organic insulating material includes an elastic material, such as urethane, thermoplastic polyurethane (TPU), etc.

[0110] In some embodiments, as shown in FIG. 10, the light-emitting device 50 and the first light-blocking layer 20 are disposed on the side of the planarization layer PLN away from the substrate SUB. The first light-blocking layer 20 has a plurality of pixel openings, and the light-emitting device 50 corresponds to the pixel openings one-to-one. The light-emitting device 50 includes, in order from the side away from the substrate SUB, the first electrode 51, the first light-emitting unit 54, the connection electrode 56, the second light-emitting unit 55, and the second electrode 52. The first electrode 51 is disposed on the planarization layer PLN and is electrically connected with the pixel driving circuit 30 through the first via hole H1 penetrating the planarization layer PLN. The first electrode 51 can be made of a material such as metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The first electrode 51 can be a single layer or a multi-layer structure. The first electrode 51 and the first light-emitting unit 54 are located in the pixel openings.

[0111] As shown in FIG. 10, the connection electrode 56 includes a first connection part 561, a second connection part 562, and a third connection part 563. The first connection part 561 is located on the side of the first light emitting unit 54 away from the substrate SUB. The second connection part 562 is located between the first light shielding layer 20 and the planarization layer PLN and is electrically connected to the pixel driving circuit 30 through a second via hole H2 penetrating the planarization layer PLN. The third connection part 563 is connected between the first connection part 561 and the second connection part 562. For example, the thickness direction of the first connection part 561 and the thickness direction of the second connection part 562 are parallel to the thickness direction of the substrate SUB, and the thickness direction of the third connection part 563 intersects the thickness direction of the first connection part 561.

[0112] For example, the first connection part 561, the second connection part 562, and the third connection part 563 are connected as an integrated structure.

[0113] In one example, the first light emitting unit 54 includes a bottom surface facing the substrate SUB, a top surface away from the substrate SUB, and a side surface connecting the bottom surface and the top surface. The top surface of the first light emitting unit 54 is in contact with the first connection part 561. The third connection part 563 is electrically connected to the edge of the side of the second connection part 562 and is in contact with the side surface of the first light emitting unit 54.

[0114] In one example, as shown in FIG. 10, an insulating layer 70 is provided between the first electrode 51 and the second connection part 562. The height difference between the surface of the insulating layer 70 away from the substrate SUB and the surface of the first electrode 51 away from the substrate SUB is less than the thickness of the first electrode 51. The surface of the first light emitting unit 54 facing the substrate SUB is in contact with the surface of the insulating layer 70 away from the substrate SUB. By providing the insulating layer 70, the electrical insulation between the first electrode 51 and the connection electrode 56 can be ensured. In addition, in the case where the insulating layer 70 is not provided, there is a certain gap between the first electrode 51 and the second connection part 562. At this gap position, the first light emitting unit 54 is in contact with the planarization layer PLN, while at the position of the first electrode 51, the first light emitting unit 54 is in contact with the first electrode 51. Since the first electrode 51 has a certain thickness, the first light emitting unit 51 will sink to a certain extent at the gap between the first electrode 51 and the second connection part 562. In the embodiment of the present disclosure, by providing the insulating layer 70, the sinking problem of the first light emitting unit 51 at the gap between the first electrode 51 and the second connection part 562 can be improved, thereby improving the light emission effect of the light emitting device 50.

[0115] For example, the surface of the insulating layer 70 away from the substrate SUB is flush or substantially flush with the surface of the first electrode 51 away from the substrate SUB, so that the first light emitting unit 54 is located on a flat or substantially flat surface, further improving the light emission effect of the light emitting device 50.

[0116] In some embodiments, the orthographic projection of the first electrode 51 on the substrate SUB and the orthographic projection of the insulating layer 70 on the substrate SUB form a first projection pattern, and the orthographic projection of the first light emitting unit 54 on the substrate SUB is located within the first projection pattern, so that the first light emitting unit 54 as a whole is located on a flat or substantially flat surface, further improving the light emitting effect of the light emitting device 50.

[0117] In some embodiments, the insulating layer 70 can be located on one side of the first electrode 51, or the insulating layer 70 is provided on multiple sides of the first electrode 51.

[0118] In the drawings of the present disclosure, the insulating layer 70 is taken as an example to be located on one side of the first electrode 51, specifically, the first electrode 51 includes oppositely arranged first and second edges, the insulating layer 70 is in contact with the first edge (i.e. the right side edge of the first electrode 51 in FIG. 10), and the second edge (i.e. the left side edge of the first electrode 51 in FIG. 10) is free of spacing between the first light shielding layer 20, thereby facilitating the increase of the area of the first electrode 51 and improving the light emitting effect of the light emitting device 50. Wherein, the case that the second edge is free of spacing between the first light shielding layer 20 can include that the orthographic projection of the second edge on the substrate SUB is located within the orthographic projection range of the first light shielding layer 20 on the substrate SUB, and is free of contact with the orthographic projection edge of the first light shielding layer 20, or the orthographic projection of the second edge on the substrate SUB is in contact with the orthographic projection edge of the first light shielding layer 20 on the substrate SUB.

[0119] In some embodiments, the orthographic projection of the third connecting portion 563 on the substrate SUB overlaps with the orthographic projection of the first light shielding layer 20 on the substrate SUB. For example, the orthographic projection of the third connecting portion 563 on the substrate SUB is located within the orthographic projection range of the first light shielding layer 20 on the substrate SUB, in which case the surface of the connecting electrode 56 exposed by the pixel opening is a flat surface, so that the surface of the second light emitting unit 55 in contact with the connecting electrode 56 is also a flat surface, thereby facilitating the improvement of the light emitting effect of the light emitting device 50.

[0120] Further, the orthographic projection of the first light emitting unit 54 and the second light emitting unit 55 on the substrate SUB are both located within the orthographic projection range of the first connecting portion 54 on the substrate SUB, so that the second light emitting unit 55 as a whole is located on a flat surface, further improving the light emitting effect of the light emitting device 50.

[0121] In some embodiments, the second electrodes 52 of the light emitting devices 50 can be connected as a whole to form a second electrode layer.

[0122] In some embodiments, the height difference between the surface of the substrate SUB and the light-out surface of the second light-emitting unit 55 is less than half the thickness of the second light-emitting unit 55, so that the first light-shielding layer 20 can shield a certain amount of light rays of large angles of the first light-emitting unit 54, so that the display substrate has a smaller viewing angle in the privacy mode; and in the sharing mode, the first light-shielding layer 20 does not shield or shields a smaller amount of light rays of large angles of the second light-emitting unit 55. In addition, the possibility of fracture of the second electrode layer can be reduced. For example, the surface of the substrate SUB and the light-out surface of the second light-emitting unit 55 can be flush, so that the first light-shielding layer 20 can shield a certain amount of light rays of large angles of the first light-emitting unit 54, and does not shield the light rays of the second light-emitting unit 55, so that the display substrate has a smaller viewing angle in the privacy mode, and has a larger viewing angle in the sharing mode; at the same time, the second electrode layer is located on a flat surface, preventing the second electrode layer from being fractured.

[0123] In the embodiments of the present disclosure, the shape of the pixel opening is not limited. For example, the cross-sectional area of the pixel opening does not change along the direction close to the substrate SUB; for example, the cross-sectional area of the pixel opening of the first light-shielding layer 20 gradually decreases along the direction close to the substrate SUB. The cross-section of the pixel opening is a cross-section perpendicular to the thickness direction of the substrate SUB.

[0124] In some embodiments, the display substrate can further include a packaging structure disposed on the side of the plurality of light-emitting devices 50 away from the substrate SUB, and covering the first light-shielding layer 20 and the light-emitting devices 50, for packaging the light-emitting devices 50 to prevent water vapor and / or oxygen in the external environment from corroding the light-emitting devices 50. The packaging structure can include a first inorganic packaging layer CVD1, a second inorganic packaging layer CVD2, and an organic packaging layer IJP between the two, which can be referred to the above description and will not be repeated here.

[0125] In some embodiments, as shown in FIG. 4, the display substrate can further include at least one second light-shielding layer BM, the second light-shielding layer BM being located on the side of the packaging structure away from the substrate SUB, the second light-shielding layer BM having a plurality of light-transmitting openings V, and the orthographic projection of each light-emitting device 50 on the substrate SUB overlaps with the orthographic projection of the light-transmitting opening V on the substrate SUB. By providing the second light-shielding layer BM, the viewing angle in the privacy mode can be reduced. In FIG. 4, two second light-shielding layers BM are taken as an example for description, and the more the number of the second light-shielding layers BM, the smaller the viewing angle. Therefore, in actual application, the number of layers of the second light-shielding layer BM can be set according to actual needs.

[0126] When the second light shielding layer BM is in multiple layers, a spacing layer 60 can be arranged between two adjacent second light shielding layers BM, for example, the spacing layer 60 can be made of an organic material, and the second light shielding layer BM can be made of a metal material or a non-metal material that is opaque.

[0127] FIG. 11 is a cross-sectional view along line C-C' in FIG. 3, provided in some embodiments of the present disclosure. As shown in FIG. 11, in some embodiments, the display substrate can further include a color filter layer including a plurality of color filter portions CF, the color filter portions CF being located on a side of the encapsulation structure away from the substrate SUB, for example, at least part of the color filter portions CF being located in a light transmission opening of a layer of the second light shielding layer BM farthest away from the substrate SUB when the display substrate includes the second light shielding layer BM. The light emitting device 50 has an orthogonal projection on the substrate SUB that overlaps with an orthogonal projection of the color filter portion CF on the substrate SUB. In some embodiments, the display substrate includes a plurality of light emitting devices 50 having a plurality of light emitting colors, for example, red, green, and blue. In some embodiments, the color filter portion CF has a color identical to a light emitting color of the corresponding light emitting device 50. By arranging the color filter portion CF, the color gamut of the display substrate can be improved, and the reflection of external ambient light can be reduced.

[0128] As shown in FIG. 11, the display substrate can further include an overcoat layer OC1, a first optical adhesive layer OCA1, and a cover plate CG, the overcoat layer OC1 being located on a side of the color filter layer away from the substrate SUB, the first optical adhesive layer OCA1 being located on a side of the overcoat layer OC1 away from the substrate SUB, and the cover plate CG being located on a side of the first optical adhesive layer OCA1 away from the substrate SUB.

[0129] FIG. 12 is a cross-sectional view along line C-C' in FIG. 3, provided in some other embodiments of the present disclosure. FIG. 12 is similar to FIG. 11, except that in FIG. 12, the display substrate no longer includes the color filter portion CF described above, and the display substrate in FIG. 12 can further include a polarizer POL, a first optical adhesive layer OCA1, a second optical adhesive layer OCA2, and a cover plate CG, the first optical adhesive layer OCA1 being located on a side of the overcoat layer OC1 away from the substrate SUB, the polarizer POL being located on a side of the first optical adhesive layer OCA1 away from the substrate SUB, and the polarizer POL being a circular polarizer, thereby reducing the reflection of external ambient light by the display substrate.

[0130] The second optical adhesive layer OCA2 is located on a side of the polarizer POL away from the substrate SUB, and the cover plate CG is located on a side of the second optical adhesive layer OCA2 away from the substrate SUB.

[0131] The preparation method of the display substrate shown in FIG. 4 will be described below. The preparation method of the display substrate includes the following steps:

[0132] S1, forming a pixel driving circuit 30 corresponding to each pixel region on a substrate SUB.

[0133] S2, forming a first electrode 51 of a light emitting device 50 in each pixel region, the first electrode 51 being electrically connected with the pixel driving circuit 30.

[0134] S3, forming an insulating layer 70 in each pixel region.

[0135] S4, forming a first light emitting unit 54 of the light emitting device 50 in each pixel region, the first light emitting unit 54 being located on a side of the first electrode 51 and the insulating layer 70 away from the substrate SUB.

[0136] The first light emitting unit 54 can be formed by a vapor deposition process.

[0137] S5, forming a connecting electrode 56 of the light emitting device 50 in each pixel region, the connecting electrode 56 including a first connecting part 561, a second connecting part 562 and a third connecting part 563, the first connecting part 561 being located on a side of the first light emitting unit 54 away from the substrate SUB, the second connecting part 561 being electrically connected with the pixel driving circuit 30, and the third connecting part 563 being connected between the first connecting part 561 and the second connecting part 562.

[0138] S6, forming a first light shielding layer 20 having a pixel opening corresponding to each pixel region, each pixel opening exposing at least part of the first connecting part 561.

[0139] S7, forming a second light emitting unit 55 on a side of the first connecting part 561 away from the substrate SUB.

[0140] S8, forming a second electrode 52 of each light emitting device 50, the second electrodes 52 of the light emitting devices 50 being connected as a second electrode layer.

[0141] S9, forming an encapsulation structure on a side of each light emitting device 50 away from the substrate SUB.

[0142] S10, sequentially forming a first layer of a second light shielding layer BM2, a spacer layer 60 and a second layer of the second light shielding layer BM2 on a side of the encapsulation structure away from the substrate SUB, each layer of the second light shielding layer BM2 having a light transmission port V corresponding to each pixel region.

[0143] The embodiments of the present disclosure further provide a display device including the display substrate in any of the above embodiments.

[0144] The display device can include any device or product having a display function. For example, the display device can be a smartphone, a mobile phone, an e-book reader, a desktop PC, a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a car display device, a wearable device (e.g., a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0145] For example, the display device can be a car display device installed in front of a co-driver position, which has a privacy mode and a sharing mode in use, in the sharing mode, users of a main driver and the co-driver can both see a display screen, and in the privacy mode, the user of the co-driver can see the display screen without disturbance of the user of the main driver position.

[0146] It can be understood that the above embodiments are merely exemplary embodiments adopted for illustrating the principles of the present disclosure, however the present disclosure is not limited thereto. Various modifications and improvements can be made by those of ordinary skill in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the present disclosure.

Claims

1. A display substrate having a plurality of pixel regions, wherein, The display substrate comprises: a substrate; a first light shielding layer disposed on the substrate, the first light shielding layer having a plurality of pixel openings, each of the pixel openings corresponding to one of the pixel regions; a plurality of light emitting devices, the light emitting device comprising a first light emitting unit and a second light emitting unit disposed in sequence and electrically connected in a direction away from the substrate; the first light emitting unit is located in the pixel opening, and the distance from the light emitting surface of the first light emitting unit to the substrate is less than the distance from the surface of the first light shielding layer away from the substrate to the substrate; a plurality of pixel driving circuits located on the side of the plurality of light emitting devices close to the substrate, the pixel driving circuit is electrically connected with the light emitting device, and is configured to drive the first light emitting unit to emit light in the privacy mode, and control the second light emitting unit to be closed; and in the sharing mode, at least drive the second light emitting unit to emit light. 2.The display substrate of claim 1, wherein, The light emitting device further comprises a first electrode, a connecting electrode and a second electrode, the first electrode is located on the side of the first light emitting unit close to the substrate, the connecting electrode is located between the first light emitting unit and the second light emitting unit, and is made of a light-transmitting material, and the second electrode is located on the side of the second light emitting unit away from the substrate; The pixel driving circuit comprises: a driving sub-circuit, the driving sub-circuit is electrically connected with the first electrode, and is configured to provide corresponding driving current for the first electrode according to a driving signal; a first switch sub-circuit, the first end of the first switch sub-circuit is electrically connected with the connecting electrode, the second end is electrically connected with the second electrode, and the first switch sub-circuit is configured to connect the first end and the second end in the privacy mode, and disconnect the first end and the second end in the sharing mode. 3.The display substrate of claim 2, wherein, The first switch sub-circuit comprises: a first switch transistor, the gate of the first switch transistor is electrically connected with a first control line, the first pole of the first switch transistor is electrically connected with the connecting electrode, and the second pole of the first switch transistor is electrically connected with the second electrode. 4.The display substrate of claim 2, wherein, The pixel driving circuit further comprises: a second switch sub-circuit, the first end of the second switch sub-circuit is electrically connected with the first electrode, and the second end is electrically connected with the connecting electrode, and the second switch sub-circuit is configured to disconnect the first end and the second end in the privacy mode, and connect or disconnect the first end and the second end in the sharing mode. 5.The display substrate of claim 4, wherein, The second switch sub-circuit comprises: a second switch transistor, the gate of the second switch transistor is electrically connected with a second control line, the first pole of the second switch transistor is electrically connected with the first electrode, and the second pole of the second switch transistor is electrically connected with the connecting electrode. 6.The display substrate of claim 2, wherein, The driving sub-circuit comprises: a driving transistor, a capacitor, a reset module, a data writing module, a compensation module, and a light emitting control module, wherein the reset module is configured to connect the first power supply line and the first end of the capacitor, and connect the initialization signal line and the second end of the capacitor in response to the reset signal on the reset line. A gate of the driving transistor is electrically connected with a second terminal of the capacitor, and a first electrode of the driving transistor is electrically connected with a first power supply line; The data writing module is configured to transmit a data voltage signal on a data line to the first terminal of the capacitor in response to a scanning signal on a scanning line; The compensation module is configured to turn on the gate and the second electrode of the driving transistor in response to the scanning signal, so as to write the threshold voltage of the driving transistor into the capacitor; The light emitting control module is configured to turn on the reference voltage line and the first terminal of the capacitor and turn on the second electrode of the driving transistor and the first electrode in response to a light emitting control signal on a light emitting control line. 7.The display substrate of claim 2, wherein, The connecting electrode comprises a first connecting part, a second connecting part and a third connecting part, the first connecting part is located on a side of the first light emitting unit away from the substrate, the second connecting part is located on a side of the first light shielding layer facing the substrate, and the third connecting part is connected between the first connecting part and the second connecting part, and the pixel driving circuit is electrically connected with the second connecting part. 8.The display substrate of claim 7, wherein, The first light emitting unit comprises a bottom surface facing the substrate, a top surface away from the substrate, and a side surface connecting the bottom surface and the top surface; The third connecting part is electrically connected with an edge on one side of the second connecting part and is in contact with the side surface of the first light emitting unit, and a projection of the third connecting part on the substrate overlaps a projection of the first light shielding layer on the substrate. 9.The display substrate of claim 7, wherein, The first light emitting unit and the second light emitting unit are located in a projection range of the first connecting part on the substrate. 10.The display substrate of claim 7, wherein, The display substrate further comprises: An insulating layer between the first electrode and the second connecting part, a height difference between a surface of the insulating layer away from the substrate and a surface of the first electrode away from the substrate is less than a thickness of the first electrode; The surface of the first light emitting unit facing the substrate is in contact with the surface of the insulating layer away from the substrate. A projection of the first electrode on the substrate and a projection of the insulating layer on the substrate form a first projection pattern, and a projection of the first light emitting unit on the substrate is located in the first projection pattern. 11.The display substrate of claim 10, wherein, The first electrode comprises a first edge and a second edge arranged oppositely, the insulating layer is in contact with the first edge, and there is no spacing between the second edge and the first light shielding layer. 12.The display substrate of claim 10, wherein, A height difference between a surface of the first light shielding layer away from the substrate and a light emitting surface of the second light emitting unit is less than 0.5 times a thickness of the second light emitting unit. 13.The display substrate according to any one of claims 1 to 10, wherein The display substrate further comprises: 14.The display substrate according to any one of claims 1 to 10, wherein An encapsulation structure on a side of the plurality of light emitting devices away from the substrate, for encapsulating the plurality of light emitting devices; At least one second light shielding layer on a side of the encapsulation structure away from the substrate, the second light shielding layer has a plurality of light transmission openings, and a projection of each of the light emitting devices on the substrate overlaps a projection of the light transmission opening on the substrate. ​ A color film layer is located on a side of the encapsulation structure away from the substrate, and the color film layer includes a plurality of color filter portions, at least part of the color filter portions being located in the light transmission port.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

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