Array substrate and display apparatus

Abstract

Provided in the present disclosure are an array substrate and a display apparatus. A non-display area of the array substrate comprises a GOA area. The GOA area comprises multi-stage cascaded GOA units and a forward scanning voltage line, each GOA unit comprises a forward input module, the forward input module comprises a first transistor located on a base substrate, a first electrode of the first transistor is electrically connected to a forward input end, a second electrode of the first transistor is electrically connected to the forward scanning voltage line, and a third electrode of the first transistor is electrically connected to a pull-up node. The GOA area further comprises a threshold voltage compensation conductive layer located on the side of each first transistor that faces away from the base substrate, the orthographic projection of the threshold voltage compensation conductive layer on the base substrate at least partially overlaps the orthographic projection of a channel area of the first transistor on the base substrate, the threshold voltage compensation conductive layer is configured to receive a fixed signal, and when an operating temperature exceeds a preset temperature, the threshold voltage compensation conductive layer is configured to compensate for a threshold voltage of the first transistor.

Description

An array substrate and a display device Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to an array substrate and a display device. Background Technology

[0002] With the rapid development of display technology, display devices are increasingly moving towards higher integration and lower cost. Among them, GOA (Gate Driver on Array) technology integrates the TFT (Thin Film Transistor) gate driving circuit on the array substrate of the display device to form a scanning drive for the display device.

[0003] Summary of the Invention

[0004] This disclosure provides an array substrate and a display device, the specific solutions of which are as follows:

[0005] An array substrate provided in this disclosure includes a display area and a non-display area. The non-display area includes a GOA region, which includes multiple cascaded GOA units and a forward scan voltage line. Each GOA unit includes a forward input module. The forward input module includes a first transistor located on the substrate. The first terminal of the first transistor is electrically connected to the forward input terminal, the second terminal of the first transistor is electrically connected to the forward scan voltage line, and the third terminal of the first transistor is electrically connected to a pull-up node.

[0006] The GOA region also includes a threshold voltage compensation conductive layer located on the side of the first transistor away from the substrate. The orthographic projection of the threshold voltage compensation conductive layer on the substrate at least partially overlaps with the orthographic projection of the channel region of the first transistor on the substrate. The threshold voltage compensation conductive layer is configured to receive a fixed signal. When the operating temperature exceeds a preset temperature, the threshold voltage compensation conductive layer is configured to compensate for the threshold voltage of the first transistor.

[0007] In one possible implementation, in the array substrate provided in the embodiments of this disclosure, the orthographic projection of the threshold voltage compensation conductive layer on the substrate coincides with the orthographic projection of the first electrode of the first transistor on the substrate.

[0008] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the display area comprises: a gate metal layer on the substrate, a gate insulating layer on a side of the gate metal layer away from the substrate, an active layer on a side of the gate insulating layer away from the substrate, a first transparent electrode layer in the same film layer as the active layer, a source-drain metal layer on a side of the active layer and the first transparent electrode layer away from the substrate, a passivation layer on a side of the source-drain metal layer away from the substrate, and a second transparent electrode layer on a side of the passivation layer away from the substrate; wherein,

[0009] The threshold voltage compensation conductive layer is provided in the same layer and with the same material as the second transparent electrode layer, or the material of the threshold voltage compensation conductive layer is metal, and the threshold voltage compensation conductive layer is in the same film layer as the second transparent electrode layer.

[0010] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the GOA area further comprises a reverse scanning voltage line, a frame reset control line, a first power supply line, and a plurality of scanning signal output lines, and the GOA unit further comprises a frame reset module and a reverse input module, the frame reset module is electrically connected with the frame reset control line, the first power supply line, the pull-up node, and the corresponding scanning signal output line respectively, and the reverse input module comprises a second transistor on the substrate, the first electrode of the second transistor is electrically connected with a reverse input end, the second electrode of the second transistor is electrically connected with the reverse scanning voltage line, and the third electrode of the second transistor is electrically connected with the pull-up node.

[0011] The cascade direction of the GOA unit is a first direction, and a direction intersecting the first direction is a second direction; the GOA area further comprises a plurality of cascade signal lines extending along the first direction, each of the cascade signal lines is electrically connected with the corresponding scanning signal output line, and each of the cascade signal lines is configured to be coupled with two GOA units.

[0012] The first power supply line is configured to provide a low-level signal, the reverse scanning voltage line is configured to provide a low-level signal in a forward scanning stage, the frame reset control line is configured to provide a low-level signal in a frame scanning time, and a part of the frame reset control line in a blanking time period between adjacent two frame scanning times is configured to provide a high-level signal.

[0013] The threshold voltage compensation conductive layer is electrically connected with the frame reset control line, the first power supply line, the cascade signal line, or the reverse scanning voltage line.

[0014] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the frame reset control line extends along the first direction, the frame reset control line is located between the first transistor and the output module in the second direction, and the frame reset control line is arranged in the same layer and of the same material as the gate metal layer.

[0015] The GOA region further includes a first connection line in one body structure with the threshold voltage compensation conductive layer, a projection of the first connection line on the substrate substrate at least partially overlaps a projection of the frame reset control line on the substrate substrate, and the first connection line is electrically connected with the frame reset control line through a via hole penetrating the passivation layer and the gate insulating layer.

[0016] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the first power supply line includes a first sub-power supply line extending along the first direction and a second sub-power supply line extending along the second direction, the first sub-power supply line is arranged in the same layer and of the same material as the gate metal layer, the second sub-power supply line is arranged in the same layer and of the same material as the source-drain metal layer, the first sub-power supply line is located on a side of the GOA unit away from the display area, and the second sub-power supply line is located between adjacent GOA units.

[0017] A first end of the second sub-power supply line is electrically connected with the first sub-power supply line, and a second end of the second sub-power supply line extends to a side adjacent to the threshold voltage compensation conductive layer.

[0018] The GOA region further includes a first connection part arranged in the same layer and of the same material as the source-drain metal layer and electrically connected with the second end of the second sub-power supply line, and the first connection part extends to a side of the threshold voltage compensation conductive layer.

[0019] The GOA region further includes a second connection line in one body structure with the threshold voltage compensation conductive layer, a projection of the second connection line on the substrate substrate at least partially overlaps a projection of the first connection part on the substrate substrate, and the second connection line is electrically connected with the first connection part through a via hole penetrating the passivation layer.

[0020] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the reverse scan voltage line extends along the first direction and is located between the reverse input module and the display area, the reverse scan voltage line is arranged in the same layer and of the same material as the gate metal layer, a second pole of the second transistor is electrically connected with the reverse scan voltage line through a second connection part, and the second connection part is arranged in the same layer and of the same material as the second transparent electrode layer.

[0021] The GOA region further comprises a third connection line electrically connecting the threshold voltage compensation conductive layer and the second connection part.

[0022] In a possible implementation, in the array substrate provided by the embodiments of the present disclosure, the forward input end of the GOA unit of the first stage is electrically connected with a first frame trigger signal line, and the forward input end of the GOA unit of the second stage is electrically connected with a second frame trigger signal line; the scan signal output line electrically connected with the GOA unit of the Mth stage is electrically connected with the forward input end of the GOA unit of the M+2th stage through a cascade signal line, and the scan signal output line electrically connected with the GOA unit of the M+2th stage is electrically connected with the reverse input end of the GOA unit of the Mth stage through a cascade signal line, and M is a positive integer.

[0023] The first transistor and the second transistor in each GOA unit are respectively electrically connected with a cascade signal line, and three cascade signal lines are arranged between the first transistor and the second transistor in each GOA unit, and the threshold voltage compensation conductive layer is electrically connected with any cascade signal line in the corresponding GOA unit.

[0024] In a possible implementation, in the array substrate provided by the embodiments of the present disclosure, the scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer; the scan signal output line electrically connected with each GOA unit is electrically connected with the corresponding cascade signal line through a third connection part, and the third connection part is arranged in the same layer and of the same material as the second transparent electrode layer.

[0025] The GOA region further comprises a fourth connection line electrically connecting the threshold voltage compensation conductive layer and the third connection part.

[0026] In a possible implementation, in the array substrate provided by the embodiments of the present disclosure, the scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer.

[0027] The GOA region further comprises a fifth connection line which is an integral structure with the threshold voltage compensation conductive layer, and the fifth connection line is electrically connected with the cascade signal line between the first transistor and the second transistor and closest to the first transistor.

[0028] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the cascade signal line closest to the first transistor is electrically connected to the fourth connection part on the side of the first transistor, the fourth connection part is arranged in the same layer and of the same material as the gate metal layer, the fifth connection line is electrically connected to the fifth connection part, the fifth connection part is an integral structure with the fifth connection line, the orthographic projection of the fifth connection part on the substrate is overlapped with the orthographic projection of the fourth connection part on the substrate, and the fifth connection part is electrically connected to the fourth connection part through the via hole penetrating the passivation layer and the gate insulating layer.

[0029] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer.

[0030] The GOA region further includes a sixth connection line which is an integral structure with the threshold voltage compensation conductive layer, and the sixth connection line is electrically connected between the cascade signal line electrically connected to the first transistor and the scan signal output line through the via hole penetrating the passivation layer and the gate insulating layer.

[0031] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer.

[0032] The GOA region further includes a seventh connection line which is an integral structure with the threshold voltage compensation conductive layer, and the seventh connection line is electrically connected to the cascade signal line located between the first transistor and the second transistor and closest to the second transistor through the via hole penetrating the passivation layer and the gate insulating layer.

[0033] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer.

[0034] The GOA region further includes an eighth connection line which is an integral structure with the threshold voltage compensation conductive layer, and the eighth connection line is electrically connected between the cascade signal line electrically connected to the second transistor and the scan signal output line through the via hole penetrating the passivation layer and the gate insulating layer.

[0035] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the forward scanning voltage line extends along the cascade direction of the GOA unit, and the GOA region further includes a frame reset control line extending along the cascade direction of the GOA unit, and a second power supply line located between the forward scanning voltage line and the frame reset control line.

[0036] The second power supply line is configured to provide a low-level signal, and the threshold voltage compensation conductive layer is electrically connected with the second power supply line.

[0037] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the second power supply line is arranged in the same layer and of the same material as the gate metal layer, and the GOA region further includes a ninth connection line in one-piece structure with the threshold voltage compensation conductive layer, a normal projection of the ninth connection line on the substrate substrate at least partially overlaps a normal projection of the second power supply line on the substrate substrate, and the ninth connection line is electrically connected with the second power supply line through a via hole penetrating the passivation layer and the gate insulating layer.

[0038] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the non-display region further includes a binding region, the binding region and the GOA region are located on adjacent sides of the display region, the binding region includes a driving chip, the driving chip includes a plurality of input pads, and a part of the input pads close to the GOA region are respectively electrically connected with the forward scanning voltage line, the second power supply line and the frame reset control line of the GOA region through GOA traces, and the GOA trace electrically connected with the second power supply line is located between the GOA trace electrically connected with the forward scanning voltage line and the GOA trace electrically connected with the frame reset control line.

[0039] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the frame reset module includes a third transistor and a fourth transistor, the first electrode of the third transistor and the fourth transistor is electrically connected with the frame reset control line, the second electrode of the third transistor and the fourth transistor is electrically connected with the first power supply line, the third electrode of the third transistor is electrically connected with the pull-up node, and the third electrode of the fourth transistor is electrically connected with a scanning signal output end.

[0040] In a possible implementation, in the array substrate provided by the embodiment of the present disclosure, the GOA unit further includes a node control module and an output module; wherein,

[0041] The node control module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the first pole and the second pole of the fifth transistor are electrically connected with a third power supply line, the third pole of the fifth transistor is electrically connected with the first pole of the sixth transistor and the second pole of the seventh transistor; the second pole of the sixth transistor is electrically connected with the third power supply line, and the third pole of the sixth transistor is electrically connected with a pull-down node; the first pole of the seventh transistor is electrically connected with the pull-up node, and the third pole of the seventh transistor is electrically connected with the first power supply line; the first pole of the eighth transistor is electrically connected with the pull-up node, the second pole of the eighth transistor is electrically connected with the pull-down node, and the third pole of the eighth transistor is electrically connected with the first power supply line; the first pole of the ninth transistor is electrically connected with the pull-down node, the second pole of the ninth transistor is electrically connected with the pull-up node, and the third pole of the ninth transistor is electrically connected with the first power supply line; the first pole of the tenth transistor is electrically connected with the pull-down node, the second pole of the tenth transistor is electrically connected with a scan signal output end, and the third pole of the tenth transistor is electrically connected with the first power supply line;

[0042] The output module comprises an eleventh transistor and a capacitor, the first pole of the eleventh transistor is electrically connected with the pull-up node, the second pole of the eleventh transistor is electrically connected with a clock signal end, and the third pole of the eleventh transistor is electrically connected with the scan signal output end.

[0043] In a possible implementation, in the array substrate provided in the embodiments of the present disclosure, the first transistor to the eleventh transistor are all N-type transistors.

[0044] Correspondingly, the embodiments of the present disclosure further provide a display device comprising the array substrate provided in the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0045] FIG. 1 is a simplified double-scan GOA unit circuit diagram provided in the embodiments of the present disclosure;

[0046] FIG. 2 is a measurement waveform diagram of the potential of a pull-up node PU when display is normal and the potential of the pull-up node PU after 85°C reliability is raised;

[0047] FIG. 3 is a plane schematic diagram of an array substrate provided in the embodiments of the present disclosure;

[0048] FIG. 4 is a specific structure schematic diagram of a GOA region in FIG. 3;

[0049] FIG. 5 is a specific circuit schematic diagram of a GOA unit in FIG. 4;

[0050] Fig. 6 is a layout diagram of the GOA unit shown in Fig. 5;

[0051] Fig. 7 is a partial cross-sectional structure diagram of the display region shown in Fig. 3;

[0052] Fig. 8 is a timing diagram of the GOA unit shown in Fig. 5;

[0053] Fig. 9 is a cross-sectional diagram along the CC' direction of Fig. 6;

[0054] Fig. 10 is another layout diagram of the GOA unit shown in Fig. 5;

[0055] Fig. 11 is a cross-sectional diagram along the CC' direction of Fig. 10;

[0056] Fig. 12 is another layout diagram of the GOA unit shown in Fig. 5;

[0057] Fig. 13 is a cross-sectional diagram along the CC' direction of Fig. 12;

[0058] Fig. 14 is another layout diagram of the GOA unit shown in Fig. 5;

[0059] Fig. 15 is a cross-sectional diagram along the CC' direction of Fig. 14;

[0060] Fig. 16 is another layout diagram of the GOA unit shown in Fig. 5;

[0061] Fig. 17 is another layout diagram of the GOA unit shown in Fig. 5;

[0062] Fig. 18 is another layout diagram of the GOA unit shown in Fig. 5;

[0063] Fig. 19 is another layout diagram of the GOA unit shown in Fig. 5;

[0064] Fig. 20 is another planar diagram of an array substrate according to an embodiment of the present disclosure;

[0065] Fig. 21 is a layout diagram of a GOA unit of the GOA region shown in Fig. 20. DETAILED DESCRIPTION

[0066] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. And the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort fall within the scope of protection of the present disclosure.

[0067] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "comprise" or "include" and similar words in the present disclosure mean that the elements or objects before the word encompass the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The terms "connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "in", "out", "upper", "lower" and the like are only used to indicate relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0068] It should be noted that the sizes and shapes of the figures in the drawings do not reflect the true proportions, but only serve to illustrate the present disclosure. And the same or similar reference signs represent the same or similar elements or elements with the same or similar functions throughout.

[0069] The GOA circuit generally includes a plurality of cascaded GOA units, and the scan signal output end of each GOA unit is electrically connected one-to-one with the gate line of the display area. Each GOA unit inputs the scan signal to each gate line row by row through timing control. At present, the GOA circuit generally supports bidirectional scanning mode of forward and reverse scanning, that is, the scan signal can be input row by row from the first row of GOA units to the last row of GOA units, or the gate signal can be input row by row from the last row of GOA units to the first row of GOA units. As shown in FIG. 1, FIG. 1 is a simplified double-scan GOA unit circuit diagram, in which the first transistor M1 is a forward input module, the second transistor M2 is a reverse input module, the third transistor M3 is an output module, and the fourth transistor M4 is a frame reset module. The types of all transistors are N-type; when the scan signal output end OUTPUT of the current row does not output the scan signal, the forward scanning voltage line VDS is connected to a high voltage signal, and the forward input end INPUT is connected to a low voltage signal. If the characteristics of the first transistor M1 are normal, that is, the drain current I offSmall, the high voltage of the forward scanning voltage line VDS is difficult to leak to the pull-up node PU through the first transistor M1 to raise the potential of the pull-up node PU. For products with a customer requirement of 85°C operating temperature, 85°C reliability testing is performed in the factory. High-temperature reliability testing generally uses the forward scanning mode of the GOA circuit, but due to the serious drift of TFT characteristics at high temperature, the scan signal output end OUTPUT is misoutput, and the jitter horizontal stripe defect occurs. The root cause of the jitter horizontal stripe defect is the negative drift of the threshold voltage Vth of the first transistor M1 during high-temperature reliability, as shown in Table 1, which is the measured data of the negative drift of the threshold voltage Vth of the first transistor M1 of a 2-inch display product before and after 85°C reliability. The leakage current I off Increases, the forward scanning voltage line VDS leaks through the first transistor M1 to the pull-up node PU, raising the potential of the pull-up node PU, as shown in FIG. 2, which is a measured waveform graph of the potential of the pull-up node PU when the display is normal and the potential of the pull-up node PU after 85°C reliability. This causes the scan signal output end OUTPUT to misoutput, resulting in noise, and over time, the GOA circuit outputs Multi, resulting in a jitter horizontal stripe defect.

[0070] Table 1

[0071] To solve the problem of Multi output of the GOA circuit after high-temperature reliability testing and the jitter horizontal stripe defect, the present embodiment provides an array substrate, as shown in FIG. 3, which is a plan view of the array substrate, including a display area AA and a non-display area BB, the non-display area BB including GOA areas (GOA1 and GOA2); as shown in FIG. 4, which is a specific structure diagram of a GOA area in FIG. 3, the GOA area (GOA1 and GOA2) including multiple cascaded GOA units (GOA_1, GOA_2, GOA_3…) and a forward scanning voltage line VDS; as shown in FIG. 5 and FIG. 6, FIG. 5 is a specific circuit diagram of a GOA unit in FIG. 4, and FIG. 6 is a layout diagram of the GOA unit shown in FIG. 5, each GOA unit includes a forward input module 10, the forward input module 10 including a first transistor M1 on a substrate 1, the first electrode of the first transistor M1 being electrically connected to the forward input end INPUT, the second electrode of the first transistor M1 being electrically connected to the forward scanning voltage line VDS, and the third electrode of the first transistor M1 being electrically connected to the pull-up node PU;

[0072] The GOA region (GOA1 and GOA2) further comprises a threshold voltage compensation conductive layer 2 located on the side of the first transistor M1 away from the substrate substrate 1, a normal projection of the threshold voltage compensation conductive layer 2 on the substrate substrate 1 at least partially overlaps with a normal projection of a channel region of the first transistor M1 on the substrate substrate 1, and the threshold voltage compensation conductive layer 2 is configured to access a fixed signal; when the working temperature exceeds a preset temperature, the threshold voltage compensation conductive layer 2 is configured to compensate the threshold voltage Vth of the first transistor M1.

[0073] The inventors of the present case found through experimental data that applying a negative voltage above the N-type transistor can cause the threshold voltage of the N-type transistor to positively drift. Therefore, the above-mentioned array substrate provided by the embodiments of the present disclosure sets a threshold voltage compensation conductive layer on the side of the first transistor away from the substrate substrate, and the threshold voltage compensation conductive layer accesses a fixed signal, which can be a signal with a low voltage time ratio of more than 99% in a frame time. In this way, the threshold voltage compensation conductive layer above the first transistor has a negative voltage signal, which in turn causes the threshold voltage of the first transistor to positively drift, thereby neutralizing the negative drift of the first transistor during the high-temperature reliability process, and improving the phenomenon of picture jitter horizontal stripe defects caused by the negative drift of the threshold voltage of the first transistor during the high-temperature reliability process.

[0074] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, as shown in FIG. 6, a normal projection of the threshold voltage compensation conductive layer 2 on the substrate substrate 1 coincides with a normal projection of the first electrode G of the first transistor M1 on the substrate substrate 1. In this way, a layer of threshold voltage compensation conductive layer 2 is covered above the first transistor M1, and the pattern size of the threshold voltage compensation conductive layer 2 is approximately the same as the pattern size of the first electrode G of the first transistor M1. As shown in Table 2 below, the threshold voltage Vth data of the first transistor M1 when different voltages (No. 1 and No. 2) are applied to the threshold voltage compensation conductive layer 2 of the present disclosure, and the threshold voltage Vth data of the first transistor M1 when no threshold voltage compensation conductive layer 2 is set in the prior art (No. 3), it can be seen that the threshold voltage Vth of the first transistor M1 with the threshold voltage compensation conductive layer 2 set above it positively drifts compared to when no threshold voltage compensation conductive layer 2 is set. Therefore, the threshold voltage compensation conductive layer 2 can neutralize the negative drift of the first transistor M1 during the high-temperature reliability process.

[0075] Table 2

[0076] Specifically, the first electrode G of the first transistor M1 is a gate electrode.

[0077] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 3, FIG. 6 and FIG. 7, FIG. 7 is a schematic diagram of a partial cross-sectional structure of the display area AA in FIG. 3, the display area AA includes: the gate metal layer 3 on the substrate 1, the gate insulating layer 4 on the side of the gate metal layer 3 away from the substrate 1, the active layer 5 on the side of the gate insulating layer 4 away from the substrate 1, the first transparent electrode layer 6 in the same film layer as the active layer 5, the source-drain metal layer 7 on the side of the active layer 5 and the first transparent electrode layer 6 away from the substrate 1, the passivation layer 8 on the side of the source-drain metal layer 7 away from the substrate 1, and the second transparent electrode layer 9 on the side of the passivation layer 8 away from the substrate 1; the embodiments of the present disclosure take the pixel structure process as the conventional 6mask product process, that is, Gate→GI→Active→1ITO→SD→PVX→2ITO, the first transparent electrode layer 6 (1ITO) is the pixel electrode layer, the first transparent electrode layer 6 (1ITO) can include the pixel electrode of each sub-pixel in the display area AA, the second transparent electrode layer 9 (2ITO) is the common electrode layer, and the common electrode layer can be a planar structure; wherein, the active layer 5 and the first transparent electrode layer 6 are in the same film layer, but two mask processes are needed.

[0078] It should be noted that the pixel structure process of the embodiments of the present disclosure is not limited to the 6mask product process.

[0079] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 6 and FIG. 7, the threshold voltage compensation conductive layer 2 can be arranged in the same layer and with the same material as the second transparent electrode layer 9, so that the pattern of the threshold voltage compensation conductive layer 2 and the second transparent electrode layer 9 can be formed by one patterning process by changing the original patterning pattern when the second transparent electrode layer 9 is formed, without increasing the process of separately preparing the threshold voltage compensation conductive layer 2, so that the preparation process flow can be simplified, the production cost can be saved, the production efficiency can be improved, and the product function does not need to be sacrificed or the product frame does not need to be increased.

[0080] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 6, the material of the threshold voltage compensation conductive layer 2 can also be metal, and the threshold voltage compensation conductive layer 2 is in the same film layer as the second transparent electrode layer 9 in FIG. 7. In the specific manufacturing, for example, after the second transparent electrode layer 9, a layer of photoresist can be coated, a photoresist pattern can be formed by exposure and development, the orthogonal projection of the photoresist pattern on the substrate 1 does not overlap with the orthogonal projection of the first electrode G of the first transistor M1 on the substrate 1, then a layer of metal is deposited, the photoresist pattern is stripped, and the threshold voltage compensation conductive layer 2 is formed above the first transistor M1.

[0081] It should be noted that the above is to compensate the conductive layer 2 with the threshold voltage of the metal material, which is made after the second transparent electrode layer 9, and of course can be made before the second transparent electrode layer 9, which is not limited here.

[0082] It should be noted that the threshold voltage compensation conductive layer 2 of the metal material and the second transparent electrode layer 9 are in the same film layer, that is, the threshold voltage compensation conductive layer 2 of the metal material and the second transparent electrode layer 9 are made by different masks, but they are in the same layer in the film layer position.

[0083] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 3-6, the GOA area (GOA1 and GOA2) further includes a reverse scan voltage line VSD, a frame reset control line STV0, a first power line VGL1, and a plurality of scan signal output lines (OUT1, OUT2, OUT3…), and the GOA unit (for example, GOA_3) further includes a frame reset module 20 and a reverse input module 30. The frame reset module 20 is electrically connected with the frame reset control line STV0, the first power line VGL1, a pull-up node PU, and a corresponding scan signal output line OUT1 respectively. The reverse input module 30 includes a second transistor M2 on the substrate 1. The first electrode of the second transistor M2 is electrically connected with a reverse input end RESET. The second electrode of the second transistor M2 is electrically connected with the reverse scan voltage line VSD. The third electrode of the second transistor M2 is electrically connected with the pull-up node PU.

[0084] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 5 and 6, the frame reset module 20 includes a third transistor M3 and a fourth transistor M4. The first electrodes of the third transistor M3 and the fourth transistor M4 are electrically connected with the frame reset control line STV0. The second electrodes of the third transistor M3 and the fourth transistor M4 are electrically connected with the first power line VGL1. The third electrode of the third transistor M3 is electrically connected with the pull-up node PU. The third electrode of the fourth transistor M4 is electrically connected with a scan signal output end OUTPUT. The scan signal output end OUTPUT is electrically connected with a corresponding scan signal output line OUT1.

[0085] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 5 and 6, the GOA unit (for example, GOA_3) further includes a node control module 40 and an output module 50; wherein,

[0086] The node control module 40 comprises a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10; the first electrode and the second electrode of the fifth transistor M5 are electrically connected with the third power supply line GCH, the third electrode of the fifth transistor M5 is electrically connected with the first electrode of the sixth transistor M6 and the second electrode of the seventh transistor M7; the second electrode of the sixth transistor M6 is electrically connected with the third power supply line GCH, and the third electrode of the sixth transistor M6 is electrically connected with the pull-down node PD; the first electrode of the seventh transistor M7 is electrically connected with the pull-up node PU, and the third electrode of the seventh transistor M7 is electrically connected with the first power supply line VGL1; the first electrode of the eighth transistor M8 is electrically connected with the pull-up node PU, the second electrode of the eighth transistor M8 is electrically connected with the pull-down node PD, and the third electrode of the eighth transistor M8 is electrically connected with the first power supply line VGL1; the first electrode of the ninth transistor M9 is electrically connected with the pull-down node PD, the second electrode of the ninth transistor M9 is electrically connected with the pull-up node PU, and the third electrode of the ninth transistor M9 is electrically connected with the first power supply line VGL1; the first electrode of the tenth transistor M10 is electrically connected with the pull-down node PD, the second electrode of the tenth transistor M10 is electrically connected with the scan signal output end OUTPUT, and the third electrode of the tenth transistor M10 is electrically connected with the first power supply line VGL1.

[0087] The output module 50 comprises an eleventh transistor M11 and a capacitor C, the first electrode of the eleventh transistor M11 is electrically connected with the pull-up node PU, the second electrode of the eleventh transistor M11 is electrically connected with the clock signal end CLK, the clock signal end CLK is electrically connected with a corresponding clock signal line (for example, CLK1, CLK2, CLK3, CLK4), and the third electrode of the eleventh transistor M11 is electrically connected with the scan signal output end OUTPUT.

[0088] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 3-6, the cascade direction of the GOA units (GOA_1, GOA_2, GOA_3…) is the first direction Y, and the direction intersecting the first direction Y is the second direction X; the GOA region (GOA1 and GOA2) further comprises a plurality of cascade signal lines (for example, OUT_1, OUT_2, OUT_3, OUT_4, OUT_5) extending along the first direction Y, each cascade signal line is electrically connected with a corresponding scan signal output line (OUT1, OUT2, OUT3…), and each cascade signal line is configured to be coupled with two GOA units.

[0089] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIGS. 4-6, the forward input end INPUT of the first-stage GOA unit (GOA_1) is configured to be electrically connected with the first frame trigger signal line STV1, and the forward input end INPUT of the second-stage GOA unit (GOA_2) is configured to be electrically connected with the second frame trigger signal line STV2; the scan signal output line electrically connected with the Mth-stage GOA unit is configured to be electrically connected with the forward input end INPUT of the M+2th-stage GOA unit through a cascade signal line, and the scan signal output line OUT3 electrically connected with the M+2th-stage GOA unit is configured to be electrically connected with the reverse input end RESET of the Mth-stage GOA unit through a cascade signal line, where M is a positive integer; for example, the scan signal output line OUT1 electrically connected with GOA_1 is electrically connected with the forward input end INPUT of GOA_3 through a cascade signal line, and the scan signal output line OUT3 electrically connected with GOA_3 is electrically connected with the reverse input end RESET of GOA_1 through a cascade signal line OUT_3; for example, the scan signal output line OUT2 electrically connected with GOA_2 is electrically connected with the forward input end INPUT of GOA_4 through a cascade signal line, and the scan signal output line OUT4 electrically connected with GOA_4 is electrically connected with the reverse input end RESET of GOA_2 through a cascade signal line; for example, the scan signal output line OUT3 electrically connected with GOA_3 is electrically connected with the forward input end INPUT of GOA_5 through a cascade signal line, and the scan signal output line OUT5 electrically connected with GOA_5 is electrically connected with the reverse input end RESET of GOA_3 through a cascade signal line; and the like.

[0090] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 6, the first transistor M1 and the second transistor M2 in each stage of GOA units (for example, GOA_3) are respectively electrically connected with a cascade signal line; for example, the first pole of the first transistor M1 electrically connected with the forward input end INPUT is electrically connected with the cascade signal line OUT_1, and the first pole of the second transistor M2 electrically connected with the reverse input end RESET is electrically connected with the cascade signal line OUT_5; and three cascade signal lines (OUT_2, OUT_3, OUT_4) are arranged between the first transistor M1 and the second transistor M2 in each stage of GOA units (for example, GOA_3). The arrangement of the five cascade signal lines can realize the cascade relationship shown in FIGS. 4 and 6.

[0091] The above is only an example of the specific structure of each module in the GOA unit provided by the embodiments of the present disclosure, and in the specific implementation, the specific structure of each module is not limited to the above structure provided by the embodiments of the present disclosure, but can also be other structures known to those skilled in the art, which are not limited herein.

[0092] In order to simplify the preparation process, in specific implementation, in the embodiments of the present disclosure, as shown in FIG. 5, the first transistor M1 to the eleventh transistor M11 are all N-type transistors, which are turned on under the action of high voltage and turned off under the action of low voltage.

[0093] Specifically, as shown in FIG. 5 and FIG. 6, the first electrode of each transistor is the gate electrode (G), the second electrode of each transistor can be the source electrode (S), and the third electrode of each transistor can be the drain electrode (D), or the first electrode of each transistor is the gate electrode (G), the second electrode of each transistor can be the drain electrode (D), and the third electrode of each transistor can be the source electrode (S).

[0094] As shown in FIG. 8, which is a working timing diagram of the GOA unit shown in FIG. 5, the forward scanning voltage line VDS is configured to provide a high-level signal in the positive scanning stage, the first power supply line VGL1 is configured to provide a low-level signal, and the reverse scanning voltage line VSD is configured to provide a low-level signal in the positive scanning stage; the frame reset control line STV0 is configured to provide a low-level signal in the frame scanning time, and the part of the frame reset control line STV0 in the blank time period (Blank Time) between adjacent two frame scanning times is configured to provide a high-level signal; the scanning signal output line (OUT1, OUT2, OUT3…) is a high-level signal in the corresponding row output time, and remains a low-level signal at other times. Taking the product with 1920 rows of gate lines and 8 CLKs in the display area AA as an example, in a frame time (16.7 ms), the high-level time of STV0, OUT1, OUT2, OUT3… is 34.7 us, the proportion of the high-level time is 0.21%, and the proportion of the low-level time is 99.79%, that is, the frame reset control line STV0, OUT1, OUT2, OUT3… maintains a low-level signal for most of the time in a frame time. Through the timing shown in FIG. 8, the output of each stage of GOA unit can be realized.

[0095] In the following, the embodiments of the present disclosure take the example that the threshold voltage compensation conductive layer 2 can be arranged in the same layer and with the same material as the second transparent electrode layer 9 shown in FIG. 7, and the specific embodiments of the threshold voltage compensation conductive layer 2 connected to the fixed signal are described in detail.

[0096] In some embodiments, in the above array substrate provided by the embodiments of the present disclosure, as shown in FIG. 6, the threshold voltage compensation conductive layer 2 can be electrically connected with the frame reset control line STV0, so that the threshold voltage compensation conductive layer 2 is connected to a low-level signal for most of the time in a frame time, that is, the threshold voltage compensation conductive layer 2 has a negative voltage signal, and then the threshold voltage of the first transistor M1 is positively shifted, so as to neutralize the negative shift degree of the first transistor M1 in the high-temperature reliability process, thereby improving the phenomenon of picture jitter horizontal stripe defects caused by the negative shift of the threshold voltage of the first transistor M1 in the high-temperature reliability process.

[0097] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 3, FIG. 6, FIG. 7 and FIG. 9, FIG. 9 is a schematic cross-sectional view of FIG. 6 along the direction of CC', the frame reset control line STV0 extends along the first direction Y, the frame reset control line STV0 is located between the first transistor M1 and the output module 50 along the second direction X, and the frame reset control line STV0 is arranged in the same layer and of the same material as the gate metal layer 3.

[0098] The GOA area (GOA1 and GOA2) further comprises a first connection line 101 which is in an integral structure with the threshold voltage compensation conductive layer 2, a normal projection of the first connection line 101 on the substrate 1 at least partially overlaps a normal projection of the frame reset control line STV0 on the substrate 1, and the first connection line 101 is electrically connected with the frame reset control line STV0 through a via (V1) penetrating the passivation layer 8 and the gate insulating layer 4.

[0099] Optionally, as shown in FIG. 6, the embodiments of the present disclosure take the example that the first connection line 101 is connected to the frame reset control line STV0 on the right side from the lower side of the threshold voltage compensation conductive layer 2, but of course it is not limited thereto, for example, the first connection line 101 can also be connected to the frame reset control line STV0 on the right side from the right side of the threshold voltage compensation conductive layer 2, as long as the first connection line 101 does not short-circuit with other signal lines.

[0100] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 10, which is another layout schematic diagram of the GOA unit shown in FIG. 5, the threshold voltage compensation conductive layer 2 can be electrically connected with the first power line VGL1, so that the threshold voltage compensation conductive layer 2 is connected with a low-level signal in a frame time, that is, the threshold voltage compensation conductive layer 2 has a negative voltage signal, thereby making the threshold voltage of the first transistor M1 positively drift, so as to neutralize the negative drift degree of the first transistor M1 in the high-temperature reliability process, thereby improving the phenomenon of picture jitter horizontal stripe defects caused by the negative drift of the threshold voltage of the first transistor M1 in the high-temperature reliability process.

[0101] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 3, FIG. 7, FIG. 10 and FIG. 11, FIG. 11 is a schematic cross-sectional view of FIG. 10 along the direction of CC', the first power line VGL1 comprises a first sub-power line VGL11 extending along the first direction Y and a second sub-power line VGL12 extending along the second direction X, the first sub-power line VGL11 is arranged in the same layer and of the same material as the gate metal layer 3, the second sub-power line VGL12 is arranged in the same layer and of the same material as the source / drain metal layer 7, the first sub-power line VGL11 is located on the side of the GOA unit away from the display area AA, and the second sub-power line VGL12 is located between adjacent GOA units.

[0102] The first end of the second sub power line VGL12 is electrically connected with the first sub power line VGL11, and the second end of the second sub power line VGL12 extends to a side adjacent to the threshold voltage compensation conductive layer 2;

[0103] The GOA region (GOA1 and GOA2) further comprises a first connecting part 201 which is arranged in the same layer and of the same material as the source-drain metal layer 7 and is electrically connected with the second end of the second sub power line VGL2, and the first connecting part 201 extends to a side of the threshold voltage compensation conductive layer 2;

[0104] The GOA region (GOA1 and GOA2) further comprises a second connecting line 102 which is an integral structure with the threshold voltage compensation conductive layer 2, and the orthographic projection of the second connecting line 102 on the substrate 1 at least partially overlaps the orthographic projection of the first connecting part 201 on the substrate 1, and the second connecting line 102 is electrically connected with the first connecting part 201 through a via (V2) penetrating the passivation layer 8.

[0105] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 12, which is another layout schematic diagram of the GOA unit shown in FIG. 5, the threshold voltage compensation conductive layer 2 can be electrically connected with the reverse scanning voltage line VSD, so that the threshold voltage compensation conductive layer 2 accesses a low-level signal in a frame time, that is, the threshold voltage compensation conductive layer 2 carries a negative voltage signal, thereby causing the threshold voltage of the first transistor M1 to positively drift, so as to neutralize the negative drift degree of the first transistor M1 in the high-temperature reliability process, thereby improving the phenomenon of picture jitter horizontal stripe defects caused by the negative drift of the threshold voltage of the first transistor M1 in the high-temperature reliability process.

[0106] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 12 and FIG. 13, which is a cross-sectional schematic diagram along the CC' direction in FIG. 12, the reverse scanning voltage line VSD extends along the first direction Y and is located between the reverse input module 30 and the display region AA, the reverse scanning voltage line VSD is arranged in the same layer and of the same material as the gate metal layer 3, the second electrode of the second transistor M2 is electrically connected with the reverse scanning voltage line VSD through a second connecting part 202, and the second connecting part 202 is arranged in the same layer and of the same material as the second transparent electrode layer 9;

[0107] The GOA region further comprises a third connecting line 103 which electrically connects the threshold voltage compensation conductive layer 2 and the second connecting part 202.

[0108] Specifically, as shown in FIGS. 12 and 13, the second electrode of the second transistor M2 is electrically connected with the first structure 301, the first structure 301 is arranged in the same layer and of the same material as the source-drain metal layer 7, the reverse scanning voltage line VSD is electrically connected with the second structure 302, the second structure 302 is arranged in the same layer and of the same material as the gate metal layer 3, the second connecting part 202 is electrically connected with the first structure 301 through a via (V3) penetrating the passivation layer 8, the second connecting part 202 is electrically connected with the second structure 302 through a via (V4) penetrating the passivation layer 8 and the gate insulating layer 4, and the threshold voltage compensation conductive layer 2, the third connecting line 103 and the second connecting part 202 can be an integrated structure.

[0109] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 14-19, FIGS. 14, 16-19 are another layout schematic diagram of the GOA unit shown in FIG. 5, the threshold voltage compensation conductive layer 2 can be electrically connected with any stage of the cascaded signal line (OUT_1, OUT_2, OUT_3, OUT_4, OUT_5) in the corresponding GOA unit; in this way, the threshold voltage compensation conductive layer 2 is connected with the low-level signal in most of the time within a frame time, that is, the threshold voltage compensation conductive layer 2 carries the negative voltage signal, and then the threshold voltage of the first transistor M1 is positively shifted, so as to neutralize the negative shift degree of the threshold voltage of the first transistor M1 in the high-temperature reliability process, thereby improving the phenomenon of picture jitter horizontal stripe defects caused by the negative shift of the threshold voltage of the first transistor M1 in the high-temperature reliability process.

[0110] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIGS. 14 and 15, FIG. 15 is a cross-sectional schematic diagram along the direction CC' in FIG. 14, the scanning signal output line (for example, OUT3) is arranged in the same layer and of the same material as the source-drain metal layer 7, the cascaded signal line OUT_3 is arranged in the same layer and of the same material as the gate metal layer 3, and the scanning signal output line (for example, OUT3) electrically connected with each stage of the GOA unit is electrically connected with the corresponding cascaded signal line OUT_3 through the third connecting part 203, and the third connecting part 203 is arranged in the same layer and of the same material as the second transparent electrode layer 9.

[0111] The GOA region further includes a fourth connecting line 104 electrically connecting the threshold voltage compensation conductive layer 2 and the third connecting part 203.

[0112] Specifically, as shown in FIGS. 14 and 15, the scan signal output line OUT3 is electrically connected with the third structure 303, the third structure 303 is arranged in the same layer and of the same material as the source-drain metal layer 7, the cascade signal line OUT_3 is electrically connected with the fourth structure 304, the fourth structure 304 is arranged in the same layer and of the same material as the gate metal layer 3, the reverse input end RESET in the GOA_1 is electrically connected with the scan signal output line OUT3 of the GOA_3 through the cascade signal line OUT_5, the cascade signal line OUT_5 is electrically connected with the fifth structure 305 at a position close to the scan signal output line OUT3, the fifth structure 305 is arranged in the same layer and of the same material as the gate metal layer 3, the third connection part 203 is electrically connected with the third structure 303 through the via (V5) penetrating the passivation layer 8, the third connection part 203 is electrically connected with the fourth structure 304 through the via (V6) penetrating the passivation layer 8 and the gate insulating layer 4, the third connection part 203 is electrically connected with the fifth structure 305 through the via (V7) penetrating the passivation layer 8 and the gate insulating layer 4, and the threshold voltage compensation conductive layer 2, the fourth connection line 104 and the third connection part 203 can be an integrated structure.

[0113] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 16, the scan signal output line (for example, OUT3) is arranged in the same layer and of the same material as the source-drain metal layer 7, and the cascade signal line OUT_3 is arranged in the same layer and of the same material as the gate metal layer 3.

[0114] The GOA region further comprises a fifth connection line 105 which is an integrated structure with the threshold voltage compensation conductive layer 2, and the fifth connection line 105 is electrically connected with the cascade signal line (OUT_2) located between the first transistor M1 and the second transistor M2 and closest to the first transistor M1.

[0115] Specifically, as shown in FIG. 16, one side of the cascade signal line (OUT_2) close to the first transistor M1 is electrically connected with the fourth connection part 204, the fourth connection part 204 is arranged in the same layer and of the same material as the gate metal layer 3, the fifth connection line 105 is electrically connected with the fifth connection part 205, the fifth connection part 205 is an integrated structure with the fifth connection line 105, and the fifth connection part 205 is electrically connected with the fourth connection part 204 through the via (V8) penetrating the passivation layer 8 and the gate insulating layer 4.

[0116] Optionally, as shown in FIG. 16, the embodiments of the present disclosure take the example that the fifth connection line 105 is connected to the left cascade signal line (OUT_2) from the lower side of the threshold voltage compensation conductive layer 2, but of course it is not limited thereto, for example, the fifth connection line 105 can also be connected to the left cascade signal line (OUT_2) from the left side of the threshold voltage compensation conductive layer 2, as long as the fifth connection line 105 does not short circuit with other signal lines.

[0117] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 17, the scan signal output line (for example, OUT3) is arranged in the same layer and of the same material as the source-drain metal layer 7, and the cascade signal line OUT_3 is arranged in the same layer and of the same material as the gate metal layer 3.

[0118] The GOA region further comprises a sixth connection line 106 which is an integral structure with the threshold voltage compensation conductive layer 2, and the sixth connection line 106 is electrically connected to the cascade signal line (OUT_1) between the first transistor M1 through a via (V9) penetrating the passivation layer 8 and the gate insulating layer 4.

[0119] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 18, the scan signal output line (for example, OUT3) is arranged in the same layer and of the same material as the source-drain metal layer 7, and the cascade signal line OUT_3 is arranged in the same layer and of the same material as the gate metal layer 3.

[0120] The GOA region further comprises a seventh connection line 107 which is an integral structure with the threshold voltage compensation conductive layer 2, and the seventh connection line 107 is electrically connected to the cascade signal line (OUT_4) between the first transistor M1 and the second transistor M2 and closest to the second transistor M2 through a via (V10) penetrating the passivation layer 8 and the gate insulating layer 4.

[0121] Optionally, as shown in FIG. 18, the embodiments of the present disclosure are taken as an example that the seventh connection line 107 is connected to the left cascade signal line (OUT_4) from the lower side of the threshold voltage compensation conductive layer 2, of course, not limited thereto, for example, the seventh connection line 107 can also be connected to the left cascade signal line (OUT_4) from the left side of the threshold voltage compensation conductive layer 2, as long as the seventh connection line 107 does not short circuit with other signal lines.

[0122] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 19, the scan signal output line (for example, OUT3) is arranged in the same layer and of the same material as the source-drain metal layer 7, and the cascade signal line OUT_3 is arranged in the same layer and of the same material as the gate metal layer 3.

[0123] The GOA region further comprises an eighth connection line 108 which is an integral structure with the threshold voltage compensation conductive layer 2, and the eighth connection line 108 is electrically connected to the cascade signal line (OUT_5) electrically connected to the second transistor M2 through a via V11 penetrating the passivation layer 8 and the gate insulating layer 4.

[0124] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 20 and FIG. 21, FIG. 20 is another plan view of the array substrate, and FIG. 21 is a layout view of one GOA unit (for example, GOA_3) in the GOA region shown in FIG. 20, the forward scanning voltage line VDS extends along the cascade direction (Y) of the GOA unit, and the GOA region further includes: a frame reset control line STV0 extending along the cascade direction (Y) of the GOA unit, and a second power supply line VGL2 located between the forward scanning voltage line VDS and the frame reset control line STV0;

[0125] The second power supply line VGL2 is configured to provide a low-level signal, and the threshold voltage compensation conductive layer 2 is electrically connected with the second power supply line VGL2. In this way, the threshold voltage compensation conductive layer 2 accesses a low-level signal in a frame time, that is, the threshold voltage compensation conductive layer 2 has a negative voltage signal, thereby causing the threshold voltage of the first transistor M1 to positively drift, thereby neutralizing the negative drift degree of the first transistor M1 in the high-temperature reliability process, thereby improving the phenomenon of picture jitter horizontal stripe defects caused by the negative drift of the threshold voltage of the first transistor M1 in the high-temperature reliability process.

[0126] In some embodiments, in the array substrate provided in the embodiments of the present disclosure, as shown in FIG. 7 and FIG. 21, the second power supply line VGL2 is arranged in the same layer and the same material as the gate metal layer 3, and the GOA region further includes a ninth connection line 109 which is an integral structure with the threshold voltage compensation conductive layer 2. The orthographic projection of the ninth connection line 109 on the substrate 1 at least partially overlaps the orthographic projection of the second power supply line VGL2 on the substrate 1, and the ninth connection line 109 is electrically connected with the second power supply line VGL2 through a via (V12) penetrating the passivation layer 8 and the gate insulating layer 4.

[0127] Optionally, as shown in FIG. 21, the ninth connection line 109 is connected to the second power supply line VGL2 on the right side from the lower right corner of the threshold voltage compensation conductive layer 2, but is not limited thereto. For example, the ninth connection line 109 can also be connected to the second power supply line VGL2 on the right side from the right side of the threshold voltage compensation conductive layer 2, as long as the ninth connection line 109 does not short-circuit with other signal lines.

[0128] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, as shown in FIG. 20, the non-display area BB further includes a binding area BD, the binding area BD and the GOA area are located at the adjacent side of the display area AA, for example, two GOA areas are respectively located at the left and right side frames, and the binding area BD is located at the lower side frame. The binding area BD includes a driving chip IC, the driving chip IC includes a plurality of input pads 100, and the part of the input pads 100 close to the GOA area are respectively electrically connected with the forward scanning voltage line VDS, the second power supply line VGL2 and the frame reset control line STV0 of the GOA area through the GOA traces 200. The GOA trace 200 electrically connected with the second power supply line VGL2 is located between the GOA traces 200 electrically connected with the forward scanning voltage line VDS and the frame reset control line STV0. In this way, the embodiments of the present disclosure additionally increase a second power supply line VGL2 between the forward scanning voltage line VDS and the frame reset control line STV0 of the GOA area, and additionally increase a new GOA trace 200 electrically connected with the second power supply line VGL2 from the driving chip IC.

[0129] It should be noted that the label STV0 (200) in FIG. 20 means that the GOA trace 200 is electrically connected with the STV0 of the GOA area, the label VGL2 (200) means that the GOA trace 200 is electrically connected with the VGL2 of the GOA area, and the label VDS (200) means that the GOA trace 200 is electrically connected with the VDS of the GOA area.

[0130] Optionally, the second power supply line VGL2 is not limited to being arranged between the forward scanning voltage line VDS and the frame reset control line STV0, and the second power supply line VGL2 can also be arranged between, for example, OUT_5 and OUT_4, OUT_4 and Out_3, OUT_3 and OUT_2, etc.

[0131] It should be noted that the embodiments of the present disclosure select the 11T1C GOA unit which is more stable in signal transmission. Of course, the GOA unit can not be limited to the 11T1C structure provided by the embodiments of the present disclosure, and can be other GOA units which can realize the shift function and have the frame reset function, such as 7T2C, 8T1C, 10T1C, 17T1C, 19T1C, 21T1C, etc.

[0132] In some embodiments, the first transistor to the eleventh transistor can also be P-type transistors, which are turned on under low voltage and turned off under high voltage; correspondingly, the threshold voltage compensation conductive layer can be configured to access a high voltage signal.

[0133] In conclusion, the embodiment of the present disclosure improves the high-temperature dithering horizontal line defect of the GOA product without increasing the cost, the product frame or sacrificing the product function, and improves the service life of the display product.

[0134] Based on the same inventive concept, the embodiment of the present disclosure also provides a display device including the array substrate provided by the embodiment of the present disclosure. Since the principle of solving the problem of the display device is similar to that of the array substrate, the implementation of the display device provided by the embodiment of the present disclosure can be referred to the implementation of the array substrate, and the repeated parts will not be described here.

[0135] In the implementation, the display device provided by the embodiment of the present disclosure can be an LCD (Liquid Crystal Display) display device, for example, an ADS (Advanced Super Dimension Switch) type liquid crystal display device, and can also be an OLED display device using the GOA technology.

[0136] In the implementation, the display device provided by the embodiment of the present disclosure can be a full-screen display device or a flexible display device, which is not limited here.

[0137] In the implementation, the display device provided by the embodiment of the present disclosure can be a mobile phone, a projector, a 3D printer, a virtual reality device, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device should be understood by those skilled in the art, and will not be described here, and should not be considered as a limitation of the present disclosure. The display device includes but is not limited to a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply, and the like. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiment of the present disclosure, in other words, the display device provided by the embodiment of the present disclosure can include more or less components, or combine some components, or different component arrangements.

[0138] The array substrate and the display device provided by the embodiments of the present disclosure can improve the phenomenon of picture jitter horizontal stripe defects caused by the negative shift of the threshold voltage of the first transistor in the high-temperature reliability process. The array substrate and the display device provided by the embodiments of the present disclosure can improve the phenomenon of picture jitter horizontal stripe defects caused by the negative shift of the threshold voltage of the first transistor in the high-temperature reliability process.

[0139] Although the preferred embodiments of the present disclosure have been described, those skilled in the art who know the basic inventive concept can make additional changes and modifications to the embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0140] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The display region and the non-display region include a GOA region, the GOA region includes a plurality of cascaded GOA units, and a forward scan voltage line, each of the GOA units includes a forward input module, the forward input module includes a first transistor on a substrate, a first electrode of the first transistor is electrically connected with a forward input end, a second electrode of the first transistor is electrically connected with the forward scan voltage line, and a third electrode of the first transistor is electrically connected with a pull-up node; The GOA region further includes a threshold voltage compensation conductive layer on a side of the first transistor away from the substrate, a normal projection of the threshold voltage compensation conductive layer on the substrate at least partially overlaps with a normal projection of a channel region of the first transistor on the substrate, and the threshold voltage compensation conductive layer is configured to access a fixed signal; When the working temperature exceeds a preset temperature, the threshold voltage compensation conductive layer is configured to compensate the threshold voltage of the first transistor.

2. The array substrate of claim 1, wherein, The normal projection of the threshold voltage compensation conductive layer on the substrate coincides with the normal projection of the first electrode of the first transistor on the substrate.

3. The array substrate of claim 2, wherein, The display region includes a gate metal layer on the substrate, a gate insulating layer on a side of the gate metal layer away from the substrate, an active layer on a side of the gate insulating layer away from the substrate, a first transparent electrode layer in the same film layer as the active layer, a source-drain metal layer on a side of the active layer and the first transparent electrode layer away from the substrate, a passivation layer on a side of the source-drain metal layer away from the substrate, and a second transparent electrode layer on a side of the passivation layer away from the substrate; wherein The threshold voltage compensation conductive layer is provided in the same layer and with the same material as the second transparent electrode layer, or the material of the threshold voltage compensation conductive layer is metal, and the threshold voltage compensation conductive layer is in the same film layer as the second transparent electrode layer.

4. The array substrate of claim 3, wherein, The GOA region further includes a reverse scan voltage line, a frame reset control line, a first power supply line, and a plurality of scan signal output lines, the GOA unit further includes a frame reset module and a reverse input module, the frame reset module is electrically connected with the frame reset control line, the first power supply line, the pull-up node, and the corresponding scan signal output line, respectively, and the reverse input module includes a second transistor on the substrate, a first electrode of the second transistor is electrically connected with a reverse input end, a second electrode of the second transistor is electrically connected with the reverse scan voltage line, and a third electrode of the second transistor is electrically connected with the pull-up node; The cascading direction of the GOA unit is a first direction, a direction intersecting with the first direction is a second direction, the GOA region further includes a plurality of cascaded signal lines extending along the first direction, each of the cascaded signal lines is electrically connected with the corresponding scan signal output line, and each of the cascaded signal lines is configured to couple two GOA units. The first power line is configured to provide a low-level signal, the reverse scanning voltage line is configured to provide a low-level signal in a positive scanning stage, a part of the frame reset control line in a blanking time period between two adjacent frame scanning time periods is configured to provide a high-level signal, and the rest of the frame reset control line is configured to provide a low-level signal; The threshold voltage compensation conductive layer is electrically connected with the frame reset control line, the first power line, the cascade signal line, or the reverse scanning voltage line.

5. The array substrate of claim 4, wherein, The frame reset control line extends in the first direction and is located between the first transistor and the output module in the second direction, and the frame reset control line is arranged in the same layer and of the same material as the gate metal layer. The GOA region further comprises a first connection line in one body structure with the threshold voltage compensation conductive layer, a projection of the first connection line on the substrate substrate at least partially overlaps a projection of the frame reset control line on the substrate substrate, and the first connection line is electrically connected with the frame reset control line through a via hole penetrating the passivation layer and the gate insulation layer.

6. The array substrate of claim 4, wherein, The first power line comprises a first sub-power line extending in the first direction and a second sub-power line extending in the second direction, the first sub-power line is arranged in the same layer and of the same material as the gate metal layer, the second sub-power line is arranged in the same layer and of the same material as the source-drain metal layer, the first sub-power line is located on the side of the GOA unit away from the display area, and the second sub-power line is located between adjacent GOA units. A first end of the second sub-power line is electrically connected with the first sub-power line, and a second end of the second sub-power line extends to a side adjacent to the threshold voltage compensation conductive layer. The GOA region further comprises a first connection part arranged in the same layer and of the same material as the source-drain metal layer and electrically connected with the second end of the second sub-power line, and the first connection part extends to a side of the threshold voltage compensation conductive layer. The GOA region further comprises a second connection line in one body structure with the threshold voltage compensation conductive layer, a projection of the second connection line on the substrate substrate at least partially overlaps a projection of the first connection part on the substrate substrate, and the second connection line is electrically connected with the first connection part through a via hole penetrating the passivation layer.

7. The array substrate of claim 4, wherein, The reverse scanning voltage line extends in the first direction and is located between the reverse input module and the display area, the reverse scanning voltage line is arranged in the same layer and of the same material as the gate metal layer, a second pole of the second transistor is electrically connected with the reverse scanning voltage line through a second connection part, and the second connection part is arranged in the same layer and of the same material as the second transparent electrode layer. The GOA region further comprises a third connection line electrically connecting the threshold voltage compensation conductive layer and the second connection part.

8. The array substrate of claim 4, wherein, The forward input end of the GOA unit of the first stage is electrically connected with a first frame trigger signal line, and the forward input end of the GOA unit of the second stage is electrically connected with a second frame trigger signal line; the scan signal output line electrically connected with the GOA unit of the Mth stage is electrically connected with the forward input end of the GOA unit of the M+2th stage through a cascade signal line, and the scan signal output line electrically connected with the GOA unit of the M+2th stage is electrically connected with the reverse input end of the GOA unit of the Mth stage through a cascade signal line, wherein M is a positive integer; The first transistor and the second transistor in each stage of the GOA unit are respectively electrically connected with a cascade signal line, and three cascade signal lines are arranged between the first transistor and the second transistor in each stage of the GOA unit, and the threshold voltage compensation conductive layer is electrically connected with Any cascade signal line in the corresponding GOA unit is electrically connected.

9. The array substrate of claim 8, wherein, The scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, the cascade signal line is arranged in the same layer and of the same material as the gate metal layer, the scan signal output line electrically connected with each stage of the GOA unit is electrically connected with the corresponding cascade signal line through a third connecting part, and the third connecting part is arranged in the same layer and of the same material as the second transparent electrode layer; The GOA region further comprises a fourth connecting line electrically connecting the threshold voltage compensation conductive layer and the third connecting part.

10. The array substrate of claim 8, wherein, The scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer; The GOA region further comprises a fifth connecting line which is an integral structure with the threshold voltage compensation conductive layer, and the fifth connecting line is electrically connected with the cascade signal line located between the first transistor and the second transistor and closest to the first transistor.

11. The array substrate of claim 10, wherein, The side of the cascade signal line closest to the first transistor is electrically connected with a fourth connecting part, the fourth connecting part is arranged in the same layer and of the same material as the gate metal layer, the fifth connecting line is electrically connected with a fifth connecting part which is an integral structure with the fifth connecting line, the orthogonal projection of the fifth connecting part on the substrate is overlapped with the orthogonal projection of the fourth connecting part on the substrate, and the fifth connecting part is electrically connected with the fourth connecting part through a via hole penetrating the passivation layer and the gate insulating layer.

12. The array substrate of claim 8, wherein, The scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer; The GOA region further comprises a sixth connecting line which is an integral structure with the threshold voltage compensation conductive layer, and the sixth connecting line is electrically connected with the cascade signal line electrically connected with the first transistor through a via hole penetrating the passivation layer and the gate insulating layer.

13. The array substrate of claim 8, wherein, The scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer; The GOA area further comprises a seventh connection line in an integral structure with the threshold voltage compensation conductive layer, and the seventh connection line is electrically connected with the cascade signal line between the first transistor and the second transistor and closest to the second transistor through a via hole penetrating the passivation layer and the gate insulating layer.

14. The array substrate of claim 8, wherein, The scan signal output line is arranged in the same layer and of the same material as the source-drain metal layer, and the cascade signal line is arranged in the same layer and of the same material as the gate metal layer. The GOA area further comprises an eighth connection line in an integral structure with the threshold voltage compensation conductive layer, and the eighth connection line is electrically connected between the cascade signal line electrically connected with the second transistor through a via hole penetrating the passivation layer and the gate insulating layer.

15. The array substrate of claim 3, wherein, The forward scan voltage line extends in the cascade direction of the GOA unit, and the GOA area further comprises a frame reset control line extending in the cascade direction of the GOA unit, and a second power supply line between the forward scan voltage line and the frame reset control line. The second power supply line is configured to provide a low-level signal, and the threshold voltage compensation conductive layer is electrically connected with the second power supply line.

16. The array substrate of claim 15, wherein, The second power supply line is arranged in the same layer and of the same material as the gate metal layer, and the GOA area further comprises a ninth connection line in an integral structure with the threshold voltage compensation conductive layer, and a projection of the ninth connection line on the substrate substrate at least partially overlaps a projection of the second power supply line on the substrate substrate, and the ninth connection line is electrically connected with the second power supply line through a via hole penetrating the passivation layer and the gate insulating layer.

17. The array substrate of claim 16, wherein, The non-display area further comprises a binding area, and the binding area and the GOA area are located on adjacent sides of the display area, and the binding area comprises a driving chip, the driving chip comprises a plurality of input pads, and a part of the input pads close to the GOA area in the plurality of input pads are respectively electrically connected with the forward scan voltage line, the second power supply line and the frame reset control line of the GOA area through GOA traces, and the GOA trace electrically connected with the second power supply line is located between the GOA trace electrically connected with the forward scan voltage line and the GOA trace electrically connected with the frame reset control line.

18. The array substrate of claim 4, wherein, The frame reset module comprises a third transistor and a fourth transistor, the first electrode of the third transistor and the fourth transistor is electrically connected with the frame reset control line, the second electrode of the third transistor and the fourth transistor is electrically connected with the first power supply line, the third electrode of the third transistor is electrically connected with the pull-up node, and the third electrode of the fourth transistor is electrically connected with a scan signal output end.

19. The array substrate of claim 18, wherein, The GOA unit further comprises a node control module and an output module; wherein, The node control module comprises a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; the first pole and the second pole of the fifth transistor are electrically connected with a third power supply line, the third pole of the fifth transistor is electrically connected with the first pole of the sixth transistor and the second pole of the seventh transistor; the second pole of the sixth transistor is electrically connected with the third power supply line, and the third pole of the sixth transistor is electrically connected with a pull-down node; the first pole of the seventh transistor is electrically connected with the pull-up node, and the third pole of the seventh transistor is electrically connected with the first power supply line; the first pole of the eighth transistor is electrically connected with the pull-up node, the second pole of the eighth transistor is electrically connected with the pull-down node, and the third pole of the eighth transistor is electrically connected with the first power supply line; the first pole of the ninth transistor is electrically connected with the pull-down node, the second pole of the ninth transistor is electrically connected with the pull-up node, and the third pole of the ninth transistor is electrically connected with the first power supply line; the first pole of the tenth transistor is electrically connected with the pull-down node, the second pole of the tenth transistor is electrically connected with a scan signal output end, and the third pole of the tenth transistor is electrically connected with the first power supply line; The output module comprises an eleventh transistor and a capacitor, the first pole of the eleventh transistor is electrically connected with the pull-up node, the second pole of the eleventh transistor is electrically connected with a clock signal end, and the third pole of the eleventh transistor is electrically connected with the scan signal output end.

20. The array substrate of claim 19, wherein, The first transistor to the eleventh transistor are N-type transistors.

21. A display device, wherein, An array substrate comprising any one of claims 1-20.

Images