Array substrate, display panel, and display apparatus

Abstract

The present disclosure provides an array substrate, a display panel, and a display apparatus. The array substrate comprises: a base substrate, the base substrate comprising a plurality of bright pixel areas and a plurality of dark pixel areas arranged in an array, the bright pixel areas and the dark pixel areas each comprising a plurality of sub-pixel areas, and each sub-pixel area comprising a plurality of domain areas; a plurality of pixel electrodes, which overlap the plurality of sub-pixel areas, each pixel electrode comprising a first middle portion extending in a row direction between the plurality of domain areas, and a first edge portion and a second edge portion extending in a column direction on two sides of the plurality of domain areas; a plurality of light-shielding structures, the plurality of light-shielding structures at least overlapping the plurality of bright pixel areas, and the orthographic projections of the plurality of light-shielding structures on the base substrate overlapping the orthographic projections of the first middle portions, the first edge portions, and the second edge portions in at least some of the sub-pixel areas of the bright pixel areas on the base substrate.

Description

Array substrate, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate, a display panel and a display device. BACKGROUND

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small volume, low power consumption, high picture quality, no radiation and convenient carrying, and has been rapidly developed in recent years, and has gradually replaced the traditional Cathode Ray Tube display (CRT) and occupies a dominant position in the current flat panel display market. At present, TFT-LCD has been widely used in various large, medium and small size products, and almost covers the main electronic products in today's information society, such as liquid crystal televisions, high-definition digital televisions, computers (desktop and notebook), mobile phones, tablet computers, navigation instruments, vehicle-mounted displays, projection displays, video cameras, digital cameras, electronic watches, calculators, electronic instruments, instruments, public displays and virtual reality displays, etc.

[0003] SUMMARY

[0004] The array substrate, the display panel and the display device provided by the present disclosure have the following specific solutions.

[0005] In one aspect, the present disclosure provides an array substrate, comprising:

[0006] A substrate, the substrate comprising a plurality of bright pixel regions and a plurality of dark pixel regions arranged in an array, the bright pixel regions and the dark pixel regions each comprising a plurality of sub-pixel regions, the sub-pixel regions comprising a plurality of domain regions;

[0007] A plurality of pixel electrodes, the plurality of pixel electrodes and the plurality of sub-pixel regions being mutually overlapped, the pixel electrodes comprising a first intermediate portion extending in a row direction between the plurality of domain regions, and a first edge portion and a second edge portion extending in a column direction on both sides of the plurality of domain regions;

[0008] A plurality of light shielding structures, the plurality of light shielding structures being at least mutually overlapped with the plurality of bright pixel regions, a projection of the plurality of light shielding structures on the substrate being mutually overlapped with a projection of at least part of the sub-pixel regions of the bright pixel regions on the substrate, the projection of the first intermediate portion, the first edge portion and the second edge portion.

[0009] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the orthogonal projection of the plurality of light-shielding structures on the substrate substrate and the orthogonal projection of the first intermediate portion, the first edge portion and the second edge portion in the plurality of sub-pixel regions of the plurality of bright pixel regions on the substrate substrate overlap with each other.

[0010] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a gate line is further included.

[0011] The portion of the first edge portion vertically overlapping with the light-shielding structure extends away from the gate line from the first intermediate portion; and the portion of the second edge portion vertically overlapping with the light-shielding structure extends toward the gate line from the first intermediate portion.

[0012] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a gate line, a discharge line and a first transistor are further included, the gate of the first transistor is electrically connected with the gate line, the first pole of the first transistor is electrically connected with the pixel electrode of the dark pixel region, and the second pole of the first transistor is electrically connected with the discharge line.

[0013] The first pole of the first transistor includes a first portion extending in the column direction and a second portion located at both ends of the first portion, wherein the orthogonal projection of the first portion on the substrate substrate is located within the orthogonal projection of the gate line on the substrate substrate, the orthogonal projection of the second portion on the substrate substrate partially overlaps with the orthogonal projection of the gate line on the substrate substrate, and the line width of the first portion in the row direction is smaller than the line width of the second portion in the row direction.

[0014] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, a data line, a second transistor and a third transistor are further included, wherein

[0015] The gate of the second transistor is electrically connected with the gate line, the first pole of the second transistor is electrically connected with the data line, and the second pole of the second transistor is electrically connected with the pixel electrode of the bright pixel region.

[0016] The gate of the third transistor is multiplexed with the gate of the second transistor, the first pole of the third transistor is multiplexed with the first pole of the second transistor, and the second pole of the third transistor is electrically connected with the pixel electrode of the dark pixel region.

[0017] The line width of the first pole of the second transistor in the direction perpendicular to the extension direction thereof is greater than the line width of the first portion in the row direction and substantially equal to the line width of the second portion in the row direction.

[0018] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the line width of at least part of the first electrode of the first transistor along the row direction is different from the line width of the second electrode of the first transistor along the row direction, and the second electrode of the first transistor is shared with the discharge line.

[0019] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the array substrate further comprises an electrode pattern and a first common electrode line, the electrode pattern is electrically connected with the pixel electrode of the dark pixel area, and the orthogonal projection of the electrode pattern on the substrate substrate and the orthogonal projection of the first common electrode line on the substrate substrate overlap with each other.

[0020] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the array substrate further comprises a discharge line and a first transistor, the first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the second electrode of the first transistor is electrically connected with the discharge line.

[0021] The orthogonal projection of the first common electrode line on the substrate substrate and the orthogonal projection of the first electrode of the first transistor on the substrate substrate overlap with each other, and the overlapping area of the orthogonal projection of the first common electrode line and the first electrode of the first transistor and the overlapping area of the orthogonal projection of the first common electrode line and the electrode pattern are arranged side by side along the row direction.

[0022] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the array substrate further comprises a data line, a discharge line, a first transistor and a third transistor; wherein,

[0023] The first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the second electrode of the first transistor is electrically connected with the discharge line.

[0024] The first electrode of the third transistor is electrically connected with the data line, and the second electrode of the third transistor is integrally arranged with the first electrode of the first transistor.

[0025] The pixel electrode further comprises a second intermediate portion extending along the column direction between the plurality of domain areas, and the orthogonal projection of the active layer of the first transistor on the substrate substrate is located on the side of the extended line of the orthogonal projection of the second intermediate portion on the substrate substrate away from the data line.

[0026] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the array substrate further comprises a discharge line and a first transistor, the first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the second electrode of the first transistor is electrically connected with the discharge line.

[0027] The pixel electrode further includes a second intermediate portion extending in the column direction between the plurality of domain regions, a projection extension line of the second intermediate portion on the substrate substrate penetrates a projection of the active layer of the first transistor on the substrate substrate.

[0028] In some embodiments, the array substrate provided by the embodiments of the present disclosure further includes a discharge line.

[0029] The pixel electrode further includes a second intermediate portion extending in the column direction between the plurality of domain regions, a projection of the second intermediate portion on the substrate substrate and a projection of the discharge line on the substrate substrate overlap each other.

[0030] In some embodiments, the array substrate provided by the embodiments of the present disclosure further includes a second common electrode line, a projection of the second common electrode line on the substrate substrate and a projection of the pixel electrode of the bright pixel region on the substrate substrate overlap each other, and the light shielding structure is integrally arranged with the second common electrode line.

[0031] In some embodiments, the array substrate provided by the embodiments of the present disclosure further includes a gate line, a data line, a discharge line, a third common electrode line and a first transistor; wherein,

[0032] The first pole of the first transistor is electrically connected with the pixel electrode of the dark pixel region, and the second pole of the first transistor is electrically connected with the discharge line;

[0033] A projection of the data line on the substrate substrate and a projection of the third common electrode line on the substrate substrate overlap each other;

[0034] A projection of an edge of the gate line close to a side of the bright pixel region on the substrate substrate and a projection of the third common electrode line on the substrate substrate overlap each other;

[0035] A projection of a part of the edge of the gate line close to the dark pixel region and located on a side of the discharge line away from the first transistor on the substrate substrate and a projection of the third common electrode line on the substrate substrate overlap each other.

[0036] In another aspect, the embodiments of the present disclosure provide a display panel, including the array substrate provided by the embodiments of the present disclosure, and an opposite substrate opposite to the array substrate.

[0037] In some embodiments, the display panel provided by the embodiments of the present disclosure further includes a common electrode.

[0038] In another aspect, the display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure, and a backlight module located at the light-in side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0039] FIG. 1 is a light efficiency simulation diagram of a 4-domain display;

[0040] FIG. 2 is a structure diagram of one pixel in an array substrate provided by the embodiments of the present disclosure;

[0041] FIG. 3 is a structure diagram of a layer where a gate line is located in FIG. 2;

[0042] FIG. 4 is a structure diagram of an active layer in FIG. 2;

[0043] FIG. 5 is a structure diagram of a layer where a data line is located in FIG. 2;

[0044] FIG. 6 is a structure diagram of a layer where a via is located in FIG. 2;

[0045] FIG. 7 is a structure diagram of a layer where a pixel electrode is located in FIG. 2;

[0046] FIG. 8 is a simulation diagram of a pixel voltage and an optimal common voltage in the related art;

[0047] FIG. 9 is another structure diagram of one pixel provided by the embodiments of the present disclosure;

[0048] FIG. 10 is an enlarged structure diagram of a Z1 region in FIG. 9;

[0049] FIG. 11 is an enlarged structure diagram of a Z2 region in FIG. 10;

[0050] FIG. 12 is a cross-sectional structure diagram along I-I' in FIG. 9;

[0051] FIG. 13 is a cross-sectional structure diagram along II-II' in FIG. 9;

[0052] FIG. 14 is a structure diagram of a layer where a data line is located in FIG. 9;

[0053] FIG. 15 is a structure diagram of a layer where a via is located in FIG. 9;

[0054] FIG. 16 is a simulation diagram of a pixel voltage and an optimal common voltage in the embodiment shown in FIG. 9;

[0055] FIG. 17 is another simulation diagram of a pixel voltage and an optimal common voltage in the embodiment shown in FIG. 9;

[0056] FIG. 18 is another structure diagram of one pixel provided by the embodiments of the present disclosure;

[0057] FIG. 19 is an enlarged structure diagram of a Z3 region in FIG. 18;

[0058] FIG. 20 is a structural schematic diagram of a layer where the gate line in FIG. 18 is located;

[0059] FIG. 21 is a structural schematic diagram of an active layer in FIG. 18;

[0060] FIG. 22 is a structural schematic diagram of a layer where the data line in FIG. 18 is located;

[0061] FIG. 23 is a structural schematic diagram of a layer where the via in FIG. 18 is located;

[0062] FIG. 24 is a structural schematic diagram of a layer where the pixel electrode in FIG. 18 is located;

[0063] FIG. 25 is a structural schematic diagram of a cross section along III-III' in FIG. 9;

[0064] FIG. 26 is a simulation diagram of a pixel voltage and an optimal common voltage of the embodiment shown in FIG. 18;

[0065] FIG. 27 is a structural schematic diagram of a display panel provided by an embodiment of the present disclosure;

[0066] FIG. 28 is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] To make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It should be noted that, in the drawings, the thicknesses of layers, films, panels, regions and the like are exaggerated for clarity. In the present disclosure, the exemplary embodiments are described with reference to cross-sectional views that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described in the present disclosure are not to be construed as being limited to the particular shapes of regions as illustrated in the present disclosure but are to include deviations in shapes that result from, for example, manufacturing. For example, an area illustrated or described as flat can typically have rough and / or nonlinear features; an illustrated sharp angle can be rounded, etc. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region and do not reflect true scales and are merely intended to schematically illustrate the disclosures. And like or similar designations refer to like or similar elements or elements with like or similar functions throughout the whole disclosure. In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of known functions and known components.

[0068] Unless otherwise defined, technical terms or scientific terms used herein shall have the same meaning to people with ordinary skills in the art to which this disclosure belongs. The terms "first", "second", and similar terms used in the description and the claims of this disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms "comprising", "including", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connected" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "In", "out", "up", "down", and the like are only used to represent relative positional relationships, which can change accordingly when the absolute position of the described object changes.

[0069] In the following description, when an element or layer is referred to as "on" or "connected to" another element or layer, the element or layer can be directly on the other element or layer, directly connected to the other element or layer, or there can be an intermediate element or intermediate layer. When an element or layer is referred to as "provided on one side of another element or layer", the element or layer can be directly on one side of the other element or layer, directly connected to the other element or layer, or there can be an intermediate element or intermediate layer. However, when an element or layer is referred to as "directly on" another element or layer, "directly connected to" another element or layer, there is no intermediate element or intermediate layer. The term "and / or" includes any and all combinations of one or more related listed items.

[0070] Multi-domain display can be divided into different areas within a sub-pixel, and the deflection of liquid crystal molecules in different areas is different. When viewing the liquid crystal display screen from different normal viewing angles (e.g. 0°-30°), the comprehensive effect of the deflection of liquid crystal in each area is seen, thereby reducing the contrast difference at different angles caused by the same deflection of all liquid crystals in a sub-pixel, and further reducing the normal viewing angle deviation.

[0071] In some embodiments, the 4-domain display scheme shown in FIG. 1 can be taken to cooperate with bright and dark to achieve 8 domains to improve the normal viewing angle deviation, specifically by adjusting the brightness ratio of the upper 4 domains and the lower 4 domains to make the normal viewing angle deviation effect better, wherein the pixel with higher brightness is called bright pixel, and the pixel with lower brightness is called dark pixel. However, the pre-tilt angle of liquid crystal molecules in different domain areas is different, so that dark lines will be formed in the area where the orientation of liquid crystal molecules is disordered. When viewed from different side viewing angles (e.g. 30°-90°), the liquid crystal transmittance observed is inconsistent, and therefore, there is still a color deviation problem at the side viewing angle.

[0072] To improve the side view character bias problem, the array substrate provided by the embodiment of the present disclosure, as shown in FIG. 2, which is a structural schematic diagram of a pixel in the array substrate, FIG. 3 is a structural schematic diagram of the layer where the gate line is located in FIG. 2, FIG. 4 is a structural schematic diagram of the active layer in FIG. 2, FIG. 5 is a structural schematic diagram of the layer where the data line is located in FIG. 2, FIG. 6 is a structural schematic diagram of the layer where the via is located in FIG. 2, and FIG. 7 is a structural schematic diagram of the layer where the pixel electrode is located in FIG. 2. As shown in FIGS. 2 to 7, the array substrate provided by the embodiment of the present disclosure can include:

[0073] The substrate 101 includes a plurality of bright pixel regions H and a plurality of dark pixel regions L arranged in an array, and the bright pixel regions H and the dark pixel regions L each include a plurality of sub-pixel regions SP, such as a red sub-pixel region R, a green sub-pixel region G, a blue sub-pixel region B, etc., and the sub-pixel region SP includes a plurality of domain regions. Optionally, the sub-pixel region SP includes four domain regions D1-D4, the liquid crystal molecules of the four domain regions D1-D4 can be aligned by an alignment film, and the pixel electrode 102 of the sub-pixel region SP can be a block electrode or a slit electrode, which can be a Chinese character-shaped or a Chinese character-shaped, etc. The drawings of the present disclosure take the block electrode as an example for illustration. The multi-domain in the present case can be realized by different alignment of the alignment film, or by the pixel electrode being provided as a branch electrode (or a slit electrode) extending in different directions, or by the alignment film alignment and the pixel electrode being provided as a branch electrode (or a slit electrode) extending in different directions at the same time to form a multi-domain. Herein, it is not limited, and in some embodiments, the substrate 101 is a substrate allowing visible light to pass through, such as glass, quartz, plastic, etc.

[0074] The plurality of pixel electrodes 102 overlap with the plurality of sub-pixel regions SP, and the pixel electrode 102 includes a first intermediate portion P1 extending between the plurality of domain regions D1-D4 in a row direction X, and a first edge portion P2 and a second edge portion P3 extending on both sides of the plurality of domain regions D1-D4 in a column direction Y; in some embodiments, the material of the pixel electrode 102 includes but is not limited to at least one of indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), and gallium zinc oxide (GZO).

[0075] The plurality of light shielding structures 103 at least partially overlap with the plurality of bright pixel regions H, and the orthogonal projection of the plurality of light shielding structures 103 on the substrate 101 overlaps with the orthogonal projection of the first intermediate portion P1, the first edge portion P2, and the second edge portion P3 in at least part of the sub-pixel region SP of the bright pixel region H on the substrate 101. In some embodiments, the light shielding structure 103 can overlap with the orthogonal projection of the first intermediate portion P1, the first edge portion P2, and the second edge portion P3 in all sub-pixel regions SP of all bright pixel regions H on the substrate 101. Optionally, the light shielding structure 103 is arranged in the same layer and of the same material as the gate line 104, and the material used by the gate line 104 can include metals such as molybdenum (Mo), aluminum (Al), titanium (Ti), chromium (Cr), nickel (Ni), etc. In some embodiments, the layer where the gate line 104 is arranged can be a single-layer structure or a laminated structure. For example, the layer where the gate line 104 is arranged can be a single-layer structure composed of a molybdenum metal layer or a copper metal layer.

[0076] As can be seen from FIGS. 1 and 2, the first intermediate portion P1, the first edge portion P2, and the third edge portion P3 of the pixel electrode P1 have dark lines, and the light shielding structure 103 of the present disclosure is arranged to vertically overlap with the first intermediate portion P1, the first edge portion P2, and the third edge portion P3, which can effectively shield the dark lines, thereby reducing the color deviation difference of different side viewing angles. Moreover, since the picture display is mainly the light transmission of the bright pixel region H, and the dark pixel region L is not transparent at low gray scale, the light shielding structure 103 can be arranged only in the bright pixel region H, but not in the dark pixel region L, so as to effectively improve the side viewing color deviation while reducing the sacrifice of the transmittance as much as possible.

[0077] As can be seen from FIG. 1, the first edge portion P2 is located in the region where the portion of the first intermediate portion P1 away from the gate line 104 has dark lines, and the second edge portion P3 is located in the region where the portion of the first intermediate portion P1 close to the gate line 104 has dark lines. The light shielding structure 103 of the present disclosure can be arranged only in the region with dark lines for shielding. In other words, in the present disclosure, the portion of the first edge portion P2 vertically overlapping with the light shielding structure 103 extends from the first intermediate portion P1 away from the gate line 104, and the portion of the second edge portion P3 vertically overlapping with the light shielding structure 103 extends from the first intermediate portion P1 toward the gate line 104. In this way, the light shielding structure 103 can be located entirely in the dark line region, without affecting the transmittance.

[0078] In some embodiments, as shown in FIGS. 2-7, the pixel electrode 102 of the dark pixel region L can be discharged by a first transistor 106 connected to a discharge line 105, and the pixel electrode 102 of the bright pixel region H can be charged by a second transistor 108 connected to a data line 107, while the pixel electrode 102 of the dark pixel region L is charged by a third transistor 109 connected to the data line 107, so that the bright pixel region H is brighter and the dark pixel region L is darker. The gate g of the first transistor 106 is connected to the gate line 104 (e.g., the gate line 104 is locally reused as the first electrode g of the first transistor 106), the first electrode s of the first transistor 106 is connected to the pixel electrode 102 of the dark pixel region L through a first via V1, and the second electrode d of the first transistor 106 is connected to the discharge line 105 (e.g., the discharge line 105 is locally reused as the second electrode d of the first transistor 106). The gate g of the second transistor 108 is connected to the gate line 104 (e.g., the gate line 104 is locally reused as the first electrode g of the second transistor 108), the first electrode s of the second transistor 108 is connected to the data line 107, and the second electrode d of the second transistor 108 is connected to the pixel electrode 102 of the bright pixel region H through a second via V2. The gate g of the third transistor 109 is reused as the gate g of the second transistor 108, the first electrode s of the third transistor 109 is reused as the first electrode s of the second transistor 108, and the second electrode d of the third transistor 109 is integrally arranged with the first electrode s of the first transistor 106.

[0079] In the above embodiment, the first transistor 106 is used for discharging, which results in a large difference between C gs (the capacitance of the gate and the pixel electrode) of the dark pixel and C gs (the capacitance of the gate and the pixel electrode) of the bright pixel, so that the feed through voltage of the bright pixel and the dark pixel is inconsistent, the feed through voltage = C gs / C total *△V, C total mainly consists of C lc (the liquid crystal capacitance: the capacitance between the pixel electrode and the common electrode CF COM on the counter substrate), C st (the storage capacitance: the capacitance between the common electrode line of the array substrate and the pixel electrode), C gs (the capacitance of the gate and the pixel electrode), and C pd (the capacitance between the pixel electrode and the data line). As shown in FIG. 8, the optimal Vcom of the positive and negative frames of the bright pixel and the optimal Vcom of the dark pixel have a deviation, and there is a difference between the bright and dark frames in actual display, so that a wobble line is generated in display. As known from the above feed through voltage formula, the present disclosure can reduce the C gsand / or increase the C of the dark pixel total to reduce the feed through voltage of the dark pixel, thereby reducing the difference between the positive and negative frame optimal Vcom of the bright and dark pixels to improve the head shake mura.

[0080] In some embodiments, FIG. 9 shows another structure schematic diagram of a pixel provided by the embodiments of the present disclosure, FIG. 10 is an enlarged structure schematic diagram of the Z1 region in FIG. 9, FIG. 11 is an enlarged structure schematic diagram of the Z2 region in FIG. 10, FIG. 12 is a cross-sectional structure schematic diagram along I-I' in FIG. 9, FIG. 13 is a cross-sectional structure schematic diagram along II-II' in FIG. 9, FIG. 14 is a structure schematic diagram of the layer where the data line is located in FIG. 9, and FIG. 15 is a structure schematic diagram of the layer where the via is located in FIG. 9. The structures of other film layers in FIG. 9 can refer to FIGS. 3, 4 and 7. FIG. 16 is a simulation diagram of the pixel voltage and optimal common voltage Vcom corresponding to the reduction of the C of the dark pixel in the embodiment shown in FIG. 9, and FIG. 17 is a simulation diagram of the pixel voltage and optimal common voltage Vcom corresponding to the increase of the C of the dark pixel in the embodiment shown in FIG. 9. total corresponding to the reduction of the C of the dark pixel in the embodiment shown in FIG. 9, and FIG. 17 is a simulation diagram of the pixel voltage and optimal common voltage Vcom corresponding to the increase of the C of the dark pixel in the embodiment shown in FIG. 9.

[0081] In the embodiment shown in FIG. 9, the line width of at least part of the first electrode s of the first transistor 106 along the row direction X is different from the line width of the second electrode s (partly multiplexed with the discharge line 105) of the first transistor 106 along the row direction X. Optionally, the first electrode s of the first transistor 106 includes a first part s1 extending along the column direction Y, and a second part s2 located at both ends of the first part s1, wherein the orthographic projection of the first part s1 on the substrate 101 is located within the orthographic projection of the gate line 104 on the substrate 101, the orthographic projection of the second part s2 on the substrate 101 partially overlaps with the orthographic projection of the gate line 104 on the substrate 101, the line width of the first part s1 along the row direction X is smaller than the line width of the second part s2 along the row direction X, the line width of the second part s2 along the row direction X can be substantially equal to the line width of the first electrode s (multiplexed with the first electrode s of the third transistor 109) of the second transistor 108 in the direction perpendicular to the extension direction thereof, and the line width of the second part s2 along the row direction X can be substantially equal to the line width of the second electrode s (partly multiplexed with the discharge line 105) of the first transistor 106 along the row direction X. Due to the limitation of process conditions or the influence of other factors such as measurement, the "substantially equal" in the present disclosure can be completely equal, or there can be some deviation (for example, ±5% deviation), so as long as the "substantially equal" relationship between the related features meets the error allowance, it belongs to the protection scope of the present disclosure.

[0082] As can be seen, the present disclosure sets the first part s1 in the region of the gate line 104 to be narrower, thereby reducing the C gsThis reduces the feed though voltage of dark pixels and decreases the difference in the optimal common voltage Vcom between bright and dark pixels, thus improving the head-shaking pattern. As shown in Figure 15, the optimal Vcom difference between bright and dark pixels is 0.46V, a reduction of 0.07V, which improves the head-shaking pattern caused by the large difference in the optimal Vcom between bright and dark pixels in positive and negative frames. In addition, compared to the first part s1, the second part s2 at the crossing point is wider, which can effectively prevent line breaks at the crossing point.

[0083] In some embodiments, as shown in Figures 9 and 10, the array substrate provided in this disclosure may further include an electrode pattern 110 and a first common electrode line 111. The electrode pattern 110 can be electrically connected to the pixel electrode 102 of the dark pixel region L through a third via V3 penetrating the first insulating layer 114, and the orthographic projection of the electrode pattern 110 on the substrate 101 overlaps with the orthographic projection of the first common electrode line 111 on the substrate 101. Thus, by adding the electrode pattern 110, the overlapping electrode pattern 110 and the first common electrode line 111 are added to form a storage capacitor C. st Part of the storage capacitor C st Increase, thereby increasing C total Lowering the feedthrough voltage reduces the difference in optimal CF COM between positive and negative frames for both bright and dark pixels, thus improving the head-shaking pattern. The simulation results in Figure 16 show that the difference in optimal Vcom between bright and dark pixels is 0.41V, a reduction of 0.12V, which reduces the head-shaking pattern caused by the large difference in optimal Vcom between bright and dark pixels in positive and negative frames.

[0084] Referring to Figures 9 and 10, the orthographic projection of the first common electrode line 111 on the substrate 101 can overlap with the orthographic projection of the first electrode s of the first transistor 106 on the substrate 101. Furthermore, the overlapping areas of the orthographic projections of the first common electrode line 111 and the first electrode s of the first transistor 106, and the overlapping areas of the orthographic projections of the first common electrode line 111 and the electrode pattern 110, are arranged approximately side-by-side along the row direction X. Compared to a scheme with staggered overlapping areas, the side-by-side arrangement of the two overlapping areas is beneficial for improving the aperture ratio. Optionally, the pixel electrode 102 can also include a second intermediate portion P4 extending along the column direction Y between multiple domain regions D1 to D4. The extended line of the orthographic projection of the second intermediate portion P4 on the substrate 101 can pass through the orthographic projection of the active layer a of the first transistor 106 on the substrate 101. In other words, the active layer a of the first transistor 106 can be arranged side-by-side with the center of the sub-pixel. In some embodiments, as shown in Figures 10 and 11, the two ends of the active layer a of this disclosure can be covered by the first electrode s and the second electrode d, or, in some embodiments, the two ends of the active layer a are flush with the first electrode s and the second electrode d, respectively.

[0085] In some embodiments, FIG. 18 shows another structure diagram of a pixel provided in the embodiments of the present disclosure, FIG. 19 is an enlarged structure diagram of the Z3 region in FIG. 18, FIG. 20 is a structure diagram of the layer where the gate line is located in FIG. 18, FIG. 21 is a structure diagram of the active layer in FIG. 18, FIG. 22 is a structure diagram of the layer where the data line is located in FIG. 18, FIG. 23 is a structure diagram of the layer where the via is located in FIG. 18, FIG. 24 is a structure diagram of the layer where the pixel electrode is located in FIG. 18, FIG. 25 is a cross-sectional structure diagram along III-III' in FIG. 9, and FIG. 26 is a simulation diagram of the pixel voltage and the optimal common voltage Vcom of the embodiment shown in FIG. 18.

[0086] As shown in FIGS. 18 to 24, in the array substrate provided in the embodiments of the present disclosure, the pixel electrode 102 can further include a second intermediate portion P4 extending along the column direction Y between the plurality of domain regions D1 to D4, and the orthographic projection of the active layer a of the first transistor 106 on the substrate 101 is located on the side of the extension line of the orthographic projection of the second intermediate portion P4 on the substrate 101 away from the data line 107, so that the active layer a of the first transistor 106 is arranged side by side with the right end of the sub-pixel, and the overlapping area of the first electrode s of the first transistor 106 and the first common electrode line 111 can be located on both sides of the extension line of the second intermediate portion P4 at the same time, thereby increasing the C st of the dark pixel, reducing the feed through voltage, and without loss of aperture ratio. As can be seen from the simulation results in FIG. 26, the difference between the optimal Vcom of the bright pixel and the optimal Vcom of the dark pixel is 0.36 V, which is reduced by 0.17 V, and the shaking phenomenon caused by the large difference between the optimal Vcom of the bright pixel and the optimal Vcom of the dark pixel in the positive and negative frames is reduced. In some embodiments, as can be seen from FIGS. 1, 2, 9 and 18, the region where the second intermediate portion P4 is located is the dark stripe region, and the orthographic projection of the second intermediate portion P4 on the substrate 101 and the orthographic projection of the discharge line 105 on the substrate 101 overlap with each other, so that the discharge line 105 is arranged in the dark stripe region, and the aperture ratio is not lost.

[0087] In some embodiments, as shown in FIGS. 2, 3, 7, 9, 18, 20 and 24, the present disclosure further provides a second common electrode line 112, which is optionally arranged in the same layer and made of the same material as the gate line 104. The orthographic projection of the second common electrode line 112 on the substrate 101 can overlap with the orthographic projection of the pixel electrode 102 of the bright pixel region H on the substrate 101, and the light shielding structure 103 can be integrally arranged with the second common electrode line 112 to manufacture the light shielding structure 103 and the first common electrode line 111 by using one mask, thereby avoiding the development of an additional mask for the light shielding structure 103 and saving costs.

[0088] In some examples, as shown in FIG. 2, FIG. 3, FIG. 5, FIG. 7, FIG. 9, FIG. 14, FIG. 18, FIG. 20, FIG. 21, FIG. 24 and FIG. 25, the array substrate provided by the embodiments of the present disclosure can further include a third common electrode line 113, which is optionally arranged in the same layer and made of the same material as the pixel electrode 102, and the third common electrode line 113 is electrically connected to the first common electrode line 111 through a fourth via V4 penetrating the first insulating layer 114 and the second insulating layer 115, and is electrically connected to the second common electrode line 112 through a fifth via V5 penetrating the first insulating layer 114 and the second insulating layer 115. In some embodiments, the third common electrode line 113 can include a first common electrode portion 1131 between adjacent pixel electrodes 102 arranged in the row direction X, a second common electrode portion 1132 connecting the two first common electrode portions 1131 and intersecting the gate line 107, and a third common electrode portion 1133 vertically overlapping with the edge of the gate line 107, wherein the line widths of the first common electrode portion 1131, the second common electrode portion 1132 and the third common electrode portion 1133 can be different, for example, the line width of the second common electrode portion 1132 can be smaller than the line width C1 of the first common electrode portion 1131 and larger than the line width of the third common electrode portion 1133.

[0089] In some embodiments, the orthogonal projection of the data line 107 on the substrate 101 can overlap with the orthogonal projection of the third common electrode line 113 on the substrate 101, for example, the orthogonal projection of the data line 107 on the substrate 101 is located within the orthogonal projection of the third common electrode line 113 (for example, the whole of the first common electrode portion 1131 and the second common electrode portion 1132) on the substrate 101, so as to shield the signal of the data line 107 by the third common electrode line 113, and avoid mutual interference between adjacent and uncoupled data lines 107 and the pixel electrode 102. Moreover, since the line width of the data line 107 is relatively narrow (for example, 8 μm), even if the third common electrode line 113 completely covers the data line 107, it will not cause a large load to the data line 107; at the same time, the complete coverage of the data line 107 by the third common electrode line 113 can ensure that the line width of the third common electrode line 113 is greater than or equal to the line width of the data line 107, thereby reducing the risk of disconnection of the third common electrode line 113.

[0090] In some embodiments, the orthogonal projection of the edge of the gate line 104 close to the side of the bright pixel region H on the substrate 101 can overlap with the orthogonal projection of the third common electrode line 113 (for example, the third common electrode part 1133) on the substrate 101, and the orthogonal projection of the edge of the gate line 104 close to the dark pixel region L and on the side of the discharge line 105 away from the first transistor 106 on the substrate 101 can overlap with the orthogonal projection of the third common electrode line 113 (for example, the third common electrode part 1133) on the substrate 101; for example, the third common electrode line 113 (for example, the third common electrode part 1133) covers the edge of the gate line 104 close to the side of the bright pixel region H and the edge of the gate line 104 close to the dark pixel region L and on the side of the discharge line 105 away from the first transistor 106, and does not overlap with the middle region of the gate line 104. In this way, the signal of the gate line 104 can be effectively shielded by the third common electrode line 113, so that the pixel electrode 102 is not disturbed by the gate line 104. In addition, the overall line width of the gate line 104 is large, and the third common electrode line 113 does not cover the middle region of the gate line 104, which is beneficial to reducing the load of the gate line 104.

[0091] In some embodiments, the transistor of the present disclosure can be a P-type transistor or an N-type transistor according to different materials; the transistor of the present disclosure can be a bottom-gate transistor, a top-gate transistor or a dual-gate transistor according to different gate positions, which are not limited herein. In addition, the first electrode of the transistor in the present disclosure can be a source electrode and the second electrode can be a drain electrode, or the first electrode of the transistor can be a drain electrode and the second electrode can be a source electrode; the active layer material of the transistor can be amorphous silicon (a-Si), polycrystalline silicon (poly), oxide (such as indium gallium zinc oxide IGZO), etc.

[0092] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure is shown in FIG. 27. The array substrate 001 and the opposite substrate 002 opposite to the array substrate 001 are provided. The common electrode 201 of the opposite substrate 002 can be provided on the whole display area AA and cover all the sub-pixel regions SP. The opposite substrate 002 can further include a substrate 202, a black matrix 203 between the substrate 202 and the common electrode 201, and a color resistance 204 between the black matrix 203 and the common electrode 201. Optionally, the black matrix 203 exposes the opening region of the bright pixel region H and the opening region of the dark pixel region L, and covers the gate line 104, the first transistor 106, the data line 107, the second transistor 108, the third transistor 109, the electrode pattern 110, the first common electrode line 111, the second common electrode line 112, and the third common electrode line 113. It should be noted that the black matrix can be provided on the opposite substrate or on the array substrate, which is not limited herein.

[0093] In some embodiments, the display panel provided by the embodiments of the present disclosure can further include a liquid crystal layer between the array substrate and the opposite substrate, a first polarizer on the side of the array substrate away from the opposite substrate, and a second polarizer on the side of the opposite substrate away from the array substrate, and the polarization direction of the first polarizer is perpendicular to the polarization direction of the second polarizer. It should be understood by those skilled in the art that other essential components in the display panel are understood, and are not described here and should not be considered as a limitation on the present disclosure.

[0094] Based on the same inventive concept, the embodiments of the present disclosure provide a display device, as shown in FIG. 28, which includes the above-mentioned display panel PNL provided by the embodiments of the present disclosure, and a backlight module BLU located on the light-in side of the display panel PNL. The backlight module BLU can be a direct type backlight module or a side type backlight module. Optionally, the side type backlight module can include a lamp strip, a reflector sheet, a light guide plate, a diffusion sheet, a prism group, etc., and the lamp strip is located on one side of the light guide plate in the thickness direction. The direct type backlight module can include a matrix light source, a reflector sheet, a diffusion plate, and a brightness enhancement film, etc., which are stacked on the light-out side of the matrix light source, and the reflector sheet includes openings corresponding to the positions of the lamp beads in the matrix light source. The lamp beads in the lamp strip and the lamp beads in the matrix light source can be light-emitting diodes (LEDs), such as micro light-emitting diodes (Mini LED, Micro LED, etc.).

[0095] The micro light-emitting diode of sub-millimeter level or even micron level is a self-luminous device like the organic light-emitting diode (OLED). It has a series of advantages such as high brightness, ultra-low delay, and ultra-large viewing angle like the organic light-emitting diode. And because the inorganic light-emitting diode emits light based on the metal semiconductor with more stable properties and lower resistance, it has the advantages of lower power consumption, longer service life, and better resistance to high and low temperatures compared with the organic light-emitting diode based on organic matter. When the micro light-emitting diode is used as a backlight source, it can achieve more precise dynamic backlight effect, effectively improve the screen brightness and contrast, and solve the glare phenomenon caused by the traditional dynamic backlight between the light and dark areas of the screen, and optimize the visual experience.

[0096] In some embodiments, the display device provided by the embodiments of the present disclosure can be any product or component with display function, such as a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigation device, a smart watch, a fitness wristband, a personal digital assistant, and the like. Optionally, the display device provided by the embodiments of the present disclosure includes, but is not limited to, a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a control chip, and the like. Optionally, the control chip is a central processing unit, a digital signal processor, a system chip (SoC), and the like. For example, the control chip can further include a memory, and can further include a power module, and the like, and the power supply and signal input and output functions are realized through wires, signal lines, and the like arranged additionally. For example, the control chip can further include hardware circuitry and computer executable code, and the like. The hardware circuitry can include conventional very large scale integration (VLSI) circuitry or gate array, and existing semiconductors or other discrete elements such as logic chips, transistors, and the like; the hardware circuitry can also include field programmable gate array, programmable array logic, programmable logic device, and the like. In addition, those skilled in the art can understand that the above structure does not constitute a limitation on the display device provided by the embodiments of the present disclosure, in other words, the display device provided by the embodiments of the present disclosure can include more or less components, or combine certain components, or arrange different components.

[0097] Although the preferred embodiments of the present disclosure have been described, those skilled in the art can make additional changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present disclosure.

[0098] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if these modifications and variations of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, Comprising: a substrate substrate comprising a plurality of bright pixel regions and a plurality of dark pixel regions arranged in an array, the bright pixel regions and the dark pixel regions respectively comprising a plurality of sub-pixel regions, the sub-pixel regions comprising a plurality of domain regions; a plurality of pixel electrodes mutually overlapping the plurality of sub-pixel regions, the pixel electrodes comprising a first intermediate portion extending in a row direction between the plurality of domain regions, and a first edge portion and a second edge portion extending in a column direction on both sides of the plurality of domain regions; a plurality of light shielding structures mutually overlapping at least the plurality of bright pixel regions, a projection of the plurality of light shielding structures on the substrate substrate mutually overlapping a projection of the first intermediate portion, the first edge portion, and the second edge portion within at least part of the sub-pixel regions of the bright pixel regions on the substrate substrate.

2. The array substrate of claim 1, wherein, a projection of the plurality of light shielding structures on the substrate substrate mutually overlapping a projection of the first intermediate portion, the first edge portion, and the second edge portion within the plurality of sub-pixel regions of the plurality of bright pixel regions on the substrate substrate.

3. The array substrate of claim 1 or 2, wherein, Further comprising a gate line; a portion of the first edge portion perpendicularly overlapping the light shielding structure extends away from the gate line from the first intermediate portion; a portion of the second edge portion perpendicularly overlapping the light shielding structure extends toward the gate line from the first intermediate portion.

4. The array substrate according to any one of claims 1 to 3, wherein, Further comprising a gate line, a discharge line, and a first transistor, a gate electrode of the first transistor being electrically connected to the gate line, a first electrode of the first transistor being electrically connected to the pixel electrode of the dark pixel region, and a second electrode of the first transistor being electrically connected to the discharge line; the first electrode of the first transistor comprises a first portion extending in a column direction, and a second portion located at both ends of the first portion, wherein a projection of the first portion on the substrate substrate is located within a projection of the gate line on the substrate substrate, a projection of the second portion on the substrate substrate partially overlaps a projection of the gate line on the substrate substrate, and a line width of the first portion in the row direction is smaller than a line width of the second portion in the row direction. Further comprising a data line, a second transistor, and a third transistor; wherein, 5. The array substrate of claim 4, wherein, a gate electrode of the second transistor is electrically connected to the gate line, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the pixel electrode of the bright pixel region; a gate electrode of the third transistor is multiplexed with the gate electrode of the second transistor, a first electrode of the third transistor is multiplexed with the first electrode of the second transistor, and a second electrode of the third transistor is electrically connected to the pixel electrode of the dark pixel region; a line width of the first electrode of the second transistor in a direction perpendicular to the extension direction thereof is greater than the line width of the first portion in the row direction and substantially equal to the line width of the second portion in the row direction. a line width of at least part of the first electrode of the first transistor in the row direction and a line width of the second electrode of the first transistor in the row direction are different, and the second electrode of the first transistor is multiplexed with the discharge line.

6. The array substrate of claim 4 or 5, wherein, ​ 7. The array substrate according to any one of claims 1 to 6, wherein, The electrode pattern is electrically connected with the pixel electrode of the dark pixel area, and the orthogonal projection of the electrode pattern on the substrate substrate and the orthogonal projection of the first common electrode line on the substrate substrate overlap each other.

8. The array substrate of claim 7, wherein, The first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the second electrode of the first transistor is electrically connected with the discharge line; The orthogonal projection of the first common electrode line on the substrate substrate and the orthogonal projection of the first electrode of the first transistor on the substrate substrate overlap each other, and the orthogonal projection overlap area of the first common electrode line and the first electrode of the first transistor and the orthogonal projection overlap area of the first common electrode line and the electrode pattern are arranged side by side along the row direction.

9. The array substrate according to any one of claims 1 to 8, wherein, Further comprising a data line, a discharge line, a first transistor and a third transistor; wherein, The first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the second electrode of the first transistor is electrically connected with the discharge line; The first electrode of the third transistor is electrically connected with the data line, and the second electrode of the third transistor is integrally arranged with the first electrode of the first transistor; The pixel electrode further comprises a second intermediate part extending along the column direction between the plurality of domain areas, and the orthogonal projection of the active layer of the first transistor on the substrate substrate is located on the side of the orthogonal projection extension line of the second intermediate part on the substrate substrate away from the data line.

10. The array substrate of any one of claims 1 to 8, wherein, The first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the second electrode of the first transistor is electrically connected with the discharge line; The pixel electrode further comprises a second intermediate part extending along the column direction between the plurality of domain areas, and the orthogonal projection extension line of the second intermediate part on the substrate substrate penetrates the orthogonal projection of the active layer of the first transistor on the substrate substrate.

11. The array substrate according to any one of claims 1 to 10, wherein, Further comprising a discharge line; The pixel electrode further comprises a second intermediate part extending along the column direction between the plurality of domain areas, and the orthogonal projection of the second intermediate part on the substrate substrate and the orthogonal projection of the discharge line on the substrate substrate overlap each other.

12. The array substrate of any one of claims 1 to 11, wherein, Further comprising a second common electrode line, the orthogonal projection of the second common electrode line on the substrate substrate and the orthogonal projection of the pixel electrode of the bright pixel area on the substrate substrate overlap each other, and the light shielding structure is integrally arranged with the second common electrode line.

13. The array substrate of any one of claims 1 to 12, wherein, Further comprising a gate line, a data line, a discharge line, a third common electrode line and a first transistor; wherein, The first electrode of the first transistor is electrically connected with the pixel electrode of the dark pixel area, and the The second electrode of the first transistor is electrically connected with the discharge line; The orthogonal projection of the data line on the substrate substrate and the orthogonal projection of the third common electrode line on the substrate substrate overlap each other; The orthogonal projection of the edge of the gate line close to one side of the bright pixel area on the substrate substrate and the orthogonal projection of the third common electrode line on the substrate substrate overlap each other; A normal projection of a portion of the gate line, which is located on a side of the discharge line far from the first transistor and close to the dark pixel area, on the substrate substrate and a normal projection of the third common electrode line on the substrate substrate overlap each other.

14. A display panel, wherein, The display panel includes the array substrate and an opposite substrate opposite to the array substrate.

15. The display panel of claim 14, wherein, The opposite substrate includes a common electrode.

16. A display device comprising: The display panel includes the array substrate and an opposite substrate opposite to the array substrate. The display panel includes the array substrate and an opposite substrate opposite to the array substrate.

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