Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base (101) and a plurality of sub-pixels (Pxij) disposed on one side of the base (101), wherein at least some of the sub-pixels (Pxij) each comprise a pixel driving circuit, each pixel driving circuit comprises a plurality of transistors, and the plurality of transistors comprise at least a driving transistor (T3); the plurality of sub-pixels (Pxij) comprise at least first-type sub-pixels (PL1) and second-type sub-pixels (PL2); and the width-to-length ratio (W1 / L1) of a channel of the driving transistor (T3) in each first-type sub-pixel (PL1) is less than the width-to-length ratio (W2 / L2) of a channel of the driving transistor (T3) in each second-type sub-pixel (PL2).

Description

Display substrate and display device TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of display, and in particular, to a display substrate and a display device. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible display devices with OLED or QLED as light-emitting devices and signal control by Thin Film Transistor (TFT) have become mainstream products in the current display field.

[0003] SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the embodiments of the present disclosure provide a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least part of the sub-pixels comprising a pixel driving circuit, the pixel driving circuit comprising a plurality of transistors, the plurality of transistors comprising at least a driving transistor; the plurality of sub-pixels comprising at least a first type of sub-pixel and a second type of sub-pixel.

[0006] The width-to-length ratio of the channel of the driving transistor in the first type of sub-pixel is less than the width-to-length ratio of the channel of the driving transistor in the second type of sub-pixel.

[0007] In an exemplary embodiment, the width-to-length ratio of the channel of the driving transistor in the first type of sub-pixel is less than or equal to 1; and the width-to-length ratio of the channel of the driving transistor in the second type of sub-pixel is greater than or equal to 1.

[0008] In an exemplary embodiment, the width-to-length ratio of the channel of the driving transistor in the first type of sub-pixel is greater than or equal to 8 / 16 and less than or equal to 8 / 8; and the width-to-length ratio of the channel of the driving transistor in the second type of sub-pixel is greater than or equal to 8 / 8 and less than or equal to 8 / 4.

[0009] In an exemplary embodiment, the width-to-length ratio of the channel of the driving transistor in the first type of sub-pixel is 8 / 10; and the width-to-length ratio of the channel of the driving transistor in the second type of sub-pixel is 8 / 6.

[0010] In an exemplary embodiment, the display substrate further comprises a constant voltage signal line, and the pixel driving circuit further comprises a first capacitor and a second capacitor.

[0011] The first plate of the first capacitor is connected to the control electrode of the driving transistor, the second plate of the first capacitor and the second plate of the second capacitor are connected to the second electrode of the driving transistor, and the first plate of the second capacitor is connected to the constant voltage signal line.

[0012] In an exemplary embodiment, the first plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer, and the second plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer; in a direction perpendicular to the plane in which the substrate is located, the second plate of the first capacitor and the second plate of the second capacitor are located on the side of the first plate of the first capacitor and the first plate of the second capacitor away from the substrate.

[0013] In the same pixel driving circuit, the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the first capacitor on the substrate, and the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the second capacitor on the substrate.

[0014] In an exemplary embodiment, the first capacitor and the second capacitor share a second plate.

[0015] In an exemplary embodiment, the orthographic projection of the first plate of the first capacitor on the substrate is within the range of the orthographic projection of the second plate of the first capacitor on the substrate.

[0016] In an exemplary embodiment, the orthographic projection of the second plate of the second capacitor on the substrate is within the range of the orthographic projection of the first plate of the second capacitor on the substrate.

[0017] In an exemplary embodiment, the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is 0.7 to 2.

[0018] In an exemplary embodiment, the ratio of the capacitance of the first capacitor to the capacitance of the second capacitor is 1.

[0019] In an exemplary embodiment, the capacitance of the first capacitor and the capacitance of the second capacitor are both greater than 60 or equal to femto, and less than or equal to 300 femto.

[0020] In an exemplary embodiment, the pixel driving circuit further comprises at least one capacitor.

[0021] In a direction perpendicular to a plane on which the substrate lies, the capacitor comprises: a first plate located on one side of the substrate, and a second plate located on a side of the first plate away from the substrate; and the transistor comprises: an active layer located on a side of the second plate away from the substrate, a control electrode located on a side of the active layer away from the substrate, a first electrode and a second electrode located on a side of the control electrode away from the substrate.

[0022] In the same capacitor, a projection of the first plate on the substrate at least partially overlaps a projection of the second plate on the substrate.

[0023] In an exemplary embodiment, a size of an overlapping region between the control electrode and the active layer of the same drive transistor in the first type of sub-pixel along a channel length direction is greater than a size of an overlapping region between the control electrode and the active layer of the same drive transistor in the second type of sub-pixel along the channel length direction.

[0024] A size of the control electrode of the drive transistor in the first type of sub-pixel along a channel width direction is consistent with a size of the control electrode of the drive transistor in the second type of sub-pixel along the channel width direction.

[0025] In an exemplary embodiment, at least one of the capacitors further comprises a third plate and a first transfer electrode, the third plate is disposed in the same layer as the control electrode, and the first transfer electrode is disposed in the same layer as the first electrode and the second electrode.

[0026] In the same capacitor, a projection of the third plate on the substrate at least partially overlaps projections of the first plate and the second plate on the substrate, and the first transfer electrode is connected to the third plate and the first plate through a via.

[0027] In an exemplary embodiment, at least one of the capacitors further comprises a fourth plate and a fifth plate, the fourth plate is disposed in the same layer as the first electrode and the second electrode, and the fifth plate is located on a side of the first plate close to the substrate.

[0028] In the same capacitor, projections of the fourth plate and the fifth plate on the substrate at least partially overlap projections of the first plate, the second plate, and the third plate on the substrate, and the fourth plate is connected to the second plate and the fifth plate through a via.

[0029] In an exemplary embodiment, the pixel driving circuit includes a first capacitor and a second capacitor, a second plate of the first capacitor and a second plate of the second capacitor are connected to each other through a connecting electrode, and the connecting electrode is located on a side of the second plate of the first capacitor and the second plate of the second capacitor away from the substrate in a direction perpendicular to a plane where the substrate is located; or the first capacitor and the second capacitor share a second plate.

[0030] At least one of the first capacitor and the second capacitor includes the third plate and the first transfer electrode.

[0031] In an exemplary embodiment, at least one of the capacitors further includes a third plate, a fourth plate, and a second transfer electrode, the third plate is disposed in the same layer as the control electrode, and the second transfer electrode and the fourth plate are disposed in the same layer as the first electrode and the second electrode.

[0032] In the same capacitor, the second transfer electrode is connected to the second plate and the third plate through a via, the fourth plate is connected to the first plate through a via, and a normal projection of the third plate and the fourth plate on the substrate at least partially overlaps a normal projection of the first plate and the second plate on the substrate.

[0033] In an exemplary embodiment, the pixel driving circuit includes a first capacitor and a second capacitor, a second plate of the first capacitor and a second plate of the second capacitor are connected to each other through a connecting electrode, and the connecting electrode is located on a side of the second plate of the first capacitor and the second plate of the second capacitor away from the substrate in a direction perpendicular to a plane where the substrate is located; or the first capacitor and the second capacitor share a second plate.

[0034] At least one of the first capacitor and the second capacitor includes the third plate, the fourth plate, and the second transfer electrode.

[0035] In an exemplary embodiment, the display substrate can further include a first initial signal line, a second initial signal line, a first power supply line, and a second power supply line, and the plurality of transistors include a first transistor as a reset transistor, a second transistor as a reset transistor, and a fifth transistor as an emission control transistor.

[0036] The first initial signal line and the second initial signal line are disposed in the same layer as the first electrode and the second electrode, and the first power supply line and the second power supply line are located on a side of the first electrode and the second electrode away from the substrate.

[0037] The first electrode of the first transistor is connected with the first initial signal line, the first electrode of the second transistor is connected with the second initial signal line, and the first electrode of the fifth transistor is connected with the first power supply line; in the same pixel driving circuit, the second electrode of the fifth transistor is connected with the first electrode of the driving transistor, the first plate of the first capacitor is connected with the control electrode of the driving transistor and the second electrode of the first transistor, the second plate of the first capacitor and the second plate of the second capacitor are connected with the second electrode of the driving transistor, and the first plate of the second capacitor is connected with one of the first initial signal line, the second initial signal line, the first power supply line and the second power supply line.

[0038] In an exemplary embodiment, the first type of sub-pixel includes a first sub-pixel and a second sub-pixel, and the second type of sub-pixel includes a third sub-pixel.

[0039] In an exemplary embodiment, the first sub-pixel is a sub-pixel that emits red light, the second sub-pixel is a sub-pixel that emits green light, and the third sub-pixel is a sub-pixel that emits blue light.

[0040] In an exemplary embodiment, the plurality of sub-pixels form a plurality of pixel units, and each pixel unit includes the first sub-pixel, the second sub-pixel and the third sub-pixel.

[0041] In an exemplary embodiment, the plurality of transistors are oxide transistors.

[0042] In a second aspect, the embodiments of the present disclosure further provide a display device, including the display substrate according to any one of the above embodiments.

[0043] Other aspects can become apparent from a review of the drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0044] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, and constitute a part of the specification, and are used to explain the technical solutions of the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation on the technical solutions of the present disclosure. The shape and size of each component in the drawings do not reflect the actual proportion, and the purpose is only to schematically illustrate the present disclosure.

[0045] FIG. 1 is a structural schematic diagram of a display device;

[0046] FIG. 2 is a structural schematic diagram of a display substrate;

[0047] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate;

[0048] FIG. 4a is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0049] Fig. 4b is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0050] Fig. 4c is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0051] Fig. 4d is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0052] Fig. 5a is a schematic diagram of a structure of a display substrate according to an embodiment of the present disclosure;

[0053] Fig. 5b is a schematic diagram of a structure of a display substrate according to an embodiment of the present disclosure;

[0054] Fig. 5c is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0055] Fig. 6a is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0056] Fig. 6b is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0057] Fig. 6c is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0058] Fig. 6d is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0059] Fig. 6e is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0060] Fig. 6f is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0061] Fig. 6g is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0062] Fig. 6h is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0063] Fig. 6i is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0064] Fig. 6j is a schematic diagram of a cross-sectional structure of a capacitor in a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0065] Fig. 7 is a schematic diagram of a display substrate after a first conductive layer is formed according to an exemplary embodiment of the present disclosure;

[0066] FIG. 8a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0067] FIG. 8b shows a schematic diagram of a second conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0068] FIG. 9a shows a schematic diagram of a display substrate after forming a semiconductor layer pattern according to an exemplary embodiment of the present disclosure;

[0069] FIG. 9b shows a schematic diagram of a semiconductor layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0070] FIG. 10a shows a schematic diagram of a display substrate after forming a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0071] FIG. 10b shows a schematic diagram of a third conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0072] FIG. 11 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0073] FIG. 12a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0074] FIG. 12b shows a schematic diagram of a fourth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0075] FIG. 13 shows a schematic diagram of a display substrate after forming a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0076] FIG. 14a shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0077] FIG. 14b shows a schematic diagram of a fifth conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0078] FIG. 15 shows a schematic diagram of a display substrate after forming a second planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0079] FIG. 16a shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0080] FIG. 16b shows a schematic diagram of an anode conductive layer in a display substrate according to an exemplary embodiment of the present disclosure;

[0081] FIG. 17a shows a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an example embodiment of the present disclosure;

[0082] FIG. 17b shows a schematic diagram of a pixel definition layer pattern of a display substrate according to an example embodiment of the present disclosure;

[0083] FIG. 18a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0084] FIG. 18b shows a schematic diagram of a second conductive layer of a display substrate according to an example embodiment of the present disclosure;

[0085] FIG. 19 shows a schematic diagram of a display substrate after forming a fourth insulating layer pattern according to an example embodiment of the present disclosure;

[0086] FIG. 20a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0087] FIG. 20b shows a schematic diagram of a fourth conductive layer of a display substrate according to an example embodiment of the present disclosure;

[0088] FIG. 20c shows a schematic diagram of a display substrate after forming an anode conductive layer pattern according to an example embodiment of the present disclosure;

[0089] FIG. 21 shows a schematic diagram of a display substrate after forming a first conductive layer pattern according to an example embodiment of the present disclosure;

[0090] FIG. 22a shows a schematic diagram of a display substrate after forming a second conductive layer pattern according to an example embodiment of the present disclosure;

[0091] FIG. 22b shows a schematic diagram of a second conductive layer of a display substrate according to an example embodiment of the present disclosure;

[0092] FIG. 23a shows a schematic diagram of a display substrate after forming a fourth conductive layer pattern according to an example embodiment of the present disclosure;

[0093] FIG. 23b shows a schematic diagram of a fourth conductive layer of a display substrate according to an example embodiment of the present disclosure;

[0094] FIG. 24 shows a schematic diagram of a display substrate after forming a first planarization layer pattern according to an example embodiment of the present disclosure;

[0095] FIG. 25a shows a schematic diagram of a display substrate after forming a fifth conductive layer pattern according to an example embodiment of the present disclosure;

[0096] FIG. 25b shows a schematic diagram of a fifth conductive layer of a display substrate according to an example embodiment of the present disclosure;

[0097] FIG. 25c is a schematic view of a display substrate after forming a pattern of an anode conductive layer according to an example embodiment of the present disclosure.

[0098] FIG. 26 is a schematic view of a display device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0099] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Embodiments can be implemented in various forms. It is obvious that those skilled in the art, to which the present disclosure pertains, can easily understand a fact that the embodiments and the contents can be variously changed without departing from the gist of the present disclosure and the scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited only to the content described in the following embodiments. Embodiments in the present disclosure and features in the embodiments can be optionally combined with each other to the extent that there is no contradiction in the combination. In order to keep the following description of the embodiments of the present disclosure clear and brief, detailed description of some known functions and known components will be omitted. The drawings attached to the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can be referred to the generally designed structures

[0100] The scale of the drawings in the present disclosure can be used as a reference in the actual process, but is not limited thereto. For example, the thickness and the interval of each film layer, the width and the interval of each signal line can be adjusted according to the actual situation. The drawings described in the present disclosure are only schematic views of the structures, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0101] In the present specification, ordinal numbers such as "first", "second", "third", and the like are set in order to avoid confusion of the components, and are not intended to be limited in terms of quantity.

[0102] In the present specification, in order to facilitate the description, words indicating the orientation or the positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain the positional relationship of the components with reference to the drawings, and are only for the convenience of the description of the present specification and the simplification of the description, and are not intended to indicate or imply that the device or the element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0103] In this specification, unless otherwise explicitly specified and limited, the terms "mount", "connected", and "linked" are to be interpreted broadly. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection via an intermediate element, or a communication between the two elements inside. The specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances for those skilled in the art.

[0104] In this specification, a transistor refers to an element including at least a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and a source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current flows mainly.

[0105] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or the first electrode can be a source electrode and the second electrode can be a drain electrode. In the case of using a transistor with opposite polarity or in the case where the direction of current flow is changed in the operation of a circuit, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other. In this embodiment of the disclosure, a gate electrode can be referred to as a control electrode.

[0106] In this specification, "electrically connected" includes the case where elements are connected through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can transmit and receive an electrical signal between elements to be connected. Examples of the element having a certain electrical action include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having a variety of functions.

[0107] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus a state where the angle is greater than or equal to -5° and less than or equal to 5° is also included. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus a state where the angle is greater than or equal to 85° and less than or equal to 95° is also included.

[0108] In this specification, "film" and "layer" can be interchanged with each other. For example, "a conductive layer" can be replaced with "a conductive film". Similarly, "an insulating film" can be replaced with "an insulating layer".

[0109] In the present specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon, etc. are not strictly defined, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon, etc. Some small deformations caused by tolerances can exist, and there can be guide angles, arc edges, and deformations, etc.

[0110] In the present disclosure, “about” means not strictly limited boundaries, and values within the range of process and measurement errors are allowed.

[0111] FIG. 1 shows a structural schematic diagram of a display device, a display substrate can include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emitting signal driving circuit, and a pixel array, the timing controller is connected with the data signal driving circuit, the scan signal driving circuit, and the light emitting signal driving circuit respectively, the data signal driving circuit is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan signal driving circuit is connected with a plurality of scan signal lines (G1 to Gm) respectively, and the light emitting signal driving circuit is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting device connected with the circuit unit, the circuit unit can include a pixel driving circuit, and the pixel driving circuit can be connected with a scan signal line, a light emitting signal line, and a data signal line (which can be referred to as a data line) respectively. In an exemplary embodiment, the timing controller can provide a gray scale value and a control signal suitable for the specification of the data signal driving circuit to the data signal driving circuit, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driving circuit to the scan signal driving circuit, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting signal driving circuit to the light emitting signal driving circuit. The data signal driving circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray scale value and the control signal received from the timing controller. For example, the data signal driving circuit can sample the gray scale value using the clock signal, and apply a data voltage corresponding to the gray scale value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan signal driving circuit can generate a scan signal to be provided to the scan signal lines G1, G2, G3, …, and Gm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan signal driving circuit can sequentially provide a scan signal having an on-level pulse to the scan signal lines G1 to Gm. For example, the scan signal driving circuit can be configured in the form of a shift register, and can generate a scan signal in such a manner that an emission start signal provided in the form of an on-level pulse is sequentially transferred to a next stage circuit under the control of a clock signal. m can be a natural number. The light emitting signal driving circuit can generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting signal driving circuit can sequentially provide an emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate an emission signal in such a manner that an emission stop signal provided in the form of an off-level pulse is sequentially transferred to a next stage circuit under the control of a clock signal. o can be a natural number.

[0112] FIG. 2 is a schematic diagram of a planar structure of a display substrate. As shown in FIG. 2, the display substrate can include a plurality of pixel units P arranged in a matrix manner, at least one of the plurality of pixel units P including a first sub-pixel P1 emitting first color light, a second sub-pixel P2 emitting second color light, and a third sub-pixel P3 emitting third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each including a pixel driving circuit and a light emitting device. The pixel driving circuit in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with a scan signal line, a data signal line, and a light emitting signal line, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light emitting signal line, and output a corresponding current to the light emitting device. The light emitting device in the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 is respectively connected with the pixel driving circuit in the sub-pixel where the light emitting device is located, and is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit in the sub-pixel where the light emitting device is located.

[0113] In an example embodiment, the pixel unit P can include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an example embodiment, the shape of the sub-pixels in the pixel unit can be rectangular, diamond, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal parallel, vertical parallel, or triangular manner, which is not limited in the present disclosure.

[0114] FIG. 3 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in FIG. 3, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a spacer, which is not limited in the present disclosure.

[0115] In the example embodiment, the substrate 101 can be a flexible substrate, or can be a rigid substrate. The driving circuit layer 102 of each sub-pixel can include a plurality of transistors and a storage capacitor constituting a pixel driving circuit. The light-emitting structure layer 103 can include an anode 301 connected to the drain electrode of the driving transistor 210 through a via, an organic light-emitting layer 302 connected to the anode 301, and a cathode 303 connected to the organic light-emitting layer 302, the organic light-emitting layer 302 emitting light of a corresponding color under the driving of the anode 301 and the cathode 303. The encapsulation layer 104 can include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together, the first encapsulation layer 401 and the third encapsulation layer 403 can be made of inorganic material, the second encapsulation layer 402 can be made of organic material, and the second encapsulation layer 402 is arranged between the first encapsulation layer 401 and the third encapsulation layer 403, so as to prevent external water vapor from entering the light-emitting structure layer 103.

[0116] In the example embodiment, the organic light-emitting layer 302 can include a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), an emitting layer (EML), a hole block layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL) stacked together. In the example embodiment, the hole injection layer of all sub-pixels can be a common layer connected together, the electron injection layer of all sub-pixels can be a common layer connected together, the hole transport layer of all sub-pixels can be a common layer connected together, the electron transport layer of all sub-pixels can be a common layer connected together, the hole block layer of all sub-pixels can be a common layer connected together, the emitting layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated, and the electron block layer of adjacent sub-pixels can have a small amount of overlap, or can be isolated.

[0117] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 8T1C or 7T2C structure. As shown in FIGS. 4a-4d, the pixel driving circuit can include 6 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors (first capacitor C1 and second capacitor C2), and can be connected with 11 signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, first emission control line EM1, second emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD and second power supply line VSS).

[0118] In an exemplary embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected with the control electrode of the third transistor T3, the second electrode of the fourth transistor T4, the first terminal of the first capacitor C1 and the second electrode of the first transistor T1 respectively. The second node N2 is connected with the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5 respectively. The third node N3 is connected with the second terminal of the first capacitor C1, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6 respectively. The fourth node N4 is connected with the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7 and the anode of the light emitting device EL respectively.

[0119] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected with the first node N1, and the second terminal of the first capacitor C1 is connected with the third node N3. The first terminal of the second capacitor C2 is connected with the third node N3, and the second terminal of the second capacitor C2 can be connected with a direct current signal line. For example, as shown in FIG. 4a, the second terminal of the second capacitor C2 can be connected with the first power supply line VDD. Or as shown in FIG. 4b, the second terminal of the second capacitor C2 can be connected with the first initial signal line Vinit1. Or as shown in FIG. 4c, the second terminal of the second capacitor C2 can be connected with the second initial signal line Vinit2. Or as shown in FIG. 4d, the second terminal of the second capacitor C2 can be connected with the second power supply line VSS. In the pixel driving circuit shown in FIGS. 4a-4d, the second terminal of the second capacitor C2 is connected with the direct current signal line (for example, connected with one of the first power supply line VDD, the second power supply line VSS, the first initial signal line Vinit1 and the second initial signal line Vinit2), which is beneficial to save the space of the display substrate.

[0120] The control electrode of the first transistor T1 is connected to a first reset control line Reset1, the first electrode of the first transistor T1 is connected to a first initial signal line Vinit1, and the second electrode of the first transistor is connected to the first node N1. When an on-level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the amount of charge at the control electrode of the third transistor T3.

[0121] The control electrode of the second transistor T2 is connected to a second reset control line Reset2, the first electrode of the second transistor T2 is connected to a second initial signal line Vinit2, and the second electrode of the second transistor T2 is connected to the first electrode of the light emitting device (also the fourth node N4). When an on-level reset signal is applied to the second reset control line Reset2, the second transistor T2 transmits an initialization voltage to the first electrode of the light emitting device EL to initialize the amount of charge accumulated in the first electrode of the light emitting device EL or release the amount of charge accumulated in the first electrode of the light emitting device.

[0122] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its control electrode and the first electrode.

[0123] The control electrode of the fourth transistor T4 is connected to a scan signal line Gate, the first electrode of the fourth transistor T4 is connected to a data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be referred to as a switching transistor, and when an on-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 inputs a data voltage of the data signal line D to the pixel driving circuit.

[0124] The control electrode of the fifth transistor T5 is connected to a first emission control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to a second emission control line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device (also the fourth node N4). The fifth transistor T5 and the sixth transistor T6 can be referred to as emission transistors. When on-level emission signals are applied to the first emission control line EM1 and the second emission control line EM2, the fifth transistor T5 and the sixth transistor T6 are turned on to form a driving current path between the first power supply line VDD and the second power supply line VSS to cause the light emitting device to emit light.

[0125] In an example embodiment, the second electrode of the light emitting device is connected to a second power line VSS, and the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a high level signal continuously provided. In an example embodiment, the first transistor T1 to the sixth transistor T6 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the sixth transistor T6 can include P-type transistors and N-type transistors.

[0126] In an example embodiment, the first transistor T1 to the sixth transistor T6 can be low temperature poly-silicon thin film transistors (which can be referred to as P-type transistors), or can be oxide thin film transistors (which can be referred to as N-type transistors), or can be low temperature poly-silicon thin film transistors and oxide thin film transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. The active layer of the low temperature poly-silicon thin film transistor uses low temperature poly-silicon (LTPS), and the active layer of the oxide thin film transistor uses oxide semiconductor (Oxide). The low temperature poly-silicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current, low frequency driving, and low power consumption. Integrating the low temperature poly-silicon thin film transistor and the oxide thin film transistor on one display substrate forms a low temperature poly-crystalline oxide (LTPO) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0127] In an example embodiment, the light emitting device EL can be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0128] In the oxide pixel driving circuit, the numerical range of the voltage value required by the data signal line is large (i.e., the Data Range value is large), which can exceed the voltage value range of the data signal provided by the drive chip (Drive IC data, connected to the data signal line and configured to provide a data signal to the data signal line). In general, the maximum voltage value required by the data signal line is large, and there is a technical problem of high power consumption.

[0129] The display substrate provided by the embodiments of the present disclosure can include a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least part of the sub-pixels can include a pixel driving circuit, the pixel driving circuit can include a plurality of transistors, and the plurality of transistors can include at least a driving transistor; the plurality of sub-pixels can include at least first-type sub-pixels and second-type sub-pixels.

[0130] The width-length ratio of the channel of the driving transistor in the first-type sub-pixel is less than the width-length ratio of the channel of the driving transistor in the second-type sub-pixel.

[0131] The display substrate provided by the embodiments of the present disclosure can include a substrate and a plurality of sub-pixels arranged on one side of the substrate, at least part of the sub-pixels can include a pixel driving circuit, the pixel driving circuit can include a plurality of transistors, and the plurality of transistors can include at least a driving transistor; the plurality of sub-pixels can include at least first-type sub-pixels and second-type sub-pixels.

[0132] As shown in FIGS. 5a-5c, the display substrate provided by the embodiments of the present disclosure can include a substrate and a plurality of sub-pixels Pxij arranged on one side of the substrate, at least part of the sub-pixels Pxij can include a pixel driving circuit, the pixel driving circuit can include a plurality of transistors, and the plurality of transistors can include at least a driving transistor T3; the plurality of sub-pixels Pxij can include at least first-type sub-pixels PL1 and second-type sub-pixels PL2.

[0133] The width-length ratio W1 / L1 of the channel of the driving transistor T3 in the first-type sub-pixel PL1 is less than the width-length ratio W2 / L2 of the channel of the driving transistor T3 in the second-type sub-pixel PL2.

[0134] In an exemplary implementation, the width-length ratio W1 / L1 of the channel of the driving transistor T3 in the first-type sub-pixel PL1 is less than or equal to 1; and the width-length ratio W2 / L2 of the channel of the driving transistor T3 in the second-type sub-pixel PL2 is greater than or equal to 1.

[0135] In an exemplary implementation, the width-length ratio W1 / L1 of the channel of the driving transistor T3 in the first-type sub-pixel PL1 is greater than or equal to 8 / 16 and less than or equal to 8 / 8; and the width-length ratio W2 / L2 of the channel of the driving transistor T3 in the second-type sub-pixel PL2 is greater than or equal to 8 / 8 and less than or equal to 8 / 4.

[0136] In an exemplary implementation, the width-length ratio W1 / L1 of the channel of the driving transistor T3 in the first-type sub-pixel PL1 is 8 / 10; and the width-length ratio W2 / L2 of the channel of the driving transistor T3 in the second-type sub-pixel PL2 is 8 / 6.

[0137] In the example embodiment, the display substrate can further include a constant voltage signal line, and the pixel driving circuit can further include a first capacitor C1 and a second capacitor C2.

[0138] The first plate C11 of the first capacitor C1 is connected to the control electrode of the driving transistor T3, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are connected to the second electrode of the driving transistor T3, and the first plate C21 of the second capacitor C2 can be connected to the constant voltage signal line. There is no need to separately provide a signal line to supply a signal to the first plate C21 of the second capacitor C2, which can save space of the display substrate and improve the utilization rate of the signal line in the display substrate.

[0139] In the example embodiment, as shown in FIGS. 4a-5c, the constant voltage signal line can include a first power line VDD, a second power line VSS, a first initial signal line Vinit1, and a second initial signal line Vinit2. The first plate C21 of the second capacitor C2 can be connected to one of the first power line VDD, the second power line VSS, the first initial signal line Vinit1, and the second initial signal line Vinit2. As shown in FIG. 4a, the first plate C21 of the second capacitor C2 can be connected to the first power line VDD. As shown in FIG. 4b, the first plate C21 of the second capacitor C2 can be connected to the first initial signal line Vinit1. As shown in FIG. 4c, the first plate C21 of the second capacitor C2 can be connected to the second initial signal line Vinit2. As shown in FIG. 4d, the first plate C21 of the second capacitor C2 can be connected to the second power line VSS. In the structure shown in FIGS. 5a-5c, the first plate C21 of the second capacitor C2 is connected to the first power line VDD, wherein the first power line VDD is connected to the first plate C21 of the second capacitor C2 through a first power connection line VDDL, the first power connection line VDDL extends along a first direction X, and the first power line VDD extends along a second direction. A plurality of first power connection lines VDDL and a plurality of first power lines VDD in the display substrate are connected to each other to form a grid structure, which can reduce the voltage drop on the first power line VDD and the first power connection line VDDL, so that the signals received by the first plates C21 of the plurality of second capacitors C2 in the display substrate are as consistent as possible, thereby improving the display uniformity.

[0140] In the example embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be disposed in the same layer, and the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be disposed in the same layer. In a direction Z perpendicular to the plane of the substrate, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are located on the side away from the substrate of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2.

[0141] In the same pixel driving circuit, the second plate C12 of the first capacitor C1 and the first plate C11 of the first capacitor C1 at least partially overlap in the projection on the substrate, and the second plate C22 of the second capacitor C2 and the first plate C21 of the second capacitor C2 at least partially overlap in the projection on the substrate.

[0142] In the exemplary embodiment, the first capacitor C1 and the second capacitor C2 share a second plate. That is, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be an integrated structure, which can reduce the number of vias and to a certain extent reduce the occurrence of via defects (in the structure in which the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are connected by a connecting electrode, the connecting electrode is connected to the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 through vias, respectively).

[0143] In the exemplary embodiment, the first plate C11 of the first capacitor C1 is located within the projection on the substrate of the second plate C12 of the first capacitor C1, that is, the second plate C12 of the first capacitor C1 covers the first plate C11 of the first capacitor C1, so that the second plate C12 of the first capacitor C1 can shield the interference of the subsequently formed signal line on the first plate C11 of the first capacitor C1. Since the first plate C11 of the first capacitor C1 is connected to the control electrode of the driving transistor T3, the second plate C12 of the first capacitor C1 can shield the crosstalk generated by the subsequently formed signal line (for example, the data signal line D) on the control electrode of the driving transistor T3, and to a certain extent, avoid the influence of the signal jump in the signal line including the data signal line on the voltage of the control electrode of the driving transistor T3.

[0144] In the exemplary embodiment, the second plate C22 of the second capacitor C2 is located within the projection on the substrate of the first plate C21 of the second capacitor C2.

[0145] In the exemplary embodiment, the ratio of the capacity of the first capacitor C1 to the capacity of the second capacitor C2 is 0.7 to 2. The capacity of the first capacitor C1 is close to the capacity of the second capacitor C2, which can to a certain extent reduce the numerical range of the voltage required by the data signal line, thereby avoiding high power consumption and avoiding the numerical range of the voltage required by the data signal line exceeding the voltage range provided by the driving chip.

[0146] In the example embodiment, the ratio of the first capacitance C1 to the second capacitance C2 is 1. That is, the first capacitance C1 is equal to the second capacitance C2, which can effectively reduce the range of the voltage required by the data signal line, avoid high power consumption, and avoid the range of the voltage required by the data signal line exceeding the voltage range provided by the driving chip.

[0147] In the example embodiment, the first capacitance C1 and the second capacitance C2 are each greater than or equal to 60 femtofarad (fF) and less than or equal to 300 femtofarad (fF). For example, the first capacitance C1 is one of 189 femtofarad, 167.8 femtofarad, 158 femtofarad, and 111.9 femtofarad, and the second capacitance C2 is one of 111.9 femtofarad, 150.5 femtofarad, 158 femtofarad, and 189 femtofarad.

[0148] The technical solutions of the embodiments of the present disclosure are described in detail below through specific examples.

[0149] In the example embodiment, as shown in FIGS. 5a-5c, the pixel driving circuit can include at least one capacitor;

[0150] In a direction perpendicular to the plane in which the substrate is located, the capacitor can include a first plate located on one side of the substrate and a second plate located on the side of the first plate away from the substrate; and the transistor can include an active layer located on the side of the second plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, a first electrode located on the side of the control electrode away from the substrate, and a second electrode located on the side of the control electrode away from the substrate.

[0151] In the same capacitor, the orthographic projection of the first plate on the substrate at least partially overlaps the orthographic projection of the second plate on the substrate.

[0152] In the example embodiment, the size L1 of the overlapping region of the control electrode and the active layer of the same driving transistor T3 in the first type of sub-pixel PL1 along the channel length direction is greater than the size L2 of the overlapping region of the control electrode and the active layer of the same driving transistor T3 in the second type of sub-pixel PL2 along the channel length direction.

[0153] The size W1 of the overlapping region of the control electrode and the active layer of the same driving transistor T3 in the first type of sub-pixel PL1 along the channel width direction is consistent with the size W2 of the overlapping region of the control electrode and the active layer of the same driving transistor T3 in the second type of sub-pixel PL2 along the channel width direction.

[0154] For example, in the first type of sub-pixel PL1, the size of the overlap region between the control electrode of the same driving transistor T3 and the active layer of the driving transistor T3 in the orthogonal projection of the substrate is L1 along the channel length direction and W1 along the channel width direction; in the second type of sub-pixel PL2, the size of the overlap region between the control electrode of the same driving transistor T3 and the active layer of the driving transistor T3 in the orthogonal projection of the substrate is L2 along the channel length direction and W2 along the channel width direction; in the structure where the value of L1 is greater than the value of L2 and the value of W1 is consistent with the value of W2 (for example, the value of W1 can be equal to the value of W2), the value of W1 / L1 is less than the value of W2 / L2.

[0155] In the exemplary embodiments, the size of the control electrode of the driving transistor T3 along the channel length direction (i.e., the second direction Y in FIGS. 5a-5c) in the first type of sub-pixel PL1 can be greater than the size of the control electrode of the driving transistor T3 along the channel length direction (i.e., the second direction Y in FIGS. 5a-5c) in the second type of sub-pixel PL2; the size of the control electrode of the driving transistor T3 along the channel width direction (i.e., the first direction X in FIGS. 5a-5c) in the first type of sub-pixel PL1 can be consistent with the size of the control electrode of the driving transistor T3 along the channel width direction (i.e., the first direction X in FIGS. 5a-5c) in the second type of sub-pixel PL2, and the shape and size of the active layer of the driving transistor T3 in the first type of sub-pixel PL1 can be consistent with the shape and size of the active layer of the driving transistor T3 in the second type of sub-pixel PL2, that is, the width-length ratio of the driving transistor T3 can be controlled by adjusting the size of the control electrode of the driving transistor T3 along the channel length direction, and thus the width-length ratio W1 / L1 of the channel of the driving transistor T3 in the first type of sub-pixel PL1 can be made less than the width-length ratio W2 / L2 of the channel of the driving transistor T3 in the second type of sub-pixel PL2 by adjusting the size of the control electrode of the driving transistor T3 along the channel length direction (i.e., the second direction Y in FIGS. 5a-5c) in the first type of sub-pixel PL1 and the second type of sub-pixel PL2.

[0156] In the exemplary embodiments, increasing the capacity of the capacitor connected to the driving transistor T3 can reduce the numerical range of the voltage required by the data signal line, reduce the maximum voltage required by the data signal line, and in the case of limited space of the display substrate, the capacity of the capacitor can be increased by setting the capacitor in a structure of multiple plate layers.

[0157] In the exemplary embodiments, as shown in FIGS. 6a and 6b, at least one capacitor Cn (n is a positive integer, for example, n is 1, representing the first capacitor C1) can further include a third plate Cn3 and a first transfer electrode ZL1, the third plate Cn3 can be disposed in the same layer as the control electrode of the transistor, and the first transfer electrode ZL1 can be disposed in the same layer as the first electrode and the second electrode of the transistor.

[0158] In the same capacitor Cn, the orthographic projection of the third plate Cn3 on the substrate can at least partially overlap the orthographic projection of the first plate Cn1 and the second plate Cn2 on the substrate, the first transfer electrode ZL1 can be connected with the third plate Cn3 and the first plate Cn1 through the via VM, and the third plate Cn3 and the first plate Cn1 can jointly serve as one of the plates of the capacitor Cn. In the premise of saving the display substrate space, the capacity of the capacitor Cn can be increased, the capacity of the capacitor can be increased in a smaller space (for example, the capacity of the same capacitor can occupy a smaller space by stacking), and the increase of the capacity of the capacitor is conducive to stabilizing the voltages of the first node N1 and the third node N3. In the structure shown in FIG. 6a, the first plate Cn1 and the third plate Cn3 can serve as one of the plates of the capacitor Cn, and the second plate Cn2 can serve as the other plate of the capacitor Cn.

[0159] In an example embodiment, as shown in FIG. 6b, at least one capacitor Cn can further include a fourth plate Cn4 and a fifth plate Cn5, the fourth plate Cn4 can be disposed in the same layer as the first electrode and the second electrode of the transistor, and the fifth plate Cn5 can be located on the side of the first plate Cn1 close to the substrate 101.

[0160] In the same capacitor Cn, the orthographic projection of the fourth plate Cn4 and the fifth plate Cn5 on the substrate 101 can at least partially overlap the orthographic projection of the first plate Cn1, the second plate Cn2 and the third plate Cn3 on the substrate 101, the fourth plate Cn4 can be connected with the second plate Cn2 and the fifth plate Cn5 through the via VM, and the second plate Cn2, the fourth plate Cn4 and the fifth plate Cn5 can jointly serve as one of the plates of the capacitor Cn. In the premise of saving the display substrate space, the capacity of the capacitor Cn can be increased. In the structure shown in FIG. 6b, the first plate Cn1 and the third plate Cn3 can serve as one of the plates of the capacitor Cn, and the second plate Cn2, the fourth plate Cn4 and the fifth plate Cn5 can serve as the other plate of the capacitor Cn.

[0161] In an example embodiment, the fifth plate Cn5 can be disposed in the same layer as the blocking layer (BSM), and the blocking layer can be located on the side of the first plate Cn1 close to the substrate 101.

[0162] In an example embodiment, as shown in FIGS. 6c-6e, the pixel driving circuit can include a first capacitor C1 and a second capacitor C2, a second plate C12 of the first capacitor C1 and a second plate C22 of the second capacitor C2 can be connected to each other through a connecting electrode, the connecting electrode can be located on a side of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 away from the substrate 101 in a direction Z perpendicular to a plane on which the substrate 101 is located; or, the first capacitor C1 and the second capacitor C2 share one second plate; at least one of the first capacitor C1 and the second capacitor C2 can include a third plate and a first transfer electrode ZL1. As shown in FIGS. 6c-6e, the first capacitor C1 and the second capacitor C2 share one second plate C12 / C22; as shown in FIG. 6c, the first capacitor C1 and the second capacitor C2 are both provided with a third plate C13 / C23 and a first transfer electrode ZL1; as shown in FIG. 6d, the first capacitor C1 is not provided with a third plate C13 and a first transfer electrode ZL1, and the second capacitor C2 is provided with a third plate C23 and a first transfer electrode ZL1; as shown in FIG. 6e, the first capacitor C1 is provided with a third plate C13 and a first transfer electrode ZL1, and the second capacitor C2 is not provided with a third plate C23 and a first transfer electrode ZL1. In an example embodiment, as shown in FIG. 6f, at least one capacitor Cn can further include a third plate Cn3, a fourth plate Cn4, and a second transfer electrode ZL2, the third plate Cn3 can be disposed in the same layer as the control electrode of the transistor, and the second transfer electrode ZL2 and the fourth plate Cn4 can be disposed in the same layer as the first electrode and the second electrode of the transistor;

[0163] In the same capacitor Cn, the second transfer electrode ZL2 can be connected to the second plate Cn2 and the third plate Cn3 through a via VM, the fourth plate Cn4 can be connected to the first plate Cn1 through a via VM, and the third plate Cn3 and the fourth plate Cn4 can at least partially overlap the first plate Cn1 and the second plate Cn2 in the substrate 101. The third plate Cn3 and the second plate Cn2 together serve as one of the plates of the capacitor Cn, and the first plate Cn1 and the fourth plate Cn4 together serve as the other plate of the capacitor Cn, which can increase the capacity of the capacitor Cn while saving space on the display substrate, increase the capacity of the capacitor in a smaller space (for example, the same capacity of the capacitor can occupy a smaller space by stacking), and the increase in the capacity of the capacitor is conducive to stabilizing the voltages of the first node N1 and the third node N3.

[0164] In an example embodiment, as shown in FIGS. 6g-6j, the pixel driving circuit can include a first capacitor C1 and a second capacitor C2, a second plate C12 of the first capacitor C1 and a second plate C22 of the second capacitor C2 can be connected to each other through a connecting electrode, the connecting electrode can be located on a side of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 away from the substrate 101 in a direction Z perpendicular to a plane on which the substrate 101 is located; or, the first capacitor C1 and the second capacitor C2 share one second plate.

[0165] At least one of the first capacitor C1 and the second capacitor C2 can include a third plate, a fourth plate, and a second transfer electrode ZL2.

[0166] As shown in FIG. 6g, each of the first capacitor C1 and the second capacitor C2 can include a third plate (C13, C23), a fourth plate (C14, C24), and a second transfer electrode ZL2, the first capacitor C1 and the second capacitor C2 share one second plate (i.e., C12 and C22 can be an integrated structure as a shared plate of the first capacitor C1 and the second capacitor C2), the third plate C13 of the first capacitor C1 is connected to the second plate C12 of the first capacitor C1 through the second transfer electrode ZL2, the third plate C23 of the second capacitor C2 is connected to the second plate C22 of the second capacitor C2 through the second transfer electrode ZL2, i.e., the second plate (C12 / C22) and the third plate (C13 / C23) of the first capacitor C1 and the second capacitor C2 can serve as one shared plate of the first capacitor C1 and the second capacitor C2, the other plate of the first capacitor C1 is composed of the first plate C11 and the fourth plate C14 of the first capacitor C1, the other plate of the second capacitor C2 is composed of the first plate C21 and the fourth plate C24 of the second capacitor C2, each plate in the first capacitor C1 and the second capacitor C2 is formed by stacking conductive structures in at least two conductive layers, which can increase the capacity of the capacitor, and can increase the capacity of the capacitor in a smaller space (e.g., the same capacity of the capacitor can occupy a smaller space by stacking), and the increase in the capacity of the capacitor is conducive to stabilizing the voltages of the first node N1 and the third node N3.

[0167] As shown in FIG. 6h, the difference from FIG. 6g is that the third plate C13 of the first capacitor C1 and the third plate C23 of the second capacitor C2 are connected through the second transfer electrode ZL2 and connected to the second plate (C12 / C22) shared by the first capacitor C1 and the second capacitor C2 through the second transfer electrode ZL2, the third plate C13 of the first capacitor C1 and the third plate C23 of the second capacitor C2 can be an integrated structure, or can be an independent structure.

[0168] As shown in FIG. 6i, the third plate C13, the fourth plate C14 and the second transfer electrode ZL2 are arranged in the first capacitor C1, and the third plate C23, the fourth plate C24 and the second transfer electrode ZL2 are arranged in the second capacitor C2; the third plate C13 and the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 constitute the common plate of the first capacitor C1 and the second capacitor C2, the fourth plate C14 and the first plate C11 of the first capacitor C1 constitute the other plate of the first capacitor C1, and the first plate C21 of the second capacitor C2 constitutes the other plate of the second capacitor C2.

[0169] As shown in FIG. 6j, the third plate C13, the fourth plate C14 and the second transfer electrode ZL2 are arranged in the first capacitor C1, and the third plate C23, the fourth plate C24 and the second transfer electrode ZL2 are arranged in the second capacitor C2; the third plate C13 and the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 constitute the common plate of the first capacitor C1 and the second capacitor C2, the fourth plate C14 and the first plate C11 of the first capacitor C1 constitute the other plate of the first capacitor C1, and the first plate C21 of the second capacitor C2 constitutes the other plate of the second capacitor C2.

[0170] In the example embodiment, by sharing the second plate by the first capacitor C1 and the second capacitor C2, the capacity of the capacitor can be effectively increased, and the expected capacity of the capacitor can be achieved with smaller space. The increase of the capacity of the capacitor is beneficial to reduce the Data Range on the one hand, and is beneficial to stabilize the voltage of the first node N1 and the third node N3 on the other hand, which is helpful to improve the image quality.

[0171] In the example embodiment, in the structures shown in FIGS. 6a to 6j, Buffer1 is the first buffer layer, GI1 is the first gate insulating layer, GI2 is the second gate insulating layer (which can be the first insulating layer described above), GI3 is the third gate insulating layer (which can be the second insulating layer and the third insulating layer described above), and ILD is the interlayer insulating layer (which can be the fourth insulating layer described above).

[0172] In the example embodiment, as shown in FIGS. 4a to 5c, the display substrate can further include a first initial signal line Vinit1, a second initial signal line Vinit2, a first power supply line VDD and a second power supply line VSS, and the plurality of transistors can include a first transistor T1 as a reset transistor, a second transistor T2 as a reset transistor, and a fifth transistor T5 as a light-emitting control transistor.

[0173] The first initial signal line Vinit1 and the second initial signal line Vinit2 can be arranged in the same layer as the first electrode and the second electrode of the transistor, and the first power supply line VDD and the second power supply line VSS can be located on the side of the first electrode and the second electrode of the transistor away from the substrate.

[0174] The first electrode of the first transistor T1 can be connected with the first initial signal line Vinit1, the second electrode of the second transistor T2 can be connected with the second initial signal line Vinit2, and the first electrode of the fifth transistor T5 can be connected with the first power supply line VDD; in the same pixel driving circuit, the second electrode of the fifth transistor T5 can be connected with the first electrode of the driving transistor T3, the first plate C11 of the first capacitor C1 can be connected with the control electrode of the driving transistor T3 and the second electrode of the first transistor T1, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be connected with the second electrode of the driving transistor T3, and the first plate C21 of the second capacitor C2 can be electrically connected with one of the first initial signal line Vinit1, the second initial signal line Vinit2, the first power supply line VDD and the second power supply line VSS, so that a signal line is not needed to be separately arranged to provide a signal to the first plate C21 of the second capacitor C2, and the space of the display substrate can be saved.

[0175] In an example embodiment, as shown in FIGS. 5a-5c, the first type of sub-pixel PL1 includes a first sub-pixel P1 and a second sub-pixel P2, and the second type of sub-pixel PL2 includes a third sub-pixel P3.

[0176] In an example embodiment, the first sub-pixel P1 can be a sub-pixel emitting red light, the second sub-pixel P2 can be a sub-pixel emitting green light, and the third sub-pixel P3 can be a sub-pixel emitting blue light.

[0177] In an example embodiment, the plurality of sub-pixels form a plurality of pixel units, and each pixel unit can include the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3.

[0178] In an example embodiment, the plurality of transistors can be oxide transistors.

[0179] In an example embodiment, as shown in FIGS. 4a-5c, the pixel driving circuit can include first to sixth transistors T1-T6, in the first direction X, the first transistor T1 (which can be a reset transistor) and the fourth transistor T4 can be located on the same side of the second transistor T2 (which can be a reset transistor), the third transistor T3 (which can be a driving transistor), the fifth transistor T5 (which can be a light-emitting control transistor), and the sixth transistor T6 (which can be a light-emitting control transistor); in the second direction Y, the first transistor T1 and the second transistor T2 can be located on the same side of the third transistor T3, the fourth transistor T4 and the fifth transistor T5 can be located on the other side of the third transistor T3, and the sixth transistor T6 can be located between the second transistor T2 and the third transistor T3.

[0180] In the pixel driving circuit shown in FIGS. 4a-4c, when the fourth transistor T4 is turned on and the data voltage Vdata is written into the first node N1, the voltage of the third node N3 will rise due to the coupling of the first capacitor C1;

[0181] The voltage of the third node N3 is: VN3=VVinit1-Vth+△N, wherein VVinit1 is the voltage of the first initial signal line Vinit1, Vth is the threshold voltage of the third transistor T3, VN3 is the voltage of the third node N3, and△N is the voltage difference;

[0182] The current flowing through the driving transistor T3 is: I=k(Vgs-Vth) 2 =k(VN1-VN3-Vth) 2

[0183] =k(Vdata-VVinit1-△N) 2 wherein I is the driving current flowing through the third transistor T3, k is a constant, Vgs is the voltage difference between the control electrode and the first electrode of the third transistor T3, VN1 is the voltage of the first node N1, Vdata is the data voltage output by the data signal line D, due to the series connection of the first capacitor C1 and the second capacitor C2, the second capacitor C2 has a certain voltage division effect, but△N still exists, the voltage VN3 of the third node N3 becomes larger, Vgs becomes smaller, and the current I becomes smaller. To achieve the same current I, the data voltage VData needs to be larger, which will cause the numerical range (Data Range) of the required voltage VData of the data signal line D to become larger. In the present embodiment, the width-length ratio of the driving transistor T3 is set and the capacity of the capacitor is increased, so that the numerical range (Data Range) of the data voltage VData provided by the data signal line D is reduced as much as possible under the condition that the current I is unchanged, and the numerical value of the maximum data voltage VData is reduced.

[0184] In the exemplary embodiment, for the pixel driving circuit of 6T2C, the width-length ratio (W / L) of the channel of the driving transistor of the first sub-pixel P1 (R), the second sub-pixel P2 (G), and the third sub-pixel P3 (B) is all set to 8 / 10. Simulation finds that the data voltage required by the second sub-pixel P2 for the picture at the L255 gray scale is large, which leads to a large Data Range value, which may cause the data voltage value to exceed the setting range of the Drive IC data value, and the large data voltage value leads to increased power consumption. By designing the width-length ratio (W / L) of the channel of the driving transistor of the first sub-pixel P1 (R), the second sub-pixel P2 (G), and the third sub-pixel P3 (B), for example, the Data Range of the third sub-pixel P3 (B) is large, which can be effectively reduced by reducing the width-length ratio W2 / L2 of the channel of the driving transistor of the third sub-pixel P3 (B). The Data Range (which can be understood as the difference between the maximum data voltage and the minimum data voltage provided by the data signal line D) of the third sub-pixel P3 (B) can be effectively reduced, as shown in Table 1:

[0185] Table 1

[0186] As can be seen from Table 1, in the structure in which the width-length ratio of the channel of the driving transistor of the first sub-pixel P1 (R), the second sub-pixel P2 (G), and the third sub-pixel P3 (B) is all 8 / 10, the voltage value required by the third sub-pixel P3 (B) at the gray scale L255 is 6.09V, and the Data Range is 5.18, which is much higher than the voltage values of the first sub-pixel P1 (R) and the second sub-pixel P2 (G). In the structure in which the width-length ratio of the channel of the driving transistor of the third sub-pixel P3 (B) is 8 / 6, the voltage value required by the third sub-pixel P3 (B) at the gray scale L255 is 5.27V, and the Data Range is 4.04V. That is, compared with the width-length ratio of 8 / 10, the width-length ratio of 8 / 6 of the channel of the driving transistor of the third sub-pixel P3 (B) leads to a voltage value of 5.27V required by the structure at the gray scale L255, and the value of the Data Range, which are both lower than those of the structure with the width-length ratio of 8 / 10. Thus, it can be seen that increasing the width-length ratio of the third sub-pixel P3 (B) can reduce the voltage value required at the gray scale L255 and the value of the Data Range.

[0187] In the pixel driving circuit of the 6T2C, the size and ratio of the first capacitor C1 and the second capacitor C2 can be adjusted to effectively adjust the Data Range. For example, the capacitances of C1 and C2 can be designed to be greater than 100 fF, and the ratio of C1:C2 can be between 0.7 and 2, for example, the ratio of C1:C2 can be 1:1. The influence of adjusting the capacitances and ratio of C1 and C2 on the Data Range can be shown in Table 2 and Table 3:

[0188] Table 2

[0189] Table 3

[0190] As can be seen from Table 2 and Table 3, when the ratio of the first capacitor C1 to the second capacitor C2 is 1:1, the required voltage at the L255 gray scale and the Data Range are the smallest. The greater the difference between the capacitances of the first capacitor C1 and the second capacitor C2, the greater the required voltage at the L255 gray scale and the Data Range. By setting the ratio of the first capacitor C1 to the second capacitor C2 within the range of 0.7 to 1.2, for example, the ratio of the first capacitor C1 to the second capacitor C2 is set to 1:1, the required voltage at the L255 gray scale and the Data Range can be reduced.

[0191] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal material, inorganic material or transparent conductive material, and includes coating organic material, mask exposure and development and the like for organic material. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate (or substrate substrate) made by deposition, coating or other processes. If the "thin film" does not need a patterning process during the entire manufacturing process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process during the entire manufacturing process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0192] In the exemplary embodiments, taking 3 sub-pixels (1 pixel driving circuit row of sub-pixels, 3 pixel driving circuit columns of sub-pixels) in the display area (AA) as an example, the preparation process of one kind of display substrate can include the following operations:

[0193] (101) A substrate is prepared on a glass carrier. In an example embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an example embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a bonding layer, a second flexible material layer, and a second inorganic material layer stacked together. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also called barrier layers, and the material of the bonding layer can be amorphous silicon (a-si). In an example embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, the preparation process can include: first coating a layer of polyimide on the glass carrier, and after curing into a film, a first flexible material (PI1) layer is formed; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating a layer of polyimide on the amorphous silicon layer, and after curing into a film, a second flexible material (PI2) layer is formed; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, and the preparation of the substrate is completed.

[0194] (102) A first conductive layer pattern is formed. In an example embodiment, forming the first conductive layer pattern can include: depositing a first conductive film on the substrate, patterning the first conductive film by a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG. 7, which is a schematic diagram of the planar structure of three sub-pixels after the first conductive layer is formed. The first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0195] In an example embodiment, the first conductive layer pattern can include at least: a first plate C11 of a first capacitor C1, and a first plate C21 of a second capacitor C2.

[0196] In the example embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be in a block structure, and the block structure can be in a polygonal shape. In the example embodiment, at least one edge of the polygonal block structure is a broken line. For example, the block structure can be in a rectangular shape, and at least one edge of the rectangle is a broken line. In the example embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be arranged in sequence in the second direction Y.

[0197] In the example embodiment, the first plate C11 of the first capacitor C1 is provided with a first connecting portion CL1, the first connecting portion CL1 is configured to accommodate a twelfth via hole formed subsequently, the orthogonal projection of the twelfth via hole on the substrate is within the range of the orthogonal projection of the first connecting portion CL1 on the substrate, and the surface of the first connecting portion CL1 is exposed, so that the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 formed subsequently are connected to the first plate C11 of the first capacitor C1 through the twelfth via hole and the first connecting portion CL1.

[0198] In the example embodiment, the first plate C21 of the second capacitor C1 is provided with a second connecting portion CL2, the second connecting portion CL2 is configured to accommodate a thirteenth via hole formed subsequently, the orthogonal projection of the thirteenth via hole on the substrate is within the range of the orthogonal projection of the second connecting portion CL2 on the substrate, and the surface of the second connecting portion CL2 is exposed, so that the first power connection line VDDL formed subsequently is connected to the first plate C21 of the second capacitor C2 through the thirteenth via hole and the second connecting portion CL2.

[0199] Taking the Mth row and the Nth column sub-pixel as an example, in the second direction Y, the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 in the sub-pixel close to the M+1th row sub-pixel.

[0200] (103) Forming a second conductive layer pattern. In the example embodiment, forming the second conductive layer pattern can include: sequentially depositing a first insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the second conductive film by a patterning process, forming a first insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the first insulating layer, as shown in FIGS. 8a and 8b, FIG. 8a is a planar structure diagram of three sub-pixels after the second conductive layer is formed, and FIG. 8b is a planar schematic diagram of the second conductive layer in FIG. 8a. In the example embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0201] In the example embodiment, the second conductive layer pattern comprises at least: the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, the first shielding line BL1, the second shielding line BL2, the first shielding structure BSM1, the second shielding structure BSM2, and the third shielding structure BSM3.

[0202] In the example embodiment, in the second direction Y, the second plate C12 of the first capacitor C1 is located on one side of the second plate C22 of the second capacitor C2 in the same sub-pixel, and the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are located between the first shielding line BL1 and the second shielding line BL2, for example, in the same sub-pixel, the second shielding line BL2, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, and the first shielding line BL1 can be arranged in sequence along the second direction Y.

[0203] In the example embodiment, in the same sub-pixel, in the second direction Y, the first shielding structure BSM1 is located between the second plate C22 of the second capacitor C2 and the second shielding line BL2, the second shielding structure BSM2 is located on the side of the second shielding line BL2 away from the second plate C22 of the second capacitor C2, and the third shielding structure BSM3 is located between the second plate C22 of the second capacitor C2 and the first shielding line BL1; in the first direction X, the third shielding structure BSM3 is located on the side of the second plate C22 of the second capacitor C2, for example, in the Mth row and Nth column sub-pixel: the third shielding structure BSM3 in the Nth column sub-pixel is located on the side of the second capacitor C2 in the column sub-pixel away from the N+1th column sub-pixel.

[0204] In the example embodiment, the first shielding line BL1 can be in the shape of a strip or a polyline, and the main body portion can extend along the first direction X; the first shielding line BL1 is configured as a shielding layer of the fifth transistor T5, shielding the channel of the fifth transistor T5, and ensuring the electrical performance of the oxide fifth transistor T5. In the example embodiment, the signal of the first shielding line BL1 and the first light-emitting control line EM1 formed subsequently can be the same, that is, the first shielding line BL1 and the first light-emitting control line EM1 formed subsequently are connected in parallel, both of which are connected to the same signal source, so that the first shielding line BL1 can be used as the bottom gate electrode (i.e., the bottom control electrode) of the fifth transistor T5, forming a double-gate structure of the fifth transistor T5.

[0205] In an example embodiment, the second shielding line BL2 can be in a strip shape or a broken line shape, and can extend along the first direction X. The second shielding line BL2 is configured to serve as a shielding layer of the sixth transistor T6, shield a channel of the sixth transistor T6, and ensure electrical performance of the oxide sixth transistor T6. In an example embodiment, the second shielding line BL2 can have the same signal as the second light-emitting control line EM2 formed subsequently, i.e., the second shielding line BL2 is connected in parallel with the second light-emitting control line EM2 formed subsequently, and both are connected to the same signal source, so that the second shielding line BL2 can serve as a bottom gate electrode (i.e., a bottom control electrode) of the sixth transistor T6, forming a double-gate structure of the sixth transistor T6.

[0206] In an example embodiment, the first shielding structure BSM1 can be in a strip shape or a broken line shape extending along the first direction X, and is configured to serve as a shielding layer of the first transistor T1, shield a channel of the first transistor T1, and ensure electrical performance of the oxide first transistor T1. In an example embodiment, the first shielding structure BSM1 can have the same signal as the first reset control line Reset1 formed subsequently, i.e., the first shielding structure BSM1 is connected to the first reset control line Reset1 formed subsequently, and is connected in parallel with a control electrode T1g of the first transistor T1 formed subsequently, both being connected to the same signal source, so that the first shielding structure BSM1 can serve as a bottom gate electrode (i.e., a bottom control electrode) of the first transistor T1, forming a double-gate structure of the first transistor T1.

[0207] In an example embodiment, the second shielding structure BSM2 can be in a strip shape or a broken line shape extending along the first direction X, and is configured to serve as a shielding layer of the second transistor T2, shield a channel of the second transistor T2, and ensure electrical performance of the oxide second transistor T2. In an example embodiment, the second shielding structure BSM2 can have the same signal as the second reset control line Reset2 formed subsequently, i.e., the second shielding structure BSM2 is connected to the second reset control line Reset2 formed subsequently, and is connected in parallel with a control electrode T2g of the second transistor T2 formed subsequently, both being connected to the same signal source, so that the second shielding structure BSM2 can serve as a bottom gate electrode (i.e., a bottom control electrode) of the second transistor T2, forming a double-gate structure of the second transistor T2.

[0208] In the example embodiment, the third shielding structure BSM3 can be a strip structure or a zigzag structure extending along the first direction X, configured as a shielding layer of the fourth transistor T4, shielding the channel of the fourth transistor T4, and ensuring the electrical performance of the oxide fourth transistor T4. In the example embodiment, the third shielding structure BSM3 can have the same signal as the subsequently formed scan signal line Gate, i.e., the third shielding structure BSM3 is connected to the subsequently formed scan signal line Gate, and is connected in parallel with the subsequently formed control electrode T4g of the fourth transistor T4, both of which are connected to the same signal source, so that the third shielding structure BSM3 can be used as the bottom gate electrode (i.e., the bottom control electrode) of the fourth transistor T4, forming a double-gate structure of the fourth transistor T4.

[0209] In the example embodiment, the profile of the second plate C12 of the first capacitor C1 can be consistent with the profile of the first plate C11 of the first capacitor C1, and the profile of the second plate C22 of the second capacitor C2 can be consistent with the profile of the first plate C21 of the second capacitor C2, for example, the profile of the second plate C12 of the first capacitor C1 and the profile of the second plate C22 of the second capacitor C2 can be polygonal (such as rectangular, and at least one edge of the rectangle is a zigzag). In the example embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate, for example, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate can be within the range of the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate can be within the range of the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate. In the example embodiment, the first plate C11 of the first capacitor C1 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 of the second capacitor C2 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0210] In the example embodiment, the third connection part CL3 can be provided on the second plate C22 of the second capacitor C2, and the third connection part CL3 is configured to accommodate the subsequently formed fourteenth via hole, the orthographic projection of the fourteenth via hole on the substrate is within the range of the orthographic projection of the third connection part CL3 on the substrate, and exposes the surface of the third connection part CL3, so that the second electrode of the subsequently formed third transistor T3 is connected to the second plate of the second capacitor C2 through the fourteenth via hole and the third connection part CL3.

[0211] In the example embodiment, the second plate C22 of the second capacitor C2 can shield the channel of the third transistor T3, ensuring the electrical performance of the oxide third transistor T3.

[0212] (104) Forming a semiconductor layer pattern. In the example embodiment, forming a semiconductor layer pattern can include: on the substrate on which the aforementioned pattern is formed, sequentially depositing a second insulating thin film and a semiconductor thin film, patterning the semiconductor thin film through a patterning process, forming a second insulating layer covering the substrate, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIGS. 9a and 9b, FIG. 9a is a planar structure diagram of three sub-pixels after forming a semiconductor layer, and FIG. 9b is a planar schematic diagram of the semiconductor layer in FIG. 9a.

[0213] In the example embodiment, the semiconductor layer pattern in at least part of the sub-pixels at least includes: an active layer AT1 of the first transistor T1 to an active layer AT6 of the sixth transistor T6.

[0214] In the example embodiment, in the same sub-pixel, the active layer AT2 of the second transistor T2 and the active layer AT6 of the sixth transistor T6 are connected to each other, and the active layer AT3 of the third transistor T3 and the active layer AT5 of the fifth transistor T5 can be connected to each other, for example, the active layer AT2 of the second transistor T2, the active layer AT6 of the sixth transistor T6, the active layer AT3 of the third transistor T3, and the active layer AT5 of the fifth transistor T5 can be an integrated structure connected to each other.

[0215] In the example embodiment, in the same sub-pixel, in the first direction X, the active layer of the first transistor T1 and the active layer AT4 of the fourth transistor T4 are located on the same side of the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6; in the second direction Y, the active layer AT4 of the fourth transistor T4 and the active layer AT5 of the fifth transistor T5 are located on the same side of the active layer AT1 of the first transistor T1 and the active layer AT2 of the second transistor T2, the active layer AT5 of the fifth transistor T5 and the active layer AT6 of the sixth transistor T6 are located on both sides of the active layer AT3 of the third transistor T3, and the active layer AT2 of the second transistor T2 is located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT3 of the third transistor T3.

[0216] In the exemplary embodiments, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" letter or a strip.

[0217] In the exemplary embodiments, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" letter or a strip.

[0218] In the exemplary embodiments, the active layer of at least part of the transistors can include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiments, the first region AT31 of the active layer AT3 of the third transistor T3 can serve as the second region AT52 of the active layer AT5 of the fifth transistor T5, the second region AT32 of the active layer AT3 of the third transistor T3 can serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT22 of the active layer AT2 of the second transistor T2, and the first region AT11 and the second region AT12 of the active layer AT1 of the first transistor T1, the first region AT21 of the active layer AT2 of the second transistor T2, the first region AT41 and the second region AT42 of the active layer AT4 of the fourth transistor T4, and the first region AT51 of the active layer AT5 of the fifth transistor T5 can be separately provided.

[0219] In the example embodiment, the conductor layer can adopt an oxide, i.e., the first to sixth transistors T1-T6 are oxide thin film transistors. In the example embodiment, the oxide can be any one or more of indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride oxide (InGaZnON), zinc oxide (ZnO), zinc nitride oxide (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfur oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film can adopt indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of the IGZO TFT is relatively small, the N-type transistor can be adopted to avoid the leakage of the first node N1 in the light emitting stage.

[0220] (105) Forming a third conductive layer pattern. In the example embodiment, forming the third conductive layer pattern can include: sequentially depositing a third insulating thin film and a third conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by using a patterning process, forming a third insulating layer covering the semiconductor layer, and a third conductive layer pattern disposed on the third insulating layer, as shown in FIGS. 10a-10b, FIG. 10a is a plan view of the three sub-pixels after the third conductive layer is formed, and FIG. 10b is a plan view of the third conductive layer in FIG. 10a. In the example embodiment, the third conductive layer can be referred to as a third gate metal (GATE3) layer.

[0221] In the example embodiment, the third conductive layer pattern at least includes: a first light emitting control line EM1, a second light emitting control line EM2, a control electrode T1g of the first transistor T1 to a control electrode T4g of the fourth transistor T4, the first light emitting control line EM1 and the second light emitting control line EM2 can be polyline or strip-shaped extending along the first direction X, in the same sub-pixel row, the second light emitting control line EM2 and the first light emitting control line EM1 can be arranged at intervals along the second direction Y, in the second direction Y, in the same sub-pixel, the control electrode T1g of the first transistor T1, the control electrode T3g of the third transistor T3, and the control electrode T4g of the fourth transistor T4 are located between the first light emitting control line EM1 and the second light emitting control line EM2, and the control electrode T2g of the second transistor T2 is located on the side of the second light emitting control line EM2 away from the first light emitting control line EM1.

[0222] In the example embodiment, the region where the first light-emitting control line EM1 overlaps with the active layer AT5 of the fifth transistor T5 can serve as the control electrode of the fifth transistor T5, and the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the control electrode of the sixth transistor T6. In the example embodiment, the orthographic projection of the first light-emitting control line EM1 on the substrate at least partially overlaps with the orthographic projection of the first shielding line BL1 on the substrate, and the orthographic projection of the second light-emitting control line EM2 on the substrate at least partially overlaps with the orthographic projection of the second shielding line BL2 on the substrate, for example, the orthographic projection of the first light-emitting control line EM1 on the substrate can be within the range of the orthographic projection of the first shielding line BL1 on the substrate, and the orthographic projection of the second light-emitting control line EM2 on the substrate can be within the range of the orthographic projection of the second shielding line BL2 on the substrate, which can save the space of the display substrate and improve the utilization rate of the space of the display substrate.

[0223] In the example embodiment, the orthographic projection of the control electrode T1g of the first transistor T1 on the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 on the substrate, the orthographic projection of the control electrode T2g of the second transistor T2 on the substrate at least partially overlaps with the orthographic projection of the active layer AT2 of the second transistor T2 on the substrate, the orthographic projection of the control electrode T3g of the third transistor T3 on the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 on the substrate, and the orthographic projection of the control electrode T4g of the fourth transistor T4 on the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 on the substrate.

[0224] In the example embodiment, in the same sub-pixel, in the second direction Y, the control electrode T1g of the first transistor T1, the control electrode T3g of the third transistor T3, and the control electrode T4g of the fourth transistor T4 are located between the first light-emitting control line EM1 and the second light-emitting control line EM2, the control electrode T2g of the second transistor T2 is located on the side of the second light-emitting control line EM2 away from the first light-emitting control line EM1, the control electrode T1g of the first transistor T1 is located between the second light-emitting control line EM2 and the control electrode T4g of the fourth transistor T4, and the control electrode T3g of the third transistor T3 is located between the control electrode T1g of the first transistor T1 and the control electrode T4g of the fourth transistor T4; in the first direction X, in the same sub-pixel, the control electrode T1g of the first transistor T1 and the control electrode T4g of the fourth transistor T4 are located on the same side of the control electrode T3g of the third transistor T3.

[0225] In the exemplary embodiments, after the third conductive layer pattern is formed, the semiconductor layer can be subjected to a conductorization process using the third conductive layer as a shield, the semiconductor layer in the region shielded by the third conductive layer forms the channel region of the first transistor T1 to the sixth transistor T6, and the semiconductor layer in the region not shielded by the third conductive layer is conductorized, i.e., the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT6 of the sixth transistor T6 are conductorized.

[0226] (106) The fourth insulating layer pattern is formed. In the exemplary embodiments, forming the fourth insulating layer pattern can include: depositing a fourth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fourth insulating thin film to form the fourth insulating layer covering the third conductive layer, the fourth insulating layer being provided with a plurality of vias, as shown in FIG. 11, which is a planar structure diagram of the three sub-pixels after the fourth insulating layer is formed.

[0227] In the exemplary embodiments, the plurality of vias in at least part of the sub-pixels at least include: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, and a nineteenth via V19.

[0228] In the exemplary embodiments, the orthographic projection of the first via V1 on the substrate is located within the orthographic projection of the active layer AT1 of the first transistor T1 on the substrate, the fourth insulating layer and the third insulating layer in the first via V1 are etched away, and the surface of the first region AT11 of the active layer AT1 of the first transistor T1 is exposed. The first via V1 is configured to enable the first electrode of the first transistor T1 formed subsequently to be connected to the active layer AT1 of the first transistor T1 through the via.

[0229] In the exemplary embodiments, the orthographic projection of the second via V2 on the substrate is located within the orthographic projection of the active layer AT1 of the first transistor T1 on the substrate, the fourth insulating layer, the third insulating layer, and the second region AT12 of the active layer AT1 of the first transistor T1 in the second via V2 are etched away, and the surface of the second region AT12 of the active layer AT1 of the first transistor T1 is exposed. The second via V2 is configured to enable the second electrode of the first transistor T1 formed subsequently to be connected to the active layer AT1 of the first transistor T1 through the via.

[0230] In an example embodiment, the third via V3 has a footprint on the substrate within a footprint of the active layer AT2 of the second transistor T2 on the substrate, the fourth insulating layer and the third insulating layer within the third via V3 are etched away, exposing a surface of the second region AT22 of the active layer AT2 of the second transistor T2. The third via V3 is configured to enable a first electrode of the second transistor T2 to be formed subsequently to be connected to the active layer AT2 of the second transistor T2 through the via.

[0231] In an example embodiment, the fourth via V4 has a footprint on the substrate within a footprint of the active layer AT2 of the second transistor T2 (also the second region AT62 of the active layer AT6 of the sixth transistor T6) on the substrate, the fourth insulating layer and the third insulating layer within the fourth via V4 are etched away, exposing a surface of the second region AT22 of the active layer AT2 of the second transistor T2 (also the second region AT62 of the active layer AT6 of the sixth transistor T6). The fourth via V4 is configured to enable a second electrode of the second transistor T2 to be formed subsequently to be connected to the active layer AT2 of the second transistor T2 through the via, and to enable a second electrode of the sixth transistor T6 to be formed subsequently to be connected to the active layer AT6 of the sixth transistor T6 through the via.

[0232] In an example embodiment, the fifth via V5 has a footprint on the substrate within a footprint of the active layer AT3 of the third transistor T3 on the substrate, the fourth insulating layer and the third insulating layer within the fifth via V5 are etched away, exposing a surface of the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6). The fifth via V5 is configured to enable a second electrode of the third transistor T3 to be formed subsequently to be connected to the active layer AT3 of the third transistor T3 through the via, and to enable a first electrode of the sixth transistor T6 to be formed subsequently to be connected to the active layer AT6 of the sixth transistor T6 through the via.

[0233] In an example embodiment, the sixth via V6 has a footprint on the substrate within a footprint of the active layer AT4 of the fourth transistor T4 on the substrate, the fourth insulating layer and the third insulating layer within the sixth via V6 are etched away, exposing the first region AT41 of the active layer AT4 of the fourth transistor T4. The sixth via V6 is configured to enable a first electrode of the fourth transistor T4 to be formed subsequently to be connected to the active layer AT4 of the fourth transistor T4 through the via.

[0234] In an exemplary embodiment, the seventh via V7 is configured such that a second electrode of the fourth transistor T4 to be formed subsequently is connected to the active layer AT4 of the fourth transistor T4 through the via.

[0235] In an exemplary embodiment, the eighth via V8 is configured such that a first electrode of the fifth transistor T5 to be formed subsequently is connected to the active layer AT5 of the fifth transistor T5 through the via.

[0236] In an exemplary embodiment, the ninth via V9 is configured such that the first reset control line Resetl to be formed subsequently is connected to the first blocking structure BSMl through the via.

[0237] In an exemplary embodiment, the tenth via V10 is configured such that the second reset control line Reset2 to be formed subsequently is connected to the second blocking structure BSM2 through the via.

[0238] In an exemplary embodiment, the eleventh via V11 is configured such that the first electrode of the fourth transistor T4 to be formed subsequently is connected to the third blocking structure BSM3 through the via.

[0239] In the example embodiment, the normal projection of the twelfth via V12 on the substrate is located within the range of the normal projection of the first plate C11 of the first capacitor C1 on the substrate (the normal projection of the twelfth via V12 on the substrate can be located within the range of the normal projection of the first connecting portion CL1 on the substrate), the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the twelfth via V12 are etched away, and the surface of the first plate C11 of the first capacitor C1 is exposed. The twelfth via V12 is configured to enable the second electrode of the first transistor T1 (also the second electrode of the fourth transistor T4) formed subsequently to be connected to the first plate C11 of the first capacitor C1 through the via.

[0240] In the example embodiment, the normal projection of the thirteenth via V13 on the substrate is located within the range of the normal projection of the first plate C21 of the second capacitor C2 on the substrate (the normal projection of the thirteenth via V13 on the substrate can be located within the range of the normal projection of the second connecting portion CL2 on the substrate), the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer within the thirteenth via V13 are etched away, and the surface of the first plate C21 of the second capacitor C2 is exposed. The thirteenth via V13 is configured to enable the first power supply connecting line VDDL formed subsequently to be connected to the first plate C21 of the second capacitor C2 through the via.

[0241] In the example embodiment, the normal projection of the fourteenth via V14 on the substrate is located within the range of the normal projection of the second plate C22 of the second capacitor C2 on the substrate (the normal projection of the fourteenth via V14 on the substrate can be located within the range of the normal projection of the third connecting portion CL3 on the substrate), the fourth insulating layer, the third insulating layer and the second insulating layer within the fourteenth via V14 are etched away, and the surface of the second plate C22 of the second capacitor C2 is exposed. The fourteenth via V14 is configured to enable the second electrode of the third transistor T3 (also the first electrode of the sixth transistor T6) formed subsequently to be connected to the second plate C22 of the second capacitor C2 through the via.

[0242] In the example embodiment, the normal projection of the fifteenth via V15 on the substrate is located within the range of the normal projection of the second plate C12 of the first capacitor C1 on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifteenth via V15 are etched away, and the surface of the second plate C12 of the first capacitor C1 is exposed. The fifteenth via V15 is configured to enable the second electrode of the third transistor T3 (also the first electrode of the sixth transistor T6) formed subsequently to be connected to the second plate C12 of the first capacitor C1 through the via.

[0243] In the exemplary embodiment, the normal projection of the sixteenth via V16 on the substrate is located within the range of the normal projection of the control electrode T1g of the first transistor T1 on the substrate, the fourth insulating layer within the sixteenth via V16 is etched away, exposing the surface of the control electrode T1g of the first transistor T1. The sixteenth via V16 is configured to enable the first reset control line Reset1 formed subsequently to pass through the via and connect with the control electrode T1g of the first transistor T1.

[0244] In the exemplary embodiment, the normal projection of the seventeenth via V17 on the substrate is located within the range of the normal projection of the control electrode T2g of the second transistor T2 on the substrate, the fourth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the control electrode T2g of the second transistor T2. The seventeenth via V17 is configured to enable the second reset control line Reset2 formed subsequently to pass through the via and connect with the control electrode T2g of the second transistor T2.

[0245] In the exemplary embodiment, the normal projection of the eighteenth via V18 on the substrate is located within the range of the normal projection of the control electrode T3g of the third transistor T3 on the substrate, the fourth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the control electrode T3g of the third transistor T3. The eighteenth via V18 is configured to enable the second electrode of the first transistor T1 (also the second electrode of the fourth transistor T4) formed subsequently to pass through the via and connect with the control electrode T3g of the third transistor T3.

[0246] In the exemplary embodiment, the normal projection of the nineteenth via V19 on the substrate is located within the range of the normal projection of the control electrode T4g of the fourth transistor T4 on the substrate, the fourth insulating layer within the nineteenth via V19 is etched away, exposing the surface of the control electrode T4g of the fourth transistor T4. The nineteenth via V19 is configured to enable the scan signal line Gate formed subsequently to pass through the via and connect with the control electrode T4g of the fourth transistor T4.

[0247] (107) Forming a fourth conductive layer pattern. In the exemplary embodiment, forming the fourth conductive layer can include: on the substrate on which the aforementioned pattern is formed, depositing a fourth conductive thin film, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer disposed on the fourth insulating layer, as shown in FIGS. 12a and 12b, FIG. 12a is a planar structure diagram of three sub-pixels after the fourth conductive layer is formed, and FIG. 12b is a planar schematic diagram of the fourth conductive layer in FIG. 12a. In the exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0248] In the example embodiment, the fourth conductive layer at least includes: a first power connection line VDDL, a scanning signal line Gate, a second power connection line VSSL, a first reset control line Reset1, a first initial signal line Vinit1, a second reset control line Reset2, a second initial signal line Vinit2, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, and a fourth connection electrode L4.

[0249] In the example embodiment, the main body part of the first power connection line VDDL, the scanning signal line Gate, the second power connection line VSSL, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be a strip-shaped structure or a broken line-shaped structure extending along the first direction X, and the first power connection line VDDL, the scanning signal line Gate, the second power connection line VSSL, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be arranged in sequence along the opposite direction of the second direction Y.

[0250] In the example embodiment, in the same sub-pixel, along the second direction Y, the first connection electrode L1 is located between the first power connection line VDDL and the scanning signal line Gate, the second connection electrode L2 and the third connection electrode L3 are located between the scanning signal line Gate and the second power connection line VSSL, and the fourth connection electrode L4 is located between the first reset control line Reset1 and the first initial signal line Vinit1.

[0251] In the example embodiment, the first power connection line VDDL can be connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 in the row of sub-pixels through the eighth via V8 in the row of sub-pixels, and connected to the first plate C21 of the second capacitor C2 in the row of sub-pixels through the thirteenth via V13 in the row of sub-pixels. In the example embodiment, the first power connection line VDDL can be set as the first electrode of the fifth transistor T5 to provide the first power voltage to the plurality of fifth transistors T5 and the first plate C21 of the second capacitor C2 in the same sub-pixel. In the same sub-pixel, the first area AT51 of the active layer AT5 of the fifth transistor T5 and the second plate C22 of the second capacitor C2 can be electrically connected through the first power connection line VDDL, so that the first area AT51 of the active layer AT5 of the fifth transistor T5 and the first plate C21 of the second capacitor C2 in the same sub-pixel have the same potential.

[0252] In the example embodiment, the scan signal line Gate can be connected with the control electrode T4g of the fourth transistor T4 in the row of sub-pixels through the nineteenth via V19 in the row of sub-pixels, and connected with the third shielding structure BSM3 in the row of sub-pixels through the eleventh via V11 in the row of sub-pixels, and be configured to provide the scan signal to the control electrodes T4g of the plurality of fourth transistors T4 and the plurality of third shielding structures BSM3 in the row of sub-pixels. In the same sub-pixel, the control electrode T4g of the fourth transistor T4 and the third shielding structure BSM3 can be electrically connected through the scan signal line Gate, so that the control electrode T4g of the fourth transistor T4 and the third shielding structure BSM3 in the same sub-pixel have the same potential.

[0253] In the example embodiment, the second power supply connection line VSSL can be connected with the plurality of second power supply lines formed subsequently, at least part of the second power supply connection line VSSL is electrically connected with the plurality of second power supply lines, at least part of the second power supply lines is electrically connected with the plurality of second power supply connection lines VSSL, at least part of the second power supply connection lines VSSL and at least part of the second power supply lines are connected to form a grid-shaped structure, which can reduce the voltage drop of the second power supply lines and improve the display uniformity of the display substrate.

[0254] In the example embodiment, the first reset control line Reset1 can be connected with the control electrode T1g of the first transistor T1 in the row of sub-pixels through the sixteenth via V16 in the row of sub-pixels, and connected with the first shielding structure BSM1 in the row of sub-pixels through the ninth via V9 in the row of sub-pixels, and be configured to provide the first reset control signal to the control electrodes T1g of the plurality of first transistors T1 and the plurality of first shielding structures BSM1 in the row of sub-pixels. In the same sub-pixel, the control electrode T1g of the first transistor T1 and the first shielding structure BSM1 can be electrically connected through the second reset control line Reset2, so that the control electrode T1g of the first transistor T1 and the first shielding structure BSM1 in the same sub-pixel have the same potential.

[0255] In the example embodiment, the first initial signal line Vinit1 can be connected with the first region AT11 of the active layer AT1 of the first transistor T1 in the row of sub-pixels through the first via V1 in the row of sub-pixels, and be configured to provide the first initial signal to the first transistor T1 in the row of sub-pixels. In the example embodiment, the first initial signal line Vinit1 can be the first electrode of the first transistor T1.

[0256] In the example embodiment, the second reset control line Reset2 can be connected with the control electrode T2g of the second transistor T2 in a row of sub-pixels through the seventeenth via V17 in the row of sub-pixels, and with the second shielding structure BSM2 in the row of sub-pixels through the tenth via V10 in the row of sub-pixels, and be configured to provide the second reset control signal to the control electrodes T2g of the plurality of second transistors T2 and the second shielding structure BSM2 in the row of sub-pixels. In the same sub-pixel, the control electrode T2g of the second transistor T2 and the second shielding structure BSM2 can be electrically connected through the second reset control line Reset2, so that the control electrode T2g of the second transistor T2 and the second shielding structure BSM2 in the same sub-pixel have the same electric potential.

[0257] In the example embodiment, the second initial signal line Vinit2 can be connected with the first region AT21 of the active layer AT2 of the second transistor T2 in a row of sub-pixels through the third via V3 in the row of sub-pixels, and be configured to provide the second initial signal to the second transistor T2 in the row of sub-pixels. In the example embodiment, the second initial signal line Vinit2 can be the first electrode of the second transistor T2.

[0258] In the example embodiment, the first connection electrode L1 is connected with the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In the example embodiment, the first connection electrode L1 can be the first electrode of the fourth transistor T4, and be configured to be connected with the data signal line formed subsequently.

[0259] In the example embodiment, the second connection electrode L2 has a shape of approximately "L" character, and is connected with the second region AT12 of the active layer AT1 of the first transistor T1 through the second via V2, with the first plate C11 of the first capacitor C1 through the twelfth via V12, with the second region AT42 of the active layer AT4 of the fourth transistor T4 through the seventh via V7, and with the control electrode T3g of the third transistor T3 through the eighteenth via V18. The second region AT12 of the active layer AT1 of the first transistor T1, the first plate C11 of the first capacitor C1, the second region AT42 of the active layer AT4 of the fourth transistor T4, and the control electrode T3g of the third transistor T3 can be electrically connected through the second connection electrode L2, so that the second electrode of the first transistor T1, the first plate C11 of the first capacitor C1, the second electrode of the fourth transistor T4, and the control electrode T3g of the third transistor T3 in the same sub-pixel have the same electric potential. In the example embodiment, the second connection electrode L2 can be the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4.

[0260] In the example embodiment, the third connection electrode L3 is substantially in the shape of an "L" character, and the third connection electrode L3 is connected to the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fifth via V5, to the second plate C12 of the first capacitor C1 through the fifteenth via V15, and to the second plate C22 of the second capacitor C2 through the fourteenth via V14, so that the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6), the second plate C12 of the first capacitor C1, and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same potential. In the example embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0261] In the example embodiment, the fourth connection electrode L4 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT22 of the active layer AT2 of the second transistor T2) through the fourth via V4. In the example embodiment, the fourth connection electrode L4 can serve as the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2, and the fourth connection electrode L4 is configured to be connected to the anode connection electrode of the light-emitting element formed subsequently.

[0262] (108) Forming the fifth insulating layer and the first planar layer pattern. In the example embodiment, forming the fifth insulating layer and the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, first depositing a fifth insulating thin film, then coating a first planar thin film, and patterning the first planar thin film and the fifth insulating thin film by using a patterning process to form the fifth insulating layer covering the fourth conductive layer pattern and the first planar layer disposed on the fifth insulating layer, and the fifth insulating layer and the first planar layer are provided with a plurality of vias, as shown in FIG. 13, which is a planar structure diagram of the three sub-pixels after the first planar layer is formed.

[0263] In the example embodiment, the plurality of vias in each sub-pixel can at least include: a twentieth via V20, a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, and a twenty-fifth via V25.

[0264] In the example embodiment, the orthogonal projection of the twentieth via V20 on the substrate is within the range of the orthogonal projection of the fourth connection electrode L4 on the substrate, and the first planar layer and the fifth insulating layer in the twentieth via V20 are etched away to expose the surface of the fourth connection electrode L4. The twentieth via V20 is configured to allow the anode connection electrode of the light-emitting element formed subsequently to be electrically connected to the fourth connection electrode L4 through the via.

[0265] In an example embodiment, a twenty-first via V21 has a footprint on the substrate within a footprint of the first power connection line VDDL on the substrate, and the first planar layer and the fifth insulating layer within the twenty-first via V21 are etched away to expose a surface of the first power connection line VDDL. The twenty-first via V21 is configured to enable a first power line formed subsequently to be connected to the first power connection line VDDL through the via.

[0266] In an example embodiment, a twenty-second via V22 has a footprint on the substrate within a footprint of the first connection electrode L1 on the substrate, and the first planar layer and the fifth insulating layer within the twenty-second via V22 are etched away to expose a surface of the first connection electrode L1. The twenty-second via V22 is configured to enable a data signal line formed subsequently to be electrically connected to the first connection electrode L1 through the via.

[0267] In an example embodiment, a twenty-third via V23 has a footprint on the substrate within a footprint of the first initial signal line Vinit1 on the substrate, and the first planar layer and the fifth insulating layer within the twenty-third via V23 are etched away to expose a surface of the first initial signal line Vinit1. The twenty-third via V23 is configured to enable a first initial signal connection line formed subsequently to be connected to the first initial signal line Vinit1 through the via.

[0268] In an example embodiment, a twenty-fourth via V24 has a footprint on the substrate within a footprint of the second initial signal line Vinit2 on the substrate, and the first planar layer and the fifth insulating layer within the twenty-fourth via V24 are etched away to expose a surface of the second initial signal line Vinit2. The twenty-fourth via V24 is configured to enable a second initial signal connection line formed subsequently to be electrically connected to the second initial signal line Vinit2 through the via.

[0269] In an example embodiment, a twenty-fifth via V25 has a footprint on the substrate within a footprint of the second power connection line VSSL on the substrate, and the first planar layer and the fifth insulating layer within the twenty-fifth via V25 are etched away to expose a surface of the second power connection line VSSL. The twenty-fifth via V25 is configured to enable a second power line formed subsequently to be connected to the second power connection line VSSL through the via.

[0270] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer can include: on the substrate on which the aforementioned patterns are formed, depositing a fifth conductive thin film, patterning the fifth conductive thin film by using a patterning process, forming the fifth conductive layer disposed on the first planar layer, as shown in FIGS. 14a-14b, FIG. 14a is a plan view of three sub-pixels after the fifth conductive layer is formed, and FIG. 14b is a plan view of the fifth conductive layer in FIG. 14a. In an exemplary embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0271] In an exemplary embodiment, the fifth conductive layer at least includes: a data signal line D, a first power supply line VDD, a second power supply line VSS, a first initial signal connection line Vinit1L, an anode connection electrode ZL, and a second initial signal connection line Vinit2L.

[0272] In an exemplary embodiment, the data signal line D is a polyline shape with a main body portion extending along the second direction Y, and the data signal line D is connected to the first connection electrode L1 through the twenty-second via V22. Since the first connection electrode L1 is connected to the first area AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection of the data signal line D to the first electrode of the fourth transistor T4 is achieved, and the data signal is written into the fourth transistor T4.

[0273] In an exemplary embodiment, the first power supply line VDD is a polyline shape with a main body portion extending along the second direction Y, and the first power supply line VDD is connected to the first power supply connection line VDDL through the twenty-first via V21. Since the first power supply connection line VDDL is connected to the first area AT51 of the active layer AT5 of the fifth transistor T5 and the first plate C21 of the second capacitor C2 through the via, the connection of the first power supply line VDD to the fifth transistor T5 and the first plate C21 of the second capacitor C2 is achieved, and the power supply signal is written into the first electrode of the fifth transistor T5 and the first plate C21 of the second capacitor C2. In an exemplary embodiment, at least part of the first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD, at least part of the first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and at least part of the first power supply line is connected to at least part of the first power supply connection line VDDL to form a grid-like structure, which can reduce the voltage drop of the first power supply line VDD, so that the first power supply signals received by a plurality of sub-pixels in the display substrate are substantially consistent, and the display uniformity of the display substrate is improved; for example, each first power supply connection line VDDL is electrically connected to a plurality of first power supply lines VDD located in a plurality of pixel driving circuits, each first power supply line VDD is electrically connected to a plurality of first power supply connection lines VDDL, and a plurality of first power supply lines are connected to a plurality of first power supply connection lines VDDL to form a grid-like structure.

[0274] In the example embodiment, the anode connecting electrode ZL can be in the shape of an "I" or a strip structure, and the anode connecting electrode ZL is connected to the fourth connecting electrode L4 through the twentieth via V20. Since the fourth connecting electrode L4 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (also the second region AT22 of the active layer AT2 of the second transistor T2) through the via, the connection of the anode connecting electrode ZL to the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2 is achieved.

[0275] In the example embodiment, the first initial signal connection line Vinit1L is in the shape of a broken line extending along the second direction Y, and the first initial signal connection line Vinit1L is connected to the first initial signal line Vinit1 through the twenty-third via V23. The plurality of first initial signal connection lines Vinit1L are connected to the plurality of first initial signal lines Vinit1 to form a grid structure, so that the first initial signals received by the first transistors T1 in adjacent sub-pixels are substantially consistent, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0276] In the example embodiment, the second initial signal connection line Vinit2L is in the shape of a broken line extending along the second direction Y, and the second initial signal connection line Vinit2L is connected to the second initial signal line Vinit2 through the twenty-fourth via V24. The plurality of second initial signal connection lines Vinit2L are connected to the plurality of second initial signal lines Vinit2 to form a grid structure, so that the second initial signals received by the second transistors T2 in adjacent sub-pixels are substantially consistent, which is conducive to improving the uniformity of panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0277] In an example embodiment, the second power supply lines VSS are in a shape of a broken line extending along the second direction, the second power supply lines VSS can be connected to the second power supply connection lines VSSL through the twenty-fifth via holes V25, at least part of the second power supply connection lines VSSL are electrically connected to the plurality of second power supply lines VSS, at least part of the second power supply lines VSS are electrically connected to the plurality of second power supply connection lines VSSL located in the plurality of pixel driving circuits, at least part of the second power supply connection lines VSSL and at least part of the second power supply lines VSS are connected to each other to form a grid structure, which can reduce the voltage drop of the second power supply lines VSS and improve the display uniformity of the display substrate; for example, each of the second power supply connection lines VSSL is electrically connected to the plurality of second power supply lines VSS, each of the second power supply lines VSS is electrically connected to the plurality of second power supply connection lines VSSL located in the plurality of pixel driving circuits, and the plurality of second power supply connection lines VSSL and the plurality of second power supply lines VSS are connected to each other to form a grid structure. In an example embodiment, the display substrate can include a display area and a frame area located at the periphery of the display area, the display area can be provided with a plurality of sub-pixels, and the frame area can be provided with a second power supply signal line, in the first direction X, the second power supply connection line VSSL can be electrically connected to the second power supply signal line located at the two sides of the display area, and in the second direction Y, the second power supply line VSS can be electrically connected to the second power supply signal line located at the two sides of the display area.

[0278] In an example embodiment, in the same pixel unit, the first power supply line VDD, the first initial signal connection line Vinit1L and the second initial signal connection line Vinit2L can be arranged in the first direction X in sequence and are respectively arranged in the three sub-pixels of the pixel unit, for example, the first power supply line VDD is located in the first sub-pixel, the first initial signal connection line Vinit1L is located in the second sub-pixel, and the second initial signal connection line Vinit2L is located in the third sub-pixel, and each sub-pixel is provided with one second power supply line VSS and one data signal line D. In the first direction X, the data signal line D and the second power supply line VSS of the first sub-pixel are located at the two sides of the first power supply line VDD, the data signal line D and the second power supply line VSS of the second sub-pixel are located at the two sides of the first initial signal connection line Vinit1L, the data signal line D and the second power supply line VSS of the third sub-pixel are located at the two sides of the second initial signal connection line Vinit2L, the anode connection electrode ZL in the first sub-pixel is located between the first power supply line VDD and the second power supply line VSS, the anode connection electrode ZL in the second sub-pixel is located between the first initial signal connection line Vinit1L and the second power supply line VSS, and the anode connection electrode ZL in the third sub-pixel is located between the second initial signal connection line Vinit2L and the second power supply line VSS.

[0279] So far, the driving circuit layer is prepared on the substrate, and the driving circuit layer is provided with pixel driving circuits of a plurality of sub-pixels. FIGS. 7 to 14b show the planar structure schematic diagram of the pixel driving circuit of the sub-pixel in the display substrate. In an exemplary embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer arranged in sequence on the substrate.

[0280] In an exemplary embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer can include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a first planar layer. The first insulating layer is arranged between the first conductive layer and the second conductive layer, the second insulating layer is arranged between the second conductive layer and the semiconductor layer, the third insulating layer is arranged between the semiconductor layer and the third conductive layer, the fourth insulating layer is arranged between the third conductive layer and the fourth conductive layer, and the fifth insulating layer and the first planar layer are arranged between the fourth conductive layer and the fifth conductive layer.

[0281] In an exemplary embodiment, after the driving circuit layer is prepared, a light-emitting structure layer is prepared on the driving circuit layer. The preparation process of the light-emitting structure layer can include the following operations. A second planar layer pattern is formed, and the second planar layer is provided with at least an anode via hole. An anode pattern (i.e., an anode conductive layer) is formed, and the anode is connected to the anode connection electrode through the anode via hole. An anode pixel definition layer is formed, and the pixel definition layer is provided with a pixel opening that exposes the anode. An organic light-emitting layer is formed by using a vapor deposition or inkjet printing process, and a cathode is formed on the organic light-emitting layer. An encapsulation layer is formed, which can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer arranged in sequence. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer, which can prevent external water vapor from entering the light-emitting structure layer. The step of forming the anode conductive layer is as follows:

[0282] (110) Forming a second planar layer pattern. In an exemplary embodiment, forming a second planar layer pattern can include: on the substrate on which the aforementioned pattern is formed, coating a second planar film, and patterning the second planar film by using a patterning process to form a second planar layer covering the fifth conductive layer pattern. The second planar layer is provided with a plurality of via holes, as shown in FIG. 15, which is a planar structure diagram of three sub-pixels after the second planar layer is formed.

[0283] In an exemplary embodiment, the plurality of via holes can include at least a twenty-sixth via hole V26.

[0284] In an example embodiment, the via of each sub-pixel includes at least a twenty-sixth via V26. The orthogonal projection of the twenty-sixth via V26 on the substrate is within the range of the orthogonal projection of the anode connecting electrode ZL on the substrate, the second planar layer in the twenty-sixth via V26 is removed to expose the surface of the anode connecting electrode ZL, and the twenty-sixth via V26 is configured to enable the subsequently formed anode to be electrically connected to the anode connecting electrode ZL through the via.

[0285] (111) Forming an anode conductive layer pattern. In an example embodiment, forming the anode conductive layer pattern can include: depositing an anode conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the anode conductive thin film using a patterning process to form the anode conductive layer pattern disposed on the second planar layer, as shown in FIGS. 16a and 16b. FIG. 16a is a schematic diagram of the planar structure of three sub-pixels after the anode conductive layer is formed, and FIG. 16b is a schematic diagram of the planar structure of the anode conductive layer in FIG. 16a.

[0286] In an example embodiment, the anode conductive layer pattern can include at least a plurality of anodes AN, which can include: a first anode AN1, a second anode AN2, and a third anode AN3. The area where the first anode AN1 is located can form a red light emitting unit that emits red light, the area where the second anode AN2 is located can form a green light emitting unit that emits green light, and the area where the third anode AN3 is located can form a blue light emitting unit that emits blue light.

[0287] In an example embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connecting electrode ZL in the corresponding sub-pixel through the twenty-sixth via V26, respectively. Since the anode connecting electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (also the second electrode of the second transistor T2) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the second transistor T2 through the anode connecting electrode ZL, respectively, thereby realizing that the pixel driving circuit drives the light emitting device to emit light.

[0288] In an example embodiment, the anode AN can include an anode main body part AN01 and an anode connecting part AN02. The anode main body part AN01 can have a rectangular structure, and the anode connecting part AN02 is connected to the anode main body part AN01 at one end and is electrically connected to the anode connecting electrode ZL at the other end through the twenty-sixth via V26. The anode connecting part AN02 can have a strip-shaped structure or a block-shaped structure extending in the first direction X or the second direction Y. The anode connecting part AN02 can be configured to compensate for the difference in parasitic capacitance between the plurality of sub-pixels due to signal wiring. By providing the anode connecting part AN02, the parasitic capacitances of the plurality of sub-pixels can be made substantially consistent, thereby improving the display uniformity of the display substrate.

[0289] (112) Forming a pixel definition layer pattern. In an example embodiment, forming a pixel definition layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing a pixel definition layer thin film, patterning the pixel definition layer using a patterning process, and forming a pixel definition layer pattern disposed on the anode conductive layer, as shown in FIGS. 17a and 17b, FIG. 17a is a schematic diagram of the planar structure of three sub-pixels after forming a pixel definition layer, and FIG. 17b is a schematic diagram of the planar structure of the pixel definition layer in FIG. 17a.

[0290] In an example embodiment, the pixel definition layer pattern can include a plurality of pixel openings K0, and the pixel openings K0 expose the anode AN. In an example embodiment, the orthographic projection of the pixel openings K0 on the substrate is within the range of the orthographic projection of the anode AN on the substrate. In an example embodiment, the pixel openings K0 can include a pixel opening K01 of the first sub-pixel, a pixel opening K02 of the second sub-pixel, and a pixel opening K03 of the third sub-pixel, and the orthographic projection of the pixel opening K01 of the first sub-pixel on the substrate has an overlapping area with the orthographic projection of the first anode AN1 on the substrate; the orthographic projection of the pixel opening K02 of the second sub-pixel on the substrate has an overlapping area with the orthographic projection of the second anode AN2 on the substrate; and the orthographic projection of the pixel opening K03 of the third sub-pixel on the substrate has an overlapping area with the orthographic projection of the third anode AN3 on the substrate.

[0291] In an example embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), which can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), which can be a single layer, a multi-layer, or a composite layer.

[0292] In an example embodiment, taking the 3 sub-pixels (1 row of pixel driving circuit of sub-pixels, 3 columns of pixel driving circuit of sub-pixels) in the display area (AA) as an example, another preparation process of a display substrate can include the steps (101) to (112) described above, and the difference from the steps (101) to (112) described above is as follows:

[0293] The second conductive layer formed in the step (103) can be as shown in FIGS. 18a and 18b. FIG. 18a is a plan view of three sub-pixels after the second conductive layer is formed, and FIG. 18b is a plan view of the second conductive layer in FIG. 18a. The difference between the second conductive layer shown in FIG. 18b and the second conductive layer shown in FIG. 8b is that, in the second conductive layer shown in FIG. 18b, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are connected to each other. For example, the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be an integral structure. The first capacitor C1 and the second capacitor C2 share one second plate, which can increase the capacitance of the first capacitor C1 and the second capacitor C2.

[0294] The fourth insulating layer formed in the step (106) can be as shown in FIG. 19. The difference between the fourth insulating layer pattern shown in FIG. 19 and the fourth insulating layer pattern shown in FIG. 11 is that, in the fourth insulating layer pattern shown in FIG. 19, the fifteenth via hole V15 is not provided, thereby reducing the number of via holes and reducing the occurrence of via hole defects.

[0295] The fourth conductive layer formed in the step (107) can be as shown in FIGS. 20a and 20b. FIG. 20a is a plan view of three sub-pixels after the fourth conductive layer is formed, and FIG. 20b is a plan view of the fourth conductive layer in FIG. 20a. The difference between the fourth conductive layer pattern shown in FIG. 20b and the fourth conductive layer pattern shown in FIG. 12b is that, in the fourth conductive layer pattern shown in FIG. 20b, the third connection electrode L3 has a strip structure extending along the first direction X, the third connection electrode L3 is connected to the second region AT32 of the active layer AT3 of the third transistor T3 (also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fifth via hole V5 and connected to the second plate C22 of the second capacitor C2 (the second plate C12 of the first capacitor C1) through the fourteenth via hole V14. The plan view of the display substrate after the fifth insulating layer and the first planar layer, the fifth conductive layer, the second planar layer, and the anode conductive layer are sequentially formed based on FIG. 20a is shown in FIG. 20c.

[0296] In the exemplary embodiments, taking three sub-pixels (one row of pixel driving circuit of one sub-pixel and one column of pixel driving circuit of three sub-pixels) in the display area (AA) as an example, another preparation process of the display substrate can include the steps (101) to (112) described above, wherein the difference between the steps (101) to (112) and the above steps is as follows.

[0297] The first conductive layer formed in the step (102) can be as shown in FIG. 21. The difference between the first conductive layer shown in FIG. 21 and the first conductive layer shown in FIG. 7 is that, in the first conductive layer shown in FIG. 21, the first plate C11 of the first capacitor C1 is not provided with the first connection portion CL11.

[0298] The second conductive layer formed in the step (103) can be as shown in FIGS. 22a and 22b. FIG. 22a is a plan view of the three sub-pixels after the second conductive layer is formed, and FIG. 22b is a plan view of the second conductive layer in FIG. 22a. The difference between the second conductive layer pattern shown in FIG. 22b and the second conductive layer pattern shown in FIG. 8b is that, in the second conductive layer shown in FIG. 22b, the second plate C22 of the second capacitor C2 is provided with an opening K11. The opening K11 can have a rectangular or circular shape. The opening K11 exposes the first insulating layer covering the first plate C21 of the second capacitor C2, and the orthographic projection of the first plate C21 of the second capacitor C2 on the base contains the orthographic projection of the opening K11 on the base. In an exemplary embodiment, the opening K11 is configured to accommodate a fifteenth via hole formed subsequently. The fifteenth via hole is located in the opening K11 and exposes the first plate C21 of the second capacitor C2, so that the second electrode of the first transistor T1 and the second electrode of the fourth transistor T4 are connected to the first plate C21 of the second capacitor C2. In the structure shown in FIGS. 21 to 22b, the orthographic projection of the second plate C22 of the second capacitor C2 on the base is within the orthographic projection of the first plate C21 of the second capacitor C2 on the base, and the orthographic projection of the first plate C11 of the first capacitor C1 on the base is within the orthographic projection of the second plate C12 of the first capacitor C1 on the base. That is, in the first capacitor C1 and the second capacitor C2, the second plate C12 of the first capacitor C1 covers the first plate C11 of the first capacitor C1, and the first plate C21 of the second capacitor C2 covers the second plate C22 of the second capacitor C2. This can better shield the first node N1 and avoid interference with the first node N1 when the signal of the data signal line D jumps, so as to avoid crosstalk in the display area caused by the signal jump of the data signal line D. Since the first node N1 is connected to the control electrode of the driving transistor T3, there is a parasitic capacitor between the control electrode T3g of the driving transistor T3 and the data signal line D. When the signal of the data signal line D jumps, the voltage of the first node N1 will be affected, thereby affecting the brightness of the light emitting device EL, and causing color crosstalk in the display area.

[0299] The fourth conductive layer formed in the step (107) can be as shown in FIGS. 23a and 23b. FIG. 23a is a plan view of the three sub-pixels after the fourth conductive layer is formed, and FIG. 23b is a plan view of the fourth conductive layer in FIG. 23a. The difference between the fourth conductive layer pattern shown in FIG. 23b and the fourth conductive layer pattern shown in FIG. 12b is that, in the fourth conductive layer pattern shown in FIG. 23b, the second power supply connection line VSSL is not provided.

[0300] The fifth insulating layer and the first planarization layer pattern formed in the step (108) can be as shown in FIG. 24, which is a planar structure diagram of three sub-pixels after forming the first planarization layer. The difference between the first planarization layer pattern shown in FIG. 27 and the first planarization layer pattern shown in FIG. 13 is that the twenty-fifth via V25 is not provided in the first planarization layer pattern shown in FIG. 27.

[0301] The fifth conductive layer formed in the step (109) can be as shown in FIGS. 25a and 25b. FIG. 25a is a planar structure diagram of three sub-pixels after forming the fifth conductive layer, and FIG. 25b is a planar diagram of the fifth conductive layer in FIG. 25a. The difference between the fifth conductive layer pattern shown in FIG. 25b and the fifth conductive layer pattern shown in FIG. 14b is that the second power supply line VSS is not connected with the second power supply connection line VSSL in the fourth conductive layer pattern shown in FIG. 25b. In an exemplary embodiment, the second power supply connection line VSSL can be provided in other sub-pixel rows, and the second power supply line VSS can be connected with the second power supply connection line VSSL in other sub-pixel rows through a via, or the second power supply connection line VSSL is not provided in the sub-pixel rows in the display area, and the second power supply line VSS is connected with the second power supply signal line located in the frame on both sides of the display area in the second direction Y. The planar structure diagram after sequentially forming the second planarization layer and the anode conductive layer based on FIG. 25a is shown in FIG. 25c.

[0302] In an exemplary embodiment, the sub-pixel row and the sub-pixel column described in the embodiments of the present disclosure can be understood as the row and column of the pixel driving circuit in the sub-pixel. The anode in the sub-pixel is connected with the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of the sub-pixel does not necessarily correspond to the row and column of the pixel driving circuit connected therewith. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate can overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel on the substrate.

[0303] The foregoing structure and the preparation process thereof in the embodiments of the present disclosure are merely exemplary descriptions. In an exemplary embodiment, the corresponding structure can be changed, and the patterning process can be increased or reduced according to actual needs. The display substrate in the embodiments of the present disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot display, which is not limited in the present disclosure.

[0304] The present disclosure also provides a display device, as shown in FIG. 29. The display device can include the display substrate of any of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, etc.

[0305] The display substrate provided by the embodiments of the present disclosure includes at least a first type of sub-pixel and a second type of sub-pixel, the width-length ratio of the channel of the driving transistor in the first type of sub-pixel is smaller than the width-length ratio of the channel of the driving transistor in the second type of sub-pixel, and the technical problem that the value range of the voltage required by the data signal line is large, the power consumption is high, and the voltage range provided by the driving chip is exceeded can be avoided to a certain extent.

[0306] The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can be referred to the general design.

[0307] In the case of no conflict, the features in the embodiments of the present disclosure can be combined with each other to obtain new embodiments.

[0308] Although the embodiments disclosed by the embodiments of the present disclosure are as above, the content is only the embodiment adopted for the purpose of facilitating the understanding of the embodiments of the present disclosure, and is not used to limit the embodiments of the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the embodiments disclosed by the present disclosure, but the patent protection scope of the present disclosure still needs to be limited by the scope defined by the appended claims.

Claims

1. A display substrate, comprising: A substrate and a plurality of sub-pixels arranged on one side of the substrate, at least part of the sub-pixels comprising a pixel driving circuit, the pixel driving circuit comprising a plurality of transistors, the plurality of transistors comprising at least a driving transistor; the plurality of sub-pixels comprising at least a first type of sub-pixel and a second type of sub-pixel; The aspect ratio of the channel of the driving transistor in the first type of sub-pixel is smaller than the aspect ratio of the channel of the driving transistor in the second type of sub-pixel. 2.The display substrate of claim 1, wherein, The aspect ratio of the channel of the driving transistor in the first type of sub-pixel is smaller than or equal to 1; the aspect ratio of the channel of the driving transistor in the second type of sub-pixel is greater than or equal to 1. 3.The display substrate of claim 2, wherein, The aspect ratio of the channel of the driving transistor in the first type of sub-pixel is greater than or equal to 8 / 16 and smaller than or equal to 8 / 8; the aspect ratio of the channel of the driving transistor in the second type of sub-pixel is greater than or equal to 8 / 8 and smaller than or equal to 8 / 4. 4.The display substrate of claim 3, wherein, The aspect ratio of the channel of the driving transistor in the first type of sub-pixel is 8 / 10; the aspect ratio of the channel of the driving transistor in the second type of sub-pixel is 8 / 6.

5. The display substrate of claim 1, further comprising a constant voltage signal line, the pixel driving circuit further comprising a first capacitor and a second capacitor; The first plate of the first capacitor is connected to the control electrode of the driving transistor, the second plate of the first capacitor and the second plate of the second capacitor are connected to the second electrode of the driving transistor, and the first plate of the second capacitor is connected to the constant voltage signal line. 6.The display substrate of claim 5, wherein, The first plate of the first capacitor and the first plate of the second capacitor are arranged in the same layer, and the second plate of the first capacitor and the second plate of the second capacitor are arranged in the same layer. In a direction perpendicular to the plane in which the substrate lies, the second plate of the first capacitor and the second plate of the second capacitor are located on the side of the first plate of the first capacitor and the first plate of the second capacitor away from the substrate. In the same pixel driving circuit, the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the first capacitor on the substrate, and the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlaps the orthographic projection of the first plate of the second capacitor on the substrate. 7.The display substrate of claim 6, wherein, The first capacitor and the second capacitor share a second plate. 8.The display substrate of claim 6, wherein, The orthographic projection of the first plate of the first capacitor on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate. 9.The display substrate of claim 8, wherein, The orthographic projection of the second plate of the second capacitor on the substrate is located within the range of the orthographic projection of the first plate of the second capacitor on the substrate. 10.The display substrate of claim 5, wherein, The ratio of the capacity of the first capacitor to the capacity of the second capacitor is 0.7 to 2. 11.The display substrate of claim 10, wherein, The ratio of the capacity of the first capacitor to the capacity of the second capacitor is 1. 12.The display substrate of claim 11, wherein, The capacity of the first capacitor and the capacity of the second capacitor are both greater than or equal to 60 femtofarads and smaller than or equal to 300 femtofarads. 13.The display substrate of claim 1, wherein, The pixel driving circuit further comprises at least one capacitor. In a direction perpendicular to a plane where the substrate is located, the capacitor comprises: a first plate located on one side of the substrate, and a second plate located on a side of the first plate away from the substrate; and the transistor comprises: an active layer located on a side of the second plate away from the substrate, a control electrode located on a side of the active layer away from the substrate, a first electrode and a second electrode located on a side of the control electrode away from the substrate. In the same capacitor, a projection of the first plate on the substrate at least partially overlaps a projection of the second plate on the substrate. 14.The display substrate of claim 13, wherein, An overlapping area of the control electrode and the active layer of the same driving transistor in the first type of sub-pixel along a channel length direction is larger than an overlapping area of the control electrode and the active layer of the same driving transistor in the second type of sub-pixel along the channel length direction. An overlapping area of the control electrode and the active layer of the same driving transistor in the first type of sub-pixel along a channel width direction is consistent with an overlapping area of the control electrode and the active layer of the same driving transistor in the second type of sub-pixel along the channel width direction. 15.The display substrate of claim 13, wherein, At least one of the capacitors further comprises a third plate and a first transfer electrode, the third plate is arranged in the same layer as the control electrode, and the first transfer electrode is arranged in the same layer as the first electrode and the second electrode. In the same capacitor, a projection of the third plate on the substrate at least partially overlaps projections of the first plate and the second plate on the substrate, and the first transfer electrode is connected to the third plate and the first plate through a via. At least one of the capacitors further comprises a fourth plate and a fifth plate, the fourth plate is arranged in the same layer as the first electrode and the second electrode, and the fifth plate is located on a side of the first plate close to the substrate. 16.The display substrate of claim 15, wherein, In the same capacitor, projections of the fourth plate and the fifth plate on the substrate at least partially overlap projections of the first plate, the second plate and the third plate on the substrate, and the fourth plate is connected to the second plate and the fifth plate through a via. The pixel driving circuit comprises a first capacitor and a second capacitor, a second plate of the first capacitor and a second plate of the second capacitor are connected to each other through a connection electrode, in a direction perpendicular to a plane where the substrate is located, the connection electrode is located on a side of the second plate of the first capacitor and the second plate of the second capacitor away from the substrate; or the first capacitor and the second capacitor share a second plate. 17.The display substrate of claim 15, wherein, At least one of the first capacitor and the second capacitor comprises the third plate and the first transfer electrode. At least one of the capacitors further comprises a third plate, a fourth plate and a second transfer electrode, the third plate is arranged in the same layer as the control electrode, and the second transfer electrode and the fourth plate are arranged in the same layer as the first electrode and the second electrode. 18.The display substrate of claim 13, wherein, ​ The second transfer electrode is connected to the second plate and the third plate by a via in the same capacitor, the fourth plate is connected to the first plate by a via, and the orthographic projection of the third plate and the fourth plate on the substrate at least partially overlaps the orthographic projection of the first plate and the second plate on the substrate.

19. The display substrate of claim 18, wherein, The pixel driving circuit includes a first capacitor and a second capacitor, the second plate of the first capacitor and the second plate of the second capacitor are connected to each other by a connecting electrode, and the connecting electrode is located on the side of the second plate of the first capacitor and the second plate of the second capacitor away from the substrate in the direction perpendicular to the plane on which the substrate lies; or the first capacitor and the second capacitor share a second plate. At least one of the first capacitor and the second capacitor includes the third plate, the fourth plate and the second transfer electrode.

20. The display substrate according to claim 17 or 19, further comprising a first initial signal line, a second initial signal line, a first power supply line and a second power supply line, the plurality of transistors including a first transistor as a reset transistor, a second transistor as a reset transistor and a fifth transistor as an emission control transistor; The first initial signal line and the second initial signal line are disposed in the same layer as the first electrode and the second electrode, and the first power supply line and the second power supply line are located on the side of the first electrode and the second electrode away from the substrate; The first electrode of the first transistor is connected to the first initial signal line, the first electrode of the second transistor is connected to the second initial signal line, and the first electrode of the fifth transistor is connected to the first power supply line; In the same pixel driving circuit, the second electrode of the fifth transistor is connected to the first electrode of the driving transistor, the first plate of the first capacitor is connected to the control electrode of the driving transistor and the second electrode of the first transistor, the second plate of the first capacitor and the second plate of the second capacitor are connected to the second electrode of the driving transistor, and the first plate of the second capacitor is connected to one of the first initial signal line, the second initial signal line, the first power supply line and the second power supply line.

21. The display substrate according to any one of claims 1 to 19, wherein, The first type of sub-pixel includes a first sub-pixel and a second sub-pixel, and the second type of sub-pixel includes a third sub-pixel.

22. The display substrate of claim 21, wherein, The first sub-pixel is a sub-pixel emitting red light, the second sub-pixel is a sub-pixel emitting green light, and the third sub-pixel is a sub-pixel emitting blue light.

23. The display substrate of any of claims 1-19, wherein, The plurality of transistors are oxide transistors.

24. A display device comprising the display substrate according to any one of claims 1 to 23.

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