Display panel and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display panel comprises: a base substrate and a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits are located on one side of the base substrate. Each pixel driving circuit comprises a driving transistor, a second transistor and a ninth transistor, wherein a first electrode of the ninth transistor is connected to a gate electrode of the driving transistor, a second electrode of the ninth transistor is connected to a first electrode of the second transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; and a channel region of the ninth transistor and a channel region of the driving transistor are formed of the same material. The display panel has a relatively good display effect.

Description

Display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] In the related art, a display panel includes a pixel driving circuit and a light emitting unit, the pixel driving circuit includes a driving transistor, and the driving transistor can provide a driving current to the light emitting unit according to a gate voltage thereof. However, there is a risk that the gate of the driving transistor leaks to other nodes, thereby causing display abnormalities of the display panel.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art.

[0004] SUMMARY

[0005] According to an aspect of the present disclosure, a display panel is provided, wherein the display panel includes:

[0006] a substrate substrate;

[0007] a plurality of pixel driving circuits located on one side of the substrate substrate, the pixel driving circuit including a driving transistor, a second transistor, and a ninth transistor, the first electrode of the ninth transistor being connected to the gate of the driving transistor, the second electrode of the ninth transistor being connected to the first electrode of the second transistor, and the second electrode of the second transistor being connected to the second electrode of the driving transistor;

[0008] wherein the channel region of the ninth transistor and the channel region of the driving transistor are formed of the same material.

[0009] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0010] a first active layer located on one side of the substrate substrate, the first active layer including a third active part and a ninth active part, the third active part being used to form the channel region of the driving transistor, and the ninth active part being used to form the channel region of the ninth transistor;

[0011] a first gate layer located on the side of the first active layer away from the substrate substrate, the first gate layer including a first gate line and a first conductive part;

[0012] a projection of the first gate line on the substrate substrate extends along a first direction and covers a projection of the ninth active part on the substrate substrate, and part of the structure of the first gate line is used to form a gate of the ninth transistor;

[0013] The first conductive part is used for forming a gate of the driving transistor, and a projection of the first conductive part on the substrate substrate covers a projection of the third active part on the substrate substrate.

[0014] A second active layer is located on a side of the first gate layer away from the substrate substrate, and the second active layer includes a second active part, and the second active part is used for forming a channel region of the second transistor.

[0015] A third gate layer includes a second gate line, a projection of the second gate line on the substrate substrate extends along the first direction and covers a projection of the second active part on the substrate substrate, and a partial structure of the second gate line is used for forming a first gate of the second transistor.

[0016] In the same pixel driving circuit, the projection of the second gate line on the substrate substrate is located between the projection of the first conductive part on the substrate substrate and the projection of the first gate line on the substrate substrate.

[0017] In an example embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to the first electrode of the driving transistor.

[0018] The display panel further includes:

[0019] A first active layer is located on a side of the substrate substrate, and the first active layer includes a fourth active part and a ninth active part, the fourth active part is used for forming a channel region of the fourth transistor, and the ninth active part is used for forming a channel region of the ninth transistor.

[0020] A first gate layer is located on a side of the first active layer away from the substrate substrate, and the first gate layer includes a first gate line.

[0021] A projection of the first gate line on the substrate substrate extends along the first direction and covers a projection of the fourth active part on the substrate substrate and a projection of the ninth active part on the substrate substrate, and a partial structure of the first gate line is used for forming a gate of the fourth transistor and a gate of the ninth transistor, respectively.

[0022] In an example embodiment of the present disclosure, in the first direction of the same pixel driving circuit, a projection of the ninth active part on the substrate substrate is located between a projection of the fourth active part on the substrate substrate and a projection of the channel region of the second transistor on the substrate substrate.

[0023] In an example embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a first electrode of the first transistor being connected to a first initial signal line, a second electrode of the first transistor being connected to a second electrode of the ninth transistor;

[0024] The display panel further includes:

[0025] A first active layer is located on one side of the substrate, and the first active layer includes a ninth active part, and the ninth active part is used for forming a channel region of the ninth transistor.

[0026] A first gate layer is located on a side of the first active layer away from the substrate, and the first gate layer includes a first gate line, a projection of the first gate line on the substrate extends along the first direction and covers a projection of the ninth active part on the substrate, and part of the structure of the first gate line is used for forming a gate of the ninth transistor.

[0027] A second active layer is located on a side of the first gate layer away from the substrate, and the second active layer includes a first active part and a second active part, the first active part is used for forming a channel region of the first transistor, and the second active part is used for forming a channel region of the second transistor.

[0028] A third gate layer includes a second gate line and a first reset signal line, a projection of the second gate line on the substrate extends along the first direction and covers a projection of the second active part on the substrate, and part of the structure of the second gate line is used for forming a first gate of the second transistor, a projection of the first reset signal line on the substrate extends along the first direction and covers a projection of the first active part on the substrate, and part of the structure of the first reset signal line is used for forming a first gate of the first transistor.

[0029] In the same pixel driving circuit, the projection of the first reset signal line on the substrate is located on a side of the projection of the first gate line on the substrate away from the projection of the second gate line on the substrate.

[0030] In an example embodiment of the present disclosure, the display panel further includes:

[0031] A first gate layer is located on one side of the substrate, and the first gate layer includes a first gate line, a projection of the first gate line on the substrate extends along the first direction, and part of the structure of the first gate line is used for forming a gate of the ninth transistor.

[0032] The first source-drain layer is located on a side of the first gate layer away from the substrate, and includes a third bridge portion connected to the second electrode of the ninth transistor through a via hole.

[0033] The first gate line and the third bridge portion at least partially overlap on the substrate.

[0034] In an example embodiment of the present disclosure, the first gate line includes a plurality of first extension segments and a plurality of second extension segments.

[0035] The second extension segment covers the channel region of the ninth transistor on the substrate, the first extension segment is connected between two adjacent second extension segments, and the first extension segment and the third bridge portion overlap on the substrate.

[0036] The size of the first extension segment on the substrate in the second direction is smaller than the size of the second extension segment on the substrate in the second direction, and the first direction and the second direction intersect.

[0037] In an example embodiment of the present disclosure, the ratio of the size of the first extension segment on the substrate in the second direction to the size of the second extension segment on the substrate in the second direction is 50%-70%.

[0038] In an example embodiment of the present disclosure, the display panel further includes:

[0039] The first gate layer is located on a side of the substrate, and includes a first gate line, the first gate line includes a plurality of first gate line segments, the plurality of first gate line segments in the same first gate line extend and are distributed along a first direction on the substrate, and part of the structure of the first gate line segment is used to form a gate of the ninth transistor.

[0040] The first source-drain layer is located on a side of the first gate layer away from the substrate, and includes a third bridge portion connected to the second electrode of the ninth transistor through a via hole.

[0041] The third bridge portion on the substrate is located between the projections of two adjacent first gate line segments in the same first gate line on the substrate.

[0042] A thirteenth bridge portion is connected between two adjacent first gate line segments in the same first gate line through vias, and a projection of the thirteenth bridge portion on the substrate and a projection of the third bridge portion on the substrate do not overlap.

[0043] In an example embodiment of the present disclosure, the thirteenth bridge portion is located in the first source-drain layer.

[0044] In an example embodiment of the present disclosure, the display panel further comprises:

[0045] A third gate layer, part of the structure of the third gate layer is used to form a first gate of the second transistor;

[0046] A first source-drain layer is located on a side of the third gate layer away from the substrate, and the first source-drain layer comprises a third bridge portion, and the third bridge portion is connected to a second electrode of the ninth transistor through a via;

[0047] A second source-drain layer is located on a side of the first source-drain layer away from the substrate, and the second source-drain layer comprises a power supply line, the power supply line is used to provide a power supply signal to the pixel driving circuit, and a projection of the power supply line on the substrate extends along a second direction;

[0048] The power supply line comprises a main body portion and a protruding portion, a projection of the protruding portion on the substrate protrudes from a side of a projection of the main body portion on the substrate in a first direction, and the first direction intersects the second direction.

[0049] The projection of the protruding portion on the substrate and the projection of the third bridge portion on the substrate at least partially overlap.

[0050] In an example embodiment of the present disclosure, a ratio of a maximum dimension of the projection of the protruding portion on the substrate in the first direction to a maximum dimension of the projection of the power supply line on the substrate in the first direction is 10%-30%.

[0051] In an example embodiment of the present disclosure, the on-state level polarity of the ninth transistor and the second transistor is opposite, and the display panel further comprises:

[0052] A third gate layer, the third gate layer comprises a second gate line, a projection of the second gate line on the substrate extends along a first direction, and part of the structure of the second gate line is used to form a first gate of the second transistor;

[0053] The first source-drain layer is located on a side of the third gate layer away from the substrate, and the first source-drain layer includes a third bridge portion, the third bridge portion includes a first via connection portion, a second via connection portion, and an extension portion, the first via connection portion is connected to a first electrode of the ninth transistor through a via, the second via connection portion is connected to a first electrode of the second transistor through a via, and the extension portion is connected to one end of the second via connection portion away from the first via connection portion.

[0054] The extension portion on the substrate and the second gate line on the substrate overlap.

[0055] In an example embodiment of the present disclosure, the first gate line on the substrate and the third bridge portion on the substrate overlap more than the second gate line on the substrate and the third bridge portion on the substrate.

[0056] In an example embodiment of the present disclosure, the display panel further includes:

[0057] The second source-drain layer is located on a side of the first source-drain layer away from the substrate, and the second source-drain layer includes a power supply line, the power supply line is used to provide a power supply signal to the pixel driving circuit, the power supply line on the substrate extends along a second direction, and the first direction and the second direction intersect.

[0058] The power supply line on the substrate and the third bridge portion on the substrate overlap.

[0059] The power supply line on the substrate and the third bridge portion on the substrate overlap more than the first gate line on the substrate and the third bridge portion on the substrate.

[0060] And / or, the power supply line on the substrate and the third bridge portion on the substrate overlap more than the second gate line on the substrate and the third bridge portion on the substrate.

[0061] In an example embodiment of the present disclosure, the ninth transistor is a double-gate structure.

[0062] In an example embodiment of the present disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a capacitor.

[0063] The first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the second electrode of the ninth transistor.

[0064] The first electrode of the fourth transistor is connected to a data line, and the second electrode is connected to the first electrode of the driving transistor.

[0065] The first electrode of the fifth transistor is connected to a power supply line, and the second electrode is connected to the first electrode of the driving transistor.

[0066] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting unit.

[0067] The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light emitting unit.

[0068] The first electrode of the eighth transistor is connected to a third initial signal line, and the second electrode is connected to the first electrode of the driving transistor.

[0069] The first electrode of the capacitor is connected to the gate electrode of the driving transistor, and the second electrode is connected to the power supply line.

[0070] The driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

[0071] In an example embodiment of the present disclosure, the display panel further includes a light emitting unit, and the pixel driving circuit further includes a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor.

[0072] The first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the second electrode of the ninth transistor.

[0073] The first electrode of the fourth transistor is connected to a data line, and the second electrode is connected to the first electrode of the driving transistor.

[0074] The first electrode of the fifth transistor is connected to a power supply line, and the second electrode is connected to the first electrode of the driving transistor.

[0075] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting unit.

[0076] The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light emitting unit.

[0077] The first electrode of the eighth transistor is connected to a third initial signal line, and the second electrode is connected to the first electrode of the driving transistor.

[0078] The display panel further comprises:

[0079] A first active layer is located on one side of the substrate substrate, at least part of the structure of the first active layer is used to form the channel region of the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor;

[0080] A first gate layer is located on the side of the first active layer away from the substrate substrate, at least part of the structure of the first gate layer is used to form the gate of the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor;

[0081] A second active layer is located on the side of the first gate layer away from the substrate substrate, at least part of the structure of the second active layer is used to form the channel region of the first transistor and the second transistor;

[0082] A third gate layer is located on the side of the second active layer away from the substrate substrate, at least part of the structure of the third gate layer is used to form the gate of the first transistor and the second transistor;

[0083] Among them, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the ninth transistor are polysilicon transistors, and the first transistor and the second transistor are oxide transistors.

[0084] In an example embodiment of the present disclosure, the display panel comprises a plurality of pixel drive circuit groups, a plurality of the pixel drive circuit groups are arrayed along a first direction and a second direction, and the first direction and the second direction intersect;

[0085] The pixel drive circuit group comprises two pixel drive circuits adjacent in the first direction, and the orthographic projections of the two pixel drive circuits in the same pixel drive circuit group on the substrate substrate are at least partially mirror-symmetrically arranged.

[0086] In an example embodiment of the present disclosure, the pixel drive circuit further comprises a fifth transistor and a sixth transistor;

[0087] The first electrode of the fifth transistor is connected to a power supply line, and the second electrode is connected to the first electrode of the driving transistor;

[0088] The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light-emitting unit;

[0089] The display panel further comprises:

[0090] An enable signal line, part of the structure of the enable signal line is used for forming a gate of the fifth transistor and the sixth transistor respectively.

[0091] According to one aspect of the present disclosure, there is provided a display device, wherein the display device comprises the display panel as described above.

[0092] It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0093] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present disclosure and serve to explain the principles of the present disclosure. It is apparent that the accompanying drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0094] FIG. 1 is a structural schematic diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure;

[0095] FIG. 2 is a structural layout of an exemplary embodiment of the display panel of the present disclosure;

[0096] FIG. 3 is a structural layout of a shielding layer in the display panel shown in FIG. 2;

[0097] FIG. 4 is a structural layout of a first active layer in the display panel shown in FIG. 2;

[0098] FIG. 5 is a structural layout of a first gate layer in the display panel shown in FIG. 2;

[0099] FIG. 6 is a structural layout of a second gate layer in the display panel shown in FIG. 2;

[0100] FIG. 7 is a structural layout of a second active layer in the display panel shown in FIG. 2;

[0101] FIG. 8 is a structural layout of a third gate layer in the display panel shown in FIG. 2;

[0102] FIG. 9 is a structural layout of a first source-drain layer in the display panel shown in FIG. 2;

[0103] FIG. 10 is a structural layout of a second source-drain layer in the display panel shown in FIG. 2;

[0104] FIG. 11 is a structural layout of the shielding layer, the first active layer in the display panel shown in FIG. 2;

[0105] FIG. 12 is a structural layout of the shielding layer, the first active layer, the first gate layer in the display panel shown in FIG. 2;

[0106] FIG. 13 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 2;

[0107] FIG. 14 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in the display panel shown in FIG. 2;

[0108] FIG. 15 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in FIG. 2;

[0109] FIG. 16 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in the display panel shown in FIG. 2;

[0110] FIG. 17 is a partial cross-sectional view of the display panel shown in FIG. 12 taken along the dashed line BB;

[0111] FIG. 18 is a structural layout in another exemplary embodiment of the display panel of the present disclosure;

[0112] FIG. 19 is a structural layout of the first gate layer in the display panel shown in FIG. 18;

[0113] FIG. 20 is a structural layout in another exemplary embodiment of the display panel of the present disclosure;

[0114] FIG. 21 is a structural layout of the first gate layer in the display panel shown in FIG. 20;

[0115] FIG. 22 is a structural layout of the second gate layer in the display panel shown in FIG. 20;

[0116] FIG. 23 is a structural layout of the third gate layer in the display panel shown in FIG. 20;

[0117] FIG. 24 is a structural layout of the first source-drain layer in the display panel shown in FIG. 20;

[0118] FIG. 25 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in FIG. 20;

[0119] FIG. 26 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 20;

[0120] FIG. 27 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the third gate layer in the display panel shown in FIG. 20;

[0121] FIG. 28 is a structural layout in an exemplary embodiment of the display panel of the present disclosure;

[0122] FIG. 29 is a structural layout of the second source-drain layer in the display panel shown in FIG. 28;

[0123] FIG. 30 is a structure layout of a display panel in an exemplary embodiment of the present disclosure;

[0124] FIG. 31 is a structure layout of a first source-drain layer in the display panel shown in FIG. 30;

[0125] FIG. 32 is a structure layout of a display panel in an exemplary embodiment of the present disclosure;

[0126] FIG. 33 is a structure layout of a first active layer in the display panel shown in FIG. 32;

[0127] FIG. 34 is a structure layout of a first gate layer in the display panel shown in FIG. 32;

[0128] FIG. 35 is a structure layout of a second gate layer in the display panel shown in FIG. 32;

[0129] FIG. 36 is a structure layout of a second active layer in the display panel shown in FIG. 32;

[0130] FIG. 37 is a structure layout of a third gate layer in the display panel shown in FIG. 32;

[0131] FIG. 38 is a structure layout of a first source-drain layer in the display panel shown in FIG. 32;

[0132] FIG. 39 is a structure layout of a second source-drain layer in the display panel shown in FIG. 32;

[0133] FIG. 40 is a structure layout of a shielding layer, a first active layer, and a first gate layer in the display panel shown in FIG. 32;

[0134] FIG. 41 is a structure layout of a shielding layer, a first active layer, a first gate layer, and a second gate layer in the display panel shown in FIG. 32;

[0135] FIG. 42 is a structure layout of a shielding layer, a first active layer, a first gate layer, a second gate layer, and a second active layer in the display panel shown in FIG. 32;

[0136] FIG. 43 is a structure layout of a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, and a third gate layer in the display panel shown in FIG. 32;

[0137] FIG. 44 is a structure layout of a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, and a first source-drain layer in the display panel shown in FIG. 32. DETAILED DESCRIPTION

[0138] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments should not be construed as limiting the example embodiments, but merely as illustrating possibly associated embodiments that, when taken in conjunction with the following description, will provide a fuller understanding of the example embodiments. The same reference numerals in different drawings can represent the same or similar elements.

[0139] The terms "one", "a", "said", "the", and "this" are used to indicate one or more of something; the terms "comprise", "comprising", "include", "including", and the like, are used to indicate an open-ended inclusion of one or more of something, and that the addition of one or more of something is not precluded.

[0140] In the description of the present disclosure, unless otherwise clearly specified and limited, the terms "first", "second", etc. are used only to describe purposes, and cannot be understood as indicating or implying relative importance; the term "multiple" means two or more; the term "and / or" includes any combination and all combinations of one or more associated listed items. In particular, referring to "the" or "one" object is also intended to represent one of possibly multiple such objects.

[0141] Unless otherwise specified or explained, the terms "connection", "fixation", and the like should be interpreted broadly, for example, "connection" can be fixed connection, or detachable connection, or integral connection, or electrical connection, or signal connection; "connection" can be direct connection, or indirect connection through intermediate medium. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0142] Further, in the description of the present disclosure, it should be understood that the orientation words "up", "down", "inner", "outer" and the like described in the example embodiments of the present disclosure are described with the angle shown in the drawings, and should not be understood as limiting the example embodiments of the present disclosure. It should also be understood that in the context, when referring to one element or feature connected to another element or feature "up", "down", or "inner", "outer", it can not only be directly connected to another element or feature "up", "down", or "inner", "outer", but also indirectly connected to another element or feature "up", "down", or "inner", "outer" through intermediate elements.

[0143] As shown in FIG. 1, a structure diagram of a pixel driving circuit in an exemplary embodiment of the display panel of the present disclosure is shown. The pixel driving circuit can include a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C. The first electrode of the fourth transistor T4 is connected to a data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to a first gate driving signal terminal G1. The first electrode of the fifth transistor T5 is connected to a first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate electrode is connected to an enable signal terminal EM. The gate electrode of the driving transistor T3 is connected to a first node N1. The first electrode of the second transistor T2 is connected to a second node N2, the second electrode is connected to the second electrode of the driving transistor T3, and the gate electrode is connected to a second gate driving signal terminal G2. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the second electrode of the seventh transistor T7, and the gate electrode is connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to a second initial signal terminal Vinit2, and the gate electrode is connected to a second reset signal terminal Re2. The second electrode of the first transistor T1 is connected to the second node N2, the first electrode is connected to a first initial signal terminal Vinit1, and the gate electrode is connected to a first reset signal terminal Re1. The first electrode of the eighth transistor T8 is connected to a third initial signal line Vinit3, the second electrode is connected to the first electrode of the driving transistor, and the gate electrode is connected to the second reset signal terminal Re2. The first electrode of the ninth transistor T9 is connected to the first node N1, the second electrode is connected to the second node N2, and the gate electrode is connected to the first gate driving signal terminal G1. The first electrode of the capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD. The pixel driving circuit can be connected to a light emitting unit L, and the pixel driving circuit is used to drive the light emitting unit L to emit light. The light emitting unit L can be connected between the second electrode of the sixth transistor T6 and a second power supply terminal VSS. The driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be polycrystalline silicon transistors, for example, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin film transistors. The first transistor T1 and the second transistor T2 can be oxide transistors, for example, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors.

[0144] The pixel driving circuit driving method can include a reset stage, a data writing stage, and a light emitting stage. In the reset stage, the first reset signal end Re1 outputs a low-level signal, the second reset signal end Re2 outputs a low-level signal, the first gate driving signal end G1 outputs a low-level signal, the first transistor T1, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 are turned on, the first initial signal end Vinit1 inputs a first initial signal to the first node N1, the second initial signal end Vinit2 inputs a second initial signal to the first electrode of the light emitting unit, and the third initial signal end Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3. In the data writing stage, the first gate driving signal end G1 outputs a low-level signal, the second gate driving signal end G2 outputs a high-level signal, the second transistor T2, the fourth transistor T4, and the ninth transistor T9 are turned on, and the data signal end Da outputs a data signal to write a compensation voltage Vdata+Vth to the first node N1, where Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3. In the light emitting stage, the enable signal end EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light emitting unit to emit light under the action of the compensation voltage Vdata+Vth stored in the capacitor C. The output current I of the driving transistor in the pixel driving circuit of the present disclosure is (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the threshold of the driving transistor on its output current. Wherein I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driving transistor channel, L is the length of the driving transistor channel, Vgs is the driving transistor gate-source voltage difference, and Vth is the threshold voltage of the driving transistor.

[0145] In the present exemplary embodiment, the ninth transistor T9 can reduce the leakage current of the driving transistor T3 gate to other nodes, thereby providing stability of the display panel light emitting.

[0146] In the example embodiment, the display panel can include a substrate, a shielding layer, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source-drain layer, and a second source-drain layer which are sequentially stacked. An insulating layer can be arranged between adjacent layers. As shown in FIGS. 2-16, FIG. 2 is a structural layout of a display panel according to an example embodiment of the present disclosure, FIG. 3 is a structural layout of the shielding layer in the display panel shown in FIG. 2, FIG. 4 is a structural layout of the first active layer in the display panel shown in FIG. 2, FIG. 5 is a structural layout of the first gate layer in the display panel shown in FIG. 2, FIG. 6 is a structural layout of the second gate layer in the display panel shown in FIG. 2, FIG. 7 is a structural layout of the second active layer in the display panel shown in FIG. 2, FIG. 8 is a structural layout of the third gate layer in the display panel shown in FIG. 2, FIG. 9 is a structural layout of the first source-drain layer in the display panel shown in FIG. 2, FIG. 10 is a structural layout of the second source-drain layer in the display panel shown in FIG. 2, FIG. 11 is a structural layout of the shielding layer and the first active layer in the display panel shown in FIG. 2, FIG. 12 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in FIG. 2, FIG. 13 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 2, FIG. 14 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in the display panel shown in FIG. 2, FIG. 15 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in FIG. 2, and FIG. 16 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in the display panel shown in FIG. 2. The display panel can include a plurality of pixel driving circuits shown in FIG. 1.

[0147] As shown in FIG. 16, the display panel can include a plurality of pixel driving circuit groups Pz which are distributed in the first direction X and the second direction Y, each of the pixel driving circuit groups Pz including two pixel driving circuits adjacent in the first direction X, i.e., a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2, and the projections of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 on the substrate are at least partially arranged in mirror symmetry along the symmetry axis AA. For example, the channel regions of the same type of transistors in the two pixel driving circuits which are at least partially mirror symmetric in structure are arranged in mirror symmetry along the symmetry axis AA on the substrate, for example, the channel region of the first transistor in the first pixel driving circuit Pix1 and the channel region of the first transistor in the second pixel driving circuit Pix2 are arranged in mirror symmetry along the symmetry axis AA on the substrate.

[0148] As shown in FIGS. 2, 3, and 11, the shielding layer includes a plurality of first shielding portions 81 and second shielding portions 82 which are arrayed in the first direction X and the second direction Y, the first shielding portions 81 are connected to each other, and the second shielding portions 82 are connected to the first shielding portions 81.

[0149] As shown in FIGS. 2, 4, 11 and 12, the first active layer can include a third active part 73, a fourth active part 74, a fifth active part 75, a sixth active part 76, a seventh active part 77, an eighth active part 78, a ninth active part 79, a tenth active part 710, an eleventh active part 711, a twelfth active part 712, a thirteenth active part 713, a fourteenth active part 714, a fifteenth active part 715, a sixteenth active part 716, a seventeenth active part 717, an eighteenth active part 718, and a nineteenth active part 719. The third active part 73 can be used to form a channel region of the driving transistor T3; the fourth active part 74 can be used to form a channel region of the fourth transistor T4; the fifth active part 75 can be used to form a channel region of the fifth transistor T5; the sixth active part 76 can be used to form a channel region of the sixth transistor T6; the seventh active part 77 can be used to form a channel region of the seventh transistor T7; the eighth active part 78 can be used to form a channel region of the eighth transistor T8; the ninth active part 79 can be used to form a channel region of the ninth transistor T9; the tenth active part 710 and the eleventh active part 711 are connected to two ends of the ninth active part 79; the twelfth active part 712 is connected to an end of the fourth active part 74 away from the third active part 73; the thirteenth active part 713 is connected between the third active part 73 and the fifth active part 75; the fourteenth active part 714 is connected to an end of the fifth active part 75 away from the third active part 73; the fifteenth active part 715 and the sixteenth active part 716 are connected to two ends of the eighth active part 78; the seventeenth active part 717 is connected to an end of the seventh active part 77 away from the sixth active part 76; the eighteenth active part 718 is connected between the seventh active part 77 and the sixth active part 76; and the nineteenth active part 719 is connected between the third active part 73 and the sixth active part 76.

[0150] In the present exemplary embodiment, as shown in FIGS. 2, 4, 11 and 12, the first active layer can be formed of a polysilicon material, and accordingly, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the ninth transistor T9 can be P-type low-temperature polysilicon thin film transistors.

[0151] As shown in FIGS. 2, 4, 11 and 12, in the same pixel driving circuit group, the two fifth active parts 75 are connected through the fourteenth active part 714, and the two eighth active parts 78 are connected through the fifteenth active part 715.

[0152] As shown in FIG. 2, 4, 11, 12, the orthographic projection of the first shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate, the first shielding portion 81 can shield the third active portion 73 to improve the stability of the output characteristics of the driving transistor T3. The orthographic projection of the second shielding portion 82 on the substrate can at least partially overlap with the orthographic projection of the ninth active portion 79 on the substrate, the second shielding portion 82 can shield the ninth active portion 79 to improve the stability of the output characteristics of the ninth transistor T9. The shielding layer can be a conductive structure, the shielding layer can be connected to a stable voltage source, the shielding layer can shield the signal of the pixel driving circuit, and the shielding layer can be connected to the first initial signal end, the second initial signal end, the third initial signal end, the first power supply end, the second power supply end and other stable voltage sources in FIG. 1.

[0153] As shown in FIG. 2, 5, 12, the first gate layer can include: a first initial signal line Vinit1, a first gate line G1, a first conductive portion 11, an enable signal line EM, and a second reset signal line Re1. The first initial signal line Vinit1 is used to provide the first initial signal end in FIG. 1; the first gate line G1 can be used to provide the first gate driving signal end in FIG. 1; the enable signal line EM can be used to provide the enable signal end in FIG. 1; and the second reset signal line Re1 can be used to provide the second reset signal end in FIG. 1. The orthographic projection of the first initial signal line Vinit1 on the substrate, the orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the enable signal line EM on the substrate, and the orthographic projection of the second reset signal line Re1 on the substrate can all extend along the first direction X. The orthographic projection of the first gate line G1 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate and the orthographic projection of the ninth active portion 79 on the substrate, part of the structure of the first gate line G1 is used to form the gate of the fourth transistor T4, and part of the structure of the first gate line G1 is used to form the gate of the ninth transistor T9. The orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 75 on the substrate and the orthographic projection of the sixth active portion 76 on the substrate, and part of the structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 77 on the substrate and the orthographic projection of the eighth active portion 78 on the substrate, and part of the structure of the second reset signal line Re2 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 73 on the substrate, and the first conductive portion 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.

[0154] In the example embodiment, as shown in FIGS. 2, 5, and 12, the display panel can perform a conductorization process on the first active layer using the first gate layer as a mask, that is, the region of the first active layer covered by the first gate layer can form a channel region of a transistor, and the region of the first active layer not covered by the first gate layer can form a conductor structure.

[0155] As shown in FIGS. 2, 6, and 13, the second gate layer can include a second conductive portion 22, a first connecting portion 23, a third reset signal line 2Re1, and a third gate line 2G2. The orthogonal projection of the second conductive portion 22 on the substrate substrate can at least partially overlap the orthogonal projection of the first conductive portion 11 on the substrate substrate, and the second conductive portion 22 is used to form a second electrode of a capacitor C. The first connecting portion 23 is connected between adjacent second conductive portions 22 in the first direction X. The orthogonal projection of the third reset signal line 2Re1 and the third gate line 2G2 on the substrate substrate extends along the first direction X, and the third reset signal line 2Re1 is used to provide the first reset signal end in FIG. 1, and the third gate line 2G2 is used to provide the second gate drive signal end in FIG. 1.

[0156] As shown in FIGS. 2, 7, and 14, the second active layer can include a first active portion 91, a second active portion 92, a twentieth active portion 920, a twenty-first active portion 921, and a twenty-second active portion 922. The first active portion 91 is used to form a channel region of a first transistor; the second active portion 92 is used to form a channel region of a second transistor; the twentieth active portion 920 is connected between the first active portion 91 and the second active portion 92; the twenty-first active portion 921 is connected to a side of the first active portion 91 away from the second active portion 92; and the twenty-second active portion 922 is connected to an end of the second active portion 92 away from the first active portion 91. The second active layer can be formed of indium gallium zinc oxide, and accordingly, the first transistor T1 and the second transistor T2 can be N-type metal oxide thin film transistors.

[0157] As shown in FIGS. 2, 7, and 14, the orthogonal projection of the third reset signal line 2Re1 on the substrate substrate can cover the orthogonal projection of the first active portion 91 on the substrate substrate, and part of the structure of the third reset signal line 2Re1 can be used to form a bottom gate of the first transistor T1. The orthogonal projection of the third gate line 2G2 on the substrate substrate can cover the orthogonal projection of the second active portion 92 on the substrate substrate, and part of the structure of the third gate line 2G2 can be used to form a bottom gate of the second transistor T2.

[0158] As shown in FIGS. 2, 8, and 15, the third gate layer can include a first reset signal line 3Re1, a second gate line 3G2, a third initial signal line Vinit3, and a second initial signal line Vinit2. The orthogonal projection of the first reset signal line 3Re1 on the substrate, the orthogonal projection of the second gate line 3G2 on the substrate, the orthogonal projection of the third initial signal line Vinit3 on the substrate, and the orthogonal projection of the second initial signal line Vinit2 on the substrate can extend along the first direction X. The first reset signal line 3Re1 is configured to provide the first reset signal terminal in FIG. 1, and the orthogonal projection of the first reset signal line 3Re1 on the substrate can cover the orthogonal projection of the first active part 91 on the substrate. Part of the structure of the first reset signal line 3Re1 can be configured to form the top gate of the first transistor T1. The second gate line 3G2 can be configured to provide the second gate driving signal terminal in FIG. 1, and the orthogonal projection of the second gate line 3G2 on the substrate can cover the orthogonal projection of the second active part 92 on the substrate. Part of the structure of the second gate line 3G2 can be configured to form the top gate of the second transistor T2. Meanwhile, the first reset signal line 3Re1 can be connected to the third reset signal line 2Re1 through a via in the display panel frame area. The second gate line 3G2 can be connected to the third gate line 2G2 through a via in the display panel frame area. The second initial signal line Vinit2 can be configured to provide the second initial signal terminal in FIG. 1, and the third initial signal line Vinit3 can be configured to provide the third initial signal terminal in FIG. 1. In addition, the display panel can perform a conductorization process on the second active layer by taking the third gate layer as a mask. That is, the region of the second active layer covered by the third gate layer can form the channel region of the transistor, and the region of the second active layer not covered by the third gate layer can form a conductor structure.

[0159] It should be noted that in other exemplary embodiments, the display panel can also not include the second gate layer. Correspondingly, the third gate layer can be located between the second active layer and the first gate layer. Correspondingly, the second gate line 3G2 can form the bottom gate of the second transistor T2, and the first reset signal line 3Re1 can be configured to form the low gate of the first transistor T1. Among them, the bottom gate or the top gate of the second transistor T2 is configured to form the first gate in the summary of the application, and the bottom gate or the top gate of the first transistor T1 is configured to form the first gate in the summary of the application.

[0160] As shown in FIGS. 2, 8, and 15, in the same pixel driving circuit, the orthogonal projection of the second gate line 3G2 on the substrate is located between the orthogonal projection of the first conductive part 11 on the substrate and the orthogonal projection of the first gate line G1 on the substrate.

[0161] In the first direction X of the same pixel driving circuit, the orthogonal projection of the ninth active part 79 on the substrate is located between the orthogonal projection of the fourth active part 74 on the substrate and the orthogonal projection of the second active part 92 on the substrate.

[0162] In the same pixel driving circuit, the orthographic projection of the first reset signal line 3Re1 on the substrate substrate is located on the side away from the orthographic projection of the second gate line 3G2 on the substrate substrate.

[0163] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers, for example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can be located in the first active layer, the first gate layer, the second gate layer, the third gate layer, the first source-drain layer, etc.

[0164] As shown in FIGS. 2, 9, and 16, the first source-drain layer can include a first bridge portion 41, a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, a tenth bridge portion 410, an eleventh bridge portion 411, and a first fan-out line FIPH. As shown in FIGS. 2, 9, and 16, the first bridge portion 41 can be connected to the twenty-first active portion 921 and the first initial signal line Vinit1 by vias, to connect the first electrode of the first transistor T1 and the first initial signal end. Among them, two adjacent pixel drive circuits in the first direction X share the same first bridge portion 41. The second bridge portion 42 can be connected to the twelfth active portion 712 by a via, to connect the first electrode of the fourth transistor T4. The third bridge portion 43 can be connected to the twentieth active portion 920 and the tenth active portion 710 by vias, to connect the second electrode of the ninth transistor T9, the second electrode of the first transistor T1, and the first electrode of the second transistor T2. The fourth bridge portion 44 can be connected to the fourteenth active portion 714 and the first connection portion 23 by vias, to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. Among them, two pixel drive circuits in the same pixel drive circuit group can share the same fourth bridge portion 44. The fifth bridge portion 45 can be connected to the first conductive portion 11 and the eleventh active portion 711 by vias, to connect the gate of the driving transistor T3 and the first electrode of the ninth transistor T9. Among them, the second conductive portion 22 is formed with an opening 221, and the via connected between the fifth bridge portion 45 and the first conductive portion 11 is arranged through the opening 221. The sixth bridge portion 46 can be connected to the nineteenth active portion 719 and the twenty-second active portion 922 by vias, to connect the second electrode of the driving transistor T3 and the second electrode of the second transistor T2. The seventh bridge portion 47 can be connected to the thirteenth active portion 713 and the sixteenth active portion 716 by vias, to connect the second electrode of the eighth transistor and the first electrode of the driving transistor T3. The eighth bridge portion 48 can be connected to the eighteenth active portion 718 by a via, to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7. The ninth bridge portion 49 can be connected to the third initial signal line Vinit3 and the fifteenth active portion 715 by vias, to connect the first electrode of the eighth transistor T8 and the third initial signal line Vinit3. The tenth bridge portion 410 can be connected to the second initial signal line Vinit2 and the seventeenth active portion 717 by vias, to connect the first electrode of the seventh transistor T7 and the second initial signal line Vinit2. The orthogonal projection of the first fan-out line FIPH on the substrate can extend along the first direction X, and the first fan-out line FIPH can be used as a first direction fan-out line for connecting the data line in the FIP (Fanout In Pixel).

[0165] As shown in FIGS. 2 and 10, the second source-drain layer can include a data line Da, a power supply line VDD, a second fan-out line FIPV, a first initial connection line 5Vinit1, a second initial connection line 5Vinit2, and a twelfth bridge portion 512. The orthogonal projection of the data line Da on the substrate, the orthogonal projection of the power supply line VDD on the substrate, the orthogonal projection of the second fan-out line FIPV on the substrate, the orthogonal projection of the first initial connection line 5Vinit1 on the substrate, and the orthogonal projection of the second initial connection line 5Vinit2 on the substrate all extend along the second direction Y. The data line Da is configured to provide a data signal terminal in FIG. 1, and the data line Da can be connected to the second bridge portion 42 through a via hole to connect the data signal terminal and the first electrode of the fourth transistor T4. The power supply line VDD can be configured to provide a first power supply terminal in FIG. 1, and the power supply line VDD can be connected to the fourth bridge portion 44 through a via hole to connect the first power supply terminal and the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. The first initial connection line 5Vinit1 can be connected to the first initial signal line Vinit1 intersecting therewith through a via hole, and a plurality of first initial connection lines 5Vinit1 and a plurality of first initial signal lines Vinit1 can form a grid structure. The first initial signal line Vinit1 of the grid structure can reduce the voltage difference of the first initial signal line Vinit1 at different positions of the display panel, thereby improving the display uniformity of the display panel. The second initial connection line 5Vinit2 can be connected to the second initial signal line Vinit2 intersecting therewith through a via hole, and a plurality of second initial connection lines 5Vinit2 and a plurality of second initial signal lines Vinit2 can form a grid structure. The second initial signal line Vinit2 of the grid structure can also improve the display uniformity of the display panel. The second source-drain layer can further include a third initial connection line, and the orthogonal projection of the third initial connection line on the substrate also extends along the second direction Y. The third initial connection line can be connected to the third initial signal line Vinit3 intersecting therewith through a via hole, and a plurality of third initial connection lines and a plurality of third initial signal lines Vinit3 can form a grid structure. The orthogonal projection of the first initial connection line 5Vinit1 on the substrate, the orthogonal projection of the second initial connection line 5Vinit2 on the substrate, and the orthogonal projection of the third initial connection line on the substrate can be alternately distributed along the first direction X in sequence. The second fan-out line FIPV can be a second direction fan-out line for connecting data lines in a FIP (Fanout In Pixel) region. The second fan-out line FIPV can include a plurality of fan-out line segments arranged at intervals in the second direction, and adjacent fan-out line segments can be bridged by an eleventh bridge portion 411. The twelfth bridge portion 512 can be connected to the eighth bridge portion 48 through a via hole, and the twelfth bridge portion 512 can be configured to connect the first electrode of the light emitting unit.

[0166] As shown in FIG. 17, it is a partial cross-sectional view of the display panel shown in FIG. 2 along the dashed line BB. The display panel can further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, and a first planarization layer 108. Among them, the substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first gate layer, the third insulating layer 103, the second gate layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third gate layer, the first dielectric layer 106, the first source-drain layer, the passivation layer 107, the first planarization layer 108, and the second source-drain layer are sequentially stacked. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure, and the materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 106 can be a silicon nitride layer; and the material of the first planarization layer 108 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), and the like. The passivation layer 107 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer which are sequentially stacked, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer. The materials of the first source-drain layer and the second source-drain layer can include a metal material, such as one of molybdenum, aluminum, copper, titanium, and niobium or an alloy, or a molybdenum / titanium alloy or a laminated conductive layer, or a titanium / aluminum / titanium laminated conductive layer. The sheet resistance of any one of the first source-drain layer and the second source-drain layer can be less than that of any one of the first gate layer, the second gate layer, and the third gate layer.

[0167] In the present exemplary embodiment, as shown in FIGS. 2-16, the orthographic projection of the third bridge portion 43 on the substrate and the orthographic projection of the first gate line G1 on the substrate overlap, and a first parasitic capacitance is formed between the third bridge portion 43 and the first gate line G1. After the pixel driving circuit is completed in the data writing stage, the voltage of the first gate line G1 changes from low to high, and under the coupling effect of the first parasitic capacitance, the third bridge portion 43 is pulled high, which will cause the third bridge portion 43 to leak current to the gate of the driving transistor T3, thereby affecting the luminous brightness of the pixel driving circuit driving the light emitting unit.

[0168] As shown in FIGS. 18 and 19, FIG. 18 is a structural layout of another exemplary embodiment of the display panel of the present disclosure, and FIG. 19 is a structural layout of the first gate layer of the display panel shown in FIG. 18. As shown in FIGS. 2-19, the first gate line G1 includes a first extension segment G01 and a second extension segment G02, the second extension segment G02 covers the orthographic projection of the ninth active part 79 on the substrate in the orthographic projection of the substrate, and part of the structure of the second extension segment G02 is used to form the gate of the ninth transistor; the first extension segment G01 is connected between two adjacent second extension segments G02, and the orthographic projection of the first extension segment G01 on the substrate and the orthographic projection of the third bridge part 43 on the substrate overlap. The size of the orthographic projection of the first extension segment G01 on the substrate in the second direction Y can be smaller than the size of the orthographic projection of the second extension segment G02 on the substrate in the second direction Y. This arrangement can reduce the parasitic capacitance between the first gate line G1 and the third bridge part 43, thereby reducing the leakage current of the third bridge part 43 to the gate of the driving transistor.

[0169] As shown in FIGS. 18 and 19, the main difference between the display panel shown in FIG. 18 and the display panel shown in FIG. 2 is the first gate layer. Compared with the display panel shown in FIG. 2, the display panel shown in FIG. 18 can reduce the size of the orthographic projection of the first extension segment G01 on the substrate in the second direction Y to reduce the overlapping area of the orthographic projection of the first gate line G1 on the substrate and the orthographic projection of the third bridge part 43 on the substrate, thereby reducing the coupling effect of the first gate line G1 on the third bridge part 43, and thus the leakage problem of the third bridge part 43 to the gate of the driving transistor can be improved. For example, the size of the orthographic projection of the first extension segment G01 on the substrate in the second direction Y can be reduced from 2.5 μm to 2.1 μm.

[0170] In the display panel shown in FIG. 18, the ratio of the size of the orthographic projection of the first extension segment G01 on the substrate in the second direction Y to the size of the orthographic projection of the second extension segment G02 on the substrate in the second direction Y can be 50%-70%, for example, the ratio can be equal to 50%, 55%, 60%, 65%, 70%, etc.

[0171] In addition, other structures of the display panel shown in FIG. 18 can be the same as those of the display panel shown in FIG. 2.

[0172] As shown in FIGS. 20-27, FIG. 20 is a structural layout of another exemplary embodiment of the display panel of the present disclosure, FIG. 21 is a structural layout of the first gate layer in the display panel shown in FIG. 20, FIG. 22 is a structural layout of the second gate layer in the display panel shown in FIG. 20, FIG. 23 is a structural layout of the third gate layer in the display panel shown in FIG. 20, FIG. 24 is a structural layout of the first source-drain layer in the display panel shown in FIG. 20, FIG. 25 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in FIG. 20, FIG. 26 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 20, and FIG. 27 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the third gate layer in the display panel shown in FIG. 20.

[0173] The main difference between the display panel shown in FIG. 20 and the display panel shown in FIG. 2 is the first gate layer and the first source-drain layer. As shown in FIGS. 20-27, the first gate line G1 includes a plurality of first gate line segments G11, and the orthogonal projections of the plurality of first gate line segments G11 in the same first gate line G1 on the substrate substrate extend along the first direction X and are spaced apart along the first direction X. The first source-drain layer further includes a thirteenth bridge portion 413, and the thirteenth bridge portion 413 connects two adjacent first gate line segments G11 in the same first gate line. Among them, the orthogonal projection of the third bridge portion 43 on the substrate substrate is located between the orthogonal projections of the two adjacent first gate line segments G11 in the same first gate line G1 on the substrate substrate, that is, the orthogonal projection of the third bridge portion 43 on the substrate substrate and the orthogonal projection of the first gate line segment G11 on the substrate substrate do not overlap. The orthogonal projection of the thirteenth bridge portion 413 on the substrate substrate and the orthogonal projection of the third bridge portion 43 on the substrate substrate are spaced apart, that is, the orthogonal projection of the thirteenth bridge portion 413 on the substrate substrate and the orthogonal projection of the third bridge portion 43 on the substrate substrate do not overlap. This setting can avoid the overlap of the first gate line G1 and the third bridge portion 43, thereby reducing the parasitic capacitance between the first gate line G1 and the third bridge portion 43.

[0174] It should be understood that in other exemplary embodiments, the thirteenth bridge portion 413 can also be located in other conductive layers, for example, the thirteenth bridge portion 413 can be located in the second source-drain layer, or in other additional conductive layers.

[0175] In addition, the second gate layer and the third gate layer in the display panel shown in FIG. 20 and the display panel shown in FIG. 2 also have slight differences. As shown in FIGS. 20-27, part of the extension segment 2G21 in the third gate line 2G2 is slightly offset downward to expose the first gate line segment G11 for the via connection of the thirteenth bridge portion via. Similarly, part of the extension segment 3G21 in the second gate line 3G2 is slightly offset downward to expose the first gate line segment G11 for the via connection of the thirteenth bridge portion 413 via.

[0176] In addition, other structures of the display panel shown in FIG. 20 can be the same as those of the display panel shown in FIG. 2.

[0177] As shown in FIGS. 2-16, the power supply line VDD can include a main body portion VD1 and a protruding portion VD2, a projection of the protruding portion VD2 on the substrate is disposed on one side of a projection of the main body portion VD1 on the substrate in the first direction. The projection of the protruding portion VD2 on the substrate and the projection of the third bridge portion 43 on the substrate at least partially overlap, and the protruding portion VD2 can be used to stabilize the third bridge portion 43, thereby reducing the coupling effect of the first gate line G1 on the third bridge portion 43.

[0178] As shown in FIGS. 28-29, FIG. 28 is a structural layout of an exemplary embodiment of the display panel of the present disclosure, and FIG. 29 is a structural layout of the second source-drain layer in the display panel shown in FIG. 28. The main difference between the display panel shown in FIG. 28 and the display panel shown in FIG. 2 is the second source-drain layer. The exemplary embodiment can increase the size of the projection of the protruding portion VD2 on the substrate in the first direction of the display panel shown in FIG. 2 to obtain the embodiment shown in FIG. 28. The display panel shown in FIG. 28 can increase the capacitance between the protruding portion VD2 and the third bridge portion 43, thereby increasing the voltage stabilizing effect of the protruding portion VD2 on the third bridge portion 43. The ratio of the maximum size L1 of the projection of the protruding portion VD2 on the substrate in the first direction X to the maximum size L2 of the projection of the power supply line VDD on the substrate in the first direction X is 10%-30%, for example, L1 / L2 can be equal to 10%, 15%, 20%, 25%, 30%, etc.

[0179] In addition, other structures of the display panel shown in FIG. 28 can be the same as those of the display panel shown in FIG. 2.

[0180] As shown in FIGS. 30-31, FIG. 30 is a structural layout of a display panel in an exemplary embodiment of the present disclosure, and FIG. 31 is a structural layout of the first source-drain layer in the display panel shown in FIG. 30. The main difference between the display panel shown in FIG. 30 and the display panel shown in FIG. 2 is the first source-drain layer. As shown in FIGS. 30-31, the third bridge portion 43 can include a first via connection portion 431, a second via connection portion 432, and an extension portion 433. The first via connection portion 431 is configured to connect the tenth active portion 710 through a via, the second via connection portion 432 is configured to connect the twentieth active portion 920 through a via, and the extension portion 433 is connected to one end of the second via connection portion 432 away from the first via connection portion 431. The extension portion 433 is at least partially overlapped with the second gate line 3G2 on the substrate. The arrangement can form a second parasitic capacitor between the second gate line 3G2 and the third bridge portion 43. After the end of the data writing stage, the second gate line 3G2 changes from high to low, and the second parasitic capacitor can couple the voltage change of the second gate line 3G2 to the third bridge portion 43 to pull down the voltage of the third bridge portion 43, thereby reducing the leakage current of the third bridge portion 43 to the gate of the driving transistor T3.

[0181] As shown in FIGS. 30-31, the overlapping area of the first gate line G1 on the substrate and the third bridge portion 43 on the substrate can be greater than the overlapping area of the second gate line 3G2 on the substrate and the third bridge portion 43 on the substrate. The ratio of the overlapping area of the first gate line G1 on the substrate and the third bridge portion 43 on the substrate to the overlapping area of the second gate line 3G2 on the substrate and the third bridge portion 43 on the substrate can be 1.2-2, for example, the ratio can be 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, etc.

[0182] As shown in FIGS. 30-31, the overlapping area of the power supply line VDD on the substrate and the third bridge portion 43 on the substrate is greater than the overlapping area of the second gate line 3G2 on the substrate and the third bridge portion 43 on the substrate. The ratio of the overlapping area of the power supply line VDD on the substrate and the third bridge portion 43 on the substrate to the overlapping area of the second gate line 3G2 on the substrate and the third bridge portion 43 on the substrate can be 1.8-5, for example, the ratio can be equal to 1.8, 2, 2.5, 3, 3.5, 4, 4.5, 5, etc.

[0183] In addition, other structures of the display panel shown in FIG. 30 can be the same as those of the display panel shown in FIG. 2.

[0184] As shown in FIGS. 32-44, FIG. 32 is a structural layout of one exemplary embodiment of the display panel of the present disclosure, FIG. 33 is a structural layout of the first active layer in the display panel shown in FIG. 32, FIG. 34 is a structural layout of the first gate layer in the display panel shown in FIG. 32, FIG. 35 is a structural layout of the second gate layer in the display panel shown in FIG. 32, FIG. 36 is a structural layout of the second active layer in the display panel shown in FIG. 32, FIG. 37 is a structural layout of the third gate layer in the display panel shown in FIG. 32, FIG. 38 is a structural layout of the first source-drain layer in the display panel shown in FIG. 32, FIG. 39 is a structural layout of the second source-drain layer in the display panel shown in FIG. 32, FIG. 40 is a structural layout of the shielding layer, the first active layer, and the first gate layer in the display panel shown in FIG. 32, FIG. 41 is a structural layout of the shielding layer, the first active layer, the first gate layer, and the second gate layer in the display panel shown in FIG. 32, FIG. 42 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, and the second active layer in the display panel shown in FIG. 32, FIG. 43 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in the display panel shown in FIG. 32, and FIG. 44 is a structural layout of the shielding layer, the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source-drain layer in the display panel shown in FIG. 32.

[0185] The main difference between the display panel shown in FIG. 32 and the display panel shown in FIG. 2 is that in the display panel shown in FIG. 32, the ninth transistor T9 is a double-gate structure, i.e., the ninth transistor T9 includes two channel regions arranged apart from each other. The double-gate structure of the ninth transistor T9 has a smaller off-leakage current, and thus this arrangement can improve the voltage stability of the gate of the driving transistor. The other structures of the display panel shown in FIG. 32 and the display panel shown in FIG. 2 can be the same or substantially the same.

[0186] As shown in FIGS. 2-44, the overlapping area of the orthogonal projection of the power supply line VDD on the substrate and the orthogonal projection of the third bridge portion 43 on the substrate is greater than the overlapping area of the orthogonal projection of the first gate line G1 on the substrate and the orthogonal projection of the third bridge portion 43 on the substrate. The ratio of the overlapping area of the orthogonal projection of the power supply line VDD on the substrate and the orthogonal projection of the third bridge portion 43 on the substrate to the overlapping area of the orthogonal projection of the first gate line G1 on the substrate and the orthogonal projection of the third bridge portion 43 on the substrate is 2-5.2, e.g., the ratio can be equal to 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 4.8, etc.

[0187] It should be noted that, as shown in FIG. 2-44, the black square with chamfer drawn on the side of the first source-drain layer away from the substrate is a via hole connecting other levels on the side facing the substrate; the black rectangle with chamfer drawn on the side of the second source-drain layer away from the substrate is a via hole connecting other levels on the side facing the substrate, and the via holes at different positions can penetrate different insulating layers.

[0188] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto, for example: the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display panel and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams. In addition, the adjectives first, second, etc. are only used to define different structural names, and do not have the meaning of a specific order, and the same structure layer can be formed by the same patterning process. In the present exemplary embodiment, the orthographic projection of a certain structure on the substrate extends in a certain direction, which can be understood as that the orthographic projection of the structure on the substrate extends linearly or bends in the direction.

[0189] The present exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, a tablet computer, a television, etc.

[0190] Other embodiments of the present disclosure will be apparent to those skilled in the art upon consideration of the specification and practice of the present disclosure. The present application is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such departures from the present disclosure that come within known or customary practice within the art to which the present disclosure pertains. The specification and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0191] It should be understood that the present disclosure is not limited to the precise structures described above and shown in the drawings and that various modifications and changes can be made without departing from its scope. The scope of the present disclosure is limited only by the claims that follow.

Claims

1. A display panel, wherein, The display panel comprises: a substrate substrate; a plurality of pixel driving circuits located on one side of the substrate substrate, the pixel driving circuit comprising a driving transistor, a second transistor, a ninth transistor, the first electrode of the ninth transistor being connected to the gate electrode of the driving transistor, the second electrode of the ninth transistor being connected to the first electrode of the second transistor, and the second electrode of the second transistor being connected to the second electrode of the driving transistor; wherein the channel region of the ninth transistor and the channel region of the driving transistor are formed of the same material.

2. The display panel of claim 1, wherein, The display panel further comprises: a first active layer located on one side of the substrate substrate, the first active layer comprising a third active part and a ninth active part, the third active part being used to form the channel region of the driving transistor, and the ninth active part being used to form the channel region of the ninth transistor; a first gate layer located on the side of the first active layer away from the substrate substrate, the first gate layer comprising a first gate line and a first conductive part; the orthographic projection of the first gate line on the substrate substrate extends along a first direction and covers the orthographic projection of the ninth active part on the substrate substrate, and part of the structure of the first gate line is used to form the gate electrode of the ninth transistor; the orthographic projection of the first conductive part on the substrate substrate covers the orthographic projection of the third active part on the substrate substrate, and the first conductive part is used to form the gate electrode of the driving transistor; a second active layer located on the side of the first gate layer away from the substrate substrate, the second active layer comprising a second active part, the second active part being used to form the channel region of the second transistor; a third gate layer, the third gate layer comprising a second gate line, the orthographic projection of the second gate line on the substrate substrate extending along the first direction and covering the orthographic projection of the second active part on the substrate substrate, and part of the structure of the second gate line being used to form the first gate electrode of the second transistor; wherein, in the same pixel driving circuit, the orthographic projection of the second gate line on the substrate substrate is located between the orthographic projection of the first conductive part on the substrate substrate and the orthographic projection of the first gate line on the substrate substrate.

3. The display panel of claim 1, wherein, The pixel driving circuit further comprises a fourth transistor, the first electrode of the fourth transistor being connected to a data line, and the second electrode of the fourth transistor being connected to the first electrode of the driving transistor; The display panel further comprises: a first active layer located on one side of the substrate substrate, the first active layer comprising a fourth active part and a ninth active part, the fourth active part being used to form the channel region of the fourth transistor, and the ninth active part being used to form the channel region of the ninth transistor; a first gate layer located on the side of the first active layer away from the substrate substrate, the first gate layer comprising a first gate line; the orthographic projection of the first gate line on the substrate substrate extends along a first direction and covers the orthographic projection of the fourth active part on the substrate substrate and the orthographic projection of the ninth active part on the substrate substrate, and part of the structure of the first gate line is used to form the gate electrode of the fourth transistor and the ninth transistor, respectively.

4. The display panel of claim 3, wherein, In the first direction of the pixel driving circuit, a projection of the ninth active part on the substrate substrate is located between a projection of the fourth active part on the substrate substrate and a projection of the second transistor channel region on the substrate substrate.

5. The display panel of claim 1, wherein, The pixel driving circuit further includes a first transistor, a first electrode of the first transistor being connected to a first initial signal line, a second electrode of the first transistor being connected to the second electrode of the ninth transistor; The display panel further includes: A first active layer located on one side of the substrate substrate, the first active layer including a ninth active part, the ninth active part being used to form a channel region of the ninth transistor; A first gate layer located on a side of the first active layer away from the substrate substrate, the first gate layer including a first gate line, a projection of the first gate line on the substrate substrate extending along the first direction and covering a projection of the ninth active part on the substrate substrate, part of a structure of the first gate line being used to form a gate of the ninth transistor; A second active layer located on a side of the first gate layer away from the substrate substrate, the second active layer including a first active part and a second active part, the first active part being used to form a channel region of the first transistor, the second active part being used to form a channel region of the second transistor; A third gate layer, the third gate layer including a second gate line and a first reset signal line, a projection of the second gate line on the substrate substrate extending along the first direction and covering a projection of the second active part on the substrate substrate, part of a structure of the second gate line being used to form a first gate of the second transistor, a projection of the first reset signal line on the substrate substrate extending along the first direction and covering a projection of the first active part on the substrate substrate, part of a structure of the first reset signal line being used to form a first gate of the first transistor; In the same pixel driving circuit, the projection of the first reset signal line on the substrate substrate is located on a side of the projection of the first gate line on the substrate substrate away from the projection of the second gate line on the substrate substrate. The display panel further includes:

6. The display panel of claim 1, wherein, A first gate layer located on one side of the substrate substrate, the first gate layer including a first gate line, a projection of the first gate line on the substrate substrate extending along a first direction, part of a structure of the first gate line being used to form a gate of the ninth transistor; A first source-drain layer located on a side of the first gate layer away from the substrate substrate, the first source-drain layer including a third bridge part, the third bridge part being connected to the second electrode of the ninth transistor through a via hole; The projection of the first gate line on the substrate substrate and the projection of the third bridge part on the substrate substrate at least partially overlap. The first gate line includes a plurality of first extension segments and a plurality of second extension segments; 7. The display panel of claim 6, wherein, ​ A projection of the second extension section on the substrate substrate covers a projection of a channel region of the ninth transistor on the substrate substrate, the first extension section is connected between two adjacent second extension sections, and a projection of the first extension section on the substrate substrate overlaps with a projection of the third bridge portion on the substrate substrate. A size of the projection of the first extension section on the substrate substrate in a second direction is smaller than a size of the projection of the second extension section on the substrate substrate in the second direction, and the first direction and the second direction intersect.

8. The display panel of claim 7, wherein, A ratio of a size of the projection of the first extension section on the substrate substrate in a second direction to a size of the projection of the second extension section on the substrate substrate in the second direction is 50%-70%.

9. The display panel of claim 1, wherein, The display panel further includes: A first gate layer is located on one side of the substrate substrate, and the first gate layer includes a first gate line. The first gate line includes a plurality of first gate line sections. The projections of the plurality of first gate line sections in the same first gate line on the substrate substrate extend along a first direction and are distributed at intervals along the first direction. Part of the structure of the first gate line section is used to form a gate of the ninth transistor. A first source-drain layer is located on a side of the first gate layer away from the substrate substrate. The first source-drain layer includes a third bridge portion. The third bridge portion is connected to the second electrode of the ninth transistor through a via. The projection of the third bridge portion on the substrate substrate is located between the projections of two adjacent first gate line sections in the same first gate line on the substrate substrate. Thirteenth bridge portions are respectively connected between two adjacent first gate line sections in the same first gate line through vias. The projection of the thirteenth bridge portion on the substrate substrate and the projection of the third bridge portion on the substrate substrate do not overlap.

10. The display panel of claim 9, wherein, The thirteenth bridge portion is located on the first source-drain layer.

11. The display panel of claim 1, wherein, The display panel further includes: A third gate layer, part of the structure of which is used to form a first gate of the second transistor. A first source-drain layer is located on a side of the third gate layer away from the substrate substrate. The first source-drain layer includes a third bridge portion. The third bridge portion is connected to the second electrode of the ninth transistor through a via. A second source-drain layer is located on a side of the first source-drain layer away from the substrate substrate. The second source-drain layer includes a power supply line. The power supply line is used to provide a power supply signal to the pixel driving circuit. The projection of the power supply line on the substrate substrate extends along a second direction. The power supply line includes a main body portion and a protruding portion. The projection of the protruding portion on the substrate substrate protrudes from one side of the projection of the main body portion on the substrate substrate in a first direction. The first direction and the second direction intersect. The projection of the protruding portion on the substrate substrate and the projection of the third bridge portion on the substrate substrate at least partially overlap.

12. The display panel of claim 11, wherein, A ratio of a maximum size of the projection of the protruding portion on the substrate substrate in the first direction to a maximum size of the projection of the power supply line on the substrate substrate in the first direction is 10%-30%.

13. The display panel of claim 6, wherein, The on level polarity of the ninth transistor and the second transistor is opposite, and the display panel further comprises: A third gate layer comprises a second gate line, a projection of the second gate line on the substrate substrate extends along a first direction, and part of the structure of the second gate line is used to form a first gate of the second transistor; A first source-drain layer is located on a side of the third gate layer away from the substrate substrate, and the first source-drain layer comprises a third bridge portion, the third bridge portion comprises a first via connection portion, a second via connection portion, and an extension portion, the first via connection portion is connected to the first electrode of the ninth transistor through a via, the second via connection portion is connected to the first electrode of the second transistor through a via, and the extension portion is connected to one end of the second via connection portion away from the first via connection portion; The projection of the extension portion on the substrate substrate and the projection of the second gate line on the substrate substrate overlap.

14. The display panel of claim 13, wherein, The overlapping area of the projection of the first gate line on the substrate substrate and the third bridge portion on the substrate substrate is greater than the overlapping area of the projection of the second gate line on the substrate substrate and the projection of the third bridge portion on the substrate substrate.

15. The display panel of claim 14, wherein, The display panel further comprises: A second source-drain layer is located on a side of the first source-drain layer away from the substrate substrate, and the second source-drain layer comprises a power supply line, the power supply line is used to provide a power supply signal to the pixel driving circuit, a projection of the power supply line on the substrate substrate extends along a second direction, and the first direction and the second direction intersect; The projection of the power supply line on the substrate substrate and the projection of the third bridge portion on the substrate substrate overlap; The overlapping area of the projection of the power supply line on the substrate substrate and the projection of the third bridge portion on the substrate substrate is greater than the overlapping area of the projection of the first gate line on the substrate substrate and the third bridge portion on the substrate substrate; And / or, the overlapping area of the projection of the power supply line on the substrate substrate and the projection of the third bridge portion on the substrate substrate is greater than the overlapping area of the projection of the second gate line on the substrate substrate and the projection of the third bridge portion on the substrate substrate. The ninth transistor is a double-gate structure.

16. The display panel of claim 1, wherein, The display panel further comprises a light emitting unit, and the pixel driving circuit further comprises a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, and a capacitor; 17. The display panel of any of claims 1-16, wherein, The first electrode of the first transistor is connected to a first initial signal line, and the second electrode is connected to the second electrode of the ninth transistor; The first electrode of the fourth transistor is connected to a data line, and the second electrode is connected to the first electrode of the driving transistor; The first electrode of the fifth transistor is connected to a power supply line, and the second electrode is connected to the first electrode of the driving transistor; The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode is connected to the first electrode of the light emitting unit; The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light emitting unit; ​ A first electrode of the eighth transistor is connected with a third initial signal line, and a second electrode of the eighth transistor is connected with a first electrode of the driving transistor; A first electrode of the capacitor is connected with a gate electrode of the driving transistor, and a second electrode of the capacitor is connected with the power supply line; The driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are P-type transistors, and the first transistor and the second transistor are N-type transistors.

18. The display panel of any of claims 1-16, wherein, The display panel further comprises a light emitting unit, and the pixel driving circuit further comprises a first transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor. A first electrode of the first transistor is connected with a first initial signal line, and a second electrode of the first transistor is connected with a second electrode of the ninth transistor; A first electrode of the fourth transistor is connected with a data line, and a second electrode of the fourth transistor is connected with a first electrode of the driving transistor; A first electrode of the fifth transistor is connected with a power supply line, and a second electrode of the fifth transistor is connected with a first electrode of the driving transistor; A first electrode of the sixth transistor is connected with a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected with a first electrode of the light emitting unit; A first electrode of the seventh transistor is connected with a second initial signal line, and a second electrode of the seventh transistor is connected with a first electrode of the light emitting unit; A first electrode of the eighth transistor is connected with a third initial signal line, and a second electrode of the eighth transistor is connected with a first electrode of the driving transistor; The display panel further comprises: A first active layer is located on one side of the substrate, and at least part of the structure of the first active layer is used to form a channel region of the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor; A first gate layer is located on a side of the first active layer away from the substrate, and at least part of the structure of the first gate layer is used to form a gate electrode of the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor; A second active layer is located on a side of the first gate layer away from the substrate, and at least part of the structure of the second active layer is used to form a channel region of the first transistor and the second transistor; A third gate layer is located on a side of the second active layer away from the substrate, and at least part of the structure of the third gate layer is used to form a gate electrode of the first transistor and the second transistor; The driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor and the ninth transistor are polycrystalline silicon transistors, and the first transistor and the second transistor are oxide transistors.

19. The display panel of any of claims 1-18, wherein, The pixel driving circuit further comprises a fifth transistor and a sixth transistor; A first electrode of the fifth transistor is connected with a power supply line, and a second electrode of the fifth transistor is connected with a first electrode of the driving transistor; A first electrode of the sixth transistor is connected with a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected with a first electrode of the light emitting unit; The display panel further comprises: Part of the structure of an enable signal line is used to form a gate electrode of the fifth transistor and the sixth transistor respectively.

20. A display device comprising: The display device comprises the display panel of any one of claims 1-19.

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