Chip packaging structure, manufacturing method therefor, and electronic device

Abstract

Embodiments of the present application relate to the technical field of semiconductors, and provide a chip packaging structure, a manufacturing method therefor, and an electronic device, for use in reducing the packaging costs of the chip packaging structure. The chip packaging structure comprises: a wafer having a first surface provided with a plurality of first contacts; a chip structure disposed on a second surface of the wafer; a plastic packaging film covering the surface and at least part of the side surface of the chip structure; and a supporting layer covering the surface of the plastic packaging film. The chip structure is electrically connected to the wafer.

Description

Chip packaging structure, preparation method thereof and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202411383775.1, filed on September 30, 2024, and entitled "Chip packaging structure, preparation method thereof and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, in particular to a chip packaging structure, a preparation method thereof and an electronic device. BACKGROUND

[0003] With the development of electronic technology, the functions of electronic devices are constantly enriched and comprehensive, and chips for realizing different functions are integrated in electronic devices, which increases the demand for integrated circuits in electronic devices. As a result, the packaging of integrated circuits develops from planar packaging to vertical stacked packaging, such as 2.5D packaging or 3D packaging, to improve the integration of integrated circuits.

[0004] However, in order to realize high-density, small-size and low-power chip packaging, the existing chip packaging process has a complex process and high cost. SUMMARY

[0005] The present application provides a chip packaging structure, a preparation method thereof and an electronic device, which can reduce the packaging cost of the chip packaging structure.

[0006] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0007] In a first aspect, the present application provides a chip packaging structure, which includes a wafer having a plurality of first contacts on a first surface, a chip structure disposed on a second surface of the wafer, a plastic packaging film covering at least part of the side surface of the chip structure, and a support layer covering the surface of the plastic packaging film. The chip structure and the wafer are electrically connected.

[0008] The chip packaging structure provided by the present application can strengthen the mechanical strength of the chip packaging structure, protect the chip structure and improve the reliability of the chip packaging structure. The plastic packaging film and the support layer are reserved on the chip structure, so the plastic packaging film and the support layer do not need to be removed by a debonding process. In the present application, the plastic packaging film is used to connect the support layer and the chip structure, so the temporary bonding glue is not needed to connect the support layer and the chip structure, which avoids the use of high-cost temporary bonding glue and the use of temporary bonding glue remover to remove the temporary bonding glue, thereby reducing the packaging cost.

[0009] In a possible implementation, the side surface of the plastic sealing film is flush with the side surface of the wafer. In this way, the side surface of the plastic sealing film formed by cutting is flush with the side surface of the wafer.

[0010] In a possible implementation, the plastic sealing film includes a blue film layer, an ultraviolet light curing film layer, a dry film layer, or a chip bonding film layer. In this way, the cost of the chip packaging structure can be reduced.

[0011] In a possible implementation, the side surface of the support layer is flush with the side surface of the plastic sealing film. In this way, the side surface of the plastic sealing film formed by cutting is flush with the side surface of the support layer.

[0012] In a possible implementation, the material of the support layer includes silicon or silicon dioxide. In this way, the cost of the chip packaging structure can be reduced.

[0013] In a possible implementation, the chip packaging structure further includes a redistribution layer and a bump; the redistribution layer is electrically connected with the first contact; the bottom of the redistribution layer is provided with the bump, and the redistribution layer and the bump are electrically connected. In this way, an embodiment of the chip packaging structure is provided.

[0014] In a possible implementation, the second surface of the wafer has a plurality of second contacts, the first contacts and the second contacts are electrically connected; the chip structure has a plurality of third contacts; the second contacts of the wafer are electrically connected with the third contacts of the chip structure. In this way, an embodiment of the 3D IC chip packaging structure is provided.

[0015] In a possible implementation, the chip structure includes a chip, a board, and a plurality of through holes penetrating through the board; the chip is electrically connected with the wafer through the board; the chip is arranged on the board and is electrically connected with the first end of the through hole; the second end of the through hole is electrically connected with the wafer. In this way, an embodiment of the 2.5D IC chip packaging structure is provided.

[0016] According to a second aspect of the embodiments of the present application, a preparation method of a chip packaging structure is provided, including: providing a wafer, the wafer having a plurality of first contacts and second contacts; the first contacts are distributed in the wafer, the second contacts are distributed on the second surface of the wafer, and the first contacts and the second contacts are electrically connected; providing a chip structure, placing the chip structure on the wafer, and connecting the chip structure with the second contacts of the wafer; connecting a support plate with the chip structure through a plastic sealing film, and the plastic sealing film also fills at least part of the side surface of the chip structure; thinning the support plate, forming a support layer, and cutting, so that the support layer, the chip structure, and the wafer after cutting form a chip packaging structure.

[0017] The preparation method of the chip packaging structure provided in the embodiments of the present application, the support plate and the chip structure are connected through the plastic packaging film, the support plate is taken as a bearing structure, and then the support plate is thinned to form a support layer. The plastic packaging film is also filled in the gap between the chip structures, which can strengthen the mechanical strength of the chip packaging structure, protect the chip structure, has fewer process steps, is high in preparation efficiency, and can reduce the cost of the chip packaging structure. The method in the embodiments of the present application does not need to remove the support plate through a debonding process, simultaneously does not need to connect the support plate and the chip structure by using temporary bonding glue, and also does not need to use a temporary bonding glue remover to remove the temporary bonding glue. Since the degreasing process and the equipment cost of the degreasing process are relatively high, and the requirement for the bonding glue is relatively high, the cost of the bonding glue is also relatively high. The scheme provided in the embodiments of the present application does not need to use the bonding glue with a relatively high cost, and has fewer process steps in the preparation method, is simple in process, and is low in packaging cost.

[0018] In a possible implementation, the support plate and the chip structure are connected through a lamination bonding process. In this way, a bonding mode is provided, and the packaging cost of the chip packaging structure can be reduced.

[0019] In a possible implementation, the wafer and the chip structure are connected through a hybrid bonding process. In this way, a bonding mode is provided, and a high-density and small-size packaging structure can be implemented, and the packaging cost of the chip packaging structure can be reduced.

[0020] In a possible implementation, after the support plate and the chip structure are connected through the plastic packaging film, before the support plate is thinned, the method further includes: thinning the wafer away from the chip structure to expose the first contact; and sequentially forming a redistribution layer and a bump on the first contact. In this way, a connection mode of the chip packaging structure is provided.

[0021] The third aspect of the embodiments of the present application provides an electronic device including the chip packaging structure of any one of the first aspect and the printed circuit board, and the chip packaging structure is electrically connected to the printed circuit board.

[0022] The electronic device provided in the third aspect of the embodiments of the present application includes the chip packaging structure of any one of the first aspect, and has the same beneficial effects as the chip packaging structure, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0023] FIG. 1 is a structural schematic diagram of an electronic device provided in the embodiments of the present application;

[0024] FIG. 2A is a structural schematic diagram of a chip packaging structure supported on a PCB provided in the embodiments of the present application;

[0025] FIG. 2B is a structural schematic diagram of a chip packaging structure;

[0026] FIG. 3 is a structural schematic diagram of a chip packaging structure according to an embodiment of the present application;

[0027] FIG. 4 is a flowchart of a method for manufacturing a chip packaging structure according to an embodiment of the present application;

[0028] FIGS. 5A-5L are process schematic diagrams of a method for manufacturing a chip packaging structure according to an embodiment of the present application;

[0029] FIG. 6A is a structural schematic diagram of another chip packaging structure according to an embodiment of the present application;

[0030] FIG. 6B is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application;

[0031] FIG. 6C is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application;

[0032] FIG. 7A is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application;

[0033] FIG. 7B is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application;

[0034] FIG. 8 is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application;

[0035] FIG. 9 is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application.

[0036] FIG. 1 is an electronic device according to an embodiment of the present application; FIG. 2 is a display module according to an embodiment of the present application; FIG. 3 is a structural schematic diagram of a chip packaging structure according to an embodiment of the present application; FIG. 4 is a flowchart of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5A is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5B is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5C is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5D is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5E is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5F is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5G is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5H is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5I is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5J is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5K is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 5L is a process schematic diagram of a method for manufacturing a chip packaging structure according to an embodiment of the present application; FIG. 6A is a structural schematic diagram of another chip packaging structure according to an embodiment of the present application; FIG. 6B is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application; FIG. 6C is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application; FIG. 7A is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application; FIG. 7B is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application; FIG. 8 is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application; FIG. 9 is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application; and FIG. 10 is a structural schematic diagram of still another chip packaging structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of the embodiments of the present application.

[0038] Hereinafter, the terms "second", "first", etc. are used only for the convenience of description and can not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "second", "first", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise stated, the meaning of "a plurality of" is two or more.

[0039] In addition, in the embodiments of the present application, the orientation terms such as "upper", "lower", "left", "right", etc. can include but not limited to the orientation defined by the relative placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for relative description and clarification, and can be changed accordingly according to the change of the placement of the components in the drawings.

[0040] In the embodiments of the present application, unless otherwise explicitly specified and limited, the term "connection" should be understood broadly, for example, "connection" can be fixed connection, or detachable connection, or integral; can be directly connected, or indirectly connected through intermediate medium. In addition, the term "coupling" can be direct electrical connection, or indirect electrical connection through intermediate medium. The term "contact" can be direct contact, or indirect contact through intermediate medium.

[0041] In the embodiments of the present application, "and / or" describes the association relationship between the associated objects, which means that there can be three kinds of relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. The character " / " generally represents that the associated objects before and after it have an "or" relationship.

[0042] Embodiments of the present application provide an electronic device. The electronic device may, for example, be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. The consumer electronic product may, for example, be a mobile phone, a pad, a notebook computer, an e-reader, a personal computer (PC), a personal digital assistant (PDA), a desktop display, a smart wearable product (for example, a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a drone, and the like. The home electronic product may, for example, be a smart door lock, a television, a remote controller, a refrigerator, a charging household small appliance (for example, a soybean milk machine, a sweeping robot), and the like. The vehicle-mounted electronic product may, for example, be a vehicle-mounted navigation device, a vehicle-mounted DVD, and the like. The financial terminal product may, for example, be an ATM machine, a self-service terminal, and the like. Embodiments of the present application do not specially limit the specific form of the electronic device. The following embodiments are exemplarily described by taking a mobile phone as an example.

[0043] An example structure of an electronic device is shown in FIG. 1. The electronic device 1 mainly includes a display module 2, a middle frame 3, a shell (or referred to as a battery cover, a back shell) 4, and a cover plate 5.

[0044] The display module 2 has a light-out side at which a display image can be seen, and a non-light-out side opposite to the light-out side. The back of the display module 2 is close to the middle frame 3. The cover plate 5 is arranged at the light-out side of the display module 2.

[0045] The cover plate 5 is located at a side of the display module 2 away from the middle frame 3. The cover plate 5 may, for example, be a cover glass (CG), which may have a certain toughness.

[0046] The middle frame 3 is located between the display module 2 and the shell 4. A surface of the middle frame 3 away from the display module 2 is used to mount internal elements such as a battery, a printed circuit board (PCB), a camera, an antenna, and the like. After the shell 4 is covered with the middle frame 3, the internal elements are located between the shell 4 and the middle frame 3.

[0047] Exemplarily, the display module 2 includes a display panel (DP).

[0048] The electronic device 1 further includes a chip package structure of a processor (CPU) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuit (PMIC), a memory chip (for example, a high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, a NAND flash, an image sensor chip, an artificial intelligence (AI) chip, and a game graphics card chip, etc. disposed on the printed circuit board. The PCB is used to carry the chip package structure and complete signal interaction with the chip package structure.

[0049] As shown in FIG. 2A, the chip package structure 10 is carried on the printed circuit board. Generally, the chip 12 with a functional circuit is electrically connected with the package board 11, and then the package board 11 is electrically connected with the PCB.

[0050] The package board 11 is a carrier of the chip package structure, and is a connecting body of the chip 12 and the PCB, and is used to realize the connection between the chip 12 and the PCB.

[0051] The first surface and the second surface of the package board 11 are both provided with external pins (solder balls or pads). The external pins on one surface of the package board 11 are connected with the chip 12, and the external pins on the other surface of the package board 11 are connected with the PCB.

[0052] For example, the external pins on the first surface of the package board 11 are connected with the chip 12, and the external pins on the second surface of the package board 11 are connected with the PCB.

[0053] The chip 12 is electrically connected with the package board 11. The chip 12 can be a bare chip or a packaged chip. The present application does not limit this, and reasonable setting can be made according to actual conditions.

[0054] For example, the chip 12 is integrated with at least one transistor. The transistor can be a field effect transistor (FET) for example.

[0055] It is clarified herein that the field effect transistor can include a planar transistor such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or a junction field-effect transistor (JFET), and can also include a three-dimensional transistor such as a fin field-effect transistor (FinFET), a gate all around field effect transistor (GAAFET), or a fork sheet field effect transistor (forksheet FET or FSFET). The embodiments of the present application do not limit this.

[0056] With the development of semiconductor technology, the functions of electronic device 1 tend to be rich and comprehensive, and chips 12 for realizing different functions are integrated in electronic device 1, which increases the demand for chip packaging structure 10 on the printed circuit board in electronic device 1. While the performance of IC dies needs to be improved, the requirements for chip packaging structure 10 are also increasing. On the one hand, chip 12 gradually develops towards miniaturization, and the process of chip 12 gradually decreases, for example, the process of chip 12 decreases to 5nm, 3nm or even 1nm, and approaches the physical limit. On the other hand, the demand for heterogeneous integration and heterogeneous integration of chips with different processes, different functions or different materials also brings new challenges to the development of planar printed circuit boards, and makes the packaging of printed circuit boards develop from planar packaging to vertical stacked packaging, thereby realizing 3D IC packaging technology and 2.5D IC packaging technology. For example, micro-electro-mechanical system chips, radio frequency communication chips, passive device chips and processor chips with different functions can be vertically stacked and integrated through the above packaging technology, thereby maximizing the use of the vertical integration space to improve the integration of the printed circuit board.

[0057] For example, in 2.5D IC packaging technology or 3D IC packaging technology, an interposer (INTP) will be used to realize the interconnection between chip 12 and chip 12, and between chip 12 and packaging board 11. Chip 12 is connected to PCB through interposer, and interposer is one of the important structures in chip packaging technology, which has significant advantages in design and preparation.

[0058] However, with the development of miniaturization of the chip 12, the design cost of the chip 12 is increased. In order to meet the miniaturization and multifunctionalization of the chip packaging structure 10, advanced packaging technology has become the development direction of semiconductor technology. Advanced packaging technology generally refers to packaging technology that integrates different systems into the same package to achieve higher system efficiency. That is, as long as the packaging technology can improve the overall performance of the chip (including transmission speed, operation speed, etc.), it can be considered as advanced packaging. Advanced packaging can realize the high-density integration, miniaturization and low cost of chips, and has the characteristics of small size, high performance and low power consumption. The common advanced packaging technologies at present include fan-out packaging, fan-in packaging, etc.

[0059] Taking the chip 12 as an IC die as an example, a fan-out packaging technology is shown in FIG. 2B. A plurality of IC dies with different functions are placed on a conversion board, and then the IC dies are connected to a wafer through the conversion board by a chip on wafer (COW) packaging process, and finally connected to the packaging board 11. That is, the chip is connected to the wafer by the COW packaging method, and then the COW chip is connected to the packaging board 11, that is, the chip on wafer on substrate (CoWoS) structure. The periphery of the IC die is also wrapped with a plastic encapsulation layer.

[0060] The above-mentioned COW bonding and chip on chip (COC) bonding are both achieved by thermal compression bonding (TCB) with micro bumps (ubumps), such as tin balls, as the bonding layer. Due to the size limitation of the tin balls, the tin ball size is large, and the shape is spherical, which leads to the chip packaging structure cannot be made smaller, which is not conducive to the development of high-density and small-size chip packaging structure. By hybrid bonding, Cu pad is used as the bonding layer, which can make the chip packaging size reach nanoscale, so the interconnection realized by Cu pad can realize higher density of chip packaging structure.

[0061] However, in the current packaging process of the chip packaging structure, first, a temporary bonding process is needed to bond the support plate as a bearing structure with one side of the chip structure by using temporary bonding glue, to form a conductive structure such as a bump on the other side of the chip structure, then the support plate needs to be removed by a laser debonding or mechanical debonding process, and the temporary bonding glue remaining on the surface of the chip structure needs to be cleaned, and finally a plastic encapsulation layer is formed and packaging processes such as cutting and scribing are performed to complete the packaging. Since the temporary bonding glue needs to be resistant to high temperature and easy to remove, for example, it can change its properties and be removed under laser irradiation, the cost of the temporary bonding glue is relatively high, and the removal cost is also relatively high. In addition, the temporary bonding process and the debonding process involved in the above packaging process have high costs, and the costs of the plastic encapsulation layer and the temporary bonding glue are also relatively high, resulting in high packaging cost of the chip packaging process.

[0062] Therefore, in order to reduce the cost of the packaging process, the chip packaging structure provided in the embodiments of the present application is shown in FIG. 3, which includes a wafer 120 having a first surface a1 with a plurality of first contacts 101, a chip structure 110 disposed on a second surface a2 of the wafer 120, a plastic encapsulation film 320 covering the surface and at least part of the side surface of the chip structure 110, and a support layer 310 covering the surface of the plastic encapsulation film 320. The chip structure 110 and the wafer 120 are electrically connected.

[0063] In this way, in the embodiments of the present application, the support layer 310 and the chip structure 110 are connected by the plastic encapsulation film 320, avoiding the use of high-cost temporary bonding glue, which can reduce the packaging cost. Similarly, the support layer 310 does not need to be removed by a debonding process, and the temporary bonding glue does not need to be removed by a temporary bonding glue remover, so the packaging cost is relatively low and the packaging process steps are relatively few.

[0064] As shown in FIG. 4, the present application provides a preparation method of a chip packaging structure, which includes:

[0065] S1, as shown in FIG. 5A, a wafer 100 is provided.

[0066] As shown in FIG. 5A, the wafer 100 has a plurality of first contacts 101 and a plurality of second contacts 102.

[0067] The wafer 100 can include a first surface a1 and a second surface a2 arranged opposite to each other.

[0068] For example, as shown in FIG. 5A, the first contacts 101 are distributed in the wafer 100, the second contacts 102 are distributed on the second surface a2 of the wafer 100, and the first contacts 101 and the second contacts 102 are electrically connected.

[0069] The first contact 101 and the second contact 102 can be directly connected, or can also be indirectly connected. The embodiments of the present application do not limit this, and reasonable settings can be made according to actual conditions.

[0070] Regarding the first contact 101 and the second contact 102, the first contact 101 and the second contact 102 can be formed on the surface of the wafer through a through silicon via (TSV) process and a damascene process. The damascene process is a process of etching a region to be formed into a metal interconnection structure, and then filling a metal material to realize a multi-layer metal interconnection. The above-mentioned surface of the wafer is the second surface a2 of the wafer 100 formed.

[0071] The embodiments of the present application do not limit the distribution of the first contact 101 and the second contact 102. For example, the distribution of the first contact 101 and the second contact 102 can be set according to the cutting path of the wafer 100 in subsequent slicing. For example, the first contact 101 and the second contact 102 are not formed on the cutting path.

[0072] The embodiments of the present application do not limit the specific structure of the wafer 100. For example, as shown in FIG. 5B, the wafer can be an unprocessed wafer obtained from a wafer factory, and the first contact 101 and the second contact 102 are formed.

[0073] S2, as shown in FIG. 5C, the chip structure 110 is placed on the wafer 100, and the chip structure 110 is connected with the second contact 102 of the wafer 100.

[0074] That is, the chip structure 110 is placed on the second surface a2 of the wafer 100.

[0075] For convenience of illustration, the thickness direction of the chip structure 110 and the wafer 100 is referred to as the first direction x, and the direction perpendicular to the first direction x is referred to as the second direction y. The chip structure 110 is placed on the wafer 100, that is, along the first direction x, the chip structure 110 and the wafer 100 are stacked.

[0076] For example, the chip structure 110 can be a die (also referred to as a die or a particle). It can be understood that the wafer obtained by cutting is a die.

[0077] At this time, the chip structure 110 can be a small chip selected by a known good die (KGD) method after cutting. For example, the known good die is picked and placed on the wafer 100.

[0078] Alternatively, the chip structure 110 can also be a packaged chip obtained by packaging a bare chip.

[0079] The chip structure 110 placed on the wafer 100 can be one or multiple.

[0080] As shown in FIG. 5D, the multiple chip structures 110 can be arranged side by side on the wafer 100. That is, the multiple chip structures 110 can be arranged side by side on the wafer 100 along the second direction y.

[0081] Alternatively, as shown in FIG. 5D, the multiple chip structures 110 can be stacked on the wafer 100. That is, the multiple chip structures 110 can be stacked on the wafer 100 along the first direction x.

[0082] It can be understood that the multiple chip structures 110 can all be bare chips, all be packaged chips, or part be bare chips and part be packaged chips.

[0083] In some embodiments, the chip structure 110 is connected to the wafer 100 through the second contact 102. As shown in FIG. 5D, the chip structure 110 and the wafer 100 can be connected through hybrid bonding. The chip structure 110 has multiple third contacts 103 and fourth contacts 104. The third contacts 103 and the fourth contacts 104 are electrically connected. The connection between the chip structure 110 and the wafer 100 is achieved through the third contacts 103 of the chip structure 110 and the second contacts 102 of the wafer 100.

[0084] As shown in FIG. 5D, the third contacts 103 and the fourth contacts 104 can be regarded as wiring layers in the chip structure 110. For example, the wiring layers can also be conductive structures such as a transition board.

[0085] In this way, hybrid bonding between chips and wafers (C2W) can be achieved, avoiding connection through bumps such as tin balls, and there is no size limitation on the chip structure 110, which can use smaller chip structures 110, thereby achieving high-density and small-size chip packaging structures, without welding, lower packaging cost, and conducive to three-dimensional stacked chip packaging structures.

[0086] Alternatively, as shown in FIG. 5E, the chip structure 110 and the wafer 100 can be connected through bumps such as tin balls.

[0087] S3, as shown in FIG. 5F, the support plate 310' is connected with the chip structure 110 through the plastic packaging film 320.

[0088] That is, as shown in FIG. 5F, the support plate 310' is placed on the side of the chip structure 110 away from the wafer. At this time, the support plate 310', the chip structure 110, and the wafer 100 are sequentially stacked along the first direction x.

[0089] The support plate 310' can include a wafer. The material of the support plate 310' can include, for example, silicon, silicon oxide, silicon dioxide, metal, or other materials having similar functions and being compatible with subsequent packaging processes. The support plate 310' can include, for example, a glass layer, a ceramic layer, or a polymer layer, etc.

[0090] The shape of the support plate 310' can be a wafer shape, a square shape, or any other arbitrary shape. The material and shape of the support plate 310' are not limited in the embodiments of the present application, and can be reasonably set according to actual conditions.

[0091] The support plate 310' is a wafer, that is, when the material of the support plate 310' includes silicon, the packaging cost can be reduced.

[0092] In some embodiments, as shown in FIG. 5F, the support plate 310' and the chip structure 110 are connected by the plastic encapsulation film 320.

[0093] For example, the material of the plastic encapsulation film 320 can include an adhesive film layer or an adhesive. For example, the plastic encapsulation film 320 can include a blue film layer, an ultra violet (UV) curing film layer, a dry film layer, or a die attach film (DAF) layer.

[0094] The connection between the support plate 310' and the chip structure 110 can be formed, for example, by a lamination bonding process to connect the support plate 310' and the chip structure 110. In order to fix the support plate 310' on the chip structure 110, the support plate 310' and the chip structure 110 are bonded by the plastic encapsulation film 320.

[0095] In some embodiments, the thickness of the chip structure 110 is small, for example, less than 100 μm. The size of the gap between the chip structures 110 along the direction perpendicular to the thickness of the chip structure 110 (the first direction x), that is, along the second direction y, is less than or equal to 30 μm. At this time, the aspect ratio of the gap between the chip structures 110 is small. At this time, as shown in FIG. 5F, the plastic encapsulation film 320 also fills the gap between the chip structures 110.

[0096] That is, the plastic encapsulation film 320 also fills at least part of the side surface of the chip structure 110.

[0097] Herein, the surface of the chip structure 110 in contact with the wafer 100 is referred to as the bottom surface of the chip structure 110, the surface opposite to the bottom surface of the chip structure 110 is referred to as the top surface of the chip structure 110, and the surface connecting the top surface of the chip structure 110 and the bottom surface of the chip structure 110 is referred to as the side surface of the chip structure 110.

[0098] For example, the adhesive material is filled into the gap between the chip structures 110, i.e., the gap between the chip structure 110 and the plastic packaging film 320 by the lamination bonding process. At this time, the surface of the chip structure 110 away from the wafer 100 still retains the adhesive material, which is used to connect the support plate 310'.

[0099] In the embodiment of the present application, the connection between the support plate 310' and the chip structure 110 does not need to be achieved by a temporary bonding process, and the support plate 310' and the chip structure 110 do not need to be connected by using a temporary bonding adhesive. Therefore, the packaging cost of the chip packaging structure can be reduced by the lamination bonding process in the embodiment of the present application.

[0100] In some embodiments, step S3 further includes: thinning the wafer 100 to expose the first contact 101, as shown in FIG. 5G.

[0101] At this time, the structure after step S3 is flipped, i.e., the support plate 310' is used to carry the wafer 100 and the chip structure 110 and other structures arranged thereon.

[0102] At this time, the first surface a1 of the wafer 100 is ground to expose the first contact 101.

[0103] S4, as shown in FIG. 5H, the conductive structure 130 is formed.

[0104] The conductive structure 130 is electrically connected with the chip structure 110.

[0105] As shown in FIG. 5H, the conductive structure 130 is formed on the side of the chip structure 110 away from the support plate 310'. That is, the conductive structure 130 is formed on the side of the wafer 100 away from the chip structure 110.

[0106] For example, the conductive structure 130 is formed on the first contact 101.

[0107] The conductive structure 130 is electrically connected with the first contact 101.

[0108] For example, the conductive structure 130 can include a redistribution layer (RDL) 311 and a bump 312.

[0109] In some embodiments, step S4 can include:

[0110] S41, forming a redistribution layer 131 on the surface of the wafer 100 far from the side of the support plate 310'.

[0111] The redistribution layer 131 is electrically connected with the first contact 101.

[0112] S42, forming a bump 132 on the surface of the redistribution layer 131 far from the side of the support plate 310'.

[0113] Exemplarily, the bump 132 can include a solder ball, a bump, a Cu pillar, an under bump metalization (UBM), a controlled collapse chip connection bump (C4 bump), and other structures composed of metal solder. Of course, the material and shape of the bump 132 are not limited in the embodiments of the present application, and the preparation process of the bump 132 is different according to the structure of the bump 132.

[0114] Exemplarily, when the structure of the bump 132 is a solder ball, the bump 132 can be prepared by coating, exposure, development, solder paste printing, ball placement, and other processes.

[0115] Alternatively, exemplarily, when the structure of the bump 132 is a Cu pillar, the bump 132 can be prepared by coating, exposure, development, solidification, sputtering, electroplating, etching, reflow, and other processes. According to the need, different preparation processes can be selected to form bumps 132 with different structures.

[0116] In the embodiments of the present application, different conductive structures 130 can be selected according to the actual need. For example, only the redistribution layer 131 can be formed, or only the bump 132 can be formed, or both the redistribution layer 131 and the bump 132 can be formed.

[0117] S43, as shown in FIG. 5I, thinning the support plate 310'.

[0118] In step S43, the structure formed in step S42 is first placed upside down, and then the support plate 310' is thinned by a grinding process or a thinning process. For example, the support plate 310' can be thinned by mechanical grinding, chemical mechanical planarization process, wet etching, or dry etching, and the thinned support plate 310' is called a support layer 310.

[0119] At this time, as shown in FIG. 5I, the chip structure 110 far from the surface of the wafer 100 still retains part of the support layer 310 and the plastic package film 320.

[0120] In the embodiment of the present application, the support plate 310' does not need to be removed by a debonding process, and temporary bonding glue and a temporary bonding glue remover are not needed, so that the packaging cost of the chip packaging structure can be reduced.

[0121] Alternatively, as shown in FIG. 5J, the support plate 310' can be removed by removing the plastic packaging film 320 between the support plate 310' and the chip structure 110.

[0122] S5, as shown in FIG. 5K, the chip packaging structure 10 is formed by cutting.

[0123] Alternatively, as shown in FIG. 5K, the chip structure 110 is covered with the plastic packaging film 320 and the support layer 310 away from the surface of the wafer 100, that is, the surface of the plastic packaging film 320 or the support layer 310 is cut to form the chip packaging structure 10.

[0124] At this time, as shown in FIG. 5K, the wafer 100 can be cut to form a plurality of discrete dies 120. The chip structure 110, the cut wafer 100 (die 120), the cut conductive structure 130, and the cut plastic packaging film 320 form the chip packaging structure 10.

[0125] Alternatively, as shown in FIG. 5L, the chip structure 110 is exposed away from the surface of the wafer 100, that is, the surface of the plastic packaging film 320 between the chip structures 110 is cut to form the chip packaging structure 10.

[0126] At this time, the cutting is performed along the gap between the chip structures 110. Alternatively, the cutting can be performed at the middle position of the gap between the chip structures 110, or the cutting can be performed close to one side of the chip structure 110, as long as the side of the cut chip structure 110 is wrapped with the plastic packaging film 320.

[0127] Here, it is clarified that whether the cutting is performed or not in the embodiment of the present application can be selected according to actual needs.

[0128] The above preparation method provided by the embodiment of the present application does not limit the order of any steps, which can be reasonably adjusted according to needs.

[0129] In addition, the steps S1-S5 described above can remove some steps according to needs, and do not need to include each step. Some steps can also be added according to needs, and do not need to include only the above steps.

[0130] The preparation method of the chip packaging structure provided in the embodiments of the present application is as follows: after the support plate 310' and the chip structure 110 are connected through the plastic packaging film 320, the support plate 310' is used as a bearing structure, the conductive structure 130 is formed on the chip structure 110, and then the support plate 310' is thinned to form the support layer 310. The method provided in the embodiments of the present application does not need to remove the support plate 310' through a debonding process, and also does not need to connect the support plate 310' and the chip structure 110 by using temporary bonding glue, and does not need to remove the temporary bonding glue by using a temporary bonding glue remover. Since the glue removing process and the equipment cost of the glue removing process are relatively high, and the requirement for the bonding glue is relatively high, the cost of the bonding glue is also relatively high. The scheme provided in the embodiments of the present application does not need to use the bonding glue with a relatively high cost, and the preparation method has fewer process steps and is simple, and the packaging cost is relatively low.

[0131] In addition, the preparation method provided in the embodiments of the present application can reduce the bonding cost by achieving the bonding between the chip structure and the support plate 310' through laminated bonding. The preparation method provided in the embodiments of the present application can achieve a high-density and small-size packaging structure by achieving the bonding between the chip structure and the wafer through hybrid bonding, without welding, and the packaging cost is relatively low, which is beneficial to achieving a three-dimensional stacked chip packaging structure. In the process of removing the support plate, the support plate is removed through grinding, without the need for debonding process, and without the need for temporary bonding glue, so that the packaging process cost can be reduced.

[0132] The following embodiments are used to illustrate the chip packaging structure provided in the embodiments of the present application, and the chip packaging structure can be prepared by using the preparation method of the chip packaging structure.

[0133] Based on this, as shown in FIG. 6A, the chip packaging structure 10 includes a wafer 120 with a plurality of first contacts 101 on a first surface a1, a chip structure 110 disposed on a second surface a2 of the wafer 120, a plastic packaging film 320 covering the surface and at least part of the side surface of the chip structure 110, and a support layer 310 covering the surface of the plastic packaging film 320. The chip structure 110 and the wafer 120 are electrically connected.

[0134] Regarding the chip structure 110, the chip included in the chip structure 110 can be one or multiple.

[0135] The embodiments of the present application do not limit the chip structure in the chip structure 110. In some embodiments, the chip can be a bare chip (also referred to as a die or a particle). It can be understood that the wafer is cut to obtain the bare chip.

[0136] In other embodiments, the chip can also be a packaged chip obtained by packaging the bare chip.

[0137] Exemplarily, the chip structure 110 includes one chip.

[0138] As shown in FIG. 6A, the chip structure 110 includes one chip.

[0139] Alternatively, exemplarily, as shown in FIG. 6B, the chip structure 110 includes multiple chips. For example, as shown in FIG. 6B, the multiple chips are arranged side by side.

[0140] Alternatively, as shown in FIG. 6C, the multiple chips can be stacked and arranged on the wafer 120.

[0141] It can be understood that, in the case that the chip structure 110 includes multiple chips, the multiple chips can all be bare chips; the multiple chips can all be packaged chips; or the multiple chips can be partly bare chips and partly packaged chips.

[0142] Regarding the wafer 120, with continued reference to FIG. 6A, the wafer 120 has a first surface a1 and a second surface a2 arranged oppositely. The first surface a1 of the wafer 120 has multiple first contacts 101, and the second surface a2 of the wafer 120 has multiple second contacts 102. The first contacts 101 and the second contacts 102 are electrically connected.

[0143] Exemplarily, the chip structure 110 is arranged on the wafer 120, i.e., the chip structure 110 is arranged on the second surface a2 of the wafer 120.

[0144] As shown in FIG. 6A, the chip structure 110 has multiple third contacts 103 and fourth contacts 104. The third contacts 103 are located on the surface of the chip structure 110, and the fourth contacts 104 are located inside the chip structure 110. The third contacts 103 and the fourth contacts 104 are electrically connected.

[0145] The chip structure 110 is electrically connected with the wafer 120. Exemplarily, the third contacts 103 of the chip structure 110 are electrically connected with the second contacts 102 of the wafer 120. That is, the connection between the chip structure 110 and the wafer 120 is achieved by the electrical connection between the third contacts 103 of the chip structure 110 and the second contacts 102 of the wafer 120.

[0146] At this time, the chip structure 110 and the wafer 120 can be connected by hybrid bonding. The connection between the chip structure 110 and the wafer 120 can be regarded as a chip packaging structure of 3D IC packaging.

[0147] In this way, hybrid bonding between wafers on a chip can be realized, avoiding connection through bumps such as tin balls, there is no size limitation on the chip structure 110, smaller chip structures 110 can be used, thereby realizing high-density and small-size chip packaging structures, without welding, lower packaging cost, and conducive to realizing three-dimensional stacked chip packaging structures.

[0148] Alternatively, as shown in FIG. 7A, the chip structure 110 and the wafer 120 can be connected through bumps such as tin balls.

[0149] At this time, the connection between the chip structure 110 and the wafer 120 can be regarded as a 2.5D IC packaging chip packaging structure.

[0150] The connection mode of the chip structure 110 and the wafer 120 in the embodiments of the present application is not limited, and can be reasonably set according to actual conditions.

[0151] In some embodiments, as shown in FIG. 7A, the chip packaging structure further includes a conductive structure 130. The conductive structure 130 is electrically connected with the first contact 101 of the wafer 120.

[0152] For example, the conductive structure 130 can include a redistribution layer 131 and a bump 132.

[0153] As shown in FIG. 7A, the bump 132 is located on the side of the redistribution layer 131 away from the chip structure 110, and the bump 132 is electrically connected with the redistribution layer 131.

[0154] The conductive structure 130 is used to connect the chip structure 110 and a packaging board (not shown in FIG. 7A).

[0155] In the embodiments of the present application, different conductive structures 130 can be selected according to actual needs. For example, the conductive structure 130 can only include the redistribution layer 131, or can only include the bump 132, or can include both the redistribution layer 131 and the bump 132.

[0156] The conductive structure 130 in the embodiments of the present application is not limited, as long as it can realize signal transmission between the chip packaging structure 10 and the packaging board.

[0157] In some embodiments, the chip structure 110 can include a chip 111 and a wiring layer stacked. The wiring layer is arranged on the side of the chip 111 close to the wafer 120.

[0158] The chip 111 is electrically connected with the wafer 120 through the wiring layer. For example, the wiring layer can include electrically connected third and fourth contacts 103 and 104.

[0159] For example, the wiring layer can be a conversion board.

[0160] As shown in FIG. 7B, the chip structure 110 can include a chip 111, a re-distribution layer 210, and a plurality of through holes 211 penetrating the re-distribution layer 210. The chip 111 and the re-distribution layer 210 are stacked.

[0161] Here, the chip 111 can be a die, for example.

[0162] As shown in FIG. 7B, the through hole 211 has a first end b1 and a second end b2 arranged oppositely.

[0163] For example, the chip 111 is arranged on the re-distribution layer 210 and is electrically connected to the first end b1 of the through hole 211. The second end b2 of the through hole 211 has a third contact 103. The second end b2 of the through hole 211 is connected to the second contact 102.

[0164] That is, the chip 111 is electrically connected to the wafer 120 through the re-distribution layer 210.

[0165] For example, the chip 111 is arranged on a first surface of the re-distribution layer 210, and the wafer 120 is arranged on a second surface of the re-distribution layer 210 opposite to the first surface. The through hole 211 penetrates the first surface and the second surface of the re-distribution layer 210. The first end b1 of the through hole 211 is located on the first surface of the re-distribution layer 210, and the second end b2 of the through hole 211 is located on the second surface of the re-distribution layer 210.

[0166] Continuing to refer to FIG. 6A, the chip package structure 10 further includes a molding film 320 and a support layer 310.

[0167] As shown in FIG. 6A, the molding film 320 covers the surface and at least part of the side surface of the chip structure 110. That is, the molding film 320 is located on a side of the chip structure 110 away from the conductive structure 130, and the support layer 310 is located on a side of the molding film 320 away from the chip structure 110.

[0168] That is, the molding film 320 covers the surface of the chip structure 110 away from the conductive structure 130, and the molding film 320 also wraps at least part of the side surface of the chip structure 110.

[0169] Here, it is clarified that the understanding of the side surface of the chip structure 110 can be that the surface of the chip structure 110 in contact with the wafer 100 is referred to as the bottom surface of the chip structure 110, the surface opposite to the bottom surface of the chip structure 110 is referred to as the top surface of the chip structure 110, and the surface connecting the top surface of the chip structure 110 and the bottom surface of the chip structure 110 is referred to as the side surface of the chip structure 110.

[0170] The plastic sealing film 320 can wrap one or more sides of the chip structure 110. In some embodiments, the plastic sealing film 320 can wrap at least part of the sides of the chip structure 110. The application does not limit the chip structure 110, and the chip structure 110 can be reasonably set according to actual conditions.

[0171] As shown in FIG. 6A, the plastic sealing film 320 is arranged on the wafer 120, and the plastic sealing film 320 covers the surface and the side of the chip structure 110.

[0172] For example, the side of the plastic sealing film 320 is flush with the side of the wafer 120.

[0173] That is, the edge of the plastic sealing film 320 is aligned with the edge of the wafer 120.

[0174] As shown in FIG. 6B, when the chip structure 110 includes a plurality of chips, the plastic sealing film 320 can also fill the gap between the plurality of chips.

[0175] The application does not limit the thickness of the chip structure 110, and the thickness of the chip structure 110 can be 100 μm, 200 μm, or 300 μm. For example, the thickness of the chip structure 110 is small, for example, the thickness of the chip structure 110 is less than 100 μm. Along the direction perpendicular to the thickness of the chip structure 110, the size of the part of the plastic sealing film 320 located on the side of the chip structure 110 is less than or equal to 30 μm.

[0176] That is, the distance between the edge of the chip structure 110 and the edge of the conductive structure 130 is less than or equal to 30 μm.

[0177] The plastic sealing film 320 can include, for example, a blue film layer, an ultraviolet light curing film layer, a dry film layer, or a chip bonding film layer.

[0178] In this way, the material cost of the plastic sealing film 320 and the plastic sealing film 320 wrapped around the periphery of the chip structure 110 is low, and the plastic sealing film 320 wrapped around the side of the chip structure 110 can be used to strengthen the mechanical strength of the chip packaging structure 10, protect the chip structure 110, and improve the reliability of the chip packaging structure 10.

[0179] Regarding the support layer 310, as shown in FIG. 6A, the support layer 310 covers the surface of the plastic sealing film 320. That is, the support layer 310 is arranged on the surface of the plastic sealing film 320 away from the chip structure 110.

[0180] For example, the side of the support layer 310 is flush with the side of the plastic sealing film 320.

[0181] That is, the edge of the support layer 310 is aligned with the edge of the plastic sealing film 320.

[0182] For example, the side of the support layer 310, the side of the plastic sealing film 320, and the side of the wafer 120 are flush.

[0183] The material of the support layer 310 can include silicon or silicon dioxide. For example, the support layer 310 can be a part of a wafer or glass.

[0184] It is clarified herein that, in some embodiments, as shown in FIG. 8, the plastic sealing film 320 only wraps the side of the chip structure 110. That is, the surface of the chip structure 110 is not covered by the plastic sealing film 320 and the support layer 310. This is not limited in the embodiments of the present application, and can be reasonably set according to actual conditions.

[0185] In some embodiments, as shown in FIG. 9, the chip packaging structure 10 further includes a packaging board 11. The above structures are all placed on the packaging board 11.

[0186] The chip packaging structure provided by the embodiments of the present application can strengthen the mechanical strength of the chip packaging structure 10, protect the chip structure 110, and improve the reliability of the chip packaging structure 10, because the plastic sealing film 320 wraps at least part of the side of the chip structure 110. The plastic sealing film 320 and the support layer 310 are reserved on the chip structure 110, and there is no need to remove the plastic sealing film 320 and the support layer 310 by a debonding process. In the embodiments of the present application, the plastic sealing film 320 is used to connect the support layer 310 and the chip structure 110, so that there is no need to use temporary bonding glue to connect the support layer 310 and the chip structure 110. The use of the temporary bonding glue with high cost is avoided, and there is no need to use a temporary bonding glue remover to remove the temporary bonding glue, so that the packaging cost can be reduced.

[0187] The above merely provides a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any change or replacement within the technical scope disclosed in the present application should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A chip package structure, characterized by, The chip package structure comprises: a wafer, a first surface of which is exposed with a plurality of first contacts; a chip structure arranged on a second surface of the wafer; the first surface and the second surface are arranged oppositely; the chip structure is electrically connected with the wafer; a plastic encapsulation film covering a surface and at least part of a side surface of the chip structure; a support layer covering a surface of the plastic encapsulation film.

2. The chip package structure of claim 1, wherein, The side surface of the plastic encapsulation film is flush with the side surface of the wafer.

3. The chip package structure of claim 1 or 2, wherein, The plastic encapsulation film comprises a blue film layer, an ultraviolet light curing film layer, a dry film layer or a chip adhesive film layer.

4. The chip package structure of any one of claims 1-3, wherein, The side surface of the support layer is flush with the side surface of the plastic encapsulation film.

5. The chip package structure of any one of claims 1-4, wherein, The material of the support layer comprises silicon or silicon dioxide.

6. The chip package structure of any one of claims 1-5, wherein, The chip package structure further comprises a rewiring layer and a bump; the rewiring layer is electrically connected with the first contacts; the bottom of the rewiring layer is provided with the bump, and the rewiring layer and the bump are electrically connected.

7. The chip package structure of any one of claims 1-6, wherein, The second surface of the wafer is provided with a plurality of second contacts, the first contacts and the second contacts are electrically connected; the chip structure is provided with a plurality of third contacts; the second contacts of the wafer are electrically connected with the third contacts of the chip structure.

8. The chip package structure of any one of claims 1-7, wherein, The chip structure comprises a chip and a wiring layer arranged in layers; the chip is electrically connected with the wafer through the wiring layer.

9. The chip package structure of any one of claims 1-8, wherein, The chip structure comprises a chip, a transition plate and a through hole penetrating through the transition plate; the chip is electrically connected with the wafer through the transition plate; the chip is arranged on the transition plate and is electrically connected with a first end of the through hole; a second end of the through hole is electrically connected with the wafer.

10. A method for fabricating a chip packaging structure, characterized in that, The chip package structure comprises: providing a wafer, the wafer being provided with a plurality of first contacts and second contacts; the first contacts are distributed in the wafer, the second contacts are distributed on a second surface of the wafer, and the first contacts and the second contacts are electrically connected; providing a chip structure, placing the chip structure on the wafer, and connecting the chip structure with the second contacts of the wafer; connecting a support plate with the chip structure through a plastic encapsulation film, the plastic encapsulation film also filling at least part of a side surface of the chip structure; thinning the support plate, forming a support layer and cutting, so that the support layer, the chip structure and the wafer after cutting form a chip package structure.

11. The method of claim 10, wherein the method further comprises: The support plate and the chip structure are connected through a lamination bonding process.

12. The method of claim 10 or 11, wherein The wafer and the chip structure are connected through a hybrid bonding process.

13. The method of claim 10-12, wherein the method further comprises: After connecting the support plate with the chip structure through the plastic encapsulation film, before thinning the support plate, the method further comprises: thinning the wafer away from the side of the chip structure to expose the first contacts; forming a rewiring layer and a bump on the first contacts in sequence.

14. An electronic device, comprising: The chip package structure and a printed circuit board according to any one of claims 1-9 are electrically connected.

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