Power module packaging structure

Abstract

Provided in the present invention is a power module packaging structure. The packaging structure comprises a lower substrate, an upper substrate, a chip layer, electrical connecting portions, leads, terminals and an encapsulation layer, wherein a first metal layer of the lower substrate comprises a first region, a second region, a first lead-out region and a second lead-out region; the chip layer comprises first chips and second chips, at least one first chip and at least one second chip are soldered to the first region and the second region, respectively, and chips above the first region and chips above the second region are symmetrically distributed; a second metal layer of the upper substrate comprises a first interconnection layer and a second interconnection layer; the electrical connecting portions located between the upper substrate and the lower substrate electrically connect the chips above the first region to the first interconnection layer, the chips above the second region to the second interconnection layer, and the first interconnection layer to the second region; the leads are respectively electrically connected to corresponding regions; the terminals are respectively electrically connected to corresponding regions; and the encapsulation layer fills the gap between the upper substrate and the lower substrate. By arranging the upper substrate above the lower substrate and electrically connecting the chips to the interconnection layers by means of the electrical connecting portions that support the upper substrate, the present invention improves the heat dissipation capability and reduces parasitic inductance.

Description

Power module packaging structure TECHNICAL FIELD

[0001] The present application belongs to the technical field of power device packaging, and relates to a power module packaging structure. BACKGROUND

[0002] In the field of power electronics, the Insulated Gate Bipolar Transistor (IGBT) is a very important semiconductor device. It has high performance, high reliability and low switching loss, and is widely used in various power electronic devices, such as inverters, frequency converters, direct current transmission systems, etc. However, IGBT generates a large amount of heat during operation, and if the device heat dissipation problem cannot be effectively handled, the chip junction temperature will be too high, affecting its performance and life. With further high-density, high-power and miniaturization of power modules, the single-face heat dissipation packaging form of power modules has only a single heat dissipation path, and the chip surface current in the power module is uneven and has a large parasitic inductance. In addition, high temperature will accelerate the aging of the packaging material, induce cracks, cause device failure, and affect the reliability of the device.

[0003] Therefore, it is urgent to find a power module packaging structure with low parasitic inductance and high heat dissipation capacity. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a power module packaging structure to solve the problems of large parasitic inductance, uneven current on the chip surface and poor heat dissipation capacity of the power module in the prior art.

[0005] To achieve the above-mentioned purposes and other related purposes, the present application provides a power module packaging structure, comprising:

[0006] a lower substrate comprising a first insulating and heat-conducting layer and a first metal layer on the upper surface of the first insulating and heat-conducting layer, the first metal layer comprising a first area, a second area, a first lead-out area and a plurality of second lead-out areas;

[0007] a chip layer comprising a plurality of first chips and a plurality of second chips, at least one of the first chips and the second chips being welded to the first area, at least one of the first chips and the second chips being welded to the second area, and the chips above the first area and the second area being symmetrically distributed;

[0008] an upper substrate above the chip layer, comprising a second insulating and heat-conducting layer and a second metal layer on the lower surface of the second insulating and heat-conducting layer, the second metal layer comprising a first interconnection layer and a second interconnection layer;

[0009] a plurality of electrical connection portions between the upper substrate and the lower substrate, electrically connecting the first interconnection layer and each chip above the first region, the first interconnection layer and the second region, the second interconnection layer and each chip above the second region, and the second interconnection layer and the first lead-out region;

[0010] a plurality of lead wires, respectively electrically connecting each of the second lead-out regions and a corresponding area of the back surface of the first chip corresponding to each of the second lead-out regions;

[0011] a plurality of terminals, respectively electrically connected to the first region, the second region, the first lead-out region, and each of the second lead-out regions;

[0012] a packaging layer, filling the gap between the upper substrate and the lower substrate.

[0013] Optionally, the material of the first insulating and heat-conducting layer comprises aluminum oxide, aluminum nitride, or silicon nitride; and the material of the second insulating and heat-conducting layer comprises aluminum oxide, aluminum nitride, or silicon nitride.

[0014] Optionally, the first chip comprises an IGBT chip or a MOS chip; and the second chip comprises a diode chip.

[0015] Optionally, the terminals comprise a plurality of power terminals and a plurality of signal terminals, the power terminals comprising a direct current positive terminal electrically connected to the first region, a direct current negative terminal electrically connected to the first lead-out region, and an alternating current terminal electrically connected to the second region.

[0016] Optionally, the direct current positive terminal and the direct current negative terminal are led out from the same side wall of the packaging layer, and the portions of the direct current positive terminal and the direct current negative terminal protruding from the side wall of the packaging layer are symmetrically distributed about the center line of the side wall of the packaging layer.

[0017] Optionally, the distance between any two adjacent signal terminals is not completely the same.

[0018] Optionally, the signal terminals comprise upper bridge signal terminals and lower bridge signal terminals, the upper bridge signal terminals comprising an upper bridge first electrode sensing terminal, an upper bridge current sensing terminal, an upper bridge second electrode sensing terminal, an upper bridge gate lead-out terminal, an upper bridge negative temperature sensing terminal, and an upper bridge positive temperature sensing terminal, and the lower bridge signal terminals comprising a lower bridge first electrode sensing terminal, a lower bridge current sensing terminal, a lower bridge second electrode sensing terminal, a lower bridge gate lead-out terminal, a lower bridge negative temperature sensing terminal, and a lower bridge positive temperature sensing terminal.

[0019] Optionally, the upper bridge first electrode sensing terminal is electrically connected with the first area, the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge gate lead-out terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with different second lead-out areas, the second lead-out areas corresponding to the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with corresponding areas on the back surface of the first chip above the first area through the lead wires, the second lead-out area corresponding to the upper bridge gate lead-out terminal is electrically connected with the gate of the first chip above the first area through the lead wire, the lower bridge first electrode sensing terminal is electrically connected with the second area, the lower bridge current sensing terminal, the lower bridge second electrode sensing terminal, the lower bridge gate lead-out terminal, the lower bridge negative temperature sensing terminal and the lower bridge positive temperature sensing terminal are respectively electrically connected with different second lead-out areas, the second lead-out areas corresponding to the lower bridge current sensing terminal, the lower bridge second electrode sensing terminal, the lower bridge negative temperature sensing terminal and the lower bridge positive temperature sensing terminal are respectively electrically connected with corresponding areas on the back surface of the first chip above the second area through the lead wires, the second lead-out area corresponding to the lower bridge gate lead-out terminal is electrically connected with the gate of the first chip above the second area through the lead wire.

[0020] Optionally, the upper bridge signal terminal, the alternating current terminal and the lower bridge signal terminal are led out from the same side wall of the packaging layer, and the upper bridge signal terminal and the lower bridge signal terminal are symmetrically arranged about the alternating current terminal.

[0021] Optionally, the power module further comprises a third metal layer covering the lower surface of the first insulating and heat-conducting layer and insulated from the first metal layer, and a fourth metal layer covering the upper surface of the second insulating and heat-conducting layer and insulated from the second metal layer.

[0022] Optionally, the first area, the second area, the first lead-out area and the second lead-out area are obtained by etching the first metal layer formed on the surface of the first insulating and heat-conducting layer.

[0023] Optionally, the emitter of the first chip above the first region is electrically connected with the first interconnection layer through an electrical connection part, the anode of the second chip above the first region is electrically connected with the first interconnection layer through an electrical connection part, the first interconnection layer electrically connecting the first chip and the second chip above the first region is electrically connected with the second region through another electrical connection part, the first chip and the second chip above the first region are interconnected through the first region, the electrical connection parts and the first interconnection layer to form an upper bridge in the power module; the emitter of the first chip above the second region is electrically connected with the first interconnection layer through an electrical connection part, the anode of the second chip above the second region is electrically connected with the second interconnection layer through an electrical connection part, the second interconnection layer electrically connecting the first chip and the second chip above the second region is electrically connected with the first lead-out region through another electrical connection part, the first chip and the second chip above the second region are interconnected through the second region, the electrical connection parts and the second interconnection layer to form a lower bridge in the power module; the upper bridge and the lower bridge combine to form a half-bridge circuit.

[0024] Optionally, the second metal layer is a copper layer with high thermal conductivity and low electrical resistivity.

[0025] Optionally, the first interconnection layer and the second interconnection layer are obtained by etching the second metal layer.

[0026] Optionally, the power module packaging structure further comprises a third metal layer covering the lower surface of the first insulating and heat-conducting layer and being insulated from the first metal layer; and a fourth metal layer covering the upper surface of the second insulating and heat-conducting layer and being insulated from the second metal layer.

[0027] As described above, the power module packaging structure of the present application improves the structure of the power module, so that the first chip and the second chip welded to the first area are symmetrically distributed with the first chip and the second chip welded to the second area, respectively, and then the current size in the upper / lower bridge of the power loop is equal, the current imbalance degree in the power module is reduced, and the current carrying capacity of the power module is enhanced; by arranging the upper substrate above the lower substrate, and by electrically connecting the first chip, the second chip and the first interconnection layer above the first area through the electrical connection part to form the upper bridge, and by electrically connecting the first chip, the second chip and the second interconnection layer above the second area through the electrical connection part to form the upper bridge, and then by connecting the first interconnection layer and the second area through the electrical connection part to interconnect the upper bridge and the lower bridge and form a three-dimensional power loop, and then a loop magnetic field is formed in the power module, the parasitic inductance in the power module is reduced; by combining the lower substrate and the upper substrate, and by the first insulating heat-conducting layer in the lower substrate and the second insulating heat-conducting layer in the upper substrate to dissipate heat, the heat dissipation path is increased, the double-sided heat dissipation of the power module is realized, the heat dissipation efficiency of the power module is improved, and then the heat dissipation capacity of the power module is improved, the chips in the power module are prevented from being damaged due to high temperature, and thus the reliability of the power module is improved, and the power module has high industrial utilization value. BRIEF DESCRIPTION OF DRAWINGS

[0028] Fig. 1 shows a structural schematic diagram of the power module packaging structure of the present application.

[0029] Fig. 2 shows a side view of the power module packaging structure of the present application.

[0030] Fig. 3 shows a top view of the power module packaging structure of the present application.

[0031] Explanation of Reference Signs 1 Lower substrate 11 First insulating and heat conducting layer 12 First metal layer 13 First region 14 Second region 15 First lead-out region 16 Second lead-out region 2 Chip layer 21 First chip 22 Second chip 3 Upper substrate 31 Second insulating and heat conducting layer 32 Second metal layer 33 First interconnection layer 34 Second interconnection layer 4 Electrical connection portion 5 Lead wire 6 Terminal 61 Direct current positive electrode terminal 62 Direct current negative electrode terminal 63 Alternating current terminal 64 Upper bridge signal terminal 641 Upper bridge first electrode sensing terminal 642 Upper bridge current sensing terminal 643 Upper bridge second electrode sensing terminal 644 Upper bridge gate lead-out terminal 645 Upper bridge negative electrode temperature sensing terminal 646 Upper bridge positive electrode temperature sensing terminal 65 Lower bridge signal terminal 651 Lower bridge current sensing terminal 652 Lower bridge second electrode sensing terminal 653 Lower bridge gate lead-out terminal 654 Lower bridge negative electrode temperature sensing terminal 655 Lower bridge positive electrode temperature sensing terminal 656 Lower bridge first electrode sensing terminal 7 Packaging layer DETAILED DESCRIPTION

[0032] The present application is herein described, by way of example only, with the comprehension that the advantages and utility thereof are not limited thereto. It should be recognized by those skilled in the art that changes can be made in the embodiment of the present application without departing from the spirit thereof, and the details can be varied without departing from the scope of the present application.

[0033] Referring to FIG. 1 to FIG. 3. It should be noted that the drawings provided in the present embodiment only schematically illustrate the basic concept of the present application, and thus the drawings only show the components related to the present application, rather than being drawn according to the number, shape and size of the components in actual implementation. The actual implementation of each component can be arbitrarily changed in shape, number and proportion, and the layout of the components can be more complex.

[0034] The present embodiment provides a power module packaging structure, as shown in FIG. 1, FIG. 2 and FIG. 3, which are respectively a structural schematic diagram of the power module packaging structure, a side view of the power module and a top view of the power module, comprising a lower substrate 1, a chip layer 2, an upper substrate 3, an electrical connection part 4, a lead wire 5, a terminal 6 and a packaging layer 7. The lower substrate 1 comprises a first insulating and heat-conducting layer 11 and a first metal layer 12 on the upper surface of the first insulating and heat-conducting layer 11. The first metal layer 12 comprises a first area 13, a second area 14, a first lead-out area 15 and a plurality of second lead-out areas 16. The chip layer 2 comprises a plurality of first chips 21 and a plurality of second chips 22. At least one first chip 21 and at least one second chip 22 are welded to the first area 13, and at least one first chip 21 and at least one second chip 22 are welded to the second area 14. The chips above the first area 13 and the second area 14 are symmetrically distributed. The upper substrate 3 is located above the chip layer 2. The upper substrate 3 comprises a second insulating and heat-conducting layer 31 and a second metal layer 32 on the lower surface of the second insulating and heat-conducting layer 31. The second metal layer 32 comprises a first interconnection layer 33 and a second interconnection layer 34. A plurality of electrical connection parts 4 are located between the upper substrate 3 and the lower substrate 2. The electrical connection parts 4 electrically connect the first interconnection layer 33 and the chips above the first area 13, the first interconnection layer 33 and the second area 14, the second interconnection layer 34 and the chips above the second area 14, and the second interconnection layer 34 and the first lead-out area 15. A plurality of lead wires 5 are respectively electrically connected to the back surface of the corresponding area of each second lead-out area 16 and the corresponding first chip 21. A plurality of terminals 6 are respectively electrically connected to the first area 13, the second area 14, the first lead-out area 15 and each second lead-out area 16. The packaging layer 7 fills the gap between the upper substrate 3 and the lower substrate 1.

[0035] Specifically, the lower substrate 1 is a process platform for carrying and soldering the chip layer 2 and the terminal 6 in the power module, and is used for enhancing the heat dissipation of the power module. The size, thickness and shape of the lower substrate 1 can be selected according to actual conditions under the condition of ensuring the performance of the power module.

[0036] For example, the material of the first insulating and heat-conducting layer 11 includes aluminum oxide, aluminum nitride, silicon nitride or other suitable high-thermal-conductivity insulating materials.

[0037] Specifically, the shape, thickness and size of the first insulating and heat-conducting layer 11 can be selected according to actual conditions under the condition of ensuring the heat dissipation performance of the power module.

[0038] Specifically, the material of the first metal layer 12 includes copper, gold, silver, aluminum or other suitable conductive materials. Preferably, a copper layer with high thermal conductivity and low resistivity is used as the first metal layer 12.

[0039] Specifically, the first region 13, the second region 14, the first lead-out region 15 and the second lead-out region 16 are usually obtained by etching the first metal layer 12 formed on the surface of the first insulating and heat-conducting layer 11; the first region 13 and the second region 14 are respectively used for soldering the first chip 21 and the second chip 22, and the first lead-out region 15 and the second lead-out region 16 are respectively used for soldering the terminal 6 of the power module and the lead wire 5 for bonding and interconnecting the devices in the power module.

[0040] Specifically, the thickness of the first metal layer 12 can be selected according to actual conditions under the condition of ensuring the performance of the power module; the size and shape of the first region 13 can be selected according to actual conditions; the size and shape of the second region 14 can be selected according to actual conditions; the size and shape of the first lead-out region 15 can be selected according to actual conditions; the size, shape and number of the second lead-out region 16 can be selected according to actual conditions; and the arrangement of the first region 13, the second region 14, the first lead-out region 15 and the second lead-out region 16 on the upper surface of the first insulating and heat-conducting layer 11 can be selected according to actual conditions.

[0041] For example, the first chip 21 includes an IGBT chip, a MOS chip or other suitable power device chip; and the second chip 22 includes a diode chip or other suitable chip. Preferably, the first chip 21 is an IGBT chip, and the second chip 22 is a freewheeling diode chip.

[0042] Specifically, the size and shape of the first chip 21 are related to the manufacturing process, which is not limited here; and the size and shape of the second chip 22 are related to the related manufacturing process, which is not limited here.

[0043] Specifically, the first chip 21 and the second chip 22 soldered on the upper surface of the first area 13 constitute the chips of the upper bridge in the power module, and the first chip 21 and the second chip 22 soldered on the upper surface of the second area 14 constitute the chips of the lower bridge in the power module. Preferably, the upper bridge and the lower bridge combine to constitute a half-bridge circuit, that is, one first chip 21 and one second chip 22 are soldered on the upper surface of the first area 13, and one first chip 21 and one second chip 22 are soldered on the upper surface of the second area 14.

[0044] Specifically, the first chip 21 and the second chip 22 are synchronously soldered on the upper surfaces of the first area 13 and the second area 14, and the soldering of the first chip 21 and the second chip 22 on the upper surfaces of the first area 13 and the second area 14 includes the following steps: synchronously forming a solder layer on the upper surfaces of the first area 13 and the second area 14; attaching the first chip 21 and the second chip 22 to the solder layer on the upper surfaces of the first area 13 and the second area 14, respectively, and the first chip 21 and the second chip 22 above the first area 13 and the second area 14 are symmetrically distributed; and soldering the first chip 21 and the second chip 22 above the first area 13 and the second area 14 through the solder layer to realize fixed electrical connection between the collector of the first chip 21 above the first area 13 and the first area 13, fixed electrical connection between the cathode of the second chip 22 above the first area 13 and the first area 13, fixed electrical connection between the collector of the first chip 21 above the second area 14 and the second area 14, and fixed electrical connection between the cathode of the second chip 22 above the second area 14 and the second area 14.

[0045] Specifically, the solder layer is usually a tin paste layer or a soldering sheet commonly used in the process of soldering power devices, which will not be described here; the method of attaching the first chip 21 and the second chip 22 includes manual attachment, attachment by an attachment machine, or other suitable methods; and the method of synchronously soldering the first chip 21 and the second chip 22 on the first area 13 and the second area 14 includes reflow soldering or other suitable soldering methods. Preferably, the first chip 21 and the second chip 22 are attached by an attachment machine to improve the soldering precision of the chips and the symmetry of the chips soldered in the first area 13 and the second area 14.

[0046] As an example, the material of the second insulating and heat-conducting layer 31 includes aluminum oxide, aluminum nitride, silicon nitride, or other suitable high-thermal-conductivity insulating materials.

[0047] Specifically, the material of the second metal layer 32 includes copper, gold, silver, aluminum, or other suitable conductive materials. Preferably, a copper layer with high thermal conductivity and low resistivity is used as the second metal layer 32.

[0048] Specifically, the first interconnection layer 33 and the second interconnection layer 34 are generally etched from the second metal layer 32, and the size and shape of the first interconnection layer 33 can be selected according to actual conditions while ensuring the performance of the power module; the size, shape and distance between the first interconnection layer 33 and the second interconnection layer 34 can be selected according to actual conditions.

[0049] Specifically, the material of the electrical connection part 4 includes copper, gold, silver, aluminum or other suitable conductive materials. Preferably, a copper block with high thermal conductivity and low resistivity is used as the electrical connection part 4.

[0050] Specifically, the emitter of the first chip 21 above the first region 13 is electrically connected to the first interconnection layer 33 through an electrical connection part 4, the anode of the second chip 22 above the first region 13 is electrically connected to the first interconnection layer 33 through an electrical connection part 4, the first interconnection layer 33 electrically connected to the first chip 21 and the second chip 22 above the first region 13 is electrically connected to the second region 14 through another electrical connection part 4, and the first chip 21 and the second chip 22 above the first region 13 are interconnected through the first region 13, the electrical connection part 4 and the first interconnection layer 33 to form an upper bridge in the power module.

[0051] Specifically, the emitter of the first chip 21 above the second region 14 is electrically connected to the first interconnection layer 33 through an electrical connection part 4, the anode of the second chip 22 above the second region 14 is electrically connected to the second interconnection layer 34 through an electrical connection part 4, the second interconnection layer 34 electrically connected to the first chip 21 and the second chip 22 above the second region 14 is electrically connected to the first lead-out region 15 through another electrical connection part 4, and the first chip 21 and the second chip 22 above the second region 14 are interconnected through the second region 14, the electrical connection part 4 and the second interconnection layer 34 to form a lower bridge in the power module.

[0052] Specifically, the electrical connection part 4, in combination with the first interconnection layer 33 and the second interconnection layer 34, realizes the electrical connection of the functional circuit in the power module, and also has the functions of supporting the upper substrate 3 and buffering the thermal stress at the electrical connection part 4. The shape, size and position of each electrical connection part 4 can be selected according to actual conditions while ensuring the performance of the power module. Preferably, a square copper column is used as the electrical connection part 4.

[0053] Specifically, two ends of the electrical connection part 4 electrically connected with the emitter of the first chip 21 above the first region 13 are fixedly connected with the emitter of the first chip 21 and the first interconnection layer 33 through the soldering layer respectively; two ends of the electrical connection part 4 electrically connected with the anode of the second chip 22 above the first region 13 are fixedly connected with the anode of the second chip 22 and the first interconnection layer 33 through the soldering layer respectively; two ends of the electrical connection part 4 electrically connecting the first interconnection layer 33 and the second region 14 are fixedly connected with the first interconnection layer 33 and the second region 14 through the soldering layer respectively; two ends of the electrical connection part 4 electrically connected with the emitter of the first chip 21 above the second region 14 are fixedly connected with the emitter of the first chip 21 and the second interconnection layer 34 through the soldering layer respectively; two ends of the electrical connection part 4 electrically connected with the anode of the second chip 22 above the second region 14 are fixedly connected with the anode of the second chip 22 and the second interconnection layer 34 through the soldering layer respectively; two ends of the electrical connection part 4 electrically connecting the second interconnection layer 34 and the first lead-out region 15 are fixedly connected with the second interconnection layer 34 and the first lead-out region 15 through the soldering layer respectively.

[0054] Specifically, the soldering layer is generally a tin paste layer or a soldering sheet commonly used in the soldering process of a power device, which will not be described herein.

[0055] Specifically, in the power module, the two ends of the lead wire 5 are electrically connected with the back electrode of the first chip 21 and the second lead-out region 16 corresponding to the back electrode through the bonding process, so as to lead the back electrode of the first chip 21 above the first region 13 and the second region 14 to the corresponding second lead-out region 16.

[0056] Specifically, the material of the lead wire 5 includes copper, gold, silver, aluminum or other suitable conductive materials.

[0057] Specifically, the shape of the lead wire 5 includes a linear shape, a strip shape or other suitable shapes. Preferably, a conductive wire in a linear shape is used as the lead wire 5.

[0058] Specifically, under the condition of ensuring the performance of the power module, the cross-sectional size, the cross-sectional shape and the length of the lead wire 5 can be selected according to actual conditions; the distance between the two adjacent lead wires 5 can be selected according to actual conditions.

[0059] As an example, the terminal 6 includes a plurality of power terminals and a plurality of signal terminals, the power terminals including a direct current positive terminal 61 electrically connected with the first region 13, a direct current negative terminal 62 electrically connected with the first lead-out region 15 and an alternating current terminal 63 electrically connected with the second region 14.

[0060] Specifically, the direct current positive terminal 61 and the direct current negative terminal 63 are respectively used for electrically connecting with the positive and negative poles of an external circuit to provide a voltage for the operation of the power module, and the alternating current terminal 63 is used for converting the switching state of the first chip 21 into an alternating current output.

[0061] Specifically, the size, shape and length of the DC positive terminal 61 protruding from the packaging layer 7 can be selected according to actual conditions; the size, shape and length of the DC negative terminal 62 protruding from the packaging layer 7 can be selected according to actual conditions; and the size, shape and length of the AC terminal 63 protruding from the packaging layer 7 can be selected according to actual conditions, while ensuring the performance of the power module.

[0062] Specifically, the material of the DC positive terminal 61 includes copper, gold, silver, aluminum, nickel, titanium, platinum or other suitable conductive materials; the material of the DC negative terminal 62 includes copper, gold, silver, aluminum, nickel, titanium, platinum or other suitable conductive materials; and the material of the AC terminal 63 includes copper, gold, silver, aluminum, nickel, titanium, platinum or other suitable conductive materials.

[0063] For example, the DC positive terminal 61 and the DC negative terminal 62 are led out from the same side wall of the packaging layer 7, and the portions of the DC positive terminal 61 and the DC negative terminal 62 protruding from the side wall of the packaging layer 7 are symmetrically distributed about the center line of the side wall of the packaging layer 7.

[0064] Specifically, by symmetrically arranging the DC positive terminal 61 and the DC negative terminal 62, the parasitic inductance of the entire power loop in the power module can be reduced, and the turn-off voltage peak and switching oscillation can be reduced, thereby improving the performance of the power module.

[0065] Specifically, when the DC positive terminal 61 and the DC negative terminal 62 are led out from the same side wall of the packaging layer 7, the distance between the DC positive terminal 61 and the DC negative terminal 62 can be selected according to actual conditions.

[0066] Specifically, the DC positive terminal 61 and the DC negative terminal 62 can also be led out from different side walls of the packaging layer 7 according to actual needs, or the portions of the DC positive terminal 61 and the DC negative terminal 62 protruding from the side wall of the packaging layer 7 can not be symmetrically distributed about the center line of the side wall of the packaging layer 7, while ensuring the performance of the power module.

[0067] For example, among the plurality of signal terminals, the distances between adjacent two signal terminals are not the same.

[0068] Specifically, the material of the signal terminal includes copper, gold, silver, aluminum, nickel, titanium, platinum or other suitable conductive materials; the materials of different signal terminals can be different or the same, while ensuring the performance of the power module; and the distances between adjacent two signal terminals can be selected according to actual conditions, which can be the same or not completely the same.

[0069] Specifically, the shape and size of each signal terminal can be selected according to actual conditions while ensuring the performance of the power module; the length of the part of each signal terminal protruding from the packaging layer 7 can be selected according to actual conditions.

[0070] Specifically, one second lead-out area 16 corresponds to one signal terminal, and each signal terminal is usually fixedly connected to its corresponding second lead-out area 16 by welding. The welding process for fixedly connecting the signal terminal to its corresponding second lead-out area 16 is a common welding process, which will not be described here.

[0071] As an example, the signal terminals include an upper bridge signal terminal 64 and a lower bridge signal terminal 65. The upper bridge signal terminal 64 includes an upper bridge first electrode sensing terminal 641, an upper bridge current sensing terminal 642, an upper bridge second electrode terminal 643, an upper bridge gate lead-out terminal 644, an upper bridge negative temperature sensing terminal 645, and an upper bridge positive temperature sensing terminal 646. The lower bridge signal terminal 65 includes a lower bridge current sensing terminal 651, a lower bridge second electrode sensing terminal 652, a lower bridge gate lead-out terminal 653, a lower bridge negative temperature sensing terminal 654, a lower bridge positive temperature sensing terminal 655, and a lower bridge first electrode sensing terminal 656. In this embodiment, the first electrode is the collector, and the second electrode is the emitter.

[0072] As an example, the upper bridge first electrode sensing terminal 641 is electrically connected to the first area 13. The upper bridge current sensing terminal 642, the upper bridge second electrode sensing terminal 643, the upper bridge gate lead-out terminal 644, the upper bridge negative temperature sensing terminal 645, and the upper bridge positive temperature sensing terminal 646 are respectively electrically connected to different second lead-out areas 16. The second lead-out areas 16 corresponding to the upper bridge current sensing terminal 642, the upper bridge second electrode sensing terminal 643, the upper bridge negative temperature sensing terminal 645, and the upper bridge positive temperature sensing terminal 646 are respectively electrically connected to the corresponding areas on the back of the first chip 21 above the first area 13 through the lead wires 5. The second lead-out area 16 corresponding to the upper bridge gate lead-out terminal 644 is electrically connected to the gate of the first chip 21 above the first area 13 through the lead wire 5. The lower bridge first electrode sensing terminal 656 is electrically connected to the second area 14. The lower bridge current sensing terminal 651, the lower bridge second electrode sensing terminal 652, the lower bridge gate lead-out terminal 653, the lower bridge negative temperature sensing terminal 654, and the lower bridge positive temperature sensing terminal 655 are respectively electrically connected to different second lead-out areas 16. The second lead-out areas 16 corresponding to the lower bridge current sensing terminal 651, the lower bridge second electrode sensing terminal 652, the lower bridge negative temperature sensing terminal 654, and the lower bridge positive temperature sensing terminal 655 are respectively electrically connected to the corresponding areas on the back of the first chip 21 above the second area 14 through the lead wires 5. The second lead-out area 16 corresponding to the lower bridge gate lead-out terminal 653 is electrically connected to the gate of the first chip 21 above the second area 14 through the lead wire 5.

[0073] Specifically, during the working process of the power module, the upper bridge first electrode sensing terminal 641 is used to detect the current of the first electrode of the first chip 21 in the upper bridge in real time, the upper bridge current sensing terminal 642 is used to detect the output current of the upper bridge in real time, the upper bridge second electrode sensing terminal 643 is used to detect the current of the second electrode of the first chip 21 in the upper bridge in real time, the upper bridge gate lead-out terminal 644 is used to input the control signal for controlling the gate of the first chip 21 of the upper bridge, so as to control the switch of the first chip 21 in the upper bridge, the upper bridge negative temperature sensing terminal 665 and the upper bridge positive temperature sensing terminal 666 are used to detect the working temperature of the first chip 21 in the upper bridge in real time, the lower bridge first electrode sensing terminal 656 is used to detect the current of the first electrode of the first chip 21 in the lower bridge in real time, the lower bridge current sensing terminal 651 is used to detect the output current of the lower bridge in real time, the lower bridge second electrode sensing terminal 652 is used to detect the current of the second electrode of the first chip 21 in the lower bridge in real time, the lower bridge gate lead-out terminal 653 is used to input the control signal for controlling the gate of the first chip 21 in the lower bridge, so as to control the switch of the first chip 21 in the lower bridge, and the lower bridge negative temperature sensing terminal 674 and the lower bridge positive temperature sensing terminal 675 are used to detect the working temperature of the first chip 21 in the lower bridge in real time.

[0074] Specifically, the detection mode of the upper bridge negative temperature sensing terminal 645, the upper bridge positive temperature sensing terminal 666, the lower bridge negative temperature sensing terminal 674 and the lower bridge positive temperature sensing terminal 675 can be selected according to actual conditions, for example, the current of the first electrode of the first chip 21 in the upper bridge can be led to the upper bridge negative temperature sensing terminal 645 through the lead wire 5, and the temperature monitoring of the power module can be realized by externally connecting a temperature sensing diode.

[0075] As an example, the upper bridge signal terminal 64, the alternating current terminal 63 and the lower bridge signal terminal 65 are led out from the same side wall of the packaging layer 7, and the upper bridge signal terminal 64 and the lower bridge signal terminal 65 are symmetrically arranged about the alternating current terminal 63.

[0076] Specifically, in the case of ensuring the performance of the power module, the terminals in the upper bridge signal terminal 64 and the terminals in the lower bridge signal terminal 65 can also not be symmetrically arranged, or the arrangement mode and the position of the side wall of the self-encapsulation layer 7 can be arranged according to the actual application scene. In the embodiment, the signal terminals are led out from the side wall opposite to the side wall leading out the direct current positive terminal 61 in the encapsulation layer 7. The upper bridge first electrode sensing terminal 641 and the lower bridge first electrode sensing terminal 656 are symmetrically arranged about the alternating current terminal 63. The upper bridge current sensing terminal 642, the upper bridge second electrode sensing terminal 643, the upper bridge gate lead-out terminal 644, the upper bridge negative temperature sensing terminal 645, the upper bridge positive temperature sensing terminal 646, the alternating current terminal 63, the lower bridge current sensing terminal 651, the lower bridge second electrode sensing terminal 652, the lower bridge gate lead-out terminal 653, the lower bridge negative temperature sensing terminal 654, and the lower bridge positive temperature sensing terminal 655 are sequentially and spacedly arranged in the direction from the upper bridge first electrode sensing terminal 641 to the lower bridge first electrode sensing terminal 656.

[0077] Specifically, the encapsulation layer 7 is used to protect the components in the power module. The material of the encapsulation layer 7 includes epoxy resin, polyimide, polymaleimide triazine resin, polyphenyl ether, or polytetrafluoroethylene, or other suitable dielectric materials.

[0078] Specifically, the encapsulation layer 7 also covers the side wall of the upper substrate 3 and the lower substrate 1. The distance between the side wall of the encapsulation layer 7 and the side wall of the upper substrate 3 is a preset distance, and the distance between the side wall of the encapsulation layer 7 and the side wall of the lower substrate 1 is a preset distance. The encapsulation layer 7 protects the components in the power module. In the case of ensuring the performance of the power module, the distance between the side wall of the encapsulation layer 7 and the side wall of the upper substrate 3 can be selected according to the actual situation, and the distance between the side wall of the encapsulation layer 7 and the side wall of the lower substrate 1 can be selected according to the actual situation.

[0079] As an example, the power module also has a third metal layer covering the lower surface of the first insulating and heat-conducting layer and insulated from the first metal layer. The power module also has a fourth metal layer covering the upper surface of the second insulating and heat-conducting layer and insulated from the second metal layer.

[0080] Specifically, by arranging the third metal layer, the heat dissipation efficiency of the power module from the side of the first insulating and heat-conducting layer 11 away from the first metal layer 12 can be enhanced, and the heat dissipation performance of the power module can be improved. It is convenient to weld a heat dissipation structure for further improving the heat dissipation performance of the power module on the side of the lower substrate 1 away from the first metal layer 12. By arranging the fourth metal layer, the heat dissipation efficiency of the power module from the side of the second insulating and heat-conducting layer 31 away from the second metal layer 32 can be enhanced, and the heat dissipation performance of the power module can be improved. It is convenient to weld a heat dissipation structure for further improving the heat dissipation performance of the power module on the side of the lower substrate 1 away from the first metal layer 12.

[0081] Specifically, the material of the third metal layer includes copper, gold, silver, aluminum or other suitable conductive materials; the material of the fourth metal layer includes copper, gold, silver, aluminum or other suitable conductive materials. Preferably, the copper layer with high thermal conductivity is used as the third metal layer and the fourth metal layer.

[0082] Specifically, under the condition of ensuring the performance of the power module, the thickness of the third metal layer can be selected according to the actual situation; the thickness of the fourth metal layer can be selected according to the actual situation.

[0083] Specifically, by using the lower substrate 1 as the substrate for welding the first chip 21 and the second chip 22 in the power module, and making the first chip 21 and the second chip 22 welded to the first area 13 and the first chip 21 and the second chip 22 welded to the second area 14 symmetrically distributed, the current size in the upper / lower bridge of the power loop is equal, and then the current distribution in the power module is more uniform, the current imbalance degree in the power module is reduced, the situation of individual chip current being too large and local temperature being too high is avoided, and the current carrying capacity of the power module is enhanced.

[0084] Specifically, by arranging the upper substrate 3 provided with the first interconnection layer 33 and the second interconnection layer 34 directly above the chip layer 2, and combining the first interconnection layer 33 and the second interconnection layer 34 with the electric connection part 4, the first area 13 and the first chip 21, the second chip 22, the electric connection part 4 and the first interconnection layer 33 above the first area 13 are constructed into the upper bridge in the power module, the second area 14 and the first chip 21, the second chip 22, the electric connection part 4 and the second interconnection layer 34 above the second area 14 are constructed into the upper bridge in the power module, the electric connection part 4 electrically connects the upper bridge and the lower bridge, and the length of the electric connection part 4 between the upper substrate 3 and the lower substrate 1 is short, so that the three-dimensional power loop with the current commutation path direction of the chips in the upper bridge and the lower bridge being opposite is formed, and then the loop magnetic field is formed in the power module, the parasitic inductance in the power module is reduced, the turn-off voltage peak and the switching oscillation are reduced, and the performance of the power module is improved.

[0085] Specifically, by combining the lower substrate 1 and the upper substrate 3, the heat in the power module can be quickly dissipated from the first insulating and heat-conducting layer 11 and the second insulating and heat-conducting layer 31 on the surface of the power module, the heat dissipation path is increased, the double-sided heat dissipation of the power module is realized, the heat dissipation efficiency of the power module is improved, the heat dissipation capacity of the power module is improved, the damage of each chip in the power module due to high temperature is avoided, and the reliability of the power module is improved.

[0086] In summary, the power module packaging structure of the present application improves the structure of the power module, the first chip and the second chip in the first area of the first metal layer of the lower substrate are symmetrically distributed with the first chip and the second chip in the second area of the first metal layer of the lower substrate, so that the current size in the upper / lower bridge of the power circuit is equal, the current imbalance in the power module is reduced, and the current carrying capacity of the power module is enhanced; by arranging the upper substrate provided with the first interconnection layer and the second interconnection layer above the lower substrate, and connecting the first area, the first chip, the second chip, the electric connection part and the first interconnection layer above the first area to form the upper bridge in the power module, the second area, the first chip, the second chip, the electric connection part and the second interconnection layer above the second area to form the upper bridge in the power module, and then connecting the first interconnection layer and the second area by the electric connection part to interconnect the upper bridge and the lower bridge and form a three-dimensional power circuit, a loop magnetic field is formed in the power module, and the parasitic inductance in the power module is reduced; the lower substrate and the upper substrate are combined, and the first insulating heat-conducting layer in the lower substrate and the second insulating heat-conducting layer in the upper substrate are used for heat dissipation, the heat dissipation path is increased, the double-sided heat dissipation of the power module is realized, the heat dissipation efficiency of the power module is improved, the heat dissipation capacity of the power module is improved, and the damage of each chip in the power module due to high temperature is avoided, so that the reliability of the power module is improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has high industrial utilization value.

[0087] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A power module package structure, characterized by, The application relates to a packaging structure of a power module, comprising: a lower substrate, comprising a first insulating and heat-conducting layer and a first metal layer on the upper surface of the first insulating and heat-conducting layer, wherein the first metal layer comprises a first area, a second area, a first lead-out area and a plurality of second lead-out areas; a chip layer, comprising a plurality of first chips and a plurality of second chips, wherein at least one first chip and at least one second chip are welded to the first area, and at least one first chip and at least one second chip are welded to the second area, and the first area and the second area are symmetrically distributed above each chip; an upper substrate above the chip layer, comprising a second insulating and heat-conducting layer and a second metal layer on the lower surface of the second insulating and heat-conducting layer, wherein the second metal layer comprises a first interconnection layer and a second interconnection layer; a plurality of electrical connection parts between the upper substrate and the lower substrate, electrically connecting the first interconnection layer and each chip above the first area, the first interconnection layer and the second area, the second interconnection layer and each chip above the second area, and the second interconnection layer and the first lead-out area; a plurality of lead wires, respectively electrically connecting each second lead-out area and a corresponding area on the back surface of the corresponding first chip of each second lead-out area; a plurality of terminals, respectively electrically connected to the first area, the second area, the first lead-out area and each second lead-out area; a packaging layer, filling the gap between the upper substrate and the lower substrate.

2. The power module package structure of claim 1, wherein: The material of the first insulating and heat-conducting layer comprises aluminum oxide, aluminum nitride and silicon nitride; the material of the second insulating and heat-conducting layer comprises aluminum oxide, aluminum nitride and silicon nitride.

3. The power module package structure of claim 1, wherein: The first chip comprises an IGBT chip and a MOS chip; and the second chip comprises a diode chip.

4. The power module package structure of claim 1, wherein: The terminals comprise a plurality of power terminals and a plurality of signal terminals, wherein the power terminals comprise a direct-current positive terminal electrically connected to the first area, a direct-current negative terminal electrically connected to the first lead-out area and an alternating-current terminal electrically connected to the second area.

5. The power module package structure of claim 4, wherein: The direct-current positive terminal and the direct-current negative terminal are led out from the same side wall of the packaging layer, and the parts of the direct-current positive terminal and the direct-current negative terminal protruding from the side wall of the packaging layer are symmetrically distributed about the center line of the side wall of the packaging layer.

6. The power module package structure of claim 4, wherein: The distance between any two adjacent signal terminals is not completely the same.

7. The power module package structure of claim 4, wherein: The signal terminals comprise upper bridge signal terminals and lower bridge signal terminals, wherein the upper bridge signal terminals comprise an upper bridge first electrode sensing terminal, an upper bridge current sensing terminal, an upper bridge second electrode sensing terminal, an upper bridge gate lead-out terminal, an upper bridge negative temperature sensing terminal and an upper bridge positive temperature sensing terminal; and the lower bridge signal terminals comprise a lower bridge first electrode sensing terminal, a lower bridge current sensing terminal, a lower bridge second electrode sensing terminal, a lower bridge gate lead-out terminal, a lower bridge negative temperature sensing terminal and a lower bridge positive temperature sensing terminal.

8. The power module package structure of claim 7, wherein: The upper bridge first electrode sensing terminal is electrically connected with the first area, the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge gate lead-out terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with different second lead-out areas, the second lead-out areas corresponding to the upper bridge current sensing terminal, the upper bridge second electrode sensing terminal, the upper bridge negative temperature sensing terminal and the upper bridge positive temperature sensing terminal are respectively electrically connected with the corresponding areas on the back surface of the first chip above the first area through the lead wires, the second lead-out area corresponding to the upper bridge gate lead-out terminal is electrically connected with the gate of the first chip above the first area through the lead wire, the lower bridge first electrode sensing terminal is electrically connected with the second area, the lower bridge current sensing terminal, the lower bridge second electrode sensing terminal, the lower bridge gate lead-out terminal, the lower bridge negative temperature sensing terminal and the lower bridge positive temperature sensing terminal are respectively electrically connected with different second lead-out areas, the second lead-out areas corresponding to the lower bridge current sensing terminal, the lower bridge second electrode sensing terminal, the lower bridge negative temperature sensing terminal and the lower bridge positive temperature sensing terminal are respectively electrically connected with the corresponding areas on the back surface of the first chip above the second area through the lead wires, the second lead-out area corresponding to the lower bridge gate lead-out terminal is electrically connected with the gate of the first chip above the second area through the lead wire.

9. The power module package structure of claim 7, wherein: The upper bridge signal terminal, the alternating current terminal and the lower bridge signal terminal are led out from the same side wall of the packaging layer, and the upper bridge signal terminal and the lower bridge signal terminal are symmetrically arranged about the alternating current terminal.

10. The power module package structure of claim 1, wherein: The power module further comprises a third metal layer covering the lower surface of the first insulating and heat-conducting layer and insulated from the first metal layer, and a fourth metal layer covering the upper surface of the second insulating and heat-conducting layer and insulated from the second metal layer.

11. The power module package structure of claim 1, wherein: The first area, the second area, the first lead-out area and the second lead-out area are obtained by etching the first metal layer formed on the surface of the first insulating and heat-conducting layer.

12. The power module package structure of claim 1, wherein: The emitter of the first chip above the first area is electrically connected with the first interconnection layer through an electric connection part, the anode of the second chip above the first area is electrically connected with the first interconnection layer through an electric connection part, the first interconnection layer electrically connecting the first chip and the second chip above the first area is electrically connected with the second area through another electric connection part, and the first chip and the second chip above the first area are interconnected through the first area, the electric connection part and the first interconnection layer to form an upper bridge in the power module; the emitter of the first chip above the second area is electrically connected with the first interconnection layer through an electric connection part, the anode of the second chip above the second area is electrically connected with the second interconnection layer through an electric connection part, the second interconnection layer electrically connecting the first chip and the second chip above the second area is electrically connected with the first lead-out area through another electric connection part, and the first chip and the second chip above the second area are interconnected through the second area, the electric connection part and the second interconnection layer to form a lower bridge in the power module; and the upper bridge and the lower bridge are combined to form a half-bridge circuit.

13. The power module package structure of claim 1, wherein: The second metal layer is a copper layer with high thermal conductivity and low resistivity.

14. The power module package structure of claim 1, wherein: The first interconnection layer and the second interconnection layer are obtained by etching the second metal layer.

15. The power module package structure of claim 1, wherein: The power module packaging structure further comprises a third metal layer covering the lower surface of the first insulating and heat-conducting layer and being insulated from the first metal layer, and a fourth metal layer covering the upper surface of the second insulating and heat-conducting layer and being insulated from the second metal layer. The second metal layer is a copper layer with high thermal conductivity and low resistivity. The first interconnection layer and the second interconnection layer are obtained by etching the second metal layer. The power module packaging structure further comprises a third metal layer covering the lower surface of the first insulating and heat-conducting layer and being insulated from the first metal layer, and a fourth metal layer covering the upper surface of the second insulating and heat-conducting layer and being insulated from the second metal layer.

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