Package for semiconductor circuit module, and power electronic conversion apparatus

Abstract

The present application provides a package for a semiconductor circuit module, comprising: a substrate, a housing, a plurality of semiconductor chips, a driver circuit board, and terminals. An accommodating space is formed inside the housing, and the substrate is arranged in the accommodating space and is connected to the housing; the plurality of semiconductor chips are disposed on the substrate, and the plurality of semiconductor chips are electrically connected to each other to form a semiconductor circuit module; the driver circuit board is electrically connected to at least some of the semiconductor chips, and the terminals are electrically connected to at least some of the semiconductor chips; the driver circuit board and at least some of the terminals are fixedly connected to the housing, the driver circuit board and at least some of the terminals are spaced apart from the substrate, and the driver circuit board and the terminals that are spaced apart from the substrate are electrically connected to the semiconductor chips only by means of one type of conductive member.

Description

Package of semiconductor circuit module and power electronic conversion device

[0001] The present application claims priority to the Chinese patent application No. 2024113841352, filed on September 29, 2024, and entitled “Package of semiconductor circuit module and power electronic conversion device”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The disclosed embodiments of the present application relate to the field of semiconductor technology, and more specifically, to a package of semiconductor circuit module and power electronic conversion device. BACKGROUND

[0003] Power electronic conversion devices are widely used in electric vehicles, aerospace, biomedical, new energy power generation and other fields. Power semiconductor circuit modules are the core devices of power electronic conversion devices, and the improvement of their performance greatly affects the performance of the devices. However, at high switching speeds, power semiconductor circuit modules are more sensitive to the parasitic inductance introduced by the package.

[0004] Therefore, how to reduce the parasitic inductance of the power semiconductor circuit module becomes a problem to be solved. SUMMARY

[0005] According to the embodiments of the present application, a package of semiconductor circuit module is provided to reduce the parasitic inductance of the power semiconductor circuit module.

[0006] According to an aspect of the present application, a package of semiconductor circuit module is disclosed, comprising: a substrate, a shell, a plurality of semiconductor chips, a driving circuit board and a terminal. The interior of the shell forms an accommodation space, the substrate is arranged in the accommodation space and connected with the shell; the plurality of semiconductor chips are arranged on the substrate, and the plurality of semiconductor chips are electrically connected to each other to form a semiconductor circuit module; the driving circuit board is electrically connected with at least part of the semiconductor chips; the terminal is electrically connected with at least part of the semiconductor chips; wherein the driving circuit board and at least part of the terminal are fixedly connected to the shell, the driving circuit board and at least part of the terminal have a gap with the substrate, and the terminal having a gap with the substrate is electrically connected with the semiconductor chips only through one type of conductive member.

[0007] The second aspect of the present application provides a power electronic conversion device comprising the package of semiconductor circuit module of the first aspect.

[0008] The above scheme, by fixing and connecting the driving circuit board and at least part of the wiring terminal to the shell, and having a gap between the driving circuit board and at least part of the wiring terminal and the substrate, so that the driving circuit board and at least part of the wiring terminal are not directly electrically connected with the substrate, but are only electrically connected through a type of conductive piece, so that the current between the chip and the driving circuit board or at least part of the wiring terminal does not pass through the substrate, thereby shortening the current loop between the semiconductor chip and the driving circuit board and at least part of the wiring terminal, and further reducing the parasitic inductance, and using a multi-layer DBC structure to reduce the power loop stray inductance by mutual inductance cancellation. In addition, by fixing and connecting the driving circuit board and at least part of the wiring terminal to the shell instead of being directly electrically connected with the substrate, the area of the reserved area on the substrate for electrical connection with the driving circuit board or at least part of the wiring terminal can be reduced, thereby saving space and reducing the volume of the package of the semiconductor circuit module. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 is a structural schematic diagram of a substrate in some embodiments of the present application.

[0010] FIG. 2 is a top view structural schematic diagram of a type A DBC in some embodiments of the present application.

[0011] FIG. 3 is a bottom view structural schematic diagram of a type A DBC in some embodiments of the present application.

[0012] FIG. 4 is a top view structural schematic diagram of a type B DBC in some embodiments of the present application.

[0013] FIG. 5 is a bottom view structural schematic diagram of a type B DBC in some embodiments of the present application.

[0014] FIG. 6 is a top view structural schematic diagram of a type C DBC in some embodiments of the present application.

[0015] FIG. 7 is a bottom view structural schematic diagram of a type C DBC in some embodiments of the present application.

[0016] FIG. 8 is a top view structural schematic diagram of a type D DBC in some embodiments of the present application.

[0017] FIG. 9 is a bottom view structural schematic diagram of a type D DBC in some embodiments of the present application.

[0018] FIG. 10 is a structural schematic diagram of a package of a semiconductor circuit module in some embodiments of the present application.

[0019] FIG. 11 is a top view structural schematic diagram of a package of a semiconductor circuit module in some embodiments of the present application.

[0020] FIG. 12 is a partial structural schematic diagram of a substrate in some embodiments of the present application.

[0021] Fig. 13 is a schematic diagram of a current loop in a double-layer substrate in some embodiments of the present application.

[0022] Fig. 14 is a schematic diagram of a current loop in a DC positive terminal and a DC negative terminal in some embodiments of the present application.

[0023] Fig. 15 is a schematic diagram of a current loop between a semiconductor chip and a terminal in some embodiments of the present application.

[0024] Fig. 16 is a schematic diagram of a top view of a substrate after sintering of a semiconductor chip and a thermistor in some embodiments of the present application.

[0025] Fig. 17a is a schematic diagram of a top view of a package of a semiconductor circuit module in some embodiments of the present application.

[0026] Fig. 17b is a schematic diagram of a perspective view of a package of a semiconductor circuit module in some embodiments of the present application.

[0027] Fig. 18 is a schematic diagram of a circuit structure of a semiconductor circuit module in some embodiments of the present application.

[0028] Fig. 19 is a schematic diagram of a structure of a terminal in a circuit of a semiconductor circuit module after packaging in some embodiments of the present application.

[0029] Fig. 20 is a schematic diagram of a frame of a power electronic conversion device in some embodiments of the present application.

[0030] BRIEF DESCRIPTION OF THE DRAWINGS: A: A-type DBC; A1: upper copper foil; A2: ceramic substrate; A3: lower copper foil; B: B-type DBC; B1: upper copper foil; B2: ceramic substrate; B3: lower copper foil; C: C-type DBC; C1: upper copper foil; C2: ceramic substrate; C3: lower copper foil; D: D-type DBC; D1: upper copper foil; D2: ceramic substrate; D3: lower copper foil; 101: small hole; 100: package; 1: substrate; 4, 401-424: semiconductor chip; 102: bonding wire; 110, t1-t13: terminal; 2: housing; 1000: drive circuit board; 3: backplane; 111: AC terminal; 112: DC positive terminal; 113: DC negative terminal; 201: heat stake; 28: terminal support; 105: bridge copper block; 425: thermistor; 4a-27a: gate bonding wire; 4b-27b: auxiliary source bonding wire; 4c-27c: power source bonding wire; 2000: power electronic conversion device. Embodiments of the present application

[0031] In order to better understand the technical solutions of the present application, the technical solutions of the present application are further described in detail below with reference to the drawings and specific embodiments. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of protection of the present application.

[0032] The terms used in the embodiments of the present application are merely for the purpose of describing particular embodiments and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. "Plural" generally includes at least two, but does not exclude the case of including at least one.

[0033] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this paper generally represents that the front and rear associated objects are a "or" relationship. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0034] It should be understood that the terms "include", "contain" or any other variation used herein are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0035] Reference to "embodiments" herein means that the specific features, structures or properties described in conjunction with the embodiments can be included in at least one embodiment of the present application. The phrase appears in the specification at each location does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] According to an aspect of the present application, a package of a semiconductor circuit module is disclosed, comprising a substrate, a housing, a plurality of semiconductor chips, a driving circuit board and a terminal. The housing has an accommodating space formed therein, and the substrate is arranged in the accommodating space and connected to the housing. The plurality of semiconductor chips are arranged on the substrate and electrically connected to each other to form a semiconductor circuit module. The driving circuit board is electrically connected to at least part of the semiconductor chips. The terminal is electrically connected to at least part of the semiconductor chips. The driving circuit board and at least part of the terminal are fixedly connected to the housing. The driving circuit board and at least part of the terminal have a gap with the substrate. The terminal having the gap with the substrate is electrically connected to the semiconductor chips only through a type of conductive member.

[0037] In some embodiments, the housing comprises a terminal support and a driving circuit board support. The terminal support is formed above the accommodating space. The terminal is fixedly connected to the housing and at least in contact with an upper surface of the terminal support. The driving circuit board support is formed above the accommodating space. The driving circuit board is fixedly connected to the housing and at least in contact with an upper surface of the driving circuit board support.

[0038] In some embodiments, a side of the housing extends in a horizontal direction away from the accommodating space to form the driving circuit board support.

[0039] In some embodiments, the terminal comprises a direct current positive terminal, a direct current negative terminal and an alternating current terminal. The direct current positive terminal, the direct current negative terminal and the alternating current terminal are electrically connected to at least part of the semiconductor chips respectively. At least one of the direct current positive terminal, the direct current negative terminal and the alternating current terminal is fixedly connected to the housing and has a gap with the substrate.

[0040] In some embodiments, the direct current negative terminal is fixedly connected to the housing and has a gap with the substrate.

[0041] In some embodiments, the direct current positive terminal is arranged close to the direct current negative terminal. The direct current positive terminal is electrically connected to the substrate. At least part of the direct current positive terminal is arranged in parallel with at least part of the direct current negative terminal, so that the direct current positive terminal has a current path opposite to the direction of the direct current negative terminal.

[0042] In some embodiments, the terminal having the gap with the substrate is electrically connected to the semiconductor chips only through a bonding wire.

[0043] In some embodiments, the substrate includes a first substrate and a second substrate; the second substrate overlaps at least a portion of the first substrate, the second substrate is electrically connected with the first substrate, and the second substrate has a current path opposite to that of the first substrate.

[0044] In some embodiments, the first substrate is electrically connected with the second substrate at least through a copper block.

[0045] In some embodiments, the plurality of semiconductor chips includes at least one of a MOSFET, a diode, a triode, and an IGBT.

[0046] According to a second aspect of the present application, there is provided a power electronic conversion device including the package of the semiconductor circuit module in any of the above embodiments.

[0047] In some embodiments, the power electronic conversion device can be a switching power supply.

[0048] In some embodiments, referring to FIG. 1, which is a structural schematic diagram of a substrate in some embodiments of the present application, the substrate 1 is a direct bonding copper (DBC) substrate.

[0049] In some embodiments, the substrate 1 includes four types of local DBCs. Please refer to Figs. 1-9; Fig. 2 is a schematic diagram of the top view of the A-type DBC in some embodiments of the present application; Fig. 3 is a schematic diagram of the bottom view of the A-type DBC in some embodiments of the present application; Fig. 4 is a schematic diagram of the top view of the B-type DBC in some embodiments of the present application; Fig. 5 is a schematic diagram of the bottom view of the B-type DBC in some embodiments of the present application; Fig. 6 is a schematic diagram of the top view of the C-type DBC in some embodiments of the present application; Fig. 7 is a schematic diagram of the bottom view of the C-type DBC in some embodiments of the present application; Fig. 8 is a schematic diagram of the top view of the D-type DBC in some embodiments of the present application; and Fig. 9 is a schematic diagram of the bottom view of the D-type DBC in some embodiments of the present application. As shown in Fig. 1, the B-type DBC, the C-type DBC and the D-type DBC can be symmetrically distributed in parallel semiconductor chips inside the semiconductor circuit module above the A-type DBC by solder stacking, and the direction of the bonding wire is perpendicular to the arrangement direction of the semiconductor chips, so that the parallel loop length is consistent. The A-type DBC includes an upper copper foil A1, a ceramic substrate A2 and a lower copper foil A3; the B-type DBC includes an upper copper foil B1, a ceramic substrate B2 and a lower copper foil B3; the C-type DBC includes an upper copper foil C1, a ceramic substrate C2 and a lower copper foil C3; and the D-type DBC includes an upper copper foil D1, a ceramic substrate D2 and a lower copper foil D3. Small holes 101 are further provided on the upper and lower copper foils of the four types of DBCs. The upper and lower layers of each local DBC are conductor layers, such as the copper foils A1-D1 and A3-D3, and the middle layer is the ceramic substrate A2-D2. The upper conductor layer is formed into multiple independent conductor layers by etching, and together with the power chip, the bonding wire, the terminal and the like, forms a circuit topology. The ceramic substrate A2-D2 of the middle layer serves as insulation and heat conduction. The lower copper foil A3-D3 is generally connected with the heat sink through a thermal interface material, and serves as heat conduction. In the present embodiment, the conductor layer is high-conductivity oxygen-free copper, hereinafter referred to as copper foil. The surface of the copper foil can be treated by electroplating to prevent oxidation. Partial silver plating facilitates sintering, reduces thermal resistance and enhances soldering stability. The ceramic substrate of the middle layer can generally be selected from ceramic materials such as alumina, aluminum nitride, zirconium-doped alumina and silicon nitride. In the present embodiment, in order to improve the heat dissipation performance, the ceramic substrate is selected to be silicon nitride ceramic with high thermal conductivity. The upper copper foil is etched with small holes 101 at the corners of part of the copper foil, and the lower copper foil is also etched with a circle of small holes 101 at a certain distance from the edge. The etched small holes 101 help to release the thermal stress at the edge of the copper foil, thereby improving the reliability. And the above scheme reduces the power loop stray inductance in a mutual inductance cancellation manner through the multi-layer DBC structure.

[0050] The outer edges of the upper and lower copper foils are away from the edges of the ceramic substrates A2-D2 by a distance determined according to the voltage withstand requirement of the module. In this embodiment, the distance between the outermost edges of the upper copper foils A1-D1 and the edges of the ceramic substrates A2-D2 is set to 1 mm, and the distance between the outermost edges of the lower copper foils A3-D3 and the edges of the ceramic substrates A2-D2 is set to 1 mm. The upper copper foils A1-D1 are processed to form circuit patterns and serve as conductive and heat transfer elements.

[0051] In some embodiments, referring to FIGS. 10-11, FIG. 10 is a structural schematic diagram of a package of a semiconductor circuit module according to some embodiments of the present application, and FIG. 11 is a top structural schematic diagram of the package of the semiconductor circuit module according to some embodiments of the present application. The package 100 of the semiconductor circuit module mainly comprises a substrate 1, a semiconductor chip 4 soldered on the substrate 1, a bonding wire 102 for connecting the surface electrodes of the semiconductor chip 4, a terminal 110 soldered on the substrate 1, a thermistor soldered on the substrate 1, a driving circuit board 1000, and a shell 2. The bottom of the shell 2 is fixedly connected to a bottom plate 3, for example, by means of adhesion, soldering, or the like. The bottom plate 3 is an electrically conductive bottom plate and can be supported by a copper material. An alternating current terminal 111 and a direct current positive terminal 112 that are pre-bent at the bottom are soldered on the substrate 1, and a direct current negative terminal 113 is supported and fixed by four hot-melt columns 201 and a terminal support 28 in the middle of the shell.

[0052] As shown in FIG. 11, different semiconductor chips are parallelly connected to each other inside the semiconductor circuit module, and the eight semiconductor chips close to the alternating current terminal 111 and the eight semiconductor chips close to the direct current negative terminal 113 are symmetrically arranged in FIG. 11. Moreover, the extension direction (indicated by X in the figure) of the bonding wires drawn from the semiconductor chips is perpendicular to the arrangement direction (indicated by Y in the figure) of the semiconductor chips. As can be seen from FIG. 11, by symmetrically arranging the semiconductor chips and making the extension direction of the bonding wires perpendicular to the arrangement direction of the semiconductor chips, the lengths of the bonding wires drawn from different semiconductor chips are substantially consistent, thereby realizing consistent lengths of parallel connection circuits and improving current sharing.

[0053] In some embodiments, the substrate 1 can be fixedly connected to the bottom plate 3, for example, by means of soldering connection, adhesion, or the like. The bottom plate 3 is fixedly connected to the shell 2, for example, by means of threaded connection. The present application does not limit the fixed connection modes between the substrate 1, the bottom plate 3, and the shell 2.

[0054] In some embodiments, several semiconductor chips are electrically connected to each other to form a bridge-type semiconductor circuit module, which is a circuit module formed by transistors based on semiconductor materials or combined with other elements such as resistors, etc., for example, a bridge-type half-wave rectifier circuit, a bridge-type full-wave rectifier circuit. The bridge-type semiconductor circuit module can be a full-bridge semiconductor circuit module or a half-bridge semiconductor circuit module. In the present embodiment, the bridge-type semiconductor circuit module is composed of two upper and lower bridge arms, which can be IGBT, MOSFET, Diode, etc. The bonding wire 102 material connected to the surface electrode of the power semiconductor chip is a conductor material such as copper, aluminum, gold, etc. In the present embodiment, the bonding wire 102 is an aluminum bonding wire which is low in cost and most commonly used.

[0055] In some embodiments, in order to improve the current-carrying capacity, the bonding wire 102 is generally composed of a plurality of thick bonding wires connected in parallel. In the present embodiment, each bonding wire is composed of 8 aluminum bonding wires with a diameter of 15 mil connected in parallel. In actual application, as many bonding wires as possible can be selected according to the size of the bondable area on the chip. In the present embodiment, considering the small size of the chip gate, the gate driving bonding wire (not marked in the figure) and the auxiliary source bonding wire (not marked in the figure) are each composed of one aluminum bonding wire with a diameter of 5 mil.

[0056] In some embodiments, the bottom of the DC positive terminal and the AC terminal is provided with a through hole (not shown in the figure) for welding with the substrate 1, which is beneficial to reduce the stress concentration during welding. The radius of the through hole can be between 0.4-0.8mm, for example, it can be 0.4, 0.5, 0.6, 0.8mm, etc.

[0057] In some embodiments, please refer to Figure 12, which is a partial structure schematic diagram of the substrate in some embodiments of the present application; since the bottom of the DC positive terminal 112 is close to the bridge copper block for electrically connecting two substrates 1 when welded to the substrate 1, in order to meet the creepage distance of the bridge copper block and the actual processability, the bottom of the DC positive terminal 112 has a certain slope.

[0058] In some embodiments, referring to FIG. 13, which is a schematic diagram of current loops in a double-layer substrate according to some embodiments of the present application, the package of the semiconductor circuit module has a double-layer substrate, and both the upper and lower layers of the double-layer substrate 1 are DBC, i.e., the uppermost layer of the upper layer of the substrate 1 is an upper copper foil, and the lowermost layer is a lower copper foil; the uppermost layer of the lower layer of the substrate 1 is an upper copper foil, and the lowermost layer is a lower copper foil; the upper and lower layers of the substrate can be electrically connected by a bridge copper block 105 or by a bonding wire 102. After the two layers of the substrate are stacked, the two layers of the substrate can form current paths in opposite directions. In the double-layer substrate 1, there are 9 current paths, as shown by the numbers 001-009 in FIG. 13. In theory, the current paths 001, 003, and 007 are opposite to the current paths 005 and 009; the current path 002 is opposite to the current paths 004, 006, and 008; and thus, there is mutual inductance between them to reduce the parasitic inductance. In practice, the mutual inductance effect of the current path 002 and the current paths 004, 006, and 008 has the greatest impact, and the effect of reducing the parasitic inductance is significant. The above scheme uses a multi-layer DBC structure to reduce the stray inductance of the power loop by mutual inductance cancellation.

[0059] In some embodiments, referring to FIG. 14, which is a schematic diagram of current loops in a DC positive terminal and a DC negative terminal according to some embodiments of the present application, the DC positive terminal 112 is arranged close to the DC negative terminal 113, the DC positive terminal 112 is electrically connected to the substrate, and at least part of the DC positive terminal 112 is arranged in parallel with at least part of the DC negative terminal 113, so that the DC positive terminal 112 has a current path in the opposite direction to the DC negative terminal 113. The dashed lines in FIG. 14 show the current paths of the current in the substrate 1, the bridge copper block 105, the bonding wire 102, the DC positive terminal 112, and the DC negative terminal 113, wherein the current paths 011-016 are formed on the DC positive terminal 112, the current paths 019-0111 are formed on the DC negative terminal 113, and the current paths 017-018 are formed on the bonding wire 102. Among them, the mutual inductance effect of the current paths 012, 014 and the current paths 017, 0110 has the greatest impact, and the effect of reducing the parasitic inductance is significant. The above scheme uses a multi-layer DBC structure to reduce the stray inductance of the power loop by mutual inductance cancellation.

[0060] In some embodiments, referring to FIG. 15, FIG. 15 is a schematic diagram of a current loop between the semiconductor chip and the terminal in some embodiments of the present application. The dotted line in FIG. 15 represents the current path, and the arrow represents the direction of the current. Therefore, by suspending at least part of the terminal 110 (for example, the DC negative terminal 113) from being directly electrically connected to the substrate 1, and only electrically connected through a type of conductive member (for example, the bonding wire 102), the current path between the semiconductor chip 4 and the DC negative terminal 113 includes: the semiconductor chip 4-the bonding wire 102-the DC negative terminal 113. In the embodiment in which the DC negative terminal is directly welded on the substrate, the current path between the semiconductor chip 4 and the DC negative terminal 113 includes: the semiconductor chip 4-the bonding wire 102-the substrate 1 (not shown)-the DC negative terminal 113. Therefore, compared with the embodiment in which the DC negative terminal is directly welded on the substrate, suspending at least part of the terminal 110 can make the current pass through the bonding wire 102 without passing through the substrate 1, thereby shortening the current loop and reducing the parasitic inductance. Similarly, after suspending the drive circuit board 1000, the semiconductor chip 4 and the drive circuit board 1000 can be electrically connected only through a type of conductive member (for example, the bonding wire 102), thereby shortening the current loop, further reducing the parasitic inductance, improving the reliability of the semiconductor circuit module, and enabling the semiconductor circuit module to work at a higher voltage level and a higher switching frequency, thereby effectively improving the power density of the semiconductor circuit module.

[0061] It should be noted that the "conductive member" mentioned in the present application refers to a device that only serves the function of electrical connection, such as a bonding wire, and a device with a substantial function, such as a resistor, does not belong to the conductive member in the present application. That is, when necessary, in addition to being electrically connected through the bonding wire 102, the semiconductor chip 4 and the drive circuit board 1000 can also be connected with a device such as a resistor.

[0062] Therefore, in the embodiments provided in the present application, by fixing and connecting the drive circuit board 1000 and at least part of the terminal to the housing instead of directly electrically connecting them to the substrate, the area of the reserved area on the substrate for electrical connection with the drive circuit board 1000 or at least part of the terminal can be reduced, thereby saving space, reducing the volume of the package of the semiconductor circuit module, and improving the power density; the commutation loop is optimized, and the parasitic inductance of the loop is reduced.

[0063] Referring to FIG. 16, FIG. 16 is a schematic diagram of the top structure of the substrate after the semiconductor chip and the thermistor are sintered in some embodiments of the present application. As shown in FIG. 16, the semiconductor chips 401-424 are sintered on the surface of the substrate 1, and the thermistor 425 is sintered on the C-type DBC. It should be understood that, for the convenience of description, different numbers are marked on the semiconductor chips in FIG. 16, but the semiconductor chips can be the same chip.

[0064] Please refer to FIG. 16, 17a-19, FIG. 17a is a top view structural schematic diagram of the package of the semiconductor circuit module in some embodiments of the present application; FIG. 17b is a three-dimensional structural schematic diagram of the package of the semiconductor circuit module in some embodiments of the present application; FIG. 18 is a circuit structural schematic diagram of the semiconductor circuit module in some embodiments of the present application; FIG. 19 is a structural schematic diagram of the terminal t1-t13 in the circuit of the semiconductor circuit module in some embodiments of the present application after packaging; as shown in FIG. 18, the semiconductor circuit module includes two half-bridge circuits, which can be used alone or simultaneously. In some embodiments, the semiconductor circuit module includes MOSFET chips, a thermistor 425. In the upper bridge arm circuit, the drain of the semiconductor chip 402-semiconductor chip 412 is welded on the upper copper foil B1 of the B type DBC, and then connected with the external circuit through the direct current positive terminal 112; the gate of the semiconductor chip 401, the semiconductor chip 403, the semiconductor chip 405, the semiconductor chip 407, the semiconductor chip 409, the semiconductor chip 411 is connected with the gate of the semiconductor chip 402, the semiconductor chip 404, the semiconductor chip 406, the semiconductor chip 408, the semiconductor chip 410, the semiconductor chip 412 through the gate bonding wire 4a, the gate bonding wire 6a, the gate bonding wire 8a, the gate bonding wire 10a, the gate bonding wire 12a, the gate bonding wire 14a; the auxiliary source of the semiconductor chip 401, the semiconductor chip 403, the semiconductor chip 405, the semiconductor chip 407, the semiconductor chip 409, the semiconductor chip 411 is connected with the auxiliary source of the semiconductor chip 402, the semiconductor chip 404, the semiconductor chip 406, the semiconductor chip 408, the semiconductor chip 410, the semiconductor chip 412 through the auxiliary source bonding wire 4b, the auxiliary source bonding wire 6b, the auxiliary source bonding wire 8b, the auxiliary source bonding wire 10b, the auxiliary source bonding wire 12b, the auxiliary source bonding wire 14b; then connected with the upper bridge drive board through the gate bonding wire 5a, the gate bonding wire 7a, the gate bonding wire 9a, the gate bonding wire 11a, the gate bonding wire 13a, the gate bonding wire 15a and the auxiliary source bonding wire 5b, the auxiliary source bonding wire 7b, the auxiliary source bonding wire 9b, the auxiliary source bonding wire 11b, the auxiliary source bonding wire 13b, the auxiliary source bonding wire 15b, and then connected with the external drive circuit.The power source of the semiconductor chip 401, the semiconductor chip 403, the semiconductor chip 405, the semiconductor chip 407, the semiconductor chip 409, and the semiconductor chip 411 is connected to the power source of the semiconductor chip 402, the semiconductor chip 404, the semiconductor chip 406, the semiconductor chip 408, the semiconductor chip 410, and the semiconductor chip 412 through the power source bonding wire 4c, the power source bonding wire 6c, the power source bonding wire 8c, the power source bonding wire 10c, the power source bonding wire 12c, and the power source bonding wire 14c, and is connected to the upper copper foil A1 of the A-type DBC through the power bonding wire 5c, the power bonding wire 7c, the power bonding wire 9c, the power bonding wire 11c, the power bonding wire 13c, and the power bonding wire 15c of the semiconductor chip 402, the semiconductor chip 404, the semiconductor chip 406, the semiconductor chip 408, the semiconductor chip 410, and the semiconductor chip 412, and then is connected to the external circuit through the alternating current terminal 111.

[0065] In the lower bridge arm circuit, the drain of the semiconductor chip 413~the semiconductor chip 418 is welded on the upper copper foil C1 of the C-type DBC, the drain of the semiconductor chip 419~the semiconductor chip 424 is welded on the upper copper foil D1 of the D-type DBC, the upper copper foil C1 of the C-type DBC and the upper copper foil D1 of the D-type DBC are electrically connected with the upper copper foil A1 of the A-type DBC through the bridge copper block 105, and then connected with the external circuit through the alternating current terminal 111. The gate of the semiconductor chip 413, the semiconductor chip 415, the semiconductor chip 417, the semiconductor chip 419, the semiconductor chip 421 and the semiconductor chip 423 is connected with the gate of the semiconductor chip 414, the semiconductor chip 416, the semiconductor chip 418, the semiconductor chip 420, the semiconductor chip 422 and the semiconductor chip 424 through the corresponding gate bonding wire (not marked in the figure); the auxiliary source of the semiconductor chip 413, the semiconductor chip 415, the semiconductor chip 417, the semiconductor chip 419, the semiconductor chip 421 and the semiconductor chip 423 is connected with the auxiliary source of the semiconductor chip 414, the semiconductor chip 416, the semiconductor chip 418, the semiconductor chip 420, the semiconductor chip 422 and the semiconductor chip 424 through the corresponding auxiliary source bonding wire (not marked in the figure); then connected with the lower bridge drive board through the gate bonding wire 17a, the gate bonding wire 19a, the gate bonding wire 21a, the gate bonding wire 23a, the gate bonding wire 25a, the gate bonding wire 27a and the auxiliary source bonding wire 17b, the auxiliary source bonding wire 19b, the auxiliary source bonding wire 21b, the auxiliary source bonding wire 23b, the auxiliary source bonding wire 25b and the auxiliary source bonding wire 27b, and then connected with the external drive circuit. The power source of the semiconductor chip 413, the semiconductor chip 415, the semiconductor chip 417, the semiconductor chip 419, the semiconductor chip 421 and the semiconductor chip 423 is connected with the power source of the semiconductor chip 414, the semiconductor chip 416, the semiconductor chip 418, the semiconductor chip 420, the semiconductor chip 422 and the semiconductor chip 424 through the power source bonding wire 17c, the power source bonding wire 19c, the power source bonding wire 21c, the power source bonding wire 23c, the power source bonding wire 25c and the power source bonding wire 27c, and then connected on the direct current negative terminal 113 through the power bonding wire 16c, the power bonding wire 18c, the power bonding wire 20c, the power bonding wire 22c, the power bonding wire 24c and the power bonding wire 26c of the semiconductor chip 413, the semiconductor chip 415, the semiconductor chip 417, the semiconductor chip 419, the semiconductor chip 421 and the semiconductor chip 423, so as to be connected with the external circuit.

[0066] It should be further noted that the power semiconductor chips included in the semiconductor circuit module in the embodiments can be implemented by different chips, and the present application is not limited thereto. For example, in one embodiment of the present application, a silicon carbide MOSFET chip with a freewheeling diode can be used. Further, it should be noted that in different embodiments, the power semiconductor chips included in the semiconductor circuit module can be implemented by different numbers of chips in parallel, and the present application is not limited thereto.

[0067] According to a second aspect of the present application, referring to FIG. 20, there is provided a power electronic conversion device 2000 comprising the package 100 of the semiconductor circuit module in any of the above embodiments.

[0068] In some embodiments, the power electronic conversion device 2000 can be a switching power supply.

[0069] It is readily apparent to those skilled in the art that numerous modifications and variations of the devices and methods described herein can be made without departing from the teachings of the present application. Accordingly, the above disclosure is intended to be illustrative only and not limiting of the scope of the application as set forth in the following claims.

Claims

1. A package of a semiconductor circuit module, characterized by comprising: include: substrate; A housing, wherein an accommodating space is formed inside the housing, and a substrate is disposed within the accommodating space and connected to the housing; A plurality of semiconductor chips are disposed on the substrate, and the plurality of semiconductor chips are electrically connected to each other to form a semiconductor circuit module; A drive circuit board, electrically connected to at least a portion of the semiconductor chip; Terminal blocks are electrically connected to at least a portion of the semiconductor chip; The drive circuit board and at least a portion of the terminals are fixedly connected to the housing. There is a gap between the drive circuit board and at least a portion of the terminals and the substrate. The drive circuit board and the terminals with gaps between them and the substrate are electrically connected to the semiconductor chip through only one type of conductive element.

2. The semiconductor circuit module package according to claim 1, wherein The terminal block includes a DC positive terminal, a DC negative terminal, and an AC terminal. The DC positive terminal, the DC negative terminal, and the AC terminal are electrically connected to at least a portion of the semiconductor chip. At least one of the DC positive terminal, the DC negative terminal, and the AC terminal is fixedly connected to the housing and has a gap between it and the substrate.

3. The semiconductor circuit module package according to claim 2, wherein The DC negative terminal is fixedly connected to the housing and has a gap between it and the substrate.

4. The semiconductor circuit module package according to claim 2, wherein The positive DC terminal is positioned close to the negative DC terminal, the positive DC terminal is electrically connected to the substrate, and at least a portion of the positive DC terminal is arranged parallel to at least a portion of the negative DC terminal, so that the positive DC terminal has a current path in the opposite direction to that of the negative DC terminal.

5. The semiconductor circuit module package according to claim 1, wherein The drive circuit board and the terminal block with a gap between it and the substrate are electrically connected to the semiconductor chip only through bonding wires.

6. The package of a semiconductor circuit module according to any one of claims 1 to 5, wherein The substrate includes: First substrate; A second substrate, which overlaps at least partially with the first substrate, is electrically connected to the first substrate, and has current paths in opposite directions to the first substrate.

7. The semiconductor circuit module package according to claim 6, wherein The first substrate and the second substrate are electrically connected at least through a copper block.

8. The semiconductor circuit module package according to claim 1, wherein The plurality of semiconductor chips include at least one of MOSFET, diode, transistor, and IGBT.

9. A power electronic conversion device, characterized by The package includes a semiconductor circuit module, the package comprising: substrate; A housing, wherein an accommodating space is formed inside the housing, and a substrate is disposed within the accommodating space and connected to the housing; A plurality of semiconductor chips are disposed on the substrate, and the plurality of semiconductor chips are electrically connected to each other to form a semiconductor circuit module; A drive circuit board, electrically connected to at least a portion of the semiconductor chip; Terminal blocks are electrically connected to at least a portion of the semiconductor chip; The drive circuit board and at least a portion of the terminals are fixedly connected to the housing. There is a gap between the drive circuit board and at least a portion of the terminals and the substrate. The drive circuit board and the terminals with gaps between them and the substrate are electrically connected to the semiconductor chip through only one type of conductive element.

10. The power electronic conversion device of claim 9, wherein, The wiring terminal comprises a direct current positive terminal, a direct current negative terminal and an alternating current terminal, the direct current positive terminal, the direct current negative terminal and the alternating current terminal are respectively electrically connected with the at least partial semiconductor chip, at least one of the direct current positive terminal, the direct current negative terminal and the alternating current terminal is fixedly connected to the shell and has a gap with the substrate.

11. The power electronic conversion device of claim 10, wherein, The direct current negative terminal is fixedly connected to the shell and has a gap with the substrate.

12. The power electronic conversion device of claim 10, wherein, The direct current positive terminal is arranged close to the direct current negative terminal, the direct current positive terminal is electrically connected with the substrate, at least part of the direct current positive terminal is arranged in parallel with at least part of the direct current negative terminal, so that the direct current positive terminal has a current path opposite to the direction of the direct current negative terminal.

13. The power electronic conversion device of claim 9, wherein, The driving circuit board and the wiring terminal having a gap with the substrate are only electrically connected with the semiconductor chip through a bonding wire.

14. The power electronic conversion device of any of claims 9-13, wherein, The substrate comprises: A first substrate; A second substrate, the second substrate overlaps at least part of the first substrate, the second substrate is electrically connected with the first substrate, the second substrate has a current path opposite to the first substrate.

15. The power electronic conversion device of claim 14, wherein, The first substrate and the second substrate are electrically connected at least through a copper block.

16. The power electronic conversion device of claim 9, wherein, The plurality of semiconductor chips comprise at least one of MOSFET, diode, triode and IGBT.

17. The power electronic conversion device of claim 9, wherein, The power electronic conversion device comprises a switching power supply.

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