Gallium nitride package

Abstract

In some examples, provided is a structure for a gallium nitride (GaN) package, the structure comprising multiple layers, wherein the multiple layers comprise a first layer arranged to connect multiple semiconductor dies, a second layer positioned beneath the first layer, wherein the second layer is arranged to electrically connect the first layer to a third layer, and the third layer positioned beneath the second layer, wherein the third layer is arranged to define a footprint of the GaN package and connect the GaN package to a printed circuit board.

Description

[0001] GALLIUM NITRIDE PACKAGE

[0002] TECHNICAL FIELD

[0003] The present disclosure relates, in general, to a gallium nitride (GaN) package and a package structure. Aspects of the disclosure relate to half-bridge GaN package.

[0004] BACKGROUND

[0005] Medium voltage gallium nitride (MV GaN) packages are essential components in modem power electronics, particularly for applications that demand high efficiency, fast switching speeds, and compact designs. MV GaN technology is increasingly utilised in a variety of applications, including power conversion, automotive, and consumer electronics, due to its superior electrical properties, such as high breakdown voltage, low on-resistance, and high switching frequency compared to traditional silicon-based technologies.

[0006] MV GaN packages play an important role in ensuring the optimal performance of GaN devices by effectively managing electrical and thermal characteristics. A key objective in the development of MV GaN packages is to minimise parasitic elements, such as stray inductances and resistances, and to maximise heat dissipation from the die to the printed circuit board (PCB) and associated cooling structures. Efficient thermal management is crucial to maintaining device performance, reliability, and longevity, especially in high-power and high-frequency applications.

[0007] One of the most challenging aspects of MV GaN packaging is observed in half-bridge configurations and half-bridge with driver packages. Half-bridge circuits are commonly used in power conversion and motor drive applications, where they operate at high frequencies and voltages. These packages typically feature an interdigitated source and gate structure, which is designed to reduce parasitic inductances and enhance switching speed. However, the traditional packaging approaches used in these configurations often fall short in terms of both electrical and thermal performance. The complex interconnections and compact design can result in increased parasitic capacitance and inductance, negatively affecting the overall efficiency and operational stability of the device.

[0008] The primary challenges associated with existing packaging technologies for MV GaN halfbridge applications include limitations in thermal management and excessive parasitic elements. Current designs often struggle to effectively dissipate heat from the GaN die to the PCB and cooling structures. Inefficient heat flow can lead to overheating, reduced performance, and potential device failure, particularly under high-power conditions. Additionally, the interdigitated source and gate structure, while beneficial for reducing parasitic inductances, contributes to increased parasitic capacitance, which can degrade the overall electrical performance. Consequently, manufacturing half-bridge packages with or without drivers that are optimised for the best possible thermal performance or capacitance behaviour remains a significant technical challenge.

[0009] SUMMARY

[0010] An objective of the present disclosure is to provide a new type of a multi-die GaN package and a package structure addressing the problems associated with the existing approaches.

[0011] The foregoing and other objectives are achieved by the features of the independent claims.

[0012] Further implementation forms are apparent from the dependent claims, the description and the Figures.

[0013] A first aspect of the present disclosure provides a structure for a gallium nitride (GaN) package, the structure comprising multiple layers, wherein the multiple layers comprise a first layer arranged to connect multiple semiconductor dies, a second layer positioned beneath the first layer, wherein the second layer is arranged to electrically connect the first layer to a third layer, and the third layer positioned beneath the second layer, wherein the third layer is arranged to define a footprint of the GaN package and connect the GaN package to a printed circuit board.

[0014] Accordingly, a new package structure for a multi-die GaN package can be provided. This structure minimises parasitics and offers a short and effective thermal path from the die to the substrate. It enables high-performance multi-die configurations with optional passive component integration within the package. The design achieves very low parasitic and thermal resistance by allowing direct connections from the die metallisation to the package footprint. Furthermore, the package can be manufactured using relatively standard processes that are already available, facilitating ease of production and scalability.

[0015] The first layer may comprise a plated copper layer. The plated copper layer may be embedded inside a polymer material.

[0016] The second layer may comprise multiple via bars.

[0017] A second aspect of the present disclosure provides a gallium nitride (GaN) as described herein.

[0018] The gallium nitride package may comprise a half-bridge package comprising at least two gallium nitride (GaN) transistors attached to the structure.

[0019] The gallium nitride package may further comprise a driver and / or at least one passive component attached to the structure.

[0020] At least one of the at least two GaN transistors, the driver and the at least one passive component may be connected to the structure via solder bumps positioned at a top of the first layer of the structure, wherein the solder bumps may comprise a round or an oval shape.

[0021] The at least two GaN transistors may comprise a low-side transistor die and a high-side transistor die, and the first layer of the structure may comprise multiple rectangular pads, wherein the multiple rectangular pads may comprise a first pad arranged substantially in a central section of the layer, wherein the pad may be aligned perpendicularly to a longitudinal axis of the first layer.

[0022] The multiple rectangular pads may comprise at least two second rectangular pads arranged at a first side of the first pad and a second side of the first pad, respectively, the at least two second rectangular pads separated from the first pad, wherein the at least two second rectangular pads may be arranged to overlap substantially the whole low-side transistor die and the high-side transistor die.

[0023] The at least two GaN transistors may comprise source and drain pads aligned perpendicular to the longitudinal axis of the first layer, and the multiple rectangular pads may comprise multiple third rectangular pads arranged at a first side of the first pad and a second side of the first pad, respectively, the multiple third rectangular pads separated from the first pad, and the multiple third rectangular pads may be aligned parallel to the longitudinal axis of the first layer and perpendicular to toe source and drain pads of the at least two GaN transistors.

[0024] The package may comprise electrically isolated side walls.

[0025] A third aspect of the present disclosure provides a method of fabricating a structure of a gallium nitride (GaN) package comprising multiple layers, the method comprising forming a first layer arranged to connect multiple semiconductor dies, forming a second layer positioned beneath the first layer, wherein the second layer is arranged to electrically connect the first layer to a third layer, and forming the third layer positioned beneath the second layer, wherein the third layer is arranged to define a footprint of the GaN package and connect the GaN package to a printed circuit board.

[0026] Forming the first layer arranged to connect multiple semiconductor dies may comprise forming a plated copper layer.

[0027] The method may further comprise embedding the plated copper layer inside a polymer material.

[0028] These and other aspects of the invention will be apparent from the embodiment(s) described below.

[0029] BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order that the present invention may be more readily understood, embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which:

[0031] Figure 1 is a schematic representation of a cross-section view of a structure according to an example;

[0032] Figure 2 is a schematic representation of a gallium nitride package comprising a structure according to an example;

[0033] Figures 3a-3c are schematic representations of a half-bridge package according to an example; Figures 4a-4c are schematic representations of a half-bridge package according to another example;

[0034] Figures 5a-5c are schematic representations of a half-bridge package according to yet another example; and Figure 6 is a flow chart of a method of fabricating a structure for a gallium nitride package comprising multiple layers according to an example.

[0035] DETAILED DESCRIPTION

[0036] Example embodiments are described below in sufficient detail to enable those of ordinary skill in the art to embody and implement the systems and processes herein described. It is important to understand that embodiments can be provided in many alternate forms and should not be construed as limited to the examples set forth herein.

[0037] Accordingly, while embodiments can be modified in various ways and take on various alternative forms, specific embodiments thereof are shown in the drawings and described in detail below as examples. There is no intent to limit to the particular forms disclosed. On the contrary, all modifications, equivalents, and alternatives falling within the scope of the appended claims should be included. Elements of the example embodiments are consistently denoted by the same reference numerals throughout the drawings and detailed description where appropriate.

[0038] The terminology used herein to describe embodiments is not intended to limit the scope. The articles “a,” “an,” and “the” are singular in that they have a single referent, however the use of the singular form in the present document should not preclude the presence of more than one referent. In other words, elements referred to in the singular can number one or more, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and / or “including,” when used herein, specify the presence of stated features, items, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, items, steps, operations, elements, components, and / or groups thereof.

[0039] Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as is customary in the art. It will be further understood that terms in common usage should also be interpreted as is customary in the relevant art and not in an idealized or overly formal sense unless expressly so defined herein.

[0040] Power electronics have increasingly focused on the development of high-efficiency, high- performance packaging solutions, particularly for gallium nitride (GaN) devices. GaN technology offers significant advantages over traditional silicon-based devices, including higher switching speeds, lower conduction losses, and improved thermal management, making it ideal for applications requiring compact, high-power density solutions. Multi-die GaN packages, which integrate multiple GaN devices and optional passive components within a single package, are particularly advantageous in power conversion applications such as halfbridges, half-bridges with integrated drivers, and parallel die configurations. However, achieving optimal electrical and thermal performance in these packages requires innovative design approaches that address parasitics and thermal resistance challenges while maintaining compatibility with existing manufacturing processes.

[0041] The most relevant currently employed solution in the market is the TI GaN Half-Bridge Power Stage package, which integrates two GaN dies and a driver within an FR4-based substrate. In this package, the GaN dies and driver are mounted on the top surface, and connections between the top and bottom sides are achieved through plated vias. The source and drain pads are relatively small and only partially overlap the dies, while the AC pad may be larger. This configuration leads to limited thermal and electrical performance due to the lateral current and heat flow paths. Additionally, the absence of large-area direct connections from the device metallisation to the package footprint further constrains overall performance.

[0042] The main disadvantages of said package design include limited electrical and thermal performance, primarily caused by the horizontal current and heat flow paths and the extremely small direct connections from the top to the bottom of the package. In contrast to thermally optimised designs, which can achieve up to 50-75% direct connection of the die source and / or drain areas to the footprint, the current design relies on much smaller, less efficient connections, thereby hindering optimal device operation.

[0043] Accordingly, there is proposed a package structure that overcomes the above-described limitations by employing advanced build-up substrates that facilitate direct connections from the die metallisation to the package footprint, significantly enhancing electrical and thermal conductivity. The inventive design minimises parasitic effects, optimises heat dissipation, and allows for high-performance, scalable manufacturing using existing production processes, making it a superior solution for modern power electronics applications. According to an example, there is provided a new type of half-bridge GaN package that distinguishes itself from existing MV GaN packages by utilising advanced build-up layer substrates instead of conventional half-etched lead-frames or standard laminate substrates. This package design minimises parasitic effects and provides a short and efficient thermal path from the die to the substrate and multilayer routing capability, resulting in high-performance multidie configurations with optional passive components. Specifically, very low parasitic and thermal resistance are achieved due to direct connections from the die metallisation to the package footprint, thereby reducing horizontal current and heat flow. For instance, even up to 50-75% of the source and drain pad lengths are directly connected to the package footprint, significantly enhancing performance. In one example, there is an option to minimise the overlap between source and drain at the die-package level, effectively reducing capacitance. Additional features include the absence of exposed copper leads on the package sidewalls to improve clearance distance and the option to expose the die top side to enhance top-side cooling. The package design can be readily adapted to standard manufacturing processes and allows for easy optimisation of isolation and creepage distances based on voltage ratings, offering a versatile and efficient solution for advanced power electronics applications.

[0044] The present disclosure is described with reference to flow charts and / or block diagrams of the method, devices and systems according to examples of the present disclosure. Although the flow diagrams described above show a specific order of execution, the order of execution may differ from that which is depicted. Blocks described in relation to one flow chart may be combined with those of another flow chart. In some examples, some blocks of the flow diagrams may not be necessary and / or additional blocks may be added. It shall be understood that each flow and / or block in the flow charts and / or block diagrams, as well as combinations of the flows and / or diagrams in the flow charts and / or block diagrams can be realized by machine readable instructions.

[0045] Figure 1 is a schematic representation of a cross-section view of a structure according to an example. The structure 100 comprises a base structure (i.e., a supporting structure) for a gallium nitride (GaN) package. As used herein, the term "gallium nitride package" may refer to a semiconductor package that encapsulates GaN devices, providing electrical connections, thermal management, and physical protection to enhance the performance and reliability of high-speed, high-efficiency power electronics. The structure 100 comprises multiple layers, including a first layer 101, a second layer 102, and a third layer 103, with the possibility of additional layers depending on design requirements. The first layer 101 may be arranged to connect multiple semiconductor dies. In this invention, the semiconductor dies remain in a bare, non-packaged form and are encapsulated within the package during the manufacturing process. The term "semiconductor die" refers to a small piece of semiconductor material, such as silicon or gallium nitride, that contains integrated electronic circuits and, in this structure, is encapsulated within the package to form a functional electronic component.

[0046] The first layer 101 may also be referred to as a routing layer. The first layer 101 may comprise a plated copper layer, where external components (e.g., drivers or similar) can be connected. The first layer 101 may have a thickness of around 70 to 120 micrometres, but the invention is not limited thereto. By increasing the thickness of the first layer 101, the resistance can be reduced, and the effective heat transfer can be maximised. The first layer 101 may be embedded within a polymer material. The polymer material may include, for example, EMC (epoxy molding compound), ABF (Ajinomoto Bonding Film), FR4 material, or other types of PCB or polymer materials.

[0047] The second layer 102 is positioned beneath the first layer 101 and is arranged to electrically connect the first layer 101 to a third layer 103. The second layer 102 may also be referred to as a via bar layer. The second layer 102 may comprise large area via bars arranged between the routing layer (first layer 101) and the package footprint (i.e., the third layer 103). Via bars may comprise conductive elements or structures that provide electrical connections between the different layers of the structure 100. These bars typically consist of metal and are designed to facilitate signal and power transfer through vertical pathways. The via bars may be located underneath solder bumps formed on top of the first layer 101. The second layer 102 may have a thickness of 30 to 70 micrometres (in order to minimise the thermal resistance), or 70 to 120 micrometres (to minimise the unwanted capacitance), but the invention is not limited thereto.

[0048] The third layer 103 is positioned beneath the second layer 102 (and thus also beneath the first layer 101, with the second layer 102 serving as an intermediary between the third layer 103 and the first layer 101). Importantly, the third layer 103 serves to define a footprint of the GaN package and connect the GaN package to an external circuit board. In other words, the third layer 103 establishes the outline or boundary of the GaN package, effectively determining the area on which the package's components, such as the GaN die and electrical connections, are arranged and mounted. The size and the location of the third layer 103 may depend on whether the device aims to maximise the thermal transfer or switching performance. The third layer 103 may have a thickness of between 30 to 60 micrometres, but the invention is not limited thereto.

[0049] Additionally, the structure 100 may comprise multiple solder bumps 104 positioned on top of the first layer 101. These solder bumps 104 may connect an external device (e.g., a driver, a passive component, or similar) to the structure 100. The size of the solder bumps 104 may depend on the device. The solder bumps 104 may comprise a round or an oval shape approximately 150 to 200 micrometres in a first dimension (y) and 600 to 1500 micrometres in a second dimension (x), but the invention is not limited thereto. The solder bumps 104 may have a height of around 80 to 120 micrometres. The solder bumps 104 may cover a large area of a device drain and source pads, preferably covering around 40 to 75% of said pads. In addition to solder bumps, other connection schemes such as copper pillars, may also be employed. Furthermore, a redistribution layer (RDL) may be included within the structure 100 to facilitate flexible routing of signals between the external device and the substrate. The selection of the connection scheme can be adjusted depending on the specific requirements of the external device and application.

[0050] Advantageously, in contrast to the prior art solutions, the invention makes use of a multilayer build-up substrate (for example, structure 100) instead of lead frames or PCB substrates, which are commonly employed by various companies. The key advantage of advanced build-up substrates is their ability to support multi-layer routing, unlike lead frames, and to connect these layers using large-area via bars, in contrast to PCB substrates. This approach enables the integration of multiple power dies, driver dies, and passive components into a single package. Unlike lead frames, where all wiring must be connected directly to the frame and "floating" wires between dies are not feasible, advanced build-up substrates allow through vias to be plated onto a carrier before lamination. The use of large-area via bar connections (i.e., second layer 102) ensures excellent electrical and thermal performance.

[0051] In the described concept, all package side walls can be isolated to enhance creepage distance, unlike traditional lead frame designs where leads are visible on the package side walls. This is achieved by using pattern plating inside a photoresist during the initial processing steps before molding, allowing leads to be positioned anywhere within the package without extending into the dicing line. However, if necessary, exposed leads can be provided for specific applications, such as lead tip inspection, where solder fillet may climb onto the exposed copper on the side wall, allowing visual inspection of the soldering or wetting quality.

[0052] Another significant advantage is the ability to process larger panel sizes compared to lead frames, enabling panel-level processing that reduces manufacturing costs. This is due to shorter processing times in parallel and sequential processes, reduced setup, waiting, and start-up times, as well as decreased material waste. Since the structure 100 can be pre-manufactured, integrating passive components and other elements is straightforward, allowing for optimal placement to ensure superior electrical performance.

[0053] As discussed earlier, the structure 100 is intended to be a part of a gallium nitride package. Figure 2 is a schematic representation of a gallium nitride package comprising a structure according to an example. The GaN package 200 may also comprise further components arranged on top of (i.e., connected to) the structure 100. The GaN package 200 comprises the structure 100.

[0054] The GaN package 200 may comprise, for example, a half-bridge package comprising at least two GaN transistors 110-1, 110-2 attached to the structure 100. The at least two GaN transistors 110-1, 110-2 may comprise a high-side transistor die and a low-side transistor die. The terms "high-side transistor die" and "low-side transistor die" may refer to the specific roles of GaN transistors within a half-bridge circuit configuration. A "high-side transistor die" is typically positioned between the positive voltage supply and the load, controlling the flow of current to the load from the high voltage side, while a "low-side transistor die" is positioned between the load and ground, controlling the current flow from the load to the low voltage side.

[0055] Additionally, in Figure 2, the GaN package 200 is depicted to also comprise multiple passive components 112 and a driver 111 soldered to the substrate structure 100, but the invention is not limited thereto. The driver 111 may be attached to the structure 100 using any suitable method such as wire-bonding or surface mounting. The skilled person would readily appreciate that the structure 100 may serve as a base for various electronic components, not just those depicted in the figure. That is, additional passives can be mounted on the substrate by soldering. The GaN transistors 110-1, 110-2 may be flip-chip mounted. In other words, the GaN transistors 110-1 and 110-2 may be mounted using a flip-chip assembly method, where the transistors are inverted and placed directly onto the package substrate with their active surfaces facing downward. The connection between the transistor dies and the substrate can be achieved using soldering, sintering, or any other suitable method. The driver 111 may also be flip-chip mounted to the substrate 100. In cases where the driver 111 does not have solder bumps and cannot be flip-chip mounted, it may be attached using a wire bonding technique, or any other suitable attachment scheme. In this arrangement, the driver may be mounted with its active surface facing upward, and wire bonds may be used to connect the driver’s pads to corresponding pads on the substrate 100.

[0056] In order to provide more detail regarding the half-bridge package, reference will now be made to Figures 3a-3c, which are schematic representations of a half-bridge package according to a first example. In particular, Figure 3a schematically depicts a design of a thermally optimised half-bridge package according to an example, Figure 3b schematically depicts the individual layers of the half-bridge package according to an example, while Figure 3c is a schematic representation of the connections from the device to the footprint according to an example. The thermally optimised half-bridge package 300 of Figures 3a-3c may comprise the structure 100 described above in relation to Figures 1 and 2. Throughout the figures, the same elements are denoted using the same reference numerals and function likewise.

[0057] The thermally optimised half-bridge package 300 may be optimised for best possible thermal performance. The first layer 101 of the structure 100 may comprise multiple rectangular pads. The multiple rectangular pads may comprise a first pad 320 arranged substantially in a central section of the first layer 101. The first pad 320 may be aligned perpendicularly to a longitudinal axis of the first layer 101. The first pad 320 may comprise, for example, an alternating current (AC) pad. Here, the term “AC pad” may refer to a pad used to provide connections for AC signals. These pads are designed to handle alternating current, allowing them to facilitate the input or output of AC signals within the device. In the context of the package comprising the structure 100, the AC pad may serve as the interface for connecting to other circuit components or systems that operate with AC power or signals.

[0058] The multiple rectangular pads may comprise at least two second rectangular pads 321-1, 321-

[0059] 2, arranged at a first side of the first pad 320 and a second side of the first pad 320. The at least two second rectangular pads 321-1, 321-2 may be separated from the first pad 320. The second rectangular pads 321-1, 321-2 may be arranged to overlap substantially the whole low-side transistor die and the high-side transistor die.

[0060] In other words, for the half-bridge package 300, the footprint pad may cover the whole or at least large part of the die. The footprint pad 331 is depicted in Figure 3b, showing the individual layers of the half-bridge package 300. Figure 3b shows the first layer 331, the second layer 332, the third layer 333, a die and oval solder bump structure 334 and a package topside 335, showing exposed die backsides. The source and drain pads of the HS transistor die and the LS transistor die may be connected to the footprint pad 331 using direct connections - in particular, using the solder bumps and the via bars 332, comprising copper. To aid understanding of the halfbridge package 300, figure 3c depicts the connections from the devices (i.e., the LS / HS transistor dies) to the footprint pad 331 - in particular, source connections 350 and drain connections 360 are depicted.

[0061] Advantageously, since direct connections may be provided from the devices to the footprint 331, effective heat and current flow from the device to the footprint can be ensured. Additionally, a reduction in the movement of electrical current and heat through the metal layers of the LS and HS transistor dies can be observed. By achieving high direct connection coverage, the vertical current and heat flow through the metallisation layers of the transistor dies (i.e., conductive metal layers or contacts on the transistor dies that facilitate internal electrical connections) can be minimised, leading to improved thermal and electrical performance.

[0062] Figures 4a-4c depict a half-bridge package according to another example. As before, Figure 4a schematically depicts a design of a switching performance optimised half-bridge package according to an example, Figure 4b schematically depicts the individual layers of the halfbridge package according to an example, while Figure 4c is a schematic representation of the connections from the device to the footprint according to an example.

[0063] The half-bridge package 400 may be optimised to achieve the best possible switching performance. To avoid unwanted capacitance phenomena, the overlapping of the PGNG and VIN pads of the package 100 and the source and drain lines of the LS / HS transistor dies can be minimised. Here, the terms PGNG and VIN pads may refer to specific types of connection pads within a semiconductor package. In particular, the PGNG pads may refer to "power ground" pads used for grounding purposes, while the VIN pads may denote "voltage in" pads, which are used to supply the input voltage to the circuit.

[0064] In contrast to the half-bridge package 300, for the half-bridge package 400, the first layer may comprise multiple third rectangular pads 421-1, 421-2, ..., 421-n arranged at a first side of a first pad 420. These rectangular pads are depicted in Figure 4b (first layer 431), showing in detail the specific geometry of the pads. Figure 4b shows the first layer 431, the second layer 432, the third layer 433, a die and oval solder bump structure 434 and a package topside 435, showing exposed die backsides.

[0065] The multiple third rectangular pads 421-n may again be separated from the first pad 420. The third rectangular pads 421-n may be aligned parallel to the longitudinal axis of the first layer 101 of the package 100 and perpendicular to the source and drain pads of the GaN transistors. The source and drain pads may be horizontally in-line or interdigitating.

[0066] Figure 4c depicts the connections from the devices (i.e., the LS / HS transistor dies) to the footprint pad 431 - in particular, source connections 450 and drain connections 460 are depicted. Although not visible in Figure 4c, all drain and source lines may be connected together. The source and drain connections from the GaN transistors to the structure footprint may be realised using solder bumps and substrate vias.

[0067] Finally, Figures 5a-5c are schematic representations of a half-bridge package according to yet another example. The half-bridge package 500 may be optimised to balance current density in the half-bridge package. A first pad 520 is shown in the Figure, as well as two second rectangular pads 521-1, 521-2. In order to optimise and balance the current flow and density in PGND, AC and VIN pads, the area of each pad may be similar or substantially similar. This approach may help in minimising the differences in current density between the pads and mitigate potential reliability risks. However, a drawback of this design is the limited thermal performance resulting from the absence of direct connections from the device to the footprint. As such, the half-bridge packages 300 and 400 may be preferred over the half-bridge package 500.

[0068] Similarly to previous figures, Figure 5b shows the first layer 531, the second layer 532, the third layer 533, a die and oval solder bump structure 534 and a package topside 535, showing exposed die backsides. Figure 5c depicts the connections from the devices (i.e., the LS / HS transistor dies) to the footprint pad 531 - in particular, source connections 550 and drain connections 560 are depicted.

[0069] Figure 6 is a flow chart of a method of fabricating a structure for a gallium nitride package comprising multiple layers according to an example. The method may result in the fabrication of the structure 100 described herein. In block 601, the method comprises forming a first layer arranged to connect multiple semiconductor dies. The first layer may comprise the first layer 101 described herein.

[0070] In block 602, the method comprises forming a second layer positioned beneath the first layer, wherein the second layer is arranged to electrically connect the first layer to a third layer. The second layer may comprise the second layer 102 described herein. The method comprises, in block 603, forming the third layer positioned between the second layer, wherein the third layer is arranged to define a footprint of the GaN package and connect the GaN package to a printed circuit board. The third layer may comprise the third layer 103 described above.

[0071] The preceding description has been provided to enable others skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the instant disclosure. The embodiments disclosed herein should be considered in all respects illustrative and not restrictive. Reference should be made to the appended claims and their equivalents in determining the scope of the instant disclosure.

Claims

CLAIMS1. A structure (100) for a gallium nitride, GaN, package, the structure (100) comprising multiple layers, wherein the multiple layers comprise: a first layer (101) arranged to connect multiple semiconductor dies; a second layer (102) positioned beneath the first layer (101), wherein the second layer (102) is arranged to electrically connect the first layer (101) to a third layer (103); and the third layer (103) positioned beneath the second layer (102), wherein the third layer (103) is arranged to define a footprint of the GaN package and connect the GaN package to a printed circuit board.

2. The structure of claim 1, wherein the first layer (101) comprises a plated copper layer.

3. The structure of claim 2, wherein the plated copper layer is embedded inside a polymer material.

4. The structure of claim 1, 2 or 3, wherein the second layer (102) comprises multiple via bars.

5. A gallium nitride, GaN, package comprising a structure (100) as claimed in any preceding claim.

6. The gallium nitride package of claim 5, comprising a half-bridge package comprising at least two gallium nitride, GaN, transistors (110-1, 110-2) attached to the structure.

7. The gallium nitride package of claim 6, further comprising a driver (111) and / or at least one passive component (112) attached to the structure (100).

8. The gallium nitride package of 6 or 7, wherein at least one of the at least two GaN transistors (110-1, 110-2), the driver (111) and the at least one passive component (112) is connected to the structure (100) via solder bumps (104) positioned at a top of the first layer (101) of the structure (100), wherein the solder bumps (104) comprise a round or an oval shape.

9. The gallium nitride package of any one of claims 6, 7 or 8, wherein the at least two GaN transistors (110-1, 110-2) comprise a low-side transistor die and a high-side transistor die, wherein the first layer (101) of the structure (100) comprises multiple rectangular pads, wherein the multiple rectangular pads comprise a first pad (320) arranged substantially in a central section of the first layer (101), wherein the first pad (320) is aligned perpendicularly to a longitudinal axis of the first layer (101).

10. The gallium nitride package of claim 9, wherein the multiple rectangular pads comprise at least two second rectangular pads (321-1, 321-2) arranged at a first side of the first pad (320) and a second side of the first pad (120), respectively, the at least two second rectangular pads (321-1, 321-2) separated from the first pad (320), wherein the at least two second rectangular pads (321-1, 321-2) are arranged to overlap substantially the whole low-side transistor die and the high-side transistor die.

11. The gallium nitride package of claim 9, wherein the at least two GaN transistors (110- 1, 110-2) comprise source and drain pads aligned perpendicular to the longitudinal axis of the first layer, wherein the multiple rectangular pads comprise multiple third rectangular pads (421-n) arranged at a first side of the first pad (420) and a second side of the first pad (420), respectively, the multiple third rectangular pads (421-n) separated from the first pad (420), wherein the multiple third rectangular pads (421-1) are aligned parallel to the longitudinal axis of the first layer and perpendicular to the source and drain pads of the at least two GaN transistors.

12. The gallium nitride package according to any one of claims 5 to 11, wherein the package comprises electrically isolated side walls.

13. A method of fabricating a structure for a gallium nitride, GaN, package comprising multiple layers, the method comprising: forming a first layer arranged to connect multiple semiconductor dies (501); forming a second layer positioned beneath the first layer, wherein the second layer is arranged to electrically connect the first layer to a third layer (502); and forming the third layer positioned beneath the second layer, wherein the third layer is arranged to define a footprint of the GaN package and connect the GaN package to a printed circuit board (503).

14. The method of claim 13, wherein forming the first layer arranged to connect multiple semiconductor dies (501) comprises forming a plated copper layer.

15. The method of claim 14, further comprising embedding the plated copper layer inside a polymer material.

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