VSWR-resilient switchless pa / LNA RF front-end for TDD

Abstract

A front-end configuration of a transceiver combines two sets of Power Amplifiers (PA) (each set comprising, e.g., one differential PA or two single-ended PAs in anti-phase) and two Quadrature Hybrid Couplers (QHC) as a balanced PA circuit that is robust to load modulation. A Low Noise Amplifier (LNA) is connected, and protected from direct and reflected TX signals, such that a TX / RX antenna switch is not needed. The ISO ports of the two QHCs are connected to a symmetrical passive 3-port network connected to the LNA input. In TX-mode, inputs of the 3-port network are excited differentially, and the network terminates any TX signal reflected from the antenna in a resistive load, while presenting a virtual ground at its input. In Rx mode, the output impedances of the sets of PAs are reconfigured to make the received signal appear at the inputs of the 3-port network in common-mode.

Description

[0001] P110769W001

[0002] VSWR-RESILIENT SWITCHLESS PA / LNA RF FRONT-END FOR TDD

[0003] TECHNICAL FIELD

[0004] The present disclosure relates generally to wireless communications, and in particular to a Time Division Duplex (TDD) transceiver featuring a VSWR-resilient, switchless Low Noise Amplifier (LNA) front-end using reflected signals from a balanced Power Amplifier (PA).

[0005] BACKGROUND

[0006] Wireless communication networks are ubiquitous in many parts of the world. These networks continue to grow in capacity and sophistication. To accommodate more users, different types of devices, and different use cases, the technical standards governing the operation of wireless communication networks continue to evolve. The fourth generation (4G) of network standards has been deployed, the fifth generation (5G) is in final development and is partially deployed, and the sixth generation (6G) is in design. With each generation, technological advances improve the capacity, spectral efficiency, and achieved bitrate of the wireless communication system, as well as introduce new use cases, such as Ultra Reliable and Low Latency Communications (URLLC) and Machine-to-Machine (M2) communications. As spectrum in lower frequencies fills up, higher frequency spectrum is taken into use.

[0007] 5G added a second frequency range, FR2. This provided a significant new available spectrum in the range 24.25-52.6 GHz (FR1 spans 410 - 7125 MHz). At these high frequencies, wavelengths are small. Correspondingly, antenna elements are small, and each captures / radiates less energy. Accordingly, more antenna elements are required to cover the same area with the same link performance and the same inter-site distance. FIG. 1 shows one example antenna array, consisting of 8x8 dual-polarized antenna elements. The antenna elements are pairwise interconnected to form 2x1 subarrays, and thus reduce the number of active radio chains required to connect to the antenna and apply beamforming. The subarrays are numbered SAO to SA31 (moving left to right and top to bottom). In general, antenna elements of an array may be grouped into any number of subarrays, each comprising any number of individual antenna elements. Subarrays in an antenna array need not be the same - that is, some antennal elements may be grouped into one or more m x n subarrays, and other antennal elements may be grouped into one or more i x j subarrays, where m i and / or n j. As used herein, a subarray may include from one antenna element up to all of the antenna elements in an antenna array.

[0008] FIG. 2 shows one example of a transceiver front end, implemented on a Radio Frequency (RF) integrated circuit (RFIC), that can be used together with the antenna array of FIG. 1. This RFIC has 8 bidirectional IQ baseband ports, an internal port expansion by four, and thus 32 antenna connections. Each antenna branch, also referred to as an RF tile, has its own Phase Locked Loop (PLL), to enable beamforming (as discussed below) by controlling the P110769W001 relative phase between antenna elements or subarrays. In transmit (TX) mode, the IQ baseband signal is split to four branches, upconverted to RF using an IQ-modulator, and amplified by a PA. An antenna switch connects either the transmitter or the receiver branch to the antenna element subarray. As depicted in FIG. 2, the tiles connect to the antenna element subarrays in column 1 of the antenna system depicted in FIG. 1 (that is, subarrays SAO, SA8, SA16, and SA24). In receive (RX) mode, each antenna element subarray signal is amplified by a Low Noise Amplifier (LNA), downconverted to baseband, and added to the other three branches sharing the IQ-interface. The antenna switch separates the TX / PA and RX / LNA paths. See, for example, the paper by C. Elgaard, et al., “Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS”, published in the IEEE Journal of Solid-State Circuits, 2023, the disclosure of which is incorporated herein in its entirety. Such a switch may have an impact on the maximum allowed voltage swing and / or it may degrade the noise figure (NF).

[0009] Advanced Antenna System (AAS) implementations contemplate hundreds, or even thousands, of antenna elements. This increases the number of data streams to be processed, increasing the system computational load. Another problem with RF carriers at these high frequencies is that they suffer higher path loss, and hence have limited range, compared to conventional wireless telecom operating frequencies. Beamforming is one technique featured in 5G and 6G, to improve both coverage and capacity.

[0010] Beamforming refers to the use of antennas having increased and controllable directionality, whereby an RF transmission (or reception sensitivity) is narrowly focused, and is “aimed” in a specific direction. This is enabled by transmitting or receiving signals with controlled relative phase and gain in the antenna elements (or subarrays of antenna elements). The relative phases of, e.g., transmit signals sent to each antenna element are controlled to create constructive or destructive interference, thus amplifying the signal in some directions, and attenuating it in others, and hence controlling the direction in which the beam is transmitted. Similar phase manipulation of signals from antenna elements (or subarrays) in a receive antenna can also result in beamforming the sensitivity of an antenna array for receiving signals. FIG. 3 shows how a successively larger phase shift at each of adjacent antenna elements results in a directionally steered RF beam.

[0011] Because beamforming combines the outputs of multiple antenna elements (or subarrays), it increases beam gain, concentrating greater RF signal energy towards a receiver. This mitigates the inherent path loss of higher frequency carrier signals and restores the rated equivalent isotropic radiated power (EIRP) rating of base stations operating in FR1 and FR2 to usable levels.

[0012] In addition to combatting path loss, another advantage to beamforming is that, particularly with large antenna arrays, multiple orthogonal beams can be formed and aimed in different directions, thus simultaneously addressing multiple wireless devices, also known as P110769WQ01

[0013] User Equipment (UE). For example, both a direct beam (line of sight) and a reflected beam may be targeted to a UE. Additionally, frequency-selective beamforming may be implemented, wherein subcarriers of the same Orthogonal Frequency Division Multiplexing (OFDM) symbol are assigned different weights, thus pointing beams in different directions as a function of frequency.

[0014] To form robust beams, antenna elements are normally placed tightly together. For example, a distance of A / 2 is commonly used (where A is the RF wavelength), to form arbitrary beams without folding. However, the tight antenna spacing causes high electromagnetic coupling between the antennas, and additionally signals leak in between the antennas. The beamsteering, combined with the antenna coupling, makes the impedance seen by each power amplifier (PA) driving the antenna elements (or subarrays) deviate from a designed impedance.

[0015] The PA is designed assuming a nominal load impedance for optimal output power, linearity, and efficiency. The PA amplifies and delivers electrical power to the antenna element / subarray, which converts it to an electromagnetic signal. However, if the load impedance seen by the PA diverges from its designed (optimum) value, there is an impedance mismatch, which degrades PA performance.

[0016] To direct a beam to a desired direction, a phase shift is required between signals sent to different antenna elements (or subarrays). The same signal, except for the phase shift, is present at all antenna elements, and electromagnetic energy of the signal leaks between them. This is seen by the PAs as a mismatch from an optimal (matched) impedance. The designed impedance seen by the PA is referred to as the impedance in the boresight direction ( / .e., where the RF signal is radiated normal to the plane of the antenna element). When coupling is present between the antenna elements (due to spacing), and the same signal is sent on all antennas, but with different phases, this is experienced by the PA as load impedance variation and mismatch, even though it originates from antenna leakage and the delay introduced by the phase shifter ( / .e., the mismatch typically grows higher as the beam-angle increases, since the relative phase shift between antennas increases). Because the impedance mismatch causes a partial reflection of the RF signal from the antenna element (or subarray) back toward the PA, a standing wave is generated along the transmission line connecting the two. This is quantified in the art as an antenna impedance Voltage Standing Wave Ratio (VSWR), which is calculated in terms of the reflection coefficient or return loss (also known as the s11 parameter). Assuming the antenna and PA are impedance-matched for signals transmitted in the boresight direction, the active impedance load, or VSWR, typically grows higher as the beam-angle increases, since the relative phase shift in between antenna elements (or subarrays) increases.

[0017] One known way to mitigate load impedance variation is to use a Quadrature Hybrid Coupler (QHC). A QHC is a special case of the general class of directional couplers for which the coupling is 3dB. FIG. 4 depicts one implementation of a QHC using transmission lines or microstrips. The transmission lines are of electrical length A / 4, where A is the wavelength of the P110769WQ01 fundamental frequency. In other aspects, the QHC may be built from lumped reactive elements, such as inductive and capacitive devices. Such an implementation may be attractive for integration, as such QHCs may be fabricated in less area than a transmission line or microstrip implementation. For example, Robert C. Frye, et al. describe a CMOS implementation of a QHC suitable for integration on a high frequency RFIC, in the paper “A 2GHz Quadrature Hybrid Implemented in CMOS Technology,” published at the IEEE 2002 Custom Integrated Circuits Conference p. 287, the disclosure of which is incorporated herein by reference in its entirety. FIG. 5 shows a QHC based on a transformer, with lumped inductive elements that may be implemented on an IC.

[0018] An ideal QHC is a symmetric, lossless, passive, four-port network, which imparts a 90° phase shift. Because it is symmetric, a QHC can split an input signal into two output signals (having 90° phase offsets) or combine two input signals (having 90° phase offsets) into one output signal. If a signal is incident on only one port of a QHC, there is a port from which no power will exit, referred to as the isolation port (ISO). When configured as a splitter or combiner, the isolation port is often terminated to ground through a characteristic impedance (e.g., 50Q).

[0019] As the Frye paper cited above discloses, one known application of a QHC is to implement a balanced PA, which exhibits reduced sensitivity to impedance mismatches by the load. This application is further described by Guiseppe Berretta, et al. in the paper “A Balanced CDMA2000 SiGe HBT Load Insensitive Power Amplifier,” published in the IEEE Radio and Wireless Symposium, 2006, pp. 523-526, the disclosure of which is incorporated herein by reference in its entirety. FIGs. 6A and 6B, copied from the Berretta paper, depict a schematic diagram of a balanced amplifier implemented using two QHCs, and a graph of output powers, respectively. As depicted in FIG. 6A, an RF signal is input to port 1 of a first QHC configured as a splitter, with a standard 50Q impedance connected to ground at port 4. The QHC outputs the signal on both output ports 2 and 3, with a 90° phase offset. These are amplified by PAs, which output the amplified quadrature RF signals, through impedance matching circuits, to a second QHC configured as a combiner, at input ports 2 and 3. The combined RF signal is output at port 1 , with a standard 50Q impedance connected to ground at port 4.

[0020] FIG. 6B shows the output power for each PA as the load impedance varies over a full VSWR=4 circle ( / .e., 0-360°). Because of the quadrature operation, the two PAs compensate each other, and the output power of the balanced PA circuit - the top curve in FIG. 6B - is nearly flat. A balanced PA architecture thus exhibits a high insensitivity to impedance mismatch, such as that caused by coupling between antenna array elements in beamforming operations.

[0021] FIG. 7 shows that the output at the ISO port of the QHC can be used to provide feedback to a baseband processor for correction and reduction of variations between TX chains. This technique is described in international patent application WO 2022 / 229682 to Shen, et al.

[0022] FIG. 8 shows a balanced PA using QHCs, wherein the ISO port is terminated with an adjustable impedance. This can be used to vary the impedance seen by the PAs of the P110769WQ01 balanced PA design, as described in published patent application US 2022 / 0006428 to Sheppard, et al.

[0023] Hence, use of a QHC is known in the art as a useful way to reduce PAs sensitivity to the variations in load impedance caused by beamforming, and to provide feedback to baseband. However, TDD solutions, even using such beneficial properties of QHCs, still typically require an antenna switch to alternately connect the antenna array to TX and RX paths. Such switches may limit the maximum allowed voltage swing, add losses, degrade linearity, and / or degrade the noise figure.

[0024] The Background section of this document is provided to place aspects of the present disclosure in technological and operational context, to assist those of skill in the art in understanding their scope and utility. Approaches described in the Background section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Unless explicitly identified as such, no statement herein is admitted to be prior art merely by its inclusion in the Background section.

[0025] SUMMARY

[0026] The following presents a simplified summary of the disclosure in order to provide a basic understanding to those of skill in the art. This summary is not an extensive overview of the disclosure and is not intended to identify key / critical elements of aspects of the disclosure or to delineate the scope of the disclosure. The sole purpose of this summary is to present some concepts disclosed herein in a simplified form as a prelude to the more detailed description that is presented later.

[0027] According to aspects of the present disclosure described and claimed herein, a PA / LNA RF front-end configuration of a transceiver combines two sets of PAs, each generating two outputs in anti-phase (for example, each set may comprise a single differential PA) and two QHCs, forming a balanced PA circuit known to be robust to load modulation. An LNA is connected, and protected from direct and reflected TX signals, such that a TX / RX antenna switch is not needed. The ISO ports of the two QHCs are connected to a symmetrical passive 3- port network, which is connected to the LNA input. In TX-mode, inputs of the 3-port network are excited differentially, and the network terminates any TX signal reflected from the antenna in a resistive load, while simultaneously protecting the LNA by presenting a virtual ground at its input. In Rx mode, the output impedances of the PAs are reconfigured to make the received signal appear at the inputs of the 3-port network in common-mode. The network then combines the signals and impedance matches them to the LNA input.

[0028] One aspect relates to a Radio Frequency (RF) transceiver front end circuit configured to operate alternatively in transmit (TX) mode or receive (RX) mode. The transceiver front end circuit includes a balanced power amplifier circuit, comprising a plurality of power amplifiers (PA); first and second quadrature hybrid couplers (QHC) each having IN, OUT, coupled (CPL), P110769WQ01 and isolation (ISO) ports. Two anti-phase outputs of a first set of PAs are independently connected to the OUT terminals of the first and second QHCs; and two anti-phase outputs of a second set of PAs are independently connected to the CPL terminals of the first and second QHCs. The IN terminals of the first and second QHCs are coupled to one or more antennas. The transceiver front end circuit further includes a 3-port network having two inputs, respectively connected to the ISO terminals of the first and second QHCs, and an output; and a low noise amplifier (LNA) having an input connected to the output of the 3-port network.

[0029] Another aspect relates to a method, performed by an RF transceiver front end circuit configured to operate alternatively in TX mode or RX mode. In TX mode, RF signals are amplified in a balanced amplifier circuit comprising first and second sets of PAs and first and second QHCs. The amplified RF signals are output to one or more antennas. RF signals reflected from the antennas are applied to a passive 3-port network in differential mode, so as to dissipate the reflected signals. A virtual signal ground is presented at an input to an LNA. In RX mode, RF signals are received from the one or more antennas. Power to the first and second sets of PAs is interrupted. A transistor driving one leg of the anti-phase output of each of the first and second sets of PAs is biased to approximate an open circuit impedance and a transistor driving the other leg of the anti-phase output of each of the first and second sets of PAs is biased to approximate a short circuit impedance. Received RF signals reflected from the first and second sets of PAs are applied to the passive 3-port network in common mode, so as to combine the reflected signals. The combined, reflected, received RF signals are applied to the LNA.

[0030] Yet another aspect relates to a UE operative in a wireless communication network. The UE includes processing circuitry, and the transceiver front end circuit described above, operatively connected to the processor circuitry.

[0031] Still another aspect relates to a base station operative in a wireless communication network. The UE includes processing circuitry and the transceiver front end circuit described above, operatively connected to the processor circuitry.

[0032] BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which aspects of the disclosure are shown. However, this disclosure should not be construed as limited to the aspects set forth herein. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like numbers refer to like elements throughout.

[0034] FIG. 1 is a diagram of an antenna array.

[0035] FIG. 2. is a schematic diagram of an RFIC suitable for use with the antenna array of FIG. 1. P110769W001

[0036] FIG. 3 is diagram showing the relationship between phase shift at adjacent antenna elements and directional beamforming.

[0037] FIG. 4 is a diagram of a QHC implemented with transmission lines or microstrips.

[0038] FIG. 5 is a diagram of a QHC implemented with a transformer.

[0039] FIG. 6A is a block diagram of a balanced PA employing QHCs.

[0040] FIG. 6B is a graph of the output(s) of the balanced PA of FIG. 6A.

[0041] FIG. 7 is a block diagram showing feedback from the ISO port of a QHC to baseband.

[0042] FIG. 8 is a schematic diagram of a balanced PA with the ISO port of the QHC resistively terminated.

[0043] FIG. 9 is a block diagram of an LNA connected to the ISO port of a QHC.

[0044] FIG. 10 is a schematic diagram of a simulation circuit corresponding to the block diagram of FIG. 9.

[0045] FIG. 11A is a graph of output power at the antenna and ISO ports, and voltage at the LNA input, as a function of PA input power.

[0046] FIG. 11B is a graph of output power at the antenna and ISO ports, and voltage at the LNA input, as a function of VSWR angle.

[0047] FIG. 12 is a schematic diagram of a transceiver front end circuit, with differential PAs and a single-ended antenna and balun, according to one aspect of the present disclosure.

[0048] FIG. 13 is a schematic diagram of a transceiver front end circuit, with sets of single- ended PAs and a differential antenna without a balun, according to a different aspect of the present disclosure.

[0049] FIG. 14A is the block diagram of FIG. 12 annotated to show operation in TX mode.

[0050] FIG. 14B is the block diagram of FIG. 12 annotated to show operation in RX mode.

[0051] FIG. 15 is a schematic diagram of the transceiver front end circuit circuitry, showing the passive 3-port network according to a first aspect of the present disclosure, annotated to show operation in TX mode.

[0052] FIG. 16 is a schematic diagram of half of the 3-port network according to the first aspect of the present disclosure, under differential mode excitation.

[0053] FIG. 17 is a schematic diagram of the transceiver front end circuit circuitry, showing the passive 3-port network according to a first aspect of the present disclosure, annotated to show operation in RX mode.

[0054] FIG. 18 is a schematic diagram of half of the 3-port network according to the first aspect of the present disclosure, under common mode excitation.

[0055] FIG. 19 is the schematic diagram of FIG. 16 with an additional, gain-boosting shunt capacitor at the LNA input.

[0056] FIG. 20 is a conceptual layout diagram showing current flow through the same inductor under differential and common mode excitations. P110769W001

[0057] FIG. 21 is a schematic diagram of transceiver circuitry, showing the passive 3-port network according to a second aspect of the present disclosure, annotated to show operation in TX mode.

[0058] FIG. 22 is a schematic diagram of half of the 3-port network according to the second aspect of the present disclosure, under differential mode excitation.

[0059] FIG. 23 is a schematic diagram of transceiver circuitry, showing the passive 3-port network according to a second aspect of the present disclosure, annotated to show operation in RX mode.

[0060] FIG. 24 is a schematic diagram of half of the 3-port network according to the second aspect of the present disclosure, under common mode excitation.

[0061] FIG. 25 is the schematic diagram of FIG. 23 with an additional, gain-boosting shunt capacitor at the LNA input.

[0062] FIG. 26A is a generalized block diagram of half of the 3-port network according to the first aspect of the present disclosure.

[0063] FIG. 26B is a generalized block diagram of half of the 3-port network according to the second aspect of the present disclosure.

[0064] FIG. 27A is a graph showing return loss in the 3-port network in differential (TX) mode.

[0065] FIG. 27B is a graph showing insertion loss in the 3-port network in common (RX) mode.

[0066] FIG. 28 is a flow diagram of a method of operating transceiver circuitry.

[0067] FIG. 29A is a diagram of a RAN of a wireless communication network.

[0068] FIG. 29B is a block diagram of a UE in the wireless communication network of FIG. 29A.

[0069] FIG. 29C is a block diagram of a base station in the wireless communication network of FIG. 29A.

[0070] DETAILED DESCRIPTION

[0071] For simplicity and illustrative purposes, the present disclosure is described by referring mainly to an exemplary aspect thereof. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be readily apparent to one of ordinary skill in the art that the present disclosure may be practiced without limitation to these specific details. In this description, well-known methods and structures have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0072] FIG. 9 depicts a balanced PA driving an antenna array, with the ISO port of the QHC providing a direct input to an LNA, avoiding an antenna switch. This circuit is described in US patent no. 10,848,197 to Pal, et al. Simulation results indicate that this circuit may generate potentially destructive voltage levels at the LNA input in the case of a VSWR situation.

[0073] FIG. 10 shows the simulated circuit configuration, including two differential PAs in a balanced configuration with a single QHC. At the ISO port, a termination was used to represent P110769WQ01 the input of an LNA. The circuit was simulated under such conditions that the output power levels at the antenna were 14 and 21 dBm, comparable to the rms and peak output power levels in actual transceiver circuitry. Under VSWR conditions, the power / signal level at the ISO port will rise compared to the nominal case when VSWR = 1. Even at nominal conditions (VSWR = 1), there is a residual signal at the ISO port of the QHC, due to non-ideal matching between the PAs and the QHC. This signal strength is increased under VSWR conditions, such as during beamforming of the antenna elements.

[0074] Two test cases were simulated: VSWR = 1 and VSWR = 2. In each case the power of the differential signal at the inputs to the PAs was ramped from -20 to 10 dBm. Key parameters are summarized in Table 1 for Pout = ~21 dBm and Pout = -14 dBm.

[0075] FIGs. 11 A. and 11 B show the output power POUT at the antenna port in dBm, the residual power Piso at the ISO port of the QHC in dBm, the isolation in dB (calculated as POUT - Piso), and the voltage of the residual signal at the ISO port in mV.

[0076] FIG. 11 A shows the sweep of PA input power for a VSWR = 1. The upper and lower curves show that the signal amplitude at the ISO port is -161 mV for an output power level POUT of -21.1 dBm, and ~75mV for an output power level POUT of -14.1 dBm.

[0077] In contrast, FIG. 11 B shows the sweep of load reflection coefficient phase for VSWR = 2 at a nominal POUT = 21 dBm. Again, considering the upper and lower curves, the voltage of the residual signal at the ISO port reaches ~830mV for an output power level Pout of -21.1 dBm at about 290 degrees (which can be considered as a worst case scenario at the nominal POUT = 21 dBm)

[0078] Table 1. Power, isolation and signal levels at the OUT and ISO ports P110769W001

[0079] The signal amplitudes, evaluated directly at the ISO port across the port termination, which are assumed to fully represent the LNA input, are about -7.5 dBc in the worst case. This means that it could be problematic to directly connect to a LNA input gate in case the output power is relatively large. The maximum allowed signal levels between device terminals to comply with reliability requirements are -1.3V. Thus, considering the peak signal and bias levels, there is a -1.3V peak, which may present excessive voltage stress levels to the LNA device. The situation may be more problematic, or even directly destructive, if a larger output power is required or if the peak levels are applied for a longer period of time. Accordingly, at least some signal levels at the ISO port preclude direct connection of an LNA. A series switch could be inserted to isolate the LNA input during TX mode; however, this would add signal loss and increase the NF.

[0080] According to aspects of the present disclosure described and claimed herein, a transceiver front end comprises two sets of PAs, each generating anti-phase outputs, two QHCs, and a three-port network and provides a direct input to an LNA, without requiring an antenna switch, and that presents signal voltage levels that do not pose a danger to the LNA, even under high VSWR conditions. The transceiver combines the outputs of the PA sets and directs them to the antenna array in TX mode. In this mode, the input to the three-port network is differential, and terminated in a virtual ground. In RX mode, the PAs are not powered, and are biased such that signals from the antenna array pass through the QHCs and are reflected by the PAs, then pass back through the QHC and are presented in common mode to the three-port network, which combines them and presents them to the LNA input.

[0081] FIG. 12 is a schematic diagram of the transceiver front end circuit 10. A balanced amplifier circuit 12 comprises two differential power amplifiers PA1 , PA2. As described further below, each differential amplifier PA1, PA2 may be considered to be a set of PAs, wherein the set has only one member. The amplifiers PA1, PA2 each receive differential inputs (180° out of phase), that are in quadrature, or have a 90° phase shift between the amplifiers PA1 , PA2. For example, as shown, PA1 receives a differential signal at -90° and 90°, and PA2 receives a differential signal at 0° and 180°. Of course, these phase measurements are taken from an arbitrary reference point of a TX signal, and those of skill in the art will readily recognize that many phase values may be generated, so long as each amplifier PA1, PA2 receives a differential signal, and the differential signals applied to the two amplifiers PA1 , PA2 are in quadrature. As discussed in greater detail below, the two sets of power amplifiers can also be implemented by four single-ended power amplifiers.

[0082] In TX mode, amplified TX signals are applied to two Quadrature Hybrid Couplers QHC1, QHC2, each having output (OUT), input (IN), isolation (ISO), and couple (CPL) ports, corresponding to ports 1 , 2, 3, and 4, respectively, of FIGs. 4, 5, and 6A. Those of skill in the art recognize that a QHC is a symmetric device, and the labels are for reference, and are not limiting. P110769WG01

[0083] The differential outputs of PA1 are independently connected to the OUT terminals of QHC1 and QHC2. The differential outputs of PA2 are independently connected to the CPL terminals of QHC1 and QHC2. A balun 14 connects to the IN terminals of QHC1 and QHC2 as a differential input, and outputs a single-ended signal to one or more antennas 16.

[0084] A passive 3-port network 18, 19 (the numbering reflecting two aspects of the disclosure, described in greater detail herein) has two inputs, each independently connected to the ISO terminals of QHC1 and QHC2, and an output. A low noise amplifier (LNA) 20 has an input connected to the output of the 3-port network. In TX mode, the 3-port network 18, 19 provides resistive termination of reflected TX signals and protects the LNA by placing a virtual ground at the input of the LNA.

[0085] In RX mode, PA1 and PA2 are powered down and biased to provide different reflection characteristics. Signals received from the antenna pass through the couplers QHC1, QHC2, are reflected from PA1 and PA2 with opposite phase shifts, and appear in common mode at the ISO ports of QHC1 and QHC2. The 3-port network 18, 19 then serves as a signal combiner and input matching network for the LNA 20.

[0086] FIG. 13 depicts an aspect of the present disclosure wherein the transceiver front end circuit 10 is implemented with three differences to the aspect depicted in FIG. 12.

[0087] First, FIG. 13 depicts the input side of the balanced amplifier - that is, QHC3 and QHC4 receiving a differential input signal to be amplified, and the relative phases of the signals at the inputs and outputs of all QHCs

[0088] Second, the first and second sets of PAs here each comprise two single-ended PAs, rather than a single differential PA. In particular, in both Tx and Rx mode, PA1 and PA3 form a first set of PAs, which operates as described for the differential PA1 in FIG. 12. Similarly, PA2 and PA4 form a second set of PAs, which operates as described for the differential PA2 in FIG. 12.

[0089] Third, the one or more antennas 16’ are differential components, which removes the need for a balun 14. In this aspect, the IN ports of QHC1 and QHC2 are directly connected to the antenna(s) 16’

[0090] For ease and consistency of explanation, the transceiver front end circuit 10 is further described herein with reference to differential PAs (PA1 , PA2) and a balun 14, as depicted in FIG. 12. However, those of skill in the art will readily recognize that any of the aspects depicted and described in the present disclosure may be implemented using neither, either, or both of single-ended PAs grouped in anti-phase, and differential antennas.

[0091] FIG. 14A shows the operation of the transceiver front end circuit 10 in TX mode. Differential TX signals are amplified by PA1 and PA2 in quadrature. These signals are combined in QHC1 and QHC2, and output as a differential signal, e.g., -90° and 90°, on the IN ports. The balun 14 combines the differential signals and outputs an amplified, single-ended signal to the antennas 16. Particularly during beamforming, VSWR > 1 at the antenna array P110769WQ01 results in reflected signals back through the balun. The QHCs then act as splitters in the reverse direction, propagating the reflected signals to the PA outputs. The amplifiers PA1 and PA2 reflect these waves equally, and they appear inverted at the ISO ports of QHC1 and QHC2,e.g., at 180° and 0°. A differential mode signal is thus applied to the input of the passive 3-port network 18, 19. As further explained herein, the passive 3-port network 18 presents a virtual ground at the LNA 20 input.

[0092] FIG. 14B shows the operation of the transceiver front end circuit 10 in RX mode. A single-ended RX signal received by the antennas 16 is converted to differential mode by the balun 14 and passes through QHC1 and QHC2. In RX mode, the amplifiers PA1 and PA2 are powered down and biased to provide different reflection characteristics at each leg of their differential outputs. This places the reflected RX wave in common mode at the ISO ports of QHC1 and QHC2. The passive 3-port network 18, 19 then combines these signals, performs impedance matching, and applies a single-ended signal to the input of the LNA 20.

[0093] To perform these different functions for differential and common mode inputs, the required scattering parameters (S-parameters) of the passive 3-port network 18, 19 are: where

[0094] A and B are complex scattering parameters for the same reference impedance Zo as for the QHCs. The reflection coefficient T.r„, is the input reflection of the LNA in a Zo reference impedance. Note that the description of S is valid for both lossy and lossless matching to the LNA in RX-mode.

[0095] In RX mode, the output impedances of PA1, PA2 must be reconfigured to create out of phase reflections, to obtain common mode excitation of the passive 3-port network 18, 19. The wanted reflection can be achieved, according to one aspect, by creating high-ohmic and low- ohmic terminations at the outputs of PA1 and PA2. G = 1 is given by (3) and (4) below, and an inverted phase of the maximum reflection coefficient, i.e., G = -1 is given by (3) and (5). P110769W001

[0096] G 1 when Zoutoo(4)

[0097] The closest one can get to Zout approaching infinity, or an open-circuit, is a PA biased to an off-state - that is, with the gate biased below pinch-off. The closest one can get to Zout approaching zero, or a short-circuit, is a PA biased to a low on-resistance - that is, the gate bias is maximized. These impedances must be symmetrically assigned to QHC1 and QHC2, but asymmetrically assigned to each pair of differential PA1 , PA2 output signals, as shown in FIG. 14B. The supply voltage to PA1 and PA2 is changed in RX mode, such as by power clamping or by reducing or disabling a voltage regulator output.

[0098] FIG. 15 is a schematic diagram of the transceiver front end circuit 10 in TX mode (for clarity, only reflected signals are shown), with details of a first aspect of the passive 3-port network 18 between the ISO ports of QHC1 , QHC2 and the LNA 20. This passive 3-port network 18 acts as a termination in TX mode, and an input matching network of the LNA 20 in RX mode. The passive 3-port network 18 in Figure 15 has a so-called L-match topology.

[0099] In order to generate a virtual ground at the input of the LNA 20, depicted as Zo / 2, and maintain a Zo nominal termination impedance at the ISO ports of QHC1 , QHC2, a differential L- match circuit is employed, with either a differential shunt capacitor and two series inductors (as shown in FIG. 15) or a differential shunt inductor and two series capacitors. The series impedances depicted as Zo / n are resistors herein because this is the most straight-forward approach, and therefore simplifies the explanation to those of skill in the art. Further, these Zo / n impedances are connected to the inductors, and also to the node where the LNA 20 input impedance (Zo / 2) is connected. This node is a virtual ground node, considered signal ground. The Zo / n impedance is up-transformed into the nominal impedance of Zo using the differential L- match circuit 18, the operation of which is shown mathematically in the initial design equations (6) below. Further, the term 1+Q2is the classic impedance transform of a resonance circuit, and this is the factor by which the series component up-transforms a series impedance. By using a series impedance (Zo / n), which is reduced by the impedance transform factor (n) (eqn. 6c), the nominal impedance can be maintained as a termination impedance at the ISO ports of the two couplers QHC1 , QHC2. The selection of n is a trade-off between bandwidth (BW - eqn. 6a), voltage attenuation (eqn. 7a), insertion loss (IL) prior to the LNA 20 (eqn. 7b), and inductor area. In order to size the components in the L-match circuit 18, (eqn. 8) is used, while considering the trade-off between the aforementioned merits. In addition, those of skill in the art will recognize that the input shunt capacitor is connected in a differential manner, because the impedance transfer should only be utilized during TX mode. In RX mode, the impedance step-up transformation should not be used, or should at least be minimized. P110769WG01

[0100] FIG. 16 shows half of the L-match circuit 18 according to the first aspect (the part within the box in FIG. 15), with differential mode (TX mode) excitation. First, the Zo / n resistance is connected between the inductor and the LNA 20 input, i.e., the LNA 20 input is a virtual ground, due to cancelation of the signals. Secondly, the inductor is resonated by the shunt capacitor (eqn. 8d), due to the differential-mode excitation of the circuit 18. The series inductor and shunt capacitor perform an up-transformation of the Zo / n impedance, to the nominal impedance Zo (eq. 6c).

[0101] FIG. 17 is a schematic diagram of the transceiver front end circuit 10 in RX mode, according to the first aspect of the present disclosure. The RF signal received at the antenna 16 is split into a differential signal by the balun 14, and enters the IN ports of QHC1 and QHC2, now acting as splitters. The differential PAs are asymmetrically terminated to achieve different reflection properties, and power to the PAs is clamped. In one aspect, output impedances of the different sides of each differential PA are tuned to approximate (1) an open circuit (gate of P110769W001 transistor is biased low to turn the transistor off) and (2) a short circuit (gate of transistor is biased high to turn the transistor on). In other aspects, different biasing may be used to obtain a 180° difference in the reflected signals. The reflected signals are cross-coupled back through the couplers QHC1 , QHC2, which generate two in-phase reflected RX signals at their ISO ports. The reflected signals at the ISO ports of QHC1 , QHC2 are in-phase and may have the same magnitude. This is the (reflected) received signal from the antenna 16. Because the signals are in-phase, the voltage across the shunt capacitor in the L-match circuit 18 is zero or very small. This means effectively the capacitor can be considered an open circuit, as little or no current flows through the shunt capacitor and therefore the series inductor and the resistor are the only components in the network during RX mode. In the RX mode, it is important to select the appropriate parameter n of the L-match circuit 18, because this will set the insertion loss (IL) prior to the LNA 20 (eqn. 7b), which directly degrades the NF of the complete RX train.

[0102] The IL of the passive 3-port network 18, here ~0.5 dB, is still less than for an antennaswitch at mm-wave frequencies, which is typically 1.2 dB. Furthermore, the IL is unchanged with regard to frequency, in contrast to an antenna-switch, which increases its IL with frequency. In addition, the series inductors in the L-match circuit can be incorporated into the input matching of a source-degenerated common-source LNA 20, as one non-limiting example. This means no significant increase in chip area is expected if this L-match circuit 18 is added to the transceiver front end circuit 10, and the effect of the inductors’ Q-value QLS) may be disregarded. Finally, by combining the two signals from the ISO port, the LNA 20 must have an input impedance of Zo / 2, in order to provide the correct matching for the two couplers QHC1 , QHC2. This can be solved by adding an impedance down-transformation equal to n in the RX mode. The impedance seen from each ISO port towards the LNA 20, is Zo / n+2*(Zo / 2), thus approximately Zo.

[0103] For the common-mode excitation (RX mode) the input resistance of the LNA 20 is assumed to be Zo / 2. The half- or single-ended circuit case for the passive 3-port network 18 is shown in FIG 18 (the portion within the box in FIG. 17), where the input resistance of the LNA 20 is Zo. A shunt capacitor is present in parallel with Zo, and this is (half of) the capacitance from the LNA 20 input transistor. This capacitance may be used to up-transform the Zo / 2 to Zo. This is the inverse operation to what is shown by eqn. 6c in the TX mode. Furthermore, this capacitor is put into resonance by the series inductor. If needed, additional shunt capacitance can be added to the coupler sides of the inductors, but this must be referenced to signal ground and cannot be differential. Note that the additional capacitance is not visible in TX mode, when the reflected ISO port signals are differential.

[0104] FIG. 19 is a schematic diagram of the transceiver front end circuit 10 in RX mode, with the first aspect of the passive 3-port network 18, and an additional shunt capacitor added to the input of the LNA 20. This results in a higher LNA 20 input impedance than Zo / 2; in this case it is Zo. This type of impedance down-transformation results in a passive voltage gain of approximately Q for the (reflected) RX signal at the two ISO ports. This feature can be used to P110769WG01 match an LNA 20 with higher input impedance. By increasing the input impedance of the LNA 20, power is saved in the LNA 20. Furthermore, the capacitor at the input of the LNA 20 has no effect when the transceiver front end circuit 10 is operating in TX mode, because the node is a virtual ground.

[0105] To further increase the flexibility with the L-match circuit 18, the two series inductors can be implemented into one physical layout. By placing the different turns in a specific way, the resulting inductance is different when exited in either differential or common mode. FIG. 20 shows current flow in an example inductor with both differential and common mode excitation. Another approach is to use a classic “8-shape” inductor to decouple the two series inductors from each other. In this case, the two series inductors have the same inductance, regardless of the mode of excitation.

[0106] At the frequency of the design, QHC1 and QHC2 each provide a characteristic impedance equivalent to a resistive value, and there is no natural point of connecting a power supply since there is not a virtual ground node. The optimal PA load impedance is typically inductive, where the reactive portion is used to tune out the device capacitances. In the configuration depicted in FIGs. 17 and 19, two inductors are inserted between the -90° and +90° signals, and between the 0° and 180° signals. The differential inductors can supply VDD at the center point and tune out the capacitances of PA1 and PA2, virtually leaving the PA load impedance equal to the characteristic impedance of QHC1 , QHC2. The PA’s transistors acting like switches, and the corresponding device capacitances, could be absorbed by the shunt capacitances, CG, of a transformer-based QHC, as shown in FIG. 5. Power clamping on VDD may be used to avoid dissipating short-circuit currents between VDD and ground when the shunt switches are turned on.

[0107] FIG. 21 is a schematic diagram of the transceiver front end circuit 10 in TX mode (for clarity, only the reflected signals are shown), with a second aspect of the L-match circuitry forming the passive 3-port network 19. This aspect does not include impedance transformation; accordingly, it has an inherently wider bandwidth, and the termination element 2Zo (a differential Zo termination) is placed differentially to the ISO ports of QHC1 and QHC2. Reflected TX signals appear across the termination element 2Zo and are dissipated in this termination. The signals at the LNA 20 input (Z^LNA) are canceled and the node is a virtual signal ground. The equivalent half- or single-ended circuit in the TX mode is shown in FIG. 22. This circuit is a parallel resonance circuit, created by the virtual signal ground at the LNA 20 input and the arrangement of the network 19 components. In other aspects, the series resistance in the L- match inductors and shunt capacitor can be incorporated into the termination element 2Zo, resulting in a theoretically loss-less network.

[0108] FIG. 23 is a schematic diagram of the transceiver front end circuit 10 in RX mode, with the second aspect of the L-match circuitry forming the passive 3-port network 19. By placing the input capacitor and the termination element 2Zo in a differential configuration, they have no P110769WG01 voltage drop across them; accordingly, the RX signal is in common mode. Additionally, the LNA 20 input matches the circuitry to the antenna 16 and is well matched when the LNA input impedance equals ZO / 2. The equivalent half- or single-ended-circuit of this second aspect of the L- match circuitry 19 in the RX mode is shown in FIG. 24. The circuit is similar to the topology of many known LNA input matching networks.

[0109] FIG. 25 is a schematic diagram of the transceiver front end circuit 10 in RX mode, with the second aspect of the L-match circuitry forming the passive 3-port network 19, with the addition of a passive gain-boosting shunt capacitance at the input to the LNA 20 (not shown), as described above with respect to FIG. 19.

[0110] FIGs. 26A-B present a general impedance representation of the first aspect (FIG. 26A) of the L-match circuitry 18 (as shown in FIGs. 15, 17, and 19) and the second aspect (FIG 26B) of the L-match circuitry 19 (as shown in FIGs. 21 , 23, and 25). The impedances Z1-Z3 are all placed in a similar way in both FIG. 26A and FIG. 26B; the difference is the placement of the termination impedance, Zo / n in the first aspect (FIG. 26A) and 2Zo in the second aspect (FIG. 26B). Furthermore, to obtain resonance at a center frequency of the L-match circuits 18, 19 in FIGs. 26A-B, in TX mode the imaginary part of Zi and Z2, jXi and jX2, respectively, should cancel each other and during RX mode the imaginary part of Z2 and Z3, jX2 and jX3, respectively, should cancel each other. The impedances Z1-Z3 can, in general, be anything from a purely resistive impedance, a capacitive impedance, and / or an inductive impedance.

[0111] For either aspect of the passive 3-port network 18, 19, the graph of FIG. 27A shows the return loss in TX mode (differential mode) and the graph of FIG. 27B shows the insertion loss in RX mode (common mode). These graphs result from simulations, assuming ideal QHCs, as shown in FIG. 5, and perfect reflections at the drain terminals of differential output transistors PA1 and PA2. In these simulations, the loss due to reflections at the transistor drains is < 0.1 dB. In actual circuitry, losses include the sum of losses at each circuit element. For example, in RX mode, at 40 GHz, the loss at the balun 14 is -1 dB, the loss through the QHC is ~0.6 dB, and the loss from the PA reflection is -1 .3 dB. Added to the -0.1 dB loss through the passive 3- point network 18, 19 yields a total loss at the LNA 20 input of -3.6 dB. The balun loss can be eliminated by use of differential antenna elements (as depicted in FIG. 13), and the losses at the PA reflections (which include both resistive losses and amplitude / phase imbalance of the on / off reflections) can be reduced by oversizing the PA transistors.

[0112] In the transceiver front end circuit 10 according to aspects of the present disclosure, for Time Division Duplex (TDD) operation, a TX / RX antenna switch can be eliminated, and RX signals are obtained at the LNA 20 as reflections from the PAs (or sets of PAs). TX signal reflections from the antenna are terminated in the passive 3-point network 18, 19, and the LNA 20 is protected in TX mode by a virtual ground. Accordingly, the transceiver front end circuit 10 is robust to high VSWR, such as that encountered in beamforming. The transceiver P110769WG01 front end circuit 10 according to aspects disclosed herein is suitable for the mid-band 2.3-5 GHz, as well as FR1, FR3, and the mm-Wave FR2 bands.

[0113] FIG. 29 depicts the steps in a method 100, performed by an RF transceiver front end circuit 10 configured to operate alternatively in TX mode or RX mode. The TDD mode is determined (block 102). In TX mode, RF signals are amplified in a balanced amplifier circuit 12 comprising first and second sets of PAs and first and second QHCs (block 104). The amplified RF signals are output to one or more antennas 16 (block 106). RF signals reflected from the antennas 16 are applied to a passive 3-port network 18, 19 in differential mode, so as to dissipate the reflected signals (block 108). A virtual signal ground is presented at an input to an LNA 20 (block 110). In RX mode (block 102), RF signals are received from the one or more antennas 16 (block 112). Power to the first and second sets of PAs is interrupted (block 114). A transistor driving one leg of the anti-phase output of each of the first and second sets of PAs is biased to approximate an open circuit impedance and a transistor driving the other leg of the anti-phase output of each of the first and second sets of PAs is biased to approximate a short circuit impedance (block 116). Received RF signals reflected from the first and second sets of PAs are applied to the passive 3-port network 18, 19 in common mode, so as to combine the reflected signals (block 118). The combined, reflected, received RF signals are applied to the LNA 20 (block 120). Although depicted as individual, ordered steps in FIG. 28 for the purpose of explanation, those of skill in the art will recognize that, within TX mode and RX mode, the listed method steps may all occur simultaneously, in an ongoing, continuous fashion. Apparatuses described herein may perform the method 100 herein and any other processing by implementing any functional means, modules, units, or circuitry. In some aspects of the disclosure, for example, the apparatuses comprise respective circuits or circuitry configured to perform the steps shown in method 100. The circuits or circuitry in this regard may comprise analog circuits dedicated to performing certain functions, and / or one or more digital signal processors in conjunction with memory.

[0114] Figure 29A is a diagram of transmissions over the air interface of a Radio Access Network (RAN) of a wireless communication network 30, such as a 3GPP 4G (Long Term Evolution, or LTE) or 5G (New Radio, or NR), or 6G network. A User Equipment (UE) 40, such as a smartphone, receives and transmits modulated Radio Frequency (RF) signals, over one or more antennas, from and to a base station 50, such as an LTE eNB, an NR gNB or any RAN node serving as (part of) a base station or access point, for example an AAS installation.

[0115] At one or both of the UE 40 and base station 50, at least one instance of transceiver front end circuit 10 according to aspects of the present disclosure receives and transmits RF signals.

[0116] Figure 29B is a block diagram of the UE 40 of Figure 29A. As used herein, the term UE may refer to a user-operated telephony terminal, a machine-to-machine (M2M) device, a machine-type communications (MTC) device, a Narrowband Internet of Things (NB-loT) device P110769W001

[0117] (in particular a UE implementing the 3GPP standard for NB-loT), etc. A UE 40 may also be referred to as a radio device, a radio communication device, a wireless communication device, a wireless terminal, or simply a terminal - unless the context indicates otherwise, the use of any of these terms is intended to include device-to-device UEs or devices, machine-type devices or devices capable of machine-to-machine communication, sensors equipped with a radio network device, wireless-enabled table computers, mobile terminals, smartphones, laptop-embedded equipped (LEE), laptop-mounted equipment (LME), USB dongles, wireless customer-premises equipment (CPE), and the like.

[0118] The UE 40 transmits and receives RF signals on at least one antenna 16, 16’ which may be internal or external, as indicated by dashed lines. In general, the antenna(s) 16, 16’ may implement beamforming, resulting in high VSWR. The RF signals are generated, and received, by a transceiver 46, which includes one or more instances of transceiver front end circuit 10 according to aspects of the present disclosure. The transceiver 46, as well as other components of the UE 40, are controlled by processing circuitry 42. Memory 44 operatively connected to the processing circuitry 42 stores software in the form of computer instructions operative to cause the processing circuitry 42 to control the transceiver 46, including the transceiver front end circuit(s) 10. A user interface 48 may include output devices such as a display and speakers (and / or a wired or wireless connection to audio devices such as ear buds), and / or input devices such as buttons, a keypad, a touchscreen, and the like. As indicated by the dashed lines, the user interface 48 may not be present in all UEs 40; for example, UEs 40 designed for Machine Type Communications (MTC) such as Internet of Things (loT) devices, may perform dedicated functions such as sensing / measuring, monitoring, meter reading, and the like, and may not have any user interface 48 features.

[0119] Figure 29C is a block diagram of the base station 50 of Figure 29A. A base station 50 - known in various network implementations as a Radio Base Station (RBS), Base Transceiver Station (BTS), Node B (NB), enhanced Node B (eNB), Next Generation Node B (gNB), or the like - is a node of a wireless communication network that implements a Radio Access Network (RAN) in a defined geographic area called a cell, by providing radio transceivers to communicate wirelessly with a plurality of UEs 40.

[0120] The base station 50 transmits and receives RF signals on a plurality of antennas 16, 16’. In particular, the antennas 16, 16’ may comprise an advanced antenna system (AAS) that enables beamforming. As indicated by the broken line, the antennas 16, 16’ may be located remotely from the base station 50, such as on a tower or building. The RF signals are generated, and received, by a transceiver 56, which includes one or more instances of transceiver front end circuit 10 according to aspects of the present disclosure. The transceiver 56, as well as other components of the base station 50, are controlled by processing circuitry 52. Memory 54 operatively connected to the processing circuitry 52 stores instructions operative to cause the processing circuitry 52 to control the transceiver 56, including transceiver P110769WG01 front end circuit(s) 10. Although the memory 54 is depicted as being separate from the processing circuitry 52, those of skill in the art understand that the processing circuitry 52 includes internal memory, such as a cache memory or register file. Those of skill in the art additionally understand that virtualization techniques allow some functions nominally executed by the processing circuitry 52 to actually be executed by other hardware, perhaps remotely located (e.g., in the so-called “cloud”). Communication circuitry 58 provides one or more communication links to one or more other network nodes, propagating communications to and from UEs 40, from and to other network nodes or other networks, such as telephony networks or the Internet.

[0121] In all aspects, the processing circuitry 42, 52 may comprise any sequential state machine operative to execute machine instructions stored as machine-readable computer programs in memory 44, 54, such as one or more hardware-implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.), programmable logic together with appropriate firmware; one or more stored-program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above.

[0122] In all aspects, the memory 44, 54 may comprise any non-transitory machine- readable media known in the art or that may be developed, including but not limited to magnetic media (e.g., floppy disc, hard disc drive, etc.), optical media (e.g., CD-ROM, DVD-ROM, etc.), solid state media (e.g., SRAM, DRAM, DDRAM, ROM, PROM, EPROM, Flash memory, solid state disc, etc.), or the like.

[0123] In all aspects, the transceiver 46, 56 is operative to communicate with one or more other transceivers via a Radio Access Network (RAN) according to one or more communication protocols known in the art or that may be developed, such as IEEE 802. xx, CDMA, WCDMA, GSM, LTE, NR, LITRAN, WiMax, NB-loT, or the like. The transceiver 46, 56 implements transmitter and receiver functionality appropriate to the RAN links (e.g., frequency allocations and the like).

[0124] In all aspects, the communication circuitry 58 may comprise a receiver and transmitter interface used to communicate with one or more other nodes over a communication network according to one or more communication protocols known in the art or that may be developed, such as Ethernet, TCP / IP, SONET, ATM, IMS, SIP, or the like. The communication circuitry 58 implements receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components and / or software, or alternatively may be implemented separately.

[0125] Aspects of the present disclosure provide numerous advantages over the prior art, and may also provide one or more of the following technical advantage(s). In TX mode, the passive 3-point network 18, 19 is excited differentially by any RF TX signals reflected by the antenna 16, 16’. The 3-point network 18, 19 is designed to resistively terminate such reflected TX signals when it is differentially excited. Hence, the LNA 20 is protected from any transmitted P110769W001 or reflected TX signals, eliminating the need for an antenna switch. The LNA 20 is additionally protected by forming a virtual signal ground at its input. Besides eliminating the antenna switch and isolating the LNA 20, the balanced amplifier design using QHCs is known as a robust solution against high VSWR at the antenna 16, 16’, such as during beamforming. In RX mode, the output impedance of the PAs is tuned so the received signal is reflected, and excites the passive 3-point network 18, 19 in common mode. In RX mode the LNA 20 is not connected to a virtual ground, and it can thus detect the received signal. The passive 3-point network 18, 19 is designed to have very low loss when excited in common mode.

[0126] Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and / or is implied from the context in which it is used. All references to a / an / the element, apparatus, component, means, step, etc., are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and / or where it is implicit that a step must follow or precede another step. Any feature of any of the aspects disclosed herein may be applied to any other aspect, wherever appropriate. Likewise, any advantage of any of the aspects may apply to any other aspects, and vice versa. Other objectives, features and advantages of the enclosed aspects will be apparent from the description.

[0127] The term “unit” may have conventional meaning in the field of electronics, electrical devices and / or electronic devices and may include, for example, electrical and / or electronic circuitry, devices, modules, processors, memories, logic solid state and / or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and / or displaying functions, and so on, as such as those that are described herein.

[0128] As used herein, the term “configured to” means set up, organized, adapted, or arranged to operate in a particular way; the term is synonymous with “designed to,” or with respect to processing circuitry, “programmed to.”

[0129] As used herein, with respect to signals, “anti-phase” and “differential” are interchangeable, and refer to two “legs” of a same signal which are 180° apart in phase. As used herein, the term “quadrature” refers to signals which are 90° apart in phase. Differential signals or sets of anti-phase signals are in quadrature when corresponding signal legs are 90° apart in phase.

[0130] The term "directly connected" or "electrically connected" or simply “connected” describes a permanent low-ohmic connection between electrically connected elements, for example a wire connection between the concerned elements. Although such a connection may have parasitic effects, such as the parasitic inductance of a bond wire, no component or element is interposed between the connected elements. By contrast, the term "electrically coupled" or simply P110769W001

[0131] “coupled” means that one or more intervening element(s) or components, configured to influence the electrical signal in some tangible way, may be (but is not necessarily) provided between the electrically coupled elements. These intervening elements may include active elements, such as transistors or switches, as well as passive elements, such as inductors, capacitors, diodes, resistors, baluns, etc.

[0132] Some of the aspects contemplated herein are described more fully with reference to the accompanying drawings. Other aspects, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the aspects set forth herein; rather, these aspects are provided by way of example to convey the scope of the subject matter to those skilled in the art.

[0133] The present disclosure may, of course, be carried out in other ways than those specifically set forth herein without departing from essential characteristics of the disclosure. The present aspects are to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended aspects are intended to be embraced therein.

Claims

1. P110769WQ01CLAIMSClaims:

1. A Radio Frequency, RF, transceiver front end circuit (10) configured to operate alternatively in transmit, TX, mode or receive, RX, mode, characterized by: a balanced power amplifier circuit (12), comprising a plurality of power amplifiers, PA (PA1 , PA2, PA3, PA4); first and second quadrature hybrid couplers, QHC, (QHC1 , QHC2) each having in, IN, out, OUT, coupled, CPL, and isolation, ISO, ports; wherein two anti-phase outputs of a first set of PAs are independently connected to the OUT terminals of the first and second QHCs (QHC1 , QHC2); and wherein two anti-phase outputs of a second set of PAs are independently connected to the CPL terminals of the first and second QHCs (QHC1, QHC2); wherein the IN terminals of the first and second QHCs are coupled to one or more antennas (16, 16’); and a 3-port network (18, 19) having two inputs, respectively connected to the ISO terminals of the first and second QHCs (QHC1, QHC2), and an output; and a low noise amplifier, LNA, (20) having an input connected to the output of the 3-port network (18, 19).

2. The transceiver front end circuit (10) of claim 1 , wherein corresponding anti-phase inputs to the first and second sets of PAs are in a quadrature phase relationship to each other.

3. The transceiver front end circuit (10) of claim 1 or 2, further comprising an inductor connected between a power supply (VDD) and each leg of the anti-phase outputs of each of the first and second sets of PAs .

4. The transceiver front end circuit (10) of any of claims 1-3, wherein the first set of PAs comprises a first differential PA (PA1) and the second set of PAs comprises a second differential PA (PA2).

5. The transceiver front end circuit (10) of any of claims 1-3, wherein the first set of PAs comprises two single-ended PAs (PA1 , PA3) and the second set of PAs comprises two single- ended PAs (PA2, PA4).

6. The transceiver front end circuit (10) of any of claims 1-5, wherein the IN terminals of the first and second QHCs are coupled to the one or more antennas (16) through a balun (14).23P110769WQ017. The transceiver front end circuit (10) of any of claims 1-5, wherein the IN terminals of the first and second QHCs are connected directly to differential antennas (16’).

8. The transceiver front end circuit (10) of any preceding claim further comprising: a third QHC (QHC3), having a first leg of a differential RF input connected to the IN port, a first leg of the anti-phase input of the first set of PAs connected to the OUT port, a first leg of the anti-phase input of the second set of PAs connected to the CPL port, and the ISO port terminated to ground through an impedance; and a fourth QHC (QHC4), having a second leg of the differential RF input connected to the IN port, a second leg of the anti-phase input of the first set of PAs connected to the OUT port, a second leg of the anti-phase input of the second set of PAs connected to the CPL port, and the ISO port terminated to ground through an impedance.

9. The transceiver front end circuit (10) of any preceding claim, wherein in TX mode, RF signals reflected from the one or more antennas (16, 16’) are applied in differential mode to the passive 3-port network (18, 19) and are absorbed, and the passive 3-port network (18, 19) presents a virtual signal ground to the LNA (20) input; and in RX mode, RF signals received from the one or more antennas (16, 16’) are reflected by the first and second sets of PAs and applied in common mode to the passive 3-port network (18, 19), which combines the signals and outputs a combined RF signal to the LNA (20) input.

10. The transceiver front end circuit (10) of claim 9, wherein in RX mode, power to the first and second sets of PAs is interrupted, and each anti-phase output of each of the first and second sets of PAs is biased to reflect received RF signals differently.11 . The transceiver front end circuit (10) of claim 10, wherein in RX mode, each anti-phase output of each of the first and second sets of PAs is biased to reflect received RF signals wherein the received signals have substantially 180° phase difference.P110769W00112. The transceiver front end circuit (10) of claim 10 or 11 , wherein in RX mode, a transistor driving one leg of the anti-phase output of each of the first and second sets of PAs is biased to approximate an open circuit impedance and a transistor driving the other leg of the anti-phase output each of the first and second sets of PAs is biased to approximate a short circuit impedance.

13. The transceiver front end circuit of any of claims 9-12, wherein the 3-port network (18) comprises an L-match circuit comprising a capacitor connected in shunt configuration across the two inputs, and an inductor and Zo / n impedance connected in series between each input and the output, where n=1+Q2, where Q is a quality factor of the inductor.

14. The transceiver front end circuit of any of claims 9-12, wherein the 3-port network (19) comprises an L-match circuit comprising a capacitor and 2Zo impedance connected in shunt configuration across the two inputs, and an inductor connected in series between each input and the output.

15. The transceiver front end circuit (10) of any preceding claim, further comprising gainboosting capacitor connected in shunt configuration at the LNA (20) input.

16. A method (100), performed by a Radio Frequency, RF, transceiver front end circuit (10) configured to operate alternatively in transmit, TX, mode or receive, RX, mode, characterized by: in TX mode, amplifying RF signals in a balanced amplifier circuit (12) comprising first and second sets of power amplifiers, PA and first and second quadrature hybrid couplers, QHC (QHC1 , QHC2); outputting the amplified RF signals to one or more antennas (16, 16’); applying RF signals reflected from the antennas to a passive 3-port network (18, 19) in differential mode, so as to dissipate the reflected signals; and presenting a virtual signal ground at an input to a Low Noise Amplifier, LNA (20); and in RX mode, receiving RF signals from the one or more antennas (16, 16’); interrupting power to the first and second sets of PAs; biasing a transistor driving one leg of the anti-phase output of each of the first and second sets of PAs to approximate an open circuit impedance and biasing a transistor driving the other leg of the anti-phase output of eachP110769W001 of the first and second sets of PAs to approximate a short circuit impedance; applying received RF signals reflected from the first and second sets of PAs to the passive 3-port network (18, 19) in common mode, so as to combine the reflected signals; and applying the combined, reflected, received RF signals to the LNA (20).

17. A User Equipment, UE, (40) operative in a wireless communication network, characterized by: processing circuitry (42); and the transceiver front end circuit (10) of any of claims 1- 15 operatively connected to the processor circuitry (52).

18. A base station (50) operative in a wireless communication network, characterized by: processing circuitry (52); and the transceiver front end circuit (10) of any of claims 1- 15 operatively connected to the processor circuitry (52).

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