Power-electronic converter circuit having a gate driver for activating semiconductor switches of a half-bridge unit, and a control method for such a converter circuit

Abstract

The invention relates to a power electronic converter circuit (1) having a control unit (10) designed to switch the half-bridge unit (2) at specified switching times and to apply a zero voltage as the gate voltage (UGS) to the closed semiconductor switch (T1, T2) at a switching time, such that a voltage change occurs at the intermediate node when switching due to the negative gate voltage at the opened semiconductor switch (T1, T2) and energy is thereby recuperated into the storage capacitor (Cs).

Description

[0001] R. 410702

[0002] - 1 -

[0003] Description

[0004] title

[0005] Power electronic converter circuit with a gate driver for controlling semiconductor switches of a half-bridge unit, and a control method for such a converter circuit.

[0006] Technical field

[0007] The invention relates to the control of power electronic half-bridge units for converter circuits, in particular power electronic half-bridges that are operated in soft switching, i.e. in zero-voltage switching.

[0008] Technical background

[0009] Typically, the gate driver circuits of power electronic semiconductor switches in a half-bridge unit are supplied with a supply voltage capable of energizing the switches at a fluctuating potential. These supply circuits are usually either galvanically isolated DC / DC converters or so-called bootstrap circuits, which provide the gate driver's amplifier stage with a regulated voltage used to charge or discharge the gate capacitance of the corresponding semiconductor switch in the power electronic half-bridge unit. Supply circuits designed as galvanically isolated DC / DC converters or bootstrap circuits require more installation space and a higher component count for their circuit design.

[0010] For soft-switching power electronic half-bridge units that require only low gate driver power, especially when using GaN transistors or HEMTs, the effort required for R. 410702 can be reduced.

[0011] - 2 -

[0012] Supply circuits can be reduced.

[0013] The object of the present invention is to provide a gate driver circuit and a method for operating the gate driver circuit for a power electronic half-bridge unit, thereby reducing the effort required to provide the supply voltage in the gate driver circuit.

[0014] Disclosure of the invention

[0015] This problem is solved by a power electronic converter circuit with energy recuperation according to claim 1 and by the method for operating a power electronic converter circuit according to the dependent claims.

[0016] Further details are specified in the dependent claims.

[0017] According to a first aspect, a power electronic converter circuit is provided, comprising: at least one half-bridge unit having a series connection of a high-side semiconductor switch and a low-side semiconductor switch, to which a supply voltage is applied in order to switchably provide a high supply potential or a low supply potential to a load at an intermediate node, wherein the semiconductor switches are configured or shelled to carry an inverse current when a negative drain-source voltage is applied.

[0018] - a gate driver circuit for each semiconductor switch, configured to apply a positive or negative gate voltage or a zero voltage to its gate terminal, wherein the gate driver circuit is supplied with electrical energy by a storage capacitor; a control unit configured to: o switch the half-bridge unit at predetermined switching times such that the intermediate node is alternately connected to the high supply potential or the low supply potential, o starting from a switching state in which one of the R. 410702

[0019] - 3 -

[0020] When one semiconductor switch is closed and the other is open, a negative gate voltage is applied to the open semiconductor switch; at the subsequent switching time, a zero voltage is applied to the closed semiconductor switch, so that a voltage change occurs at the intermediate node during switching due to the negative gate voltage at the open semiconductor switch, thereby recuperating energy into the storage capacitor; after a predetermined time period after the last switching time or after reaching a zero voltage across the open semiconductor switch, a positive gate voltage is applied to the open semiconductor switch to be closed.

[0021] Furthermore, the gate driver circuit can be designed to cause a charging current due to the voltage transition between the gate terminal of the open semiconductor switch and the intermediate node into the gate driver circuit of the open semiconductor switch when the zero voltage is applied as the gate voltage to the closed semiconductor switch, and to use the charging current due to the negative gate voltage at the gate terminal of the open semiconductor switch to charge the storage capacitor of the gate driver circuit for the open semiconductor switch.

[0022] A half-bridge unit comprises a series connection of a high-side semiconductor switch and a low-side semiconductor switch, connected between the high and low supply potentials of a supply voltage. The supply voltage can be in the low-voltage range of a few tens to a few hundred volts or in the medium-voltage range of several hundred to several thousand volts. The intermediate node is connected to the load. The semiconductor switches can include at least one MOSFET, IGBT, IGCT, SiC / GaN FET, HEMT, CAVET (current aperture vertical electron transistor), or the like. Depending on their design, the semiconductor switches have an extrinsic freewheeling diode, an intrinsic freewheeling diode, or an intrinsic reverse current path (HEMTs), making it possible to implement an inverse R. 410702

[0023] - 4 -

[0024] To absorb load current at the intermediate node.

[0025] Furthermore, the gate driver circuit can include a full bridge circuit, which is supplied by the storage capacitor and whose intermediate nodes contain the respective gate voltage. The semiconductor switches are controlled via their gate terminals by a gate driver circuit. Each gate driver circuit can include a full bridge circuit to drive a semiconductor switch in a power electronic half-bridge unit with suitable control voltages (i.e., positive and negative control voltages or a zero voltage, e.g., relative to the low supply potential) via its gate terminals. The driver circuit described above is designed to supply the full bridge circuit with energy recovered during the charging process when the respective semiconductor switch of the power electronic half-bridge unit is switched off.

[0026] The method utilizes the application of a negative gate voltage to the open power electronic semiconductor switch to charge the gate capacitance accordingly, while the other power electronic semiconductor switch, which is to be switched off, causes a voltage transition that initiates a gate current in the switched-off power electronic semiconductor switch via capacitive coupling. The switching operations of the power electronic half-bridge circuit are briefly outlined below. As is typical for half-bridge units, the semiconductor switches are regularly and / or alternately opened and closed at predetermined switching times by applying a corresponding voltage potential to their gate terminals. A dead time may be incorporated if necessary, i.e.,A time interval between the opening of the previously closed semiconductor switch at the corresponding switching time and the closing of the corresponding other semiconductor switch. The switching cycle frequency can, for example, be between 50 kHz and 500 kHz, meaning the duration of a half-cycle is then between 1 and 10 ps.

[0027] The initial state is assumed to be that of a state in which the power electronic high-side semiconductor switch of the half-bridge unit is open and therefore sensitized with a negative gate voltage. At the gate terminal of the then closed power electronic R. 410702

[0028] - 5 -

[0029] A positive gate voltage is applied to the low-side semiconductor switch.

[0030] The gate voltage at the gate terminal of the low-side semiconductor switch is switched to zero. This causes the half-bridge unit to switch, as it opens the low-side semiconductor switch, and the opening of the low-side semiconductor switch increases the potential at the intermediate node. This potential increase at the intermediate node occurs while the high-side semiconductor switch remains closed. During the switching process, the parasitic capacitance of the semiconductor switch is first discharged. Only when the freewheeling diode is negatively biased does the existing (usually inductance-related) reverse current flow through the load connected to the intermediate node cause a current to flow through the freewheeling diode (in the case of MOSFETs, IGBTs, IGCTs, or similar devices) or through a reverse current path (in the case of HEMTs) of the high-side semiconductor switch. This reduces the voltage across the high-side semiconductor switch.

[0031] The direction of the load current is such that the switching process causes a voltage transition between the power electronic high-side semiconductor switch and the power electronic low-side semiconductor switch, while both semiconductor switches are briefly open. The voltage gradient is high and leads to the coupling of a transient positive gate current at the high-side semiconductor switch, which, due to the applied negative gate voltage, transfers energy into the gate driver circuit of the high-side semiconductor switch.

[0032] At a subsequent time, particularly after a period of 5 to 20 ns, or after completion of the voltage transition, a positive gate voltage is applied to the gate terminal of the high-side semiconductor switch, causing a voltage transition from the previously negative gate voltage to a positive gate voltage. This recharges the gate capacitance of the high-side semiconductor switch. The energy required for recharging the gate capacitance is drawn from the gate driver circuit. The high-side semiconductor switch closes, thereby achieving so-called zero-voltage switching, since essentially zero voltage is present at the high-side semiconductor switch. R. 410702

[0033] - 6 -

[0034] Subsequently, after a further period of 5–20 ns, a negative gate voltage is applied to the gate terminal of the low-side semiconductor switch to prepare for energy recuperation, and the gate capacitance of the low-side semiconductor switch is recharged accordingly. The energy required for this is taken from the gate driver circuit. This serves to prepare the energy recuperation for the low-side semiconductor switch.

[0035] At the end of the half-cycle, the gate voltage of the high-side semiconductor switch is set to zero, thus opening it. To switch the low-side semiconductor switch on / off, a so-called zero-voltage switching, i.e., soft switching, is implemented, allowing the closing of the low-side semiconductor switch to be delayed. This means the low-side semiconductor switch only closes when the voltage across it has essentially reached zero.

[0036] The load current is directed such that a voltage transition occurs between the power electronic low-side semiconductor switch and the power electronic high-side semiconductor switch. This transition is caused by the current through the freewheeling diode of the low-side semiconductor switch. The voltage gradient is high and leads to the coupling of a transient positive gate current at the low-side semiconductor switch. Due to the applied negative gate voltage, this current transfers energy into the gate driver circuit of the low-side semiconductor switch.

[0037] At a subsequent time, particularly after a period of 5 to 20 ns, or after completion of the voltage transition, a positive gate voltage is applied to the gate terminal of the low-side semiconductor switch, causing a voltage transition from a negative gate voltage to a positive gate voltage. This recharges the gate capacitance of the low-side semiconductor switch. The energy required for recharging the gate capacitance is drawn from the gate driver circuit. The low-side semiconductor switch closes, thereby achieving so-called zero-voltage switching, since essentially zero voltage is present at the low-side semiconductor switch. R. 410702

[0038] - 7 -

[0039] Subsequently, after a further period of 5–20 ns, a negative gate voltage is applied to the gate terminal of the high-side semiconductor switch to prepare for energy recuperation, and the gate capacitance of the high-side semiconductor switch is recharged accordingly. The energy required for this is taken from the gate driver circuit. This serves to prepare the energy recuperation for the high-side semiconductor switch.

[0040] The low-side semiconductor switch, which is closed, is then switched off by reducing its gate voltage to zero.

[0041] The direction of the load current is such that a voltage transition occurs between the high-side semiconductor switch and the low-side semiconductor switch.

[0042] The method described above makes it possible to extract energy from the crosstalk voltage edge for driving the gate terminals of the semiconductor switches and, in addition, to gain the energy to supply the standby losses of the gate driver unit.

[0043] To apply positive, negative, and zero voltages to the gate terminals of semiconductor switches, full bridge circuits are suitable as gate driver circuits. These are powered by a recuperative energy storage device in the form of a storage capacitor, which can temporarily store the recuperated energy. The corresponding gate voltage is then generated by the corresponding switching states of the four semiconductor switches of the full bridge circuit in a manner known per se. A control unit applies the corresponding switching states of the full bridge circuit appropriately.

[0044] The control unit may be designed to regulate the voltage in the storage capacitor to a predetermined target voltage. For example, switching to the negative bias voltage can be omitted for one or more cycles to prevent recuperation. This means that energy recuperation must be designed so that sufficient energy is recuperated in the storage capacitor at all operating points of the power electronic converter. This is generally easier to achieve with semiconductor switches with very low gate resistance. 410702

[0045] - 8 -

[0046] Power supply provided, for example, by GaN FETs, HEMTs and the like.

[0047] The amount of energy recovery can be adjusted by increasing the capacitance between the drain and gate terminals of the power semiconductor switch. A higher drain-gate capacitance leads to increased energy recovery. However, since the increased drain-gate capacitance also increases the switching losses of the switch, the benefit of increasing the drain-gate capacitance is limited.

[0048] It may be provided that a Zener diode can be arranged in parallel to the storage capacitor in order to limit the voltage in the storage capacitor.

[0049] To reduce slight overvoltages in the storage capacity, a circuit device can be provided, such as a Zener diode connected in parallel to the storage capacity, which dissipates the excess energy.

[0050] Furthermore, a start circuit can be provided to initially charge the storage capacity of the gate driver circuit. This can be achieved using a switchable charging resistor or a small inductive or capacitive high-frequency coupler with a rectifier diode.

[0051] In alternative embodiments, the gate driver circuit can be designed to operate the half-bridge unit in hard-switching mode. Since in this case the Miller capacitance, i.e., the drain-gate capacitance, must be recharged with increased gate driver power, more energy is required for the switching process, thus necessitating a greater amount of energy recuperation.

[0052] According to another aspect, a method for operating a power electronic converter circuit is provided, comprising: at least one half-bridge unit having a series connection of a high-side semiconductor switch and a low-side semiconductor switch, to which a supply voltage is applied in order to provide a load at an intermediate node with a high supply potential or a low R. 410702

[0053] - 9 -

[0054] to provide switchable supply potential, wherein the semiconductor switches are designed or shelled to conduct an inverse current when a negative drain-source voltage is applied,

[0055] - a gate driver circuit for each semiconductor switch, configured to apply a positive or negative gate voltage or a zero voltage to its gate terminal, wherein the gate driver circuit is supplied with electrical energy by a storage capacitor; wherein the method comprises the following steps:

[0056] The half-bridge unit is switched at predetermined switching times such that the intermediate node is alternately connected to the high supply potential or the low supply potential, starting from a switching state in which one of the semiconductor switches is closed and the other is open. A negative gate voltage is applied to the open semiconductor switch. At the subsequent switching time, a zero voltage (the gate voltage) is applied to the closed semiconductor switch, so that a voltage change occurs at the intermediate node during switching due to the negative gate voltage at the open semiconductor switch, thereby recuperating energy into the storage capacitor.After a predetermined time period following the last switching point or after reaching zero voltage across the open semiconductor switch, a positive gate voltage is applied to the semiconductor switch to be closed.

[0057] Brief description of the drawings

[0058] The embodiments are explained in more detail below with reference to the accompanying drawings. These show:

[0059] Figure 1 shows a schematic representation of a power electronic device

[0060] Converters with an example of a half-bridge unit;

[0061] Figure 2 shows a schematic representation of a gate driver circuit for controlling each of the semiconductor switches of the R. 410702.

[0062] - 10 -

[0063] Half-bridge unit of Figure 1; and

[0064] Figure 3 shows a flowchart for controlling the gate driver circuit;

[0065] Figure 4 shows a voltage / current-time diagram of the drain-source

[0066] Voltages of the semiconductor switches, gate voltages and gate currents, as well as the energies stored in the storage capacitors of the gate driver circuits.

[0067] Description of embodiments

[0068] Figure 1 shows a schematic representation of a power electronic converter (converter circuit) 1 with a power electronic half-bridge unit 2. The converter 1 can also be configured with several half-bridge units 2, which can be operated in the manner described below. The half-bridge units 2 are supplied by a supply voltage U. ve The supply voltage is provided by a voltage that is provided between a high and a low supply potential. The supply voltage can be up to several hundred volts, e.g., between 100 and 900 volts.

[0069] The power electronic half-bridge unit 2 comprises a series connection of a first high-side semiconductor switch Ti and a low-side semiconductor switch T2, which are electrically connected to each other via an intermediate node Z. The semiconductor switches can be designed as power electronic semiconductor switches, such as MOSFETs, IGBTs, IGCTs, SiC / GaN FETs, HEMTs, or the like, and each has a gate terminal G, a drain terminal D, and a source terminal S. The semiconductor switches Ti and T2 each have an extrinsic or an intrinsic freewheeling diode or a reverse current path at a negative drain-source voltage.

[0070] An inductive load, represented by L and Ile, is connected to an intermediate node Z between the series connection of the semiconductor switches and the low supply potential. The load path generally exhibits inductive behavior, so that when the half-bridge unit is switched off, an RDS(on) of 410702 is generated.

[0071] - 11 -

[0072] forms a freewheeling current through one of the freewheeling diodes or a reverse current path through one of the semiconductor switches.

[0073] Parasitic capacitances CDS (between drain and source terminals), CM (between gate and drain terminals), and CGS (between gate and source terminals) are present between the terminals of the semiconductor switches Ti and T2. The gate terminals G are driven by a low-impedance gate resistor. Furthermore, the semiconductor switches Ti and T2 exhibit low gate-source capacitance, enabling switching with low energy consumption.

[0074] The gate terminals G of the semiconductor switches Ti, T2 are each connected to a gate driver circuit 3. The circuit of the gate driver circuit 3 is shown and configured in Figure 2 to supply the necessary voltage and energy for switching the corresponding semiconductor switch Ti, T2 on and off, and to store the energy recovered by the switching operations in a storage capacitor.

[0075] Gate driver circuit 3 features a full bridge circuit consisting of two MOSFETs S1, S2 and S3, S4 connected in series. The intermediate nodes between S1 and S2 and between S3 and S4 of the series connections represent the output of the full bridge circuit and are applied as a gate voltage UGS, i.e., as a gate-source voltage, to the respective semiconductor switches Ti, T2. The full bridge circuit is powered by a storage capacitor Cs.

[0076] The gate driver circuits 3 are controlled by a control unit 10 to specify the switching of the MOSFETs. The control is performed to provide a positive gate voltage, a zero voltage, and a negative gate voltage according to the control procedure described below.

[0077] The gate driver circuit 3 can be controlled according to the following circuit diagram: R. 410702

[0078] - 12 -

[0079] Figure 3 shows a flowchart for the control of the gate driver circuits 3 by the control unit 10. In conjunction with the signal-time diagram in Figure 4, the operation of the power electronic converter 1 is described in more detail. The signal-time diagram in Figure 4 shows the course of the switching voltages, i.e., the drain-source voltages of the semiconductor switches Ti and T2, the gate voltages UGS(TI) and UGS(T2) of the semiconductor switches Ti and T2, as well as their gate currents ics(Ti) and ics(T2), and the negatively balanced energy E. ga t e , which can be recuperated from the respective gate connection G.

[0080] The initial state is assumed to be one in which the power electronic high-side semiconductor switch Ti of the half-bridge unit 2 is open and sensitized with a negative gate voltage -Ud. A positive gate voltage is applied to the gate terminal G of the then closed power electronic low-side semiconductor switch T2.

[0081] In step S11, at time TA, the gate voltage UGS at the gate terminal G of the low-side semiconductor switch T2 is switched to zero. This causes the half-bridge unit 2 to switch, as it opens the low-side semiconductor switch T2, and the opening of the low-side semiconductor switch increases the potential at the intermediate node Z. This increase in potential at the intermediate node Z occurs while the high-side semiconductor switch Ti remains closed, because the existing (usually inductance-related) reverse current flow through the load L connected to the intermediate node Z now flows through a freewheeling diode (in the case of MOSFETs, IGBTs, IGCTs, or similar devices) / reverse current path (in the case of HEMTs) of the high-side semiconductor switch Ti. This reduces the voltage across the high-side semiconductor switch Ti.

[0082] The direction of the load current is therefore directional, so that the switching process results in a voltage transition between the power electronic high-side semiconductor switch Ti and the power electronic low-side semiconductor switch T2 while both semiconductor switches Ti and T2 are open. R. 410702

[0083] - 13 -

[0084] This causes a freewheeling current (inverse current direction) to flow through the high-side semiconductor switch Ti. The voltage gradient is high and leads to the coupling of a transient positive gate current at the high-side semiconductor switch Ti, as the drain-gate capacitance, i.e., the Miller capacitance CM, is discharged. The resulting gate current iß is stored as energy E due to the applied negative gate voltage. ga t e transferred to the gate driver circuit 3 of the high-side semiconductor switch Ti.

[0085] In step S12, at a subsequent time TB, specifically after a time interval of between 5 and 20 ns, or after completion of the voltage transition, a positive gate voltage is applied to the gate terminal (G) of the high-side semiconductor switch Ti (i.e., after a dead time for zero-voltage switching), causing a voltage transition from the negative gate voltage to a positive gate voltage. This charges the gate capacitance CGS of the high-side semiconductor switch Ti. The energy required for charging the gate capacitance CGS is drawn from the gate driver circuit 3. The high-side semiconductor switch Ti closes, thereby realizing so-called zero-voltage switching (soft switching), since essentially zero voltage is present at the high-side semiconductor switch Ti at this time.

[0086] Subsequently, in step S13, at a time Tc, specifically after a further 5-20 ns, a negative gate voltage is applied to the gate terminal of the low-side semiconductor switch T2 to prepare for energy recuperation, and the gate capacitance of the low-side semiconductor switch is recharged accordingly. The energy required for this is taken from the gate driver circuit 3. This serves to prepare the energy recuperation for the low-side semiconductor switch T2.

[0087] At the end of the half-cycle, in step S14 at time TA*, the gate voltage of the high-side semiconductor switch Ti is set to zero, thereby opening it. To turn on the low-side semiconductor switch T2, a so-called zero-voltage switching, i.e., soft switching, is implemented. This means that the low-side semiconductor switch is only closed when the voltage across the low-side semiconductor switch T2 has reached virtually zero. R. 410702

[0088] - 14 -

[0089] The load current is directed such that a voltage transition occurs between the power electronic high-side semiconductor switch Ti and the power electronic low-side semiconductor switch T2. This transition is caused by the current through the freewheeling diode of the low-side semiconductor switch T2. The voltage gradient is high and leads to the coupling of a transient positive gate current at the low-side semiconductor switch T2, as the drain-gate capacitance, i.e., the Miller capacitance, is discharged. Due to the applied negative gate voltage, the resulting gate current is transferred as energy Egate into the gate driver circuit of the low-side semiconductor switch T2.

[0090] In step S15, at a subsequent time TB*, specifically after a time interval of between 5 and 20 ns, or after completion of the voltage transition, a positive gate voltage is applied to the gate terminal of the low-side semiconductor switch T2, causing a voltage transition from a negative gate voltage to a positive gate voltage. This charges the gate capacitance CGS of the low-side semiconductor switch T2. The energy required for charging the gate capacitance is drawn from the gate driver circuit 3. The low-side semiconductor switch T2 closes, thereby achieving so-called zero-voltage switching, since essentially zero voltage is present at the low-side semiconductor switch T2.

[0091] Subsequently, in step S16, at a time Tc*, specifically after a further 5-20 ns, a negative gate voltage is applied to the gate terminal G of the high-side semiconductor switch Ti to prepare for energy recuperation, and the gate capacitance of the high-side semiconductor switch Ti is recharged accordingly. The energy required for this is taken from the gate driver circuit 3. This serves to prepare the energy recuperation for the high-side semiconductor switch Ti.

[0092] Then, returning to step S11, the low-side semiconductor switch, which is closed, is switched off by reducing its gate voltage to zero. The load current is directed such that a voltage transition occurs between the high-side semiconductor switch Ti and R. 410702

[0093] - 15 - the low-side semiconductor switch T2 is coming.

[0094] To prevent overvoltages at the storage capacitor, a parallel Zener diode (not shown) can be provided to dissipate excess energy from recuperation.

[0095] Furthermore, a start circuit (not shown) may be provided which uses the storage capacitor C s The gate driver circuits 3 are initially charged. This can be achieved, for example, with a charging resistor dedicated solely to the charging process. Alternatively, the startup circuit can also be an inductive or capacitive high-frequency coupler with a rectifier diode.

Claims

R. 410702 - 16 - Claims 1. Power electronic converter circuit (1) comprising: at least one half-bridge unit (2) having a series connection of a high-side semiconductor switch (Ti) and a low-side semiconductor switch (T2) and to which a supply voltage (U) is applied. ve rs) is applied to provide a high supply potential or a low supply potential to a load (L, Ue) at an intermediate node (Z) in a switchable manner, wherein the semiconductor switches (Ti, T2) are configured or wired to carry an inverse current when a negative drain-source voltage (UDS) is applied, - each a gate driver circuit (3) for each semiconductor switch (Ti, T2), configured to apply a positive or negative gate voltage (UGS) or a zero voltage to its gate terminal (G), wherein the gate driver circuit (3) is connected by a storage capacitor (C s) is supplied with electrical energy; a control unit (10) configured to: o switch the half-bridge unit (2) at predetermined switching times such that the intermediate node (Z) is alternately connected to the high supply potential or the low supply potential; o apply a negative gate voltage to the open semiconductor switch (Ti, T2) starting from a switching state in which one of the semiconductor switches (Ti, T2) is closed and the other is open; o apply a zero voltage as the gate voltage (UGS) to the closed semiconductor switch (Ti, T2) at the subsequent switching time, so that a voltage change at the intermediate node occurs during a switching due to the negative gate voltage at the open semiconductor switch (Ti, T2), thereby storing energy in the storage capacitor (C). s ) is recuperated; R. 410702 - 17 - o to apply a positive gate voltage to the semiconductor switch (Ti , T2) to be closed after a predetermined time period after the last switching time or after reaching a zero voltage across the open semiconductor switch (Ti, T2).

2. Converter circuit (1) according to claim 1, wherein the gate driver circuit (3) is configured to cause a charging current to flow into the gate driver circuit (3) of the open semiconductor switch (Ti, T2) when the zero voltage is applied as the gate voltage (UGS) to the closed semiconductor switch (Ti, T2) due to the voltage transition between the gate terminal (G) of the open semiconductor switch (Ti, T2) and the intermediate node (Z), and to charge the storage capacitor (C) due to the negative gate voltage at the gate terminal (G) of the open semiconductor switch (Ti, T2). s) the gate driver circuit (3) for the open semiconductor switch (Ti, T2).

3. Converter circuit (1) according to claim 1 or 2, wherein the semiconductor switches comprise at least one MOSFET, IGBT, IGCT, SiC / GaN-FET, CAVET or HEMT.

4. Converter circuit (1) according to one of claims 1 to 3, wherein the gate driver circuit (3) has a full bridge circuit which is supplied by the storage capacitor (Cs) and at whose intermediate node (Z) the respective gate voltage is applied.

5. Converter circuit (1) according to one of claims 1 to 4, wherein the control unit (10) is configured to control the voltage (Ud) in the storage capacitor (C). s ) to regulate to a predetermined target voltage, in particular by not applying the negative gate voltage for one or more cycles.

6. Converter circuit (1) according to one of claims 1 to 5, wherein in parallel to the storage capacitor (C) s) a Zener diode may be arranged to regulate the voltage in the storage capacitor (C s to limit it.

7. Converter circuit (1) according to one of claims 1 to 6, wherein a start circuit is provided to activate the storage capacitor (C s ) the gate- R. 410702 - 18 - To initially charge the driver circuit (3).

8. Method for operating a power electronic converter circuit (1), comprising: at least one half-bridge unit (2) having a series connection of a high-side semiconductor switch (Ti) and a low-side semiconductor switch (T2) and to which a supply voltage (U) is applied. vers) is applied to provide a high supply potential or a low supply potential to a load (L,Ue) at an intermediate node (Z) in a switchable manner, wherein the semiconductor switches (Ti, T2) are configured or wired to carry an inverse current when a negative drain-source voltage (UDS) is applied, - each a gate driver circuit (3) for each semiconductor switch (Ti, T2), configured to apply a positive or negative gate voltage (UGS) or a zero voltage to its gate terminal (G), wherein the gate driver circuit (3) is connected by a storage capacitor (C s ) is supplied with electrical energy; the method comprising the following steps: The half-bridge unit (2) is switched at predetermined switching times such that the intermediate node (Z) is alternately connected to the high supply potential or the low supply potential, starting from a switching state in which one of the semiconductor switches (Ti, T2) is closed and the other is open. A negative gate voltage is applied to the open semiconductor switch (Ti, T2). At the subsequent switching time, a zero voltage (UGS) is applied to the closed semiconductor switch (Ti, T2), so that a voltage change occurs at the intermediate node during switching due to the negative gate voltage at the open semiconductor switch (Ti, T2), thereby storing energy in the storage capacitor (C). s) is recuperated; after a predetermined time period after the last switching time or after reaching zero voltage across the open semiconductor switch (Ti, T2), a positive gate voltage is applied to the semiconductor switch (Ti, T2) to be closed.

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