Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device that has a transistor with little variation in electrical characteristics. This semiconductor device includes a transistor, and first and second insulating layers. The transistor includes first to third conductive layers, a semiconductor layer, and a third insulating layer. The first insulating layer overlaps with the first conductive layer and is located on the first conductive layer, the second conductive layer is located on the first insulating layer, ends of the first insulating layer and the second conductive layer coincide or substantially coincide, the second insulating layer is in contact with each of an upper surface and a side surface of the first conductive layer, a side surface of the first insulating layer, and an upper surface and a side surface of the second conductive layer, the second insulating layer has a first opening overlapping with each of the first conductive layer and the second conductive layer, the semiconductor layer overlaps with the first opening and is located on the second insulating layer, and is in contact with, in the first opening, each of the upper surface of the first conductive layer, the side surface of the first insulating layer, and the upper surface and the side surface of the second conductive layer, the third insulating layer is located on the semiconductor layer, and the third conductive layer overlaps with the semiconductor layer and is located on the third insulating layer.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a semiconductor device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices having the same, methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] Semiconductor devices containing transistors are widely used in electronic devices. For example, in display devices, reducing the area occupied by transistors can reduce the pixel size and improve resolution. Therefore, there is a demand for miniaturized transistors.

[0005] As devices requiring high-definition display capabilities, for example, devices for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR) are being actively developed.

[0006] As display devices, for example, light-emitting devices having organic EL (Electroluminescence) elements or light-emitting diodes (LEDs) have been developed.

[0007] Patent Document 1 discloses a high-definition display device using an organic EL element.

[0008] International Publication No. 2016 / 038508

[0009] Takashi Koida, "High-Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology (AIST), AIST Photovoltaic Power Generation Research Results Presentation 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] To further increase the resolution of display devices, further miniaturization of the semiconductor devices they contain is required. However, the more miniaturization is pursued for the transistors in the semiconductor devices, the more difficult it becomes to ensure good electrical characteristics, maintain processing accuracy, and reduce variations in electrical characteristics between transistors.

[0011] One aspect of the present invention aims to provide a semiconductor device having a transistor of a very small size and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a short channel length and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a large on-current and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with good electrical characteristics and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with small variations in electrical characteristics between transistors and a method for manufacturing the same.

[0012] Alternatively, one aspect of the present invention aims to provide a semiconductor device that operates at high speed and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device that occupies a small area and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device or display device with low power consumption and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a high-definition display device. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a semiconductor device or display device with high productivity. Alternatively, one aspect of the present invention aims to provide a novel transistor, semiconductor device, display device, or a method for manufacturing the same.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0014] One aspect of the present invention comprises a transistor, a first insulating layer, and a second insulating layer, wherein the transistor comprises a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer, the first insulating layer being located on the first conductive layer such that it overlaps with the first conductive layer, the second conductive layer being located on the first insulating layer, the second insulating layer being located on the first conductive layer, the first insulating layer and the second conductive layer, and the upper and side surfaces of the first conductive layer, the side surfaces of the first insulating layer and the second conductive layer The semiconductor device is configured such that the second insulating layer is in contact with the upper and side surfaces of the first conductive layer, has a first opening that overlaps with the first conductive layer and the second conductive layer, and the semiconductor layer is located on the second insulating layer such that it has a region that overlaps with the first opening, and the third insulating layer is located on the semiconductor layer, in contact with the upper surface of the first conductive layer, the side surfaces of the first insulating layer, and the upper and side surfaces of the second conductive layer within the first opening, and the third insulating layer is located on the third insulating layer such that it has a region that overlaps with the semiconductor layer.

[0015] Furthermore, in the above, the semiconductor layer is preferably an oxide semiconductor layer having indium, the first insulating layer has a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer, the fourth insulating layer and the sixth insulating layer each have silicon and nitrogen, the fifth insulating layer has silicon and oxygen, and the second insulating layer is preferably one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0016] Furthermore, in the above, it is preferable that a seventh insulating layer is provided between the second insulating layer and the semiconductor layer, the seventh insulating layer is in contact with the upper surface of the second insulating layer and has a second opening in a region that overlaps with the first opening, the semiconductor layer is in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the upper surface and side surface of the second conductive layer, respectively, inside the first and second openings, and is in contact with the upper surface of the seventh insulating layer outside the first and second openings, and the seventh insulating layer is preferably made of silicon and oxygen.

[0017] Furthermore, in the above, it is preferable that the edges of the semiconductor layer and the insulating layer 7 coincide or substantially coincide when viewed in plan.

[0018] Furthermore, in the above, it is preferable that an eighth insulating layer is located below the first conductive layer, the upper surface of the eighth insulating layer is in contact with the first conductive layer, and the eighth insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0019] Furthermore, in the above, it is preferable that the first insulating layer is provided in an island shape, and that the ends of the first insulating layer and the second conductive layer coincide or substantially coincide in a plan view.

[0020] Furthermore, in the above, it is preferable that the first insulating layer is divided by a slit reaching the first conductive layer, and that the second insulating layer, semiconductor layer, third insulating layer, and third conductive layer are stacked in this order on a pair of sides facing each other across the slit.

[0021] Furthermore, in the above, it is preferable that the first insulating layer and the second conductive layer have a third opening that reaches the first conductive layer, and that within the third opening, there is a region on the side surface of the first insulating layer in which the second insulating layer, the semiconductor layer, the third insulating layer, and the third conductive layer are stacked in this order.

[0022] Furthermore, in the above, it is preferable that the semiconductor layer has a configuration that is enclosed within the first opening in a plan view.

[0023] Furthermore, in the above, the first opening and the semiconductor layer each have a region that overlaps with the first corner of the first insulating layer and the second conductive layer in a plan view, and it is preferable that the first corner is a corner whose interior angle in a plan view is greater than 0 degrees and less than 180 degrees.

[0024] Furthermore, in the above, the first opening and the semiconductor layer each have a region that overlaps with the second corner of the first insulating layer and the second conductive layer in a plan view, and it is preferable that the second corner is a corner whose interior angle in a plan view is greater than 180 degrees and less than 360 degrees.

[0025] Furthermore, in one aspect of the present invention, a first conductive layer is formed, a first insulating film and a first conductive film are deposited on the first conductive layer in that order, the first conductive film and the first insulating film are processed to have a region that overlaps with the first conductive layer to form a second conductive layer and a first insulating layer, respectively, a second insulating film and a third insulating film are deposited in that order in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the upper surface of the second conductive layer, a portion of the second insulating film and the third insulating film is removed to form an opening that overlaps with the first conductive layer and the second conductive layer, respectively, and This is a method for manufacturing a semiconductor device, comprising: forming a second insulating layer and a third insulating layer, respectively; depositing a metal oxide film in contact with the upper surface of the third insulating layer, the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the upper surface of the second conductive layer; processing the metal oxide film and the third insulating layer so that they have a region overlapping with the opening and so that their respective edges coincide or substantially coincide in a plan view, thereby forming a semiconductor layer and a fourth insulating layer, respectively; depositing a fifth insulating layer on the semiconductor layer; and forming a third conductive layer on the fifth insulating layer so that it has a region overlapping with the semiconductor layer.

[0026] According to one aspect of the present invention, a semiconductor device having a small-sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a short channel length and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a large on-current and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with high field-effect mobility and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with small variations in electrical characteristics between transistors and a method for manufacturing the same can be provided.

[0027] Alternatively, according to one aspect of the present invention, a high-speed semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with a small footprint and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device or display device with low power consumption and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a high-definition display device can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a semiconductor device or display device with high productivity can be provided. Alternatively, according to one aspect of the present invention, a novel transistor, semiconductor device, display device, or a method for manufacturing the same can be provided.

[0028] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0029] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figures 2A and 2B are perspective views showing an example of a semiconductor device. Figure 3 is a perspective view showing an example of a semiconductor device. Figures 4A and 4B are cross-sectional views showing an example of a semiconductor device. Figure 5A is a cross-sectional view showing an example of a semiconductor device. Figure 5B is a plan view showing an example of a semiconductor device. Figure 6A is a plan view showing an example of a semiconductor device. Figures 6B and 6C are cross-sectional views showing an example of a semiconductor device. Figures 7A and 7B are perspective views showing an example of a semiconductor device. Figure 8 is a perspective view showing an example of a semiconductor device. Figure 9A is a plan view showing an example of a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device. Figures 10A and 10B are perspective views showing an example of a semiconductor device. Figure 11 is a perspective view showing an example of a semiconductor device. Figure 12A is a plan view showing an example of a semiconductor device. Figures 12B and 12C are cross-sectional views showing an example of a semiconductor device. Figures 13A and 13B are perspective views showing an example of a semiconductor device. Figure 14 is a perspective view showing an example of a semiconductor device. Figure 15A is a plan view showing an example of a semiconductor device. Figures 15B and 15C are cross-sectional views showing an example of a semiconductor device. Figure 16A is a plan view showing an example of a semiconductor device. Figures 16B and 16C are cross-sectional views showing an example of a semiconductor device. Figure 17A is a plan view showing an example of a semiconductor device. Figures 17B and 17C are cross-sectional views showing an example of a semiconductor device. Figure 18A is a plan view showing an example of a semiconductor device. Figures 18B and 18C are cross-sectional views showing an example of a semiconductor device. Figure 19A is a plan view showing an example of a semiconductor device. Figures 19B and 19C are cross-sectional views showing an example of a semiconductor device. Figure 20A is a plan view showing an example of a semiconductor device. Figures 20B and 20C are cross-sectional views showing an example of a semiconductor device. Figure 21A is a plan view showing an example of a semiconductor device. Figures 21B and 21C are cross-sectional views showing an example of a semiconductor device. Figures 22A and 22B illustrate the carrier concentration dependence of hole mobility. Figure 22C is a cross-sectional view illustrating an indium oxide film.Figures 23A, 23B, 23C, 23D, and 23E are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 24A, 24B, 24C, and 24D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 25A, 25B, 25C, and 25D are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 26A and 26B are perspective views showing an example of a semiconductor device manufacturing method. Figures 27A and 27B are perspective views showing an example of a semiconductor device manufacturing method. Figures 28A and 28B are perspective views showing an example of a semiconductor device manufacturing method. Figures 29A and 29B are perspective views showing an example of a semiconductor device manufacturing method. Figure 30 is a perspective view showing an example of a display device. Figures 31A and 31B are cross-sectional views showing an example of a display device. Figure 32 is a cross-sectional view showing an example of a display device. Figures 33A, 33B, and 33C are cross-sectional views showing an example of a display device. Figures 34A and 34B are cross-sectional views showing an example of a display device. Figure 35 is a cross-sectional view showing an example of a display device. Figures 36A, 36B, and 36C are cross-sectional views showing an example of a display device. Figure 37 is a cross-sectional view showing an example of a display device. Figures 38A and 38B are cross-sectional views showing an example of a display device. Figures 39A, 39B, 39C, and 39D show an example of an electronic device. Figures 40A, 40B, 40C, 40D, 40E, and 40F show an example of an electronic device. Figures 41A, 41B, 41C, 41D, 41E, 41F, and 41G show an example of an electronic device.

[0030] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0031] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0032] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0033] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Also, the ordinal numbers attached to components in one part of this specification may not be the same as the ordinal numbers attached to those components in other parts of this specification or in the claims.

[0034] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0035] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0036] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, etc., depending on the situation.

[0037] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0038] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0039] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0040] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0041] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0042] In this specification, unless otherwise specified, on-current refers to the drain current (also written as Id) when the transistor is in the ON state (also called the conducting state). Unless otherwise specified, the ON state refers to the state in an n-channel transistor where the voltage between the gate and source (also written as Vg or Vgs) is equal to or greater than the threshold voltage (also written as Vth), and to the state in a p-channel transistor where it is less than or equal to the threshold voltage.

[0043] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0044] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0045] In this specification, the top surface shape of a component refers to the contour shape of the component in a plan view (also called a top view). A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0046] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlaps between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case too, it may be said that "matching or roughly matching top shapes." Furthermore, when the top shapes match or roughly match, it may also be said that "the edges match or roughly match," or "the edges are aligned or roughly aligned."

[0047] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes called the taper angle.

[0048] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask, high-resolution metal mask) may be referred to as MM (metal mask) structured devices. Furthermore, in this specification, devices manufactured without using a metal mask or FMM may be referred to as MML (metal maskless) structured devices. Since MML structured devices can be manufactured without using a metal mask, they can exceed the upper limit of resolution imposed by the alignment accuracy of the metal mask. Additionally, MML structured devices eliminate the need for metal mask manufacturing equipment and metal mask cleaning processes. Moreover, because MML structured devices can be manufactured at a lower cost, they are suitable for mass production.

[0049] In this specification, a structure in which different light-emitting layers are created using light-emitting elements (also called light-emitting devices) with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0050] In this specification, holes or electrons may be referred to as "carriers." Specifically, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." It should be noted that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of these layers.

[0051] In this specification, a light-emitting element has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. Examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier blocking layer (hole blocking layer and electron blocking layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the pair of electrodes may be referred to as a pixel electrode and the other as a common electrode.

[0052] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0053] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated.

[0054] In this specification, the sacrificial layer (which may also be called the mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers constituting the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.

[0055] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 21C.

[0056] One aspect of the present invention is a semiconductor device having a transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0057] A transistor according to one aspect of the present invention includes a first conductive layer on a first insulating layer, a second conductive layer, a third conductive layer, an oxide semiconductor layer, and a fifth insulating layer.

[0058] The first conductive layer functions as either the source electrode or the drain electrode of the transistor. The second conductive layer functions as the other source electrode or drain electrode of the transistor. The third conductive layer functions as the gate electrode of the transistor. The fifth insulating layer functions as the gate insulating layer of the transistor. The region of the oxide semiconductor layer in contact with the first conductive layer functions as either the source region or the drain region of the transistor. The region of the oxide semiconductor layer in contact with the second conductive layer functions as the other source region or drain region of the transistor. In the oxide semiconductor layer, the channel formation region of the transistor is located between the source region and the drain region.

[0059] The second insulating layer is located on the first conductive layer. The second insulating layer has regions that are in contact with the upper surface and the side surface of the first conductive layer, respectively.

[0060] The second conductive layer is located on the second insulating layer. The second insulating layer and the second conductive layer have regions where their respective edges coincide or substantially coincide in a plan view.

[0061] The third insulating layer is provided so as to cover the structure composed of the first insulating layer, the first conductive layer, the second insulating layer, and the second conductive layer. The third insulating layer has regions that are in contact with the upper surface of the first insulating layer, the upper and side surfaces of the first conductive layer, the side surfaces of the second insulating layer, and the upper and side surfaces of the second conductive layer, respectively.

[0062] The fourth insulating layer is located on the third insulating layer. The fourth insulating layer has a region that is in contact with the upper surface of the third insulating layer. The fourth insulating layer is provided such that, in a plan view, it has a region that overlaps with the first conductive layer and the second conductive layer, respectively.

[0063] The third insulating layer and the fourth insulating layer each have openings in regions that overlap with the channel formation region of the transistor, as well as the source region and drain region, respectively. These openings are provided such that, in a plan view, they overlap with the first conductive layer and the second conductive layer, respectively. In a structure composed of the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, and the fourth insulating layer, these openings overlap with the channel formation region of the transistor, as well as the source region and drain region, respectively.

[0064] The oxide semiconductor layer is located on the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, and the fourth insulating layer. The oxide semiconductor layer is provided such that, in a plan view, it has regions that overlap with the first conductive layer and the second conductive layer, respectively. Inside the opening, the oxide semiconductor layer has regions that are in contact with the upper surface of the first conductive layer, the side surface of the second insulating layer, and the upper and side surfaces of the second conductive layer, respectively, and outside the opening, it has a region that is in contact with the upper surface of the fourth insulating layer.

[0065] The fourth insulating layer and the oxide semiconductor layer have matching or approximately matching top surfaces (in this case, outer contours). That is, in a plan view, the edges of the fourth insulating layer and the oxide semiconductor layer match or approximately match.

[0066] The first insulating layer preferably contains hydrogen. The hydrogen contained in the first insulating layer diffuses into the oxide semiconductor layer through the first conductive layer. The region of the oxide semiconductor layer in contact with the first conductive layer, that is, either the source region or the drain region, contains hydrogen. As a result, the electrical resistance of either the source region or the drain region is reduced, which allows the on-current of the transistor to be increased.

[0067] The second insulating layer preferably contains oxygen. The oxygen contained in the second insulating layer is supplied to the oxide semiconductor layer through the side surface of the second insulating layer within the opening. This fills the oxygen vacancies (V) in the oxide semiconductor layer (mainly the channel formation region). Ｏ(Oxygen Vacancy) is compensated, enabling the realization of a transistor with good electrical characteristics.

[0068] The third insulating layer is preferably an insulating layer capable of suppressing oxygen permeation. The third insulating layer has a configuration that covers the entire side surface of the second insulating layer, excluding the opening. Therefore, it is possible to suppress the release of oxygen contained in the second insulating layer to the outside from the side surface of the second insulating layer other than the region in contact with the oxide semiconductor layer (i.e., the region overlapping with the opening). This makes it possible to efficiently supply oxygen contained in the second insulating layer into the oxide semiconductor layer (mainly the channel formation region).

[0069] The fourth insulating layer preferably contains oxygen, similar to the second insulating layer. This allows oxygen to be supplied from the fourth insulating layer to the region of the oxide semiconductor layer outside the opening. In other words, oxygen is supplied from the second insulating layer to the region of the oxide semiconductor layer overlapping with the inside of the opening, and from the fourth insulating layer to the region of the oxide semiconductor layer overlapping with the outside of the opening, thus supplying oxygen to the entire oxide semiconductor layer.

[0070] The fifth insulating layer is located on the oxide semiconductor layer. The fifth insulating layer has regions that are in contact with the top and side surfaces of the oxide semiconductor layer, the side surfaces of the fourth insulating layer, and the top surface of the third insulating layer. The third conductive layer is located on the fifth insulating layer. The third conductive layer is provided so as to have a region that overlaps with the oxide semiconductor layer. The third conductive layer has a region that faces the side surfaces of the second insulating layer via the fifth insulating layer and the oxide semiconductor layer.

[0071] A transistor according to one aspect of the present invention is a vertical transistor whose channel length can be controlled by the thickness of a second insulating layer sandwiched between a first conductive layer and a second conductive layer. In other words, unlike a planar transistor, the channel length of the transistor is not affected by the exposure performance of the exposure apparatus used for fabrication. Therefore, the channel length of the transistor can be made smaller than the minimum dimension that the exposure apparatus can expose (hereinafter also referred to as the minimum dimension). By shortening the channel length, a transistor with a large on-current can be made. Therefore, a semiconductor device that operates at high speed can be made.

[0072] Furthermore, since vertical transistors can have their source electrode, oxide semiconductor layer, and drain electrode stacked on top of each other, the area occupied by the transistor can be reduced compared to planar transistors. Therefore, the area occupied by the semiconductor device having such a transistor can be reduced. For example, by applying such a semiconductor device to a display device, the resolution of the display device can be increased.

[0073] <Configuration Example 1> A semiconductor device according to one aspect of the present invention will be described. A plan view (also called a top view) of the semiconductor device 10 is shown in Figure 1A. A cross-sectional view along the dashed line A1-A2 shown in Figure 1A is shown in Figure 1B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 1C. Note that in Figure 1A, some of the components of the semiconductor device 10 (such as the gate insulating layer) are omitted. In subsequent drawings, as in Figure 1A, some of the components may also be omitted in the plan view of the semiconductor device.

[0074] The semiconductor device 10 includes a transistor 100, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The insulating layer 109 is provided on the substrate 102, and the transistor 100 and the like are provided on the insulating layer 109.

[0075] In Figures 1B and 1C, an example is shown in which the insulating layer 110 has a laminated structure comprising insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. The insulating layer 110b is made of an insulating material that contains oxygen and can release oxygen. The insulating layers 110a and 110c are made of insulating materials that can suppress oxygen permeation (insulating materials that have barrier properties against oxygen), respectively.

[0076] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for a target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability); and a function that captures or fixes the substance (also known as gettering). For example, an insulating layer that possesses barrier properties can be called a barrier insulating layer.

[0077] The transistor 100 includes a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b. The conductive layer 104 functions as a gate electrode, and a portion of the insulating layer 106 functions as a gate insulating layer. The conductive layer 112a functions as either a source electrode or a drain electrode, and the conductive layer 112b functions as either a source electrode or a drain electrode. Of the semiconductor layer 108, the region between the source electrode and the drain electrode that overlaps with the gate electrode via the gate insulating layer functions as a channel forming region. Furthermore, of the semiconductor layer 108, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0078] Figure 2A is a perspective view of the semiconductor device 10. Figure 2B is a perspective view of the structure obtained by omitting the conductive layer 104 and the insulating layer 106 from the semiconductor device 10 shown in Figure 2A. Figure 3 is a perspective view of the structure shown in Figure 2B, with the semiconductor layer 108, insulating layer 118, and insulating layer 116 shown separately.

[0079] A conductive layer 112a is provided on the insulating layer 109. An insulating layer 110 is provided on the conductive layer 112a and on the insulating layer 109, such that it has a region that overlaps with the conductive layer 112a. A conductive layer 112b is provided on the insulating layer 110. The conductive layer 112a has a region that is in contact with the insulating layer 109. The insulating layer 110 is in contact with both the conductive layer 112a and the conductive layer 112b, and has a region sandwiched between them. The conductive layer 112a has a region that overlaps with the conductive layer 112b via the insulating layer 110.

[0080] As shown in Figure 3, the insulating layer 110 is provided in an island-like manner. The insulating layer 110 has regions that are in contact with the upper and side surfaces of the conductive layer 112a, and the upper surface of the insulating layer 109. The conductive layer 112b has a region that is in contact with the upper surface of the insulating layer 110. The upper surface shapes of the insulating layer 110 and the conductive layer 112b are identical or approximately identical. That is, in a plan view, the edges of the insulating layer 110 and the conductive layer 112b are identical or approximately identical.

[0081] As shown in Figure 3, the insulating layer 116 is provided to cover the structure composed of the substrate 102, insulating layer 109, conductive layer 112a, insulating layer 110, and conductive layer 112b. As shown in Figures 1B and 1C, the insulating layer 116 has regions that are in contact with the upper and side surfaces of the conductive layer 112b, the side surfaces of the insulating layer 110, the upper and side surfaces of the conductive layer 112a, and the upper surface of the insulating layer 109.

[0082] The insulating layer 116 has an opening (an opening 145 shown in Figure 1A), as shown in Figure 3, etc. The opening 145 is provided such that, in a plan view, it has a region that overlaps with the conductive layer 112a and the conductive layer 112b, respectively.

[0083] The insulating layer 116 is made of an insulating material that has barrier properties against oxygen, similar to the insulating layers 110a and 110c described above.

[0084] The insulating layer 118 is provided on the insulating layer 116. As shown in Figures 1B, 1C, and 2B, the insulating layer 118 has a region that is in contact with the upper surface of the insulating layer 116. In a plan view, the insulating layer 118 is provided such that it has regions that overlap with the conductive layer 112a and the conductive layer 112b, respectively.

[0085] As shown in Figure 3, the insulating layer 118 has an opening similar to that of the insulating layer 116 (an opening 145 shown in Figure 1A). The opening 145 can be said to be formed by both the opening in the insulating layer 116 and the opening in the insulating layer 118. Within the opening 145, a part of the upper surface of the conductive layer 112a, a part of the side surface of the insulating layer 110, a part of the side surface of the conductive layer 112b, and a part of the upper surface of the conductive layer 112b are exposed, respectively.

[0086] Similar to the insulating layer 110b described above, the insulating layer 118 uses an insulating material that contains oxygen and is capable of releasing oxygen.

[0087] The semiconductor layer 108 is provided on the conductive layer 112a, the insulating layer 110, the conductive layer 112b, the insulating layer 116, and the insulating layer 118. The semiconductor layer 108 is provided such that, in a plan view, it has regions that overlap with the conductive layer 112a and the conductive layer 112b, respectively. The semiconductor layer 108 can also be provided spanning the region on the conductive layer 112a where the insulating layer 110 is provided and the region on the conductive layer 112a where the insulating layer 110 is not provided.

[0088] As shown in Figures 1B, 1C, and 2B, the semiconductor layer 108 has regions that are in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110, the upper and side surfaces of the conductive layer 112b, the side surface of the insulating layer 116, and the upper and side surfaces of the insulating layer 118, respectively. As shown in Figure 1B, the semiconductor layer 108 has a shape that follows the upper and side surfaces of the insulating layer 118, the side surface of the insulating layer 116, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110, and the upper and side surfaces of the conductive layer 112b, respectively. As shown in Figure 3, the semiconductor layer 108 is in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110, and the upper and side surfaces of the conductive layer 112b inside the openings (openings 145 shown in Figure 1A) of the insulating layers 116 and 118, and is in contact with the upper surface of the insulating layer 118 outside the openings.

[0089] Within the opening 145, the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as either the source region or the drain region of the transistor 100. Within the opening 145, the region of the semiconductor layer 108 in contact with the conductive layer 112b functions as the other source region or drain region of the transistor 100. Within the opening 145, the region of the semiconductor layer 108 in contact with the insulating layer 110 functions as the channel formation region of the transistor 100. In Figure 3, a hatching pattern is applied to the region of the insulating layer 110 in contact with the semiconductor layer 108 within the opening 145 (the region opposite the channel formation region of the transistor 100).

[0090] As shown in Figures 1B, 1C, and 2B, the insulating layer 118 and the semiconductor layer 108 have matching or approximately matching top surfaces (in this case, outer contours). That is, in a plan view, the edges of the insulating layer 118 and the semiconductor layer 108 match or approximately match.

[0091] As shown in Figures 1B, 1C, and 3, the multiple sides of the island-shaped insulating layer 110 are all covered with insulating layer 116, except for a portion of the area in contact with the semiconductor layer 108. Therefore, in the insulating layer 110, the lower surface (the surface on the substrate 102 side) of the insulating layer 110b is in contact with insulating layer 110a, and the upper surface is in contact with insulating layer 110c. The sides of the insulating layer 110b are all in contact with insulating layer 116, except for a portion of the area in contact with the semiconductor layer 108. In other words, the insulating layer 110b can be covered with insulating layer 110a, insulating layer 110c, and insulating layer 116, each having barrier properties against oxygen, except for the area in contact with the semiconductor layer 108. As a result, the release of oxygen from the insulating layer 110b to the outside can be suppressed, and the oxygen can be efficiently supplied to the semiconductor layer 108 (mainly the channel formation region).

[0092] Here, we consider the case where the semiconductor device does not have an insulating layer 116 covering the side surface of the insulating layer 110. In this case, the region of the side surface of the insulating layer 110 that is not in contact with the semiconductor layer 108 is in contact with the insulating layer 106, so that some of the oxygen contained in the insulating layer 110b can be released to the outside from that region. This oxygen can then diffuse through the insulating layer 106 and reach, for example, the conductive layers 112a and 112b that function as the source electrode and drain electrode of a transistor. Figure 4A shows an image diagram of the above concept. In Figure 4A, the semiconductor device is shown as semiconductor device 10X, and the transistor contained in semiconductor device 10X is shown as transistor 100X. Figure 4A is a cross-sectional view of semiconductor device 10X corresponding to the dashed line B1-B2 in the plan view shown in Figure 1A. It can be said that semiconductor device 10X is a configuration in which the insulating layer 116 and insulating layer 118 are excluded from semiconductor device 10.

[0093] As described above, in the semiconductor device 10X, oxygen released from the exposed side surface of the insulating layer 110 (the side surface not in contact with the semiconductor layer 108) can diffuse through the insulating layer 106. This oxygen can then move through the insulating layer 106, for example, due to heat treatment during the manufacturing process of the semiconductor device 10X, and may reach the conductive layer 112a or conductive layer 112b that is in contact with the insulating layer 106. In Figure 4A, oxygen (O) is shown as a white circle, and the direction of oxygen diffusion is shown as a dashed arrow.

[0094] For example, if oxygen released from the exposed side of the insulating layer 110 diffuses through the insulating layer 106 and reaches the conductive layer 112a or conductive layer 112b, there is a risk that this oxygen will oxidize and increase the resistance of the conductive layer 112a or conductive layer 112b. This may also increase the contact resistance between the semiconductor layer 108 and the conductive layer 112a, or between the semiconductor layer 108 and the conductive layer 112b, potentially causing the on-current of the transistor 100X to plateau (i.e., the drain current will not increase as easily as the gate voltage increases). Furthermore, the oxygen may diffuse through the insulating layer 106 and into the conductive layer 104. This could also oxidize and increase the resistance of the conductive layer 104.

[0095] In contrast, in one embodiment of the present invention, the semiconductor device 10, as described above, is covered by an insulating layer 116 in the area of ​​the insulating layer 110 that is not in contact with the semiconductor layer 108 on its side surface. Therefore, the oxygen contained in the insulating layer 110b can be confined by the insulating layer 110a, insulating layer 110c, and insulating layer 116 that cover each surface of the insulating layer 110b. Consequently, it is possible to suppress the release of the oxygen to the outside from the side surface of the insulating layer 110 that is not in contact with the semiconductor layer 108, and to efficiently supply the oxygen to the semiconductor layer 108 (mainly the channel formation region). Furthermore, there is no risk of inducing the above-mentioned problems that may occur in the semiconductor device 10X. Figure 4B shows an image diagram of the above concept. Figure 4B is a cross-sectional view of the semiconductor device 10 corresponding to the dashed line B1-B2 in the plan view shown in Figure 1A. In Figure 4B, the oxygen (O) confined in the insulating layer 110b is shown by white circles.

[0096] Furthermore, in one embodiment of the present invention, the semiconductor device 10 has a configuration in which the semiconductor layer 108 is in contact with the upper surface of the insulating layer 118 outside the opening 145, as described above. Therefore, oxygen can be supplied from the insulating layer 118 to the region of the semiconductor layer 108 outside the opening 145 that is not in contact with the insulating layer 110. That is, oxygen can be supplied from the insulating layer 110 to the region of the semiconductor layer 108 that overlaps with the opening 145, and oxygen can be supplied from the insulating layer 118 to the region of the semiconductor layer 108 that does not overlap with the opening 145. As a result, compared to the case without the insulating layer 118, there are many oxygen vacancies (V) in the region of the semiconductor layer 108 located outside the opening 145 (especially two regions extending in the X direction). Ｏ This allows the remaining region to be suppressed, preventing leakage current from occurring between the source and drain of the transistor 100.

[0097] As shown in Figure 4B and other figures, the sides of the insulating layer 118 are not covered by the insulating layer 116 and are in contact with the insulating layer 106. Therefore, some of the oxygen contained in the insulating layer 118 may diffuse into the insulating layer 106. However, in one embodiment of the present invention, the semiconductor device 10 has a configuration in which the regions of the conductive layer 112a and conductive layer 112b that are not in contact with the semiconductor layer 108 are covered by the insulating layer 116. Therefore, even if oxygen diffuses from the insulating layer 118 into the insulating layer 106, there is no risk of the conductive layer 112a or conductive layer 112b being oxidized by that oxygen.

[0098] As described above, in one aspect of the present invention, a semiconductor device 10 can be realized that exhibits good electrical characteristics and is highly reliable as a transistor 100.

[0099] The semiconductor material used in the semiconductor layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities that act as dopants.

[0100] The crystallinity of the semiconductor material used in the semiconductor layer 108 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0101] For example, silicon can be used for the semiconductor layer 108. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0102] The semiconductor layer 108 preferably has a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. Transistors using oxide semiconductors (hereinafter referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, by applying OS transistors, the power consumption of the semiconductor device can be reduced. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0103] As the insulating layer 110, one or both of an inorganic insulating layer and an organic insulating layer can be used. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. Preferably, the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0104] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0105] The insulating layer 110 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 110. Specifically, it is preferable that the portion of the insulating layer 110 that is in contact with the channel-forming region of the semiconductor layer 108 contains oxygen. One or more oxides and oxiditrides can be suitably used in the portion of the insulating layer 110 that is in contact with the channel-forming region of the semiconductor layer 108.

[0106] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 108 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 110 to the semiconductor layer 108, and reduces oxygen deficiencies (V) in the semiconductor layer 108. Ｏ), and defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ This can reduce the amount of H (which is denoted as H).

[0107] The insulating layer 106, which functions as a gate insulating layer for transistor 100, is provided so as to cover the semiconductor layer 108. The insulating layer 106 has regions that are in contact with the upper and side surfaces of semiconductor layer 108, the side surfaces of insulating layer 118, and the upper surface of insulating layer 116.

[0108] The conductive layer 104, which functions as the gate electrode of transistor 100, is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 also has a region that faces the side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 is provided so as to cover at least the side surface of the insulating layer 110 in the region that overlaps with the semiconductor layer 108 in a plan view. This allows the region of the semiconductor layer 108 facing the said side surface to function as the channel formation region of transistor 100.

[0109] It is preferable that the conductive layer 104 covers the entire semiconductor layer 108. As shown in Figure 1A, it is preferable that the conductive layer 104 encompasses the semiconductor layer 108 in a plan view. By covering the semiconductor layer 108 with the conductive layer 104, damage to the semiconductor layer 108 when a layer is formed on the transistor 100 can be suppressed. This makes it possible to realize a transistor 100 that exhibits good electrical characteristics and is highly reliable. It is also possible to have a configuration in which the semiconductor layer 108 has regions that are not covered by the conductive layer 104.

[0110] A step is formed between the region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are provided and the region on the conductive layer 112a where the insulating layer 110 and the conductive layer 112b are not provided, and a semiconductor layer 108, insulating layer 106, conductive layer 104, etc. can be provided along this step.

[0111] In transistor 100, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, and the drain current flows perpendicular to, or approximately perpendicular to, the surface of the substrate 102. In transistor 100, it can also be said that the drain current flows in the vertical direction, or approximately vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical channel transistor, a vertical transistor, or a VFET (Vertical Field Effect Transistor).

[0112] The channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, transistors with a channel length shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. Furthermore, variations in the electrical characteristics between multiple transistors 100 can be reduced. As a result, the operation of the semiconductor device 10 becomes more stable and its reliability can be increased. In addition, when variations in the electrical characteristics between transistors 100 are reduced, the degree of freedom in circuit design increases, and the operating voltage of the semiconductor device 10 can be lowered. As a result, the power consumption of the semiconductor device 10 can be reduced.

[0113] In one embodiment of the present invention, the source electrode, semiconductor layer, and drain electrode can be arranged in a stacked manner. Therefore, compared to a so-called planar transistor in which the source electrode, semiconductor layer, and drain electrode are arranged on a plane, the occupied area can be significantly reduced.

[0114] The conductive layers 112a, 112b, and 104 can each function as wiring, and the transistor 100 can be placed in the region where these wirings overlap. In other words, in a circuit having the transistor 100 and wiring, the area occupied by the transistor 100 and wiring can be reduced. Therefore, a semiconductor device 10 with a small occupied area can be realized.

[0115] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device.

[0116] The insulating layer 109 is provided between the transistor 100, the insulating layer 110, and the substrate 102. The insulating layer 109 has regions that are in contact with the conductive layer 112a, the insulating layer 110, and the insulating layer 116. The insulating layer 109 can be made from the materials listed for the insulating layer 110.

[0117] The insulating layer 109 preferably has barrier properties. It is preferable to use a material for the insulating layer 109 that does not easily allow impurities (e.g., water and hydrogen) contained in the substrate 102 to diffuse. This makes it possible to suppress the diffusion of impurities from the substrate 102 to the transistor 100.

[0118] The insulating layer 109, which functions as a barrier film, can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, an aluminum nitride, an aluminum nitride, an aluminum nitride, and an oxide silicon nitride. Specifically, the insulating layer 109 can preferably be made from, for example, one or more aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0119] The insulating layer 109 contains impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layer 108, and it is preferable to use a material that releases these impurities. The impurities released from the insulating layer 109 diffuse into the region of the conductive layer 112a that is in contact with the insulating layer 109. Furthermore, the impurities diffused into the conductive layer 112a diffuse into the region of the semiconductor layer 108 that is in contact with the conductive layer 112a, so that region contains impurities, and the electrical resistance of that region can be lowered. In other words, the electrical resistance of either the source region or the drain region can be lowered. Therefore, a transistor 100 with a large on-current can be made, and a semiconductor device 10 that operates at high speed can be made.

[0120] When a metal oxide is used for the semiconductor layer 108, it is more preferable that the impurities released by the insulating layer 109 include hydrogen. The hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108 via the conductive layer 112a, causing the region of the semiconductor layer 108 in contact with the conductive layer 112a to contain hydrogen, thereby increasing the carrier concentration in that region. In other words, the electrical resistance of either the source region or the drain region can be lowered. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 109.

[0121] It is more preferable to use a material for the insulating layer 109 that releases impurities that lower the electrical resistance of the conductive layer 112a. This makes it possible to lower the electrical resistance of the conductive layer 112a.

[0122] For example, a conductive metal oxide (also called an oxide conductor) can be used for the conductive layer 112a. Examples of oxide conductors (OC) include indium oxide (also called indium oxide), zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. In particular, oxide conductors containing indium have high conductivity and can therefore be suitably used for the conductive layer 112a.

[0123] When a metal oxide is used for the conductive layer 112a, it is more preferable that the impurities released from the insulating layer 109 contain hydrogen. The impurities released from the insulating layer 109 diffuse through the conductive layer 112a, causing the conductive layer 112a to contain impurities. As a result, the carrier concentration of the conductive layer 112a increases, and the electrical resistance can be lowered. Also, since the conductive layer 112a can function as a wiring, a semiconductor device 10 with low wiring resistance can be realized. Note that the impurities that lower the electrical resistance of the conductive layer 112a can be the same as the impurities that lower the electrical resistance of the semiconductor layer 108. Or, these impurities can have different configurations from each other. It is more preferable that the conductive layer 112a allows impurities to permeate easily. It is more preferable that the conductive layer 112a is less likely to adsorb impurities.

[0124] The thickness of the insulating layer 109 is preferably 5 nm or more and 100 nm or less, more preferably 10 nm or more and 100 nm or less, still more preferably 20 nm or more and 100 nm or less, and even more preferably 20 nm or more and 50 nm or less. For example, as shown in FIG. 5A, the thickness T109 of the insulating layer 109 can be the shortest distance between the formed surface of the insulating layer 109 (here, the upper surface of the substrate 102) and the upper surface of the insulating layer 109 in a cross-sectional view.

[0125] When the thickness T109 is large and the amount of impurities released from the insulating layer 109 becomes too large, the amount of impurities diffusing into the semiconductor layer 108 increases, and the oxygen vacancies (V Ｏ ) and V Ｏ The amount of H may become larger than the amount of oxygen vacancies (V Ｏ ) and V Ｏ The amount of H repaired by the oxygen supplied from the insulating layer 110b. On the other hand, when the thickness T109 is small, the amount of impurities diffusing into the conductive layer 112a and the semiconductor layer 108 decreases, and there is a risk that the electrical resistance of the conductive layer 112a and the electrical resistance of either the source region or the drain region will increase. By setting the thickness T109 within the above range, the oxygen vacancies (V Ｏ ) and V ＯThis can suppress the increase in H and lower these electrical resistances. Note that the thickness T109 is not limited to the range described above.

[0126] Furthermore, it is also possible to omit the insulating layer 109.

[0127] The insulating layer 110 preferably has a laminated structure. Figure 1B and others show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on insulating layer 110a, and an insulating layer 110c on insulating layer 110b. The insulating layers 110a, 110b, and 110c can be made from the materials listed for insulating layer 110, respectively.

[0128] In transistor 100, the region of semiconductor layer 108 in contact with insulating layer 110b functions as a channel-forming region. As mentioned above, the insulating layer 110b preferably contains oxygen, and it is preferable to use one or more of the aforementioned oxides and oxiditrides. Typically, silicon oxide and silicon oxiditride, or both, can be suitably used for the insulating layer 110b.

[0129] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 110b. The heat applied during the manufacturing process of the semiconductor device 10 causes the insulating layer 110b to release oxygen, thereby supplying oxygen to the semiconductor layer 108. By supplying oxygen from the insulating layer 110b to the semiconductor layer 108, particularly to the channel formation region of the semiconductor layer 108, oxygen deficiencies (V) in that region can be reduced. Ｏ ) is repaired, and oxygen deficiency (V Ｏ This can reduce the V in the region. Ｏ H can be reduced. Therefore, a transistor 100 that exhibits good electrical characteristics and is highly reliable can be realized.

[0130] For example, oxygen can be supplied to the insulating layer 110b by heat treatment in an oxygen-containing atmosphere or by plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the upper surface of the insulating layer 110b by forming a film in an oxygen-containing atmosphere using a sputtering method. The film can then be removed. The method for supplying oxygen to the insulating layer 110b will be specifically described in Embodiment 3.

[0131] The insulating layer 110b is preferably deposited using sputtering or plasma chemical vapor deposition (PECVD: Plasma Enhanced Chemical Vapor Deposition, also known as plasma CVD). In particular, by using sputtering and depositing the film without using hydrogen-containing gases (e.g., hydrogen gas and ammonia gas) as the deposition gas, a film with an extremely low hydrogen content can be obtained. This suppresses the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of the transistor 100.

[0132] The insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a and insulating layer 109. The insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. It is preferable that the insulating layer 110a and insulating layer 110c each release small amounts of impurities (e.g., hydrogen and water). Furthermore, it is preferable that the insulating layer 110a and insulating layer 110c each impede substances to be difficult to permeate. It can also be said that the insulating layer 110a and insulating layer 110c function as barrier films. Specifically, it is preferable that the insulating layer 110a and insulating layer 110c each impede substances to be difficult to permeate. This makes it possible to suppress the diffusion of impurities contained in the insulating layer 110a and insulating layer 110c into the channel formation region. Therefore, it is possible to realize a transistor 100 that exhibits good electrical characteristics and is highly reliable.

[0133] As mentioned above, it is preferable to use materials that are impermeable to oxygen for the insulating layer 110a and insulating layer 110c. This suppresses the diffusion of oxygen contained in the insulating layer 110b to the conductive layer 112a side via the insulating layer 110a. Similarly, it suppresses the diffusion of oxygen contained in the insulating layer 110b to the conductive layer 112b side via the insulating layer 110c. This increases the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, resulting in oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. This makes it possible to realize a transistor 100 that exhibits good electrical characteristics and is highly reliable. Furthermore, oxidation of the conductive layer 112a by oxygen contained in the insulating layer 110b and an increase in the electrical resistance of the conductive layer 112a can be suppressed. Similarly, oxidation of the conductive layer 112b by oxygen contained in the insulating layer 110b and an increase in the electrical resistance of the conductive layer 112b can be suppressed. Therefore, a transistor 100 with a large on-current can be realized.

[0134] The insulating layer 110a and insulating layer 110c can be made from the materials listed above for the barrier film. For example, the insulating layer 110a and insulating layer 110c can preferably be made from one or more of the following materials: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. The insulating layer 110a and insulating layer 110c can be made from the same material, or different materials can be used for the insulating layer 110a and insulating layer 110c.

[0135] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0136] One or more of the insulating layers 110a, 110b, and 110c can also be arranged in a laminated structure. For example, the insulating layer 110c can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0137] The thickness of the insulating layer 110c is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, and more preferably 100 nm to 200 nm. For example, as shown in Figure 5A, the thickness T110c of the insulating layer 110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.

[0138] The thickness T110c is preferably a value that functions as a barrier film against oxygen. The thickness T110c can be thinner than the thickness of the insulating layer 110a. If the thickness T110c of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, if the thickness T110c is thin, the oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and the oxygen deficiency (V) in the channel formation region can be reduced. Ｏ ) and V Ｏ H can be reduced. In addition, oxidation of the conductive layer 112b by oxygen contained in the insulating layer 110b can be suppressed, which would increase the electrical resistance of the conductive layer 112b. Note that the thickness T110c is not limited to the range described above.

[0139] The thickness of the insulating layer 110a is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, more preferably 100 nm to 250 nm, and more preferably 150 nm to 250 nm. For example, as shown in Figure 5A, the thickness T110a of the insulating layer 110a can be the shortest distance between the surface on which the insulating layer 110a is formed (in this case, the upper surface of the conductive layer 112a) and the upper surface of the insulating layer 110a in a cross-sectional view.

[0140] If the thickness T110a is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, reducing the amount of oxygen supplied to the channel formation region. On the other hand, if the thickness T110a is thick, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region increases. By setting the thickness T110a within the aforementioned range, the amount of oxygen supplied to the channel formation region can be increased, and the oxygen deficiency (V) in the channel formation region can be reduced. Ｏ ) and V Ｏ H can be reduced. In addition, oxidation of the conductive layer 112a by oxygen contained in the insulating layer 110b can be suppressed, which would increase the electrical resistance of the conductive layer 112a. Note that the thickness T110a is not limited to the range described above.

[0141] The thickness T110a can be made thicker than the thickness T110c. When the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region, increasing the thickness T110a makes the distance from the source region or drain region to the gate electrode more uniform. This makes the electric field of the gate electrode acting on the channel formation region more uniform.

[0142] At least one of the regions of the semiconductor layer 108 that are in contact with the insulating layer 110a and the region that are in contact with the insulating layer 110c can be a region with lower electrical resistance compared to the channel-forming region (hereinafter also referred to as the low-resistance region). This region can also be described as a region with a higher carrier concentration or a higher oxygen vacancy density compared to the channel-forming region. By using a material that releases impurities (e.g., water and hydrogen) in the insulating layer 110a, the region of the semiconductor layer 108 in contact with the insulating layer 110a can contain impurities, making this region a low-resistance region. The semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (either the source region or the drain region) and the channel-forming region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can contain impurities, making this region a low-resistance region. The semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region or drain region) and the channel-forming region. The low-resistance region can function as a buffer region to mitigate the drain electric field. These low-resistance regions can also function as either the source region or the drain region.

[0143] Furthermore, impurities released from the insulating layer 110a may diffuse into the channel formation region via the insulating layer 110b, or via either the source region or the drain region of the semiconductor layer 108. Similarly, impurities released from the insulating layer 110c may diffuse into the channel formation region via the insulating layer 110b, or via the other of the source region or the drain region of the semiconductor layer 108. However, since oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 in contact with the insulating layer 110b, oxygen deficiency (V) in the channel formation region occurs. Ｏ ) and V Ｏ H can be reduced. This suppresses the shift of the threshold voltage to the normally-on side, making it possible to realize a transistor 100 that achieves both a small cutoff current (drain current when the gate voltage is 0V) and a large on current. Therefore, it is possible to realize a semiconductor device 10 that achieves both low power consumption and high performance.

[0144] However, if the amount of impurities released from insulating layer 110a and insulating layer 110c becomes too large, the amount of impurities contained in semiconductor layer 108 will increase. As a result, oxygen vacancies (V) will be formed in semiconductor layer 108. Ｏ ) and V Ｏ The amount of H is the oxygen deficiency (V) that is repaired by the oxygen supplied from the insulating layer 110b. Ｏ ) and V Ｏ There is a risk that the amount of H may exceed the amount of H. Even when materials that release impurities are used for the insulating layer 110a and insulating layer 110c, it is more preferable that the amount of released impurities be small.

[0145] The insulating layer 110a has regions that are in contact with the upper surface of the insulating layer 109 and the upper and side surfaces of the conductive layer 112a. This suppresses the diffusion of impurities contained in the insulating layer 109 and the conductive layer 112a into the channel formation region of the semiconductor layer 108 via the insulating layer 110b.

[0146] The insulating layer 109 preferably has a region with a higher hydrogen content than the insulating layer 110a. The film density of the insulating layer 110a is preferably higher than that of the insulating layer 109.

[0147] Furthermore, for analyzing the hydrogen content of the insulating layer 109, etc., secondary ion mass spectrometry (SIMS) can be used, for example.

[0148] Furthermore, impurities released from the insulating layer 109 may diffuse into the channel formation region via the conductive layer 112a and either the source region or the drain region of the semiconductor layer 108. However, at least the region of the semiconductor layer 108 in contact with the insulating layer 110b receives oxygen from the insulating layer 110b, thus preventing oxygen deficiency (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. This suppresses the shift in the threshold voltage, making it possible to realize a transistor 100 that achieves both a small cutoff current and a large on-current. Therefore, a semiconductor device 10 that achieves both low power consumption and high performance can be realized.

[0149] The amount of hydrogen released can be adjusted by differentiating the film formation conditions for the insulating layer 109 and the insulating layer 110a. Specifically, one or more of the following can be made different for the insulating layer 109 and the insulating layer 110a: film formation power (film formation power density), film formation pressure, type of film formation gas, film formation gas flow rate ratio, film formation temperature, and the distance between the substrate and the electrode. For example, by making the film formation power density of the insulating layer 109 lower than that of the insulating layer 110a, the hydrogen content in the insulating layer 109 can be made higher than that in the insulating layer 110a. This increases the amount of hydrogen released from the insulating layer 109 due to the heat applied to it.

[0150] The film-forming gas used to form the insulating layer 109 preferably has a higher hydrogen content than the film-forming gas used to form the insulating layer 110a. Specifically, when forming a silicon nitride film or a silicon nitride oxide film on the insulating layer 109 and the insulating layer 110a using the PECVD method, the ratio of the flow rate of ammonia gas to the total film-forming gas used to form the insulating layer 109 (hereinafter also referred to as the ammonia flow rate ratio) is preferably higher than the ammonia flow rate ratio of the film-forming gas used to form the insulating layer 110a. By forming the insulating layer 109 under conditions of a high ammonia flow rate ratio, the hydrogen content in the insulating layer 109 can be increased. In addition, the amount of hydrogen released from the insulating layer 109 due to the heat applied to it can be increased.

[0151] It is more preferable that the film density of the insulating layer 110a is higher than that of the insulating layer 109. This suppresses the diffusion of hydrogen contained in the insulating layer 109 into the channel formation region of the semiconductor layer 108 via the insulating layers 110a and 110b. For evaluation of film density, for example, Rutherford backscattering (RBS) or X-ray reflectivity (XRR) can be used. Differences in film density can sometimes be evaluated using a transmission electron microscope (TEM) image of the cross-section. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, in the transmission electron (TE) image, the insulating layer 110a may appear darker (more intense) compared to the insulating layer 109. Even when the same material is applied to the insulating layer 109 and the insulating layer 110a, the film densities are different, so in some cases, the boundary between them can be observed as a difference in contrast in the cross-sectional TEM image.

[0152] Although the insulating layer 110 is shown here as a three-layer laminated structure, the present invention is not limited to this. Preferably, the insulating layer 110 has at least an insulating layer 110b. It is also possible to have a configuration that does not have one or both of the insulating layers 110a and 110c. Furthermore, it is also possible to have a configuration in which the insulating layer 110 has a laminated structure of four or more layers.

[0153] [Semiconductor Layer 108] The metal oxides that can be used in the semiconductor layer 108 will be described in detail. Examples of metal oxides include indium oxide (also called indium oxide, IO). Examples of metal oxides include gallium oxide and zinc oxide. The metal oxide preferably contains at least indium. It is also preferable that the metal oxide contains either or both indium and zinc. Furthermore, it is preferable that the metal oxide has one or more elements selected from indium, element M, and zinc. Element M is a metal element or metalloid with a high bond energy with oxygen, for example, a metal element or metalloid with a higher bond energy with oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferable because they have high bonding energy with oxygen and similar ionic radii to indium or zinc. Furthermore, tin is more preferable because its tetravalent state enhances carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the term "metallic elements" as used here may include metalloid elements.

[0154] For example, indium oxide can be used for the semiconductor layer 108. Alternatively, for example, indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide) can be used for the semiconductor layer 108. Indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. can be used. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0155] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0156] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0157] By increasing the ratio of indium atoms to the sum of all metal element atoms in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized.

[0158] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0159] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0160] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be obtained. Furthermore, oxygen vacancies (V) can be added to the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed, Ｏ This suppresses carrier generation caused by (), thereby preventing a shift in the transistor's threshold voltage. This allows for a smaller cutoff current, enabling a normally-off transistor. It also allows for a transistor with a small off-current. Furthermore, it suppresses fluctuations in the transistor's electrical characteristics, improving reliability.

[0161] The composition of the metal oxide applied to the semiconductor layer 108 affects the electrical characteristics and reliability of the transistor. Therefore, by varying the composition of the metal oxide according to the required electrical characteristics and reliability of the transistor, it is possible to create a semiconductor device that achieves both excellent electrical characteristics and high reliability.

[0162] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=2:1:3, In:M:Zn=3:1:1, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In: Compositions such as M:Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. Note that compositions near these include a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0163] The atomic ratio of In in an In-M-Zn oxide can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. By increasing the proportion of M atoms in the metal oxide, oxygen deficiency (V) can be reduced. Ｏ This can suppress the generation of ()

[0164] Furthermore, if element M comprises multiple elements, the sum of their atomic ratios can be used as the atomic ratio of element M.

[0165] By using a material with a high indium content in the semiconductor layer 108, the on-current or field-effect mobility of the transistor can be increased. Furthermore, the presence of element M allows for oxygen deficiency (V ＯThe generation of ) can be suppressed. The content of element M (the ratio of the number of atoms of element M to the sum of the number of atoms of all contained metal elements) is preferably 0.1% to 25%, more preferably 0.1% to 20%, more preferably 0.1% to 10%, more preferably 0.1% to 8%, more preferably 0.1% to 6%, and more preferably 0.1% to 4%. This makes it possible to make a transistor with good electrical properties. For example, it is preferable to use metal oxides of In:M:Zn = 40:1:10 and nearby elements. Element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium. Specifically, metal oxides of In:Sn:Zn = 40:1:10 and nearby elements can be suitably used. Alternatively, metal oxides of In:Al:Zn = 40:1:10 and nearby elements can be suitably used.

[0166] A metal oxide that does not contain element M can be applied to the semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0167] For analyzing the composition of the semiconductor layer 108, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), or Electron Spectrometry for Chemical Analysis (ESCA), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Spectrometry can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or the content of element M may be below the detection limit.

[0168] For depositing metal oxide films, sputtering or atomic layer deposition (ALD) can be suitably used. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from the composition of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% compared to the sputtering target.

[0169] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of crystalline metal oxide structures include CAAC (C-Axis Aligned Crystal) structure, polycrystalline structure, and microcrystalline (nc: nano-crystalline) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0170] It is preferable to use CAAC-OS or nc-OS for the semiconductor layer 108.

[0171] CAAC-OS has multiple layered crystals. The c-axis of the crystals is oriented in the direction normal to the surface to be formed. It is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the surface to be formed. For example, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the upper surface of the conductive layer 112b in the region in contact with the upper surface of the conductive layer 112b, and layered crystals that are parallel or approximately parallel to the side surface in the region in contact with the side surface of the conductive layer 112b. In particular, it is preferable that the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the side surface, which is the surface to be formed, in the region in contact with the side surface of the insulating layer 110. With this configuration, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, so that a transistor with a large on-current can be made.

[0172] By using a highly crystalline metal oxide in the channel formation region, the defect level density in the channel formation region can be reduced. On the other hand, by using a less crystalline metal oxide, it is possible to realize a transistor that can carry a large current.

[0173] The higher the substrate temperature during metal oxide film deposition, the more crystalline the metal oxide film can be formed. The substrate temperature during deposition can be adjusted, for example, by the temperature of the stage on which the substrate is placed during deposition. Furthermore, the higher the oxygen flow rate ratio of the deposition gas used for film formation, or the higher the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide film can be formed.

[0174] The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods can be used for the analysis.

[0175] When a metal oxide is used for the semiconductor layer 108, the V of the channel formation region Ｏ It is preferable to reduce H as much as possible and make it high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain a metal oxide with sufficiently reduced H content, impurities such as water and hydrogen must be removed from the metal oxide (sometimes referred to as dehydration and dehydrogenation treatment), and oxygen must be supplied to the metal oxide to eliminate oxygen deficiency (V). Ｏ It is important to repair ). Ｏ By using metal oxides with sufficiently reduced defects such as H in the channel formation region of a transistor, stable electrical characteristics can be provided. Furthermore, by supplying oxygen to the metal oxide, oxygen deficiencies (V) can be reduced. Ｏ The process of repairing this is sometimes referred to as oxygenation treatment.

[0176] When a metal oxide is used for the semiconductor layer 108, the carrier concentration in the channel formation region is 1 × 10⁻⁶ １８ cm −３ The following is preferable: 1 × 10 １７ cm −３ It is more preferable that it be less than 1 × 10 １６ cm −３ It is even more preferable that it be less than 1 × 10 １３ cm −３ It is even more preferable that it be less than 1 × 10 １２ cm −３ It is even more preferable that it be less than 10⁻¹⁰. There is no limit to the lower limit of the carrier concentration in the channel-forming region, but for example, 1 × 10⁻¹⁰ −９ cm −３ It can be done this way.

[0177] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, protons, and neutrons).

[0178] The semiconductor layer 108 may also have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent or ionic bonds are stacked via weaker bonds than covalent or ionic bonds, such as van der Waals bonds. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be realized.

[0179] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0180] The semiconductor layer 108 can have a laminated structure having two or more metal oxide layers. The two or more metal oxide layers of the semiconductor layer 108 can have the same or substantially the same composition. By having a laminated structure of metal oxide layers with the same composition, for example, it can be formed using the same sputtering target, thus reducing manufacturing costs. When the two or more metal oxide layers of the semiconductor layer 108 have the same or substantially the same composition, it may not be possible to clearly identify the boundaries (interfaces) of these metal oxide layers.

[0181] The channel length and channel width of transistor 100 will be explained using Figures 5A and 5B. Figure 5B is a plan view of semiconductor device 10. Figure 5A is an enlarged cross-sectional view of transistor 100 along the dashed line A1-A2 in the plan view shown in Figure 5B. Here, in the cross-sectional view shown in Figure 5A, the region in contact with the side surface of the insulating layer 110b of the semiconductor layer 108 will be described as the channel formation region of transistor 100.

[0182] In Figure 5A, the channel length L100 of transistor 100 is indicated by a dashed double arrow. The channel length L100 of transistor 100 corresponds to the length of the region in contact between the semiconductor layer 108 and the side surface of the insulating layer 110b in a cross-sectional view. In other words, the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle θ110b, which is the angle between the side surface of the insulating layer 110b on the semiconductor layer 108 side and the surface of the insulating layer 110b to be formed (in this case, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure apparatus, enabling the realization of minute transistors. Specifically, it is possible to realize transistors with extremely short channel lengths, which were difficult to achieve with conventional exposure apparatuses for mass production of flat panel displays (for example, with a minimum dimension of about 2 μm or 1.5 μm). Furthermore, it is possible to realize transistors with channel lengths of less than 10 nm without using extremely expensive exposure apparatuses used in state-of-the-art LSI technology.

[0183] The channel length L100 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L100 can also be 100 nm or more and 1 μm or less.

[0184] By shortening the channel length L100, the on-current of the transistor 100 can be increased. Using the transistor 100, a circuit capable of high-speed operation can be fabricated. Furthermore, the circuit's occupied area can be reduced. Therefore, a compact semiconductor device can be made. For example, when a semiconductor device according to one aspect of the present invention is applied to a large display device or a high-definition display device, even when the number of wires increases, the signal delay in each wire can be reduced, and display unevenness can be suppressed. In addition, since the circuit's occupied area can be reduced, the bezel of the display device can be narrowed.

[0185] The channel length L100 can be controlled by adjusting the thickness T110b and angle θ110b of the insulating layer 110b.

[0186] The thickness T110b of the insulating layer 110b can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0187] The side surface of the insulating layer 110 facing the semiconductor layer 108 is preferably tapered. The angle θ110b is preferably less than 90 degrees. By reducing the angle θ110b, the coverage of the layer formed on the insulating layer 110 (for example, the semiconductor layer 108) can be improved. Also, the smaller the angle θ110b, the longer the channel length L100 can be made, and the larger the angle θ110b, the shorter the channel length L100 can be made.

[0188] Although Figure 1B and other figures show the angle θ110b as less than 90 degrees, the present invention is not limited to this. The angle θ110b can also be 90 degrees or approximately 90 degrees. This allows for a shorter channel length L100 of the transistor 100 and a smaller footprint of the semiconductor device.

[0189] The angle θ110b can be, for example, 30 degrees or more and 90 degrees or less, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 75 degrees or less, 50 degrees or more and 70 degrees or less, 55 degrees or more and 70 degrees or less, 60 degrees or more and 70 degrees or less, or 65 degrees or more and 70 degrees or less.

[0190] Figure 1B and others show a configuration in which the side shape of the insulating layer 110 is straight in a cross-sectional view, but the present invention is not limited to this. The side shape of the insulating layer 110 can also be curved in a cross-sectional view. Alternatively, the side shape of the insulating layer 110 can include both a region where the side shape is straight and a region where it is curved in a cross-sectional view.

[0191] The upper surface shape of the conductive layer 112b is preferably the same as or approximately the same as the upper surface shape of the insulating layer 110. Figure 1A, etc., shows a configuration in which the upper surface shape of the conductive layer 112b is the same as the upper surface shape of the insulating layer 110. The conductive layer 112b and the insulating layer 110 can be formed using the same mask layer. For example, an insulating film that will become the insulating layer 110 and a conductive film that will become the conductive layer 112b on the insulating film are formed, and a mask layer (for example, a resist mask) is formed on the conductive film. Then, by processing the conductive film and the insulating film using the mask layer as a mask, a conductive layer 112b and an insulating layer 110 with the same or approximately the same upper surface shape can be formed. By processing the insulating film that will become the insulating layer 110 and the conductive film that will become the conductive layer 112b in the same process, manufacturing costs can be reduced. In Figure 1A, etc., the top surfaces of the conductive layer 112b and the insulating layer 110 are shown as rectangles, but the top surfaces of the conductive layer 112b and the insulating layer 110 are not particularly limited.

[0192] It is preferable that there is no step between the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface of the insulating layer 110 facing the semiconductor layer 108, and that the surfaces are flat (i.e., the two surfaces coincide or roughly coincide). This improves the coverage of the layers (e.g., the semiconductor layer 108) provided on the insulating layer 110 and the conductive layer 112b. It is also possible to have a configuration where the side surface of the conductive layer 112b facing the semiconductor layer 108 and the side surface of the insulating layer 110 facing the semiconductor layer 108 are discontinuous. Furthermore, it is also possible to have a configuration where the upper surface shape of the conductive layer 112b does not coincide with the upper surface shape of the insulating layer 110.

[0193] Here, it is preferable that the conductive layer 112b does not have a region that is in contact with the side surface of the insulating layer 110 on the semiconductor layer 108 side. If the conductive layer 112b is in contact with the side surface of the insulating layer 110 on the semiconductor layer 108 side, the channel length L100 of the transistor 100 may become shorter than the length of the side surface of the insulating layer 110b, making it difficult to control the channel length L100. Therefore, it is preferable that the upper surface shape of the conductive layer 112b and the upper surface shape of the insulating layer 110 are the same or approximately the same. Alternatively, it is preferable that the insulating layer 110 encompasses the conductive layer 112b in a plan view.

[0194] The channel width of transistor 100 is the length of the region where the channel formation area in the semiconductor layer 108 and the conductive layer 104 overlap in a plan view. In Figure 5B, the channel width W100 of transistor 100 is shown by the double-headed arrow.

[0195] When forming the semiconductor layer 108 and the conductive layer 104 using lithography, the channel width W100 is greater than or equal to the limiting resolution of the exposure apparatus. The channel width W100 can be, for example, 20 nm or more and less than 500 μm, 50 nm or more and 200 μm or less, 100 nm or more and 100 μm or less, 200 nm or more and 50 μm or less, 500 nm or more and 20 μm or less, 1 μm or more and 10 μm or less, or 1 μm or more and 5 μm or less.

[0196] In this explanation, we have used as an example a configuration in which the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel-forming region, but the present invention is not limited to this. The region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel-forming region. Similarly, the region in contact with the insulating layer 110c may also function as a channel-forming region.

[0197] [Conductive layer 112a, conductive layer 112b, conductive layer 104] Conductive layer 112a, conductive layer 112b, and conductive layer 104 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for conductive layer 112a, conductive layer 112b, and conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive layers 112a, conductive layer 112b, and conductive layer 104 can preferably be conductive materials with low electrical resistivity that include one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred because they are easy to mass-produce.

[0198] Oxide conductors can be used for conductive layer 112a, conductive layer 112b, and conductive layer 104, respectively. For details on oxide conductors, please refer to the above description.

[0199] Oxygen vacancies (V) in metal oxides with semiconductor properties Ｏ When hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has turned into a conductor can be called an oxide conductor.

[0200] The conductive layers 112a, 112b, and 104 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0201] A Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be applied to the conductive layer 112a, conductive layer 112b, and conductive layer 104, respectively. By using a Cu-X alloy film, processing can be performed by wet etching, thus reducing manufacturing costs.

[0202] The conductive layer 112a, conductive layer 112b, and conductive layer 104 may be made of the same material. Alternatively, at least one of them may be made of a different material.

[0203] The conductive layer 112a and the conductive layer 112b each have a region that is in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, if an easily oxidized metal (e.g., aluminum) is used for the conductive layer 112a or the conductive layer 112b, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 112a or the conductive layer 112b and the semiconductor layer 108, which may hinder conductivity. Therefore, it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor for the conductive layer 112a and the conductive layer 112b.

[0204] For conductive layers 112a and 112b, it is preferable to use materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel, respectively. These are preferred because they are conductive materials that are resistant to oxidation, or materials that maintain low electrical resistance even when oxidized. Furthermore, if conductive layer 112a or conductive layer 112b has a laminated structure, it is preferable to use a conductive material that is resistant to oxidation in at least the layer in contact with the semiconductor layer 108.

[0205] The aforementioned oxide conductors can be used for conductive layer 112a and conductive layer 112b, respectively. Specifically, oxide conductors such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, silicon-containing In-Sn oxide, and gallium-doped zinc oxide can be used. In particular, oxide conductors containing indium have high conductivity and are therefore suitable for use in conductive layer 112a and conductive layer 112b.

[0206] Nitride conductors can also be used for conductive layers 112a and 112b, respectively. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0207] [Insulating layer 106] The insulating layer 106 preferably has one or more inorganic insulating layers. The insulating layer 106 can be made of the same material that can be used for the insulating layer 110.

[0208] The insulating layer 106 has regions that are in contact with the semiconductor layer 108, insulating layer 118, insulating layer 116, and conductive layer 104. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least the film constituting the insulating layer 106 that is in contact with the semiconductor layer 108 uses one of the aforementioned oxides and oxiditrides. When the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxiditride, or aluminum oxide can be suitably used for the insulating layer 106.

[0209] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxidized nitrides having aluminum and hafnium, oxides having silicon and hafnium, oxidized nitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0210] Although the insulating layer 106 is shown as a single layer in Figure 1B, etc., the present invention is not limited to this. The insulating layer 106 can also be a laminated structure of two or more layers.

[0211] When the insulating layer 106 has a laminated structure, it is preferable to use an oxide or oxidized nitride for the insulating layer on the semiconductor layer 108 side. For example, one or more of silicon oxide, silicon oxidized nitride, or aluminum oxide can be suitably used. Alternatively, nitrides or nitride oxides can be used. For example, aluminum nitride can be suitably used.

[0212] Preferably, one or more layers constituting the insulating layer 106 function as a barrier film. By providing a barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the insulating layer 110b into the conductive layer 104 side via the insulating layer 106. As a result, the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108 increases, reducing oxygen deficiencies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized. In addition, oxidation of the conductive layer 104 by oxygen contained in the insulating layer 110b and the resulting increase in the electrical resistance of the conductive layer 104 can be suppressed. As a result, a transistor exhibiting good electrical characteristics and high reliability can be realized. The aforementioned materials can be used as the barrier film. For example, silicon nitride, aluminum oxide, and one or more of the aluminum nitride can be suitably used in one or more of the layers constituting the insulating layer 106.

[0213] [Insulating layer 116] It is preferable to use an insulating material that can suppress oxygen permeation (an insulating material having barrier properties against oxygen) for the insulating layer 116. The insulating layer 116 can be made from the same materials that can be used for the insulating layer 110a and insulating layer 110c described above.

[0214] For the insulating layer 116, one or more of the following can be suitably used: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, aluminum nitride, silicon nitride, and silicon nitride oxide.

[0215] The insulating layer 116 can also be a laminated structure. For example, the insulating layer 116 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0216] The thickness of the insulating layer 116 is preferably about the same as the thickness of the insulating layer 110a or insulating layer 110c described above. For example, the thickness of the insulating layer 116 is preferably 3 nm to 500 nm, more preferably 5 nm to 400 nm, more preferably 10 nm to 300 nm, more preferably 20 nm to 300 nm, more preferably 50 nm to 300 nm, more preferably 100 nm to 300 nm, and more preferably 100 nm to 200 nm.

[0217] The thickness of the insulating layer 116 is preferably such that it functions as a barrier film against oxygen. If the insulating layer 116 is too thick, the amount of impurities (e.g., water and hydrogen) released from the insulating layer 116 increases, and the amount of impurities that diffuse into the channel formation region of the semiconductor layer 108 via the insulating layer 106 may increase. On the other hand, if the insulating layer 116 is too thin, its function as a barrier film against oxygen may be reduced. By setting the thickness of the insulating layer 116 within the aforementioned range, an insulating layer with sufficient barrier properties against oxygen can be obtained without increasing the amount of impurities that diffuse into the channel formation region of the semiconductor layer 108. Note that the thickness of the insulating layer 116 is not limited to the aforementioned range.

[0218] [Insulating layer 118] It is preferable to use an insulating material that contains oxygen and can release oxygen for the insulating layer 118. The insulating layer 118 can be made from the same material that can be used for the insulating layer 110b described above.

[0219] For example, silicon oxide and silicon oxide nitride, or both, can be suitably used for the insulating layer 118.

[0220] It is more preferable to use a material that releases oxygen when heat is applied for the insulating layer 118. During the manufacturing process of the semiconductor device 10, the heat applied causes the insulating layer 118 to release oxygen, thereby supplying oxygen to the semiconductor layer 108. As mentioned above, the insulating layer 118 is in contact with the region of the semiconductor layer 108 that is not in contact with the insulating layer 110 (outside the opening 145). Therefore, oxygen deficiencies in the semiconductor layer 108 in that region, which cannot be fully repaired by oxygen supply from the insulating layer 110 alone (V Ｏ The region in the semiconductor layer 108 that is not supplied with oxygen can be repaired by supplying oxygen from the insulating layer 118. This significantly reduces the area of ​​the region in the semiconductor layer 108 that is not supplied with oxygen, thereby enabling the realization of a transistor 100 that exhibits good electrical characteristics and is highly reliable.

[0221] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates can be used as the substrate 102. In addition, a substrate on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0222] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0223] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, and does not concern itself with elasticity or the ability to restore to its original shape.

[0224] For example, flexible electronic devices can deform in response to external forces. Flexible electronic devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Similarly, flexible display devices (also called flexible display devices, flexible display devices, flexible displays, etc.) can deform in response to external forces. Flexible display devices can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Furthermore, flexible substrates (also called flexible substrates, flexible substrates, etc.) can deform in response to external forces. Flexible substrates can be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. Note that "deforms in response to external forces" above means that it can be deformed by an average adult's hand without requiring excessive force. Note that flexibility can be quantified as the deformation of an object in response to an external force using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.).

[0225] Furthermore, in this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that do not have flexibility (also called rigid parts).

[0226] Furthermore, in this specification, a highly flexible object is defined as the object that deforms more when two objects are deformed with the same external force. Also, when a first part and a second part of an object are deformed with the same external force, the part that deforms more is considered to be the highly flexible part.

[0227] The following describes a semiconductor device configuration example that differs in some aspects from the previously described configuration example. Note that in the following, explanations of parts that overlap with the previously described configuration example may be omitted. Also, in the drawings shown below, parts having the same function as the previously described configuration example may use the same hatching pattern and may not be labeled with reference numerals.

[0228] <Configuration Example 2> Figure 6A shows a plan view of a semiconductor device 10A, which is one embodiment of the present invention. Figure 6B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 6A, and Figure 6C shows a cross-sectional view along the dashed line B1-B2.

[0229] Figure 7A shows a perspective view of the semiconductor device 10A. Figure 7B shows a perspective view of the structure obtained by omitting the conductive layer 104 and the insulating layer 106 from the semiconductor device 10A shown in Figure 7A. Figure 8 shows a perspective view of the structure obtained by separating the semiconductor layer 108, the insulating layer 118, and the insulating layer 116 from the structure shown in Figure 7B.

[0230] The semiconductor device 10A includes a transistor 100A, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The semiconductor device 10A mainly differs from the semiconductor device 10 shown in Figure 1B, etc., in that the insulating layer 116 is in contact with the upper surface of the insulating layer 110. In Figure 6A, the opening corresponding to the opening 145 (see Figure 1A) in the semiconductor device 10 is shown as opening 146.

[0231] Figure 8 and others show a configuration in which the upper surface shape of the conductive layer 112b does not match the upper surface shape of the insulating layer 110. A portion of the edge of the conductive layer 112b is in contact with the upper surface of the insulating layer 110. The insulating layer 110 has a region that protrudes more than the conductive layer 112b. In a plan view, it is preferable that the insulating layer 110 encompasses the conductive layer 112b. As shown in Figure 8 and others, the insulating layer 110 has a region on its upper surface where the conductive layer 112b is provided and a region where the conductive layer 112b is not provided. In the region where the conductive layer 112b is not provided, the insulating layer 116 is in contact with the upper surface of the insulating layer 110.

[0232] For example, an insulating film to become an insulating layer 110 is formed, island-shaped conductive layers to become a conductive layer 112b are formed on the insulating film, and a mask layer (for example, a resist mask) is formed on the conductive layer and the insulating film. Then, the conductive layer 112b and the insulating layer 110 can be formed by processing the conductive layer and the insulating film using the mask layer as a mask. It is preferable that there is no step between the side surface of the conductive layer 112b on the semiconductor layer 108 side and the side surface of the insulating layer 110 on the semiconductor layer 108 side, and that they are flat (i.e., the two surfaces coincide or roughly coincide). However, it is also possible to have a configuration in which the side surface of the conductive layer 112b on the semiconductor layer 108 side and the side surface of the insulating layer 110 on the semiconductor layer 108 side are discontinuous.

[0233] By forming the insulating layer 110 using a different mask layer than the conductive layer 112b, the degree of freedom in the layout of the insulating layer 110 can be increased. For example, by increasing the area on which the insulating layer 110 is provided, the amount of oxygen supplied from the insulating layer 110 (e.g., insulating layer 110b) to the semiconductor layer 108 can be increased. This reduces oxygen vacancies (V) in the channel formation region. Ｏ ) and V Ｏ H can be reduced.

[0234] Furthermore, while Figure 7A and other figures show a configuration in which one transistor (here, transistor 100A) is provided on the insulating layer 110, the present invention is not limited to this. Multiple transistors can also be provided on the insulating layer 110. For example, multiple transistors can be provided by providing multiple semiconductor layers on the side surface of the insulating layer 110 on which the semiconductor layer 108 is provided. Also, for example, a transistor having a semiconductor layer can be provided not only on the above-mentioned side surface, but also on a side surface of the insulating layer 110 that is in contact with the above-mentioned side surface.

[0235] In the case where the semiconductor device 10A does not have an insulating layer 116, the area of ​​the insulating layer 110 on the side where the semiconductor layer 108 is provided will be exposed, except for a portion of the area in contact with the semiconductor layer 108 (in Figure 8, this area is marked with a hatching pattern). As a result, oxygen contained in the insulating layer 110 (oxygen that could not be supplied to the semiconductor layer 108) can be released to the outside from this exposed area. In contrast, in the case of the semiconductor device 10A according to one embodiment of the present invention, the presence of the insulating layer 116 suppresses the release of oxygen from the area of ​​the insulating layer 110 that is not in contact with the semiconductor layer 108. Furthermore, the presence of the insulating layer 118 allows oxygen to be supplied to the area of ​​the semiconductor layer 108 that is not in contact with the insulating layer 110 (the area located outside the opening 146). Therefore, a transistor 100A that exhibits good electrical characteristics and is highly reliable can be realized.

[0236] Regarding semiconductor device 10A, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0237] <Configuration Example 3> Figure 9A shows a plan view of a semiconductor device 10B, which is one embodiment of the present invention. Figure 9B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 9A, and Figure 9C shows a cross-sectional view along the dashed line B1-B2.

[0238] Figure 10A shows a perspective view of the semiconductor device 10B. Figure 10B shows a perspective view of the structure obtained by omitting the conductive layer 104 and the insulating layer 106 from the semiconductor device 10B shown in Figure 10A. Figure 11 shows a perspective view of the structure shown in Figure 10B, with the semiconductor layer 108, insulating layer 118, and insulating layer 116 separated and displayed.

[0239] The semiconductor device 10B includes a transistor 100B, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The semiconductor device 10B differs from the semiconductor device 10 shown in Figure 1B, etc., in that the insulating layer 110 is divided by grooves (also called slits). In Figure 9A, the opening corresponding to the opening 145 in the semiconductor device 10 (see Figure 1A) is shown as opening 147.

[0240] The insulating layer 110 has a slit 137 that reaches the conductive layer 112a and the insulating layer 109. As shown in Figure 9B, the insulating layer 110 has a pair of sides (side A1 and side A2) facing each other across the slit 137. Both sides include a portion located on the conductive layer 112a and a portion located on the insulating layer 109.

[0241] A conductive layer 112b and a conductive layer 112bS are provided on the insulating layer 110. The conductive layer 112bS is the portion of the conductive layer 112b that remains after being separated during the formation of the slit 137. The conductive layer 112b is provided on the insulating layer 110 on the A2 side, and the conductive layer 112bS is provided on the insulating layer 110 on the A1 side. It is also possible to have a configuration in which the conductive layer 112bS is not provided.

[0242] The semiconductor layer 108 has regions that are in contact with the upper and side surfaces of the insulating layer 118, the side surfaces of the insulating layer 116, the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the conductive layer 112bS, the A2 side surface of the insulating layer 110, the A1 side surface of the insulating layer 110, and the upper surface of the conductive layer 112a. The semiconductor layer 108 has a shape that conforms to the shapes of the upper and side surfaces of the insulating layer 118, the side surfaces of the insulating layer 116, the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the conductive layer 112bS, the A2 side surface of the insulating layer 110, the A1 side surface of the insulating layer 110, and the upper surface of the conductive layer 112a. The semiconductor layer 108 is provided spanning a region on the conductive layer 112a where the insulating layer 110 is provided and a region on the conductive layer 112a where the insulating layer 110 is not provided. Furthermore, the semiconductor layer 108 is provided not only on the A2 side of the insulating layer 110, but also on the A1 side of the insulating layer 110.

[0243] An insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. The conductive layer 104 has a region that faces the A2 side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108. The conductive layer 104 also has a region that faces the A1 side surface of the insulating layer 110 via the insulating layer 106 and the semiconductor layer 108. Note that the conductive layer 112bS does not contact the conductive layer 112b and is not connected to either the source electrode or the drain electrode, so the region of the semiconductor layer 108 that is in contact with the A1 side surface of the insulating layer 110 does not function as a channel formation region of transistor 100B. The region of the semiconductor layer 108 that is in contact with the A2 side surface of the insulating layer 110 functions as a channel formation region of transistor 100B.

[0244] It is preferable that the conductive layer 104 covers not only the channel formation region but also the entire semiconductor layer 108. This helps to suppress damage to the semiconductor layer 108 when the layer is formed on the transistor 100B. However, it is also possible to have a configuration in which the semiconductor layer 108 has regions that are not covered by the conductive layer 104.

[0245] Figure 9A and others show a configuration in which the insulating layer 110 is divided into two by a slit 137 extending in one direction. The shape of the upper surface of the slit 137 is not particularly limited.

[0246] Figure 9A and other figures show a configuration in which one transistor (here, transistor 100B) is provided on the insulating layer 110, but the present invention is not limited to this. Multiple transistors can also be provided on the insulating layer 110. For example, multiple transistors can be provided by providing multiple semiconductor layers on the A2 side of the semiconductor layer 108 of the insulating layer 110.

[0247] In this case, if the semiconductor device 10B does not have an insulating layer 116, then the area of ​​the insulating layer 110 on the side where the semiconductor layer 108 is provided will be exposed, except for a portion of the area in contact with the semiconductor layer 108 (in Figure 11, this area is marked with a hatching pattern). As a result, oxygen contained in the insulating layer 110 (oxygen that could not be supplied to the semiconductor layer 108) may be released to the outside from this exposed area. In contrast, in the case of the semiconductor device 10B according to one embodiment of the present invention, the presence of the insulating layer 116 suppresses the release of oxygen from the area of ​​the insulating layer 110 that is not in contact with the semiconductor layer 108. Furthermore, the presence of the insulating layer 118 allows oxygen to be supplied to the area of ​​the semiconductor layer 108 that is not in contact with the insulating layer 110 (the area located outside the opening 147). Therefore, a transistor 100B that exhibits good electrical characteristics and is highly reliable can be realized.

[0248] Regarding semiconductor device 10B, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0249] <Configuration Example 4> A plan view of a semiconductor device 10C, which is one embodiment of the present invention, is shown in Figure 12A. A cross-sectional view along the dashed line A1-A2 shown in Figure 12A is shown in Figure 12B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 12C.

[0250] Figure 13A shows a perspective view of the semiconductor device 10C. Figure 13B shows a perspective view of the structure obtained by omitting the conductive layer 104 and the insulating layer 106 from the semiconductor device 10C shown in Figure 13A. Figure 14 shows a perspective view of the structure obtained by separating the semiconductor layer 108, the insulating layer 118, and the insulating layer 116 from the structure shown in Figure 13B.

[0251] The semiconductor device 10C includes a transistor 100C, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The semiconductor device 10C mainly differs from the semiconductor device 10 shown in Figure 1B, etc., in that the conductive layer 112b and the insulating layer 110 have openings. In Figure 12A, the opening corresponding to the opening 145 in the semiconductor device 10 (see Figure 1A) is shown as opening 148.

[0252] The conductive layer 112b and the insulating layer 110 have an opening 141 that reaches the conductive layer 112a. The opening 141 includes an opening in the conductive layer 112b and an opening in the insulating layer 110. It can also be said that the side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a are exposed at the opening 141.

[0253] In a plan view, the semiconductor layer 108 is provided such that it has a region that overlaps with the opening 141.

[0254] An insulating layer 106 is provided on the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106. The semiconductor layer 108, the insulating layer 106, and the conductive layer 104 each have a region located within the opening 141.

[0255] Figure 12A and others show that the top surface shape of the opening 141 is a quadrilateral with rounded corners, but the present invention is not limited to this. The top surface shape of the opening 141 is not limited and can be a circular, elliptical, triangular, quadrilateral (including rectangles, rhombuses, and squares), pentagon, or any of these polygons with rounded corners. The polygon can be either a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are 180 degrees or less). By making the top surface shape of the opening 141 circular, the processing accuracy when forming the opening 141 can be improved, and a fine-sized opening 141 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0256] The opening 141 is provided only in the semiconductor layer 108 and its vicinity, while the insulating layer 110 is provided in the remaining areas. Therefore, the area of ​​the region where the insulating layer 110 is provided can be increased, and the unevenness caused by the difference between the region where the insulating layer 110 is provided and the region where it is not can be reduced. As a result, the coverage of the layer provided on the transistor 100C and the insulating layer 110 can be improved, and defects such as step breaks or porosity in the layer can be suppressed.

[0257] In the case where the semiconductor device 10C does not have an insulating layer 116, the area of ​​the insulating layer 110 on the side where the semiconductor layer 108 is provided will be exposed, except for a portion of the area in contact with the semiconductor layer 108 (in Figure 14, this area is marked with a hatching pattern). As a result, oxygen contained in the insulating layer 110 (oxygen that could not be supplied to the semiconductor layer 108) can be released to the outside from this exposed area. In contrast, in the case of the semiconductor device 10C according to one aspect of the present invention, the presence of the insulating layer 116 suppresses the release of oxygen from the area of ​​the insulating layer 110 that is not in contact with the semiconductor layer 108. Furthermore, the presence of the insulating layer 118 allows oxygen to be supplied to the area of ​​the semiconductor layer 108 that is not in contact with the insulating layer 110 (the area located outside the opening 148). Therefore, a transistor 100C that exhibits good electrical characteristics and is highly reliable can be realized.

[0258] Furthermore, in semiconductor device 10C, the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are stacked in this order against the two sides (the side on the A1 side and the side on the A2 side) of the insulating layer 110 within the opening 141. Therefore, the transistor 100C in semiconductor device 10C can output twice the on-current compared to the transistor 100 in semiconductor device 10, the transistor 100A in semiconductor device 10A, etc.

[0259] Regarding semiconductor device 10C, for details other than those mentioned above, please refer to the content described for semiconductor device 10.

[0260] <Configuration Example 5> A plan view of a semiconductor device 10D, which is one embodiment of the present invention, is shown in Figure 15A. A cross-sectional view along the dashed line A1-A2 shown in Figure 15A is shown in Figure 15B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 15C.

[0261] The semiconductor device 10D includes a transistor 100D, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The semiconductor device 10D differs from the semiconductor device 10 shown in Figure 1B, etc., in that the upper surface shape of the insulating layer 118 does not match or substantially match the upper surface shape of the semiconductor layer 108.

[0262] As shown in Figures 15B and 15C, in the semiconductor device 10D, the insulating layer 118 has a configuration that covers the entire upper surface of the insulating layer 116. That is, in the semiconductor device 10D, the area where the insulating layer 118 is formed is much larger than the area where the insulating layer 118 is formed in the semiconductor device 10. Therefore, in the semiconductor device 10D, the amount of oxygen that the entire insulating layer 118 can have can be increased much more than in the semiconductor device 10. Consequently, more oxygen can be supplied to the area of ​​the semiconductor layer 108 that is not in contact with the insulating layer 110 (the area located outside the opening 145) than in the semiconductor device 10D.

[0263] In semiconductor device 10D, an insulating layer 106 is provided along the entire upper surface of the insulating layer 118. Therefore, oxygen contained in the insulating layer 118 (oxygen not supplied to the semiconductor layer 108) diffuses through the insulating layer 106, and depending on the material of the conductive layer 104, it may oxidize the conductive layer 104. Consequently, if sufficient oxygen is supplied from the insulating layer 118 to the semiconductor layer 108, it may be better to have a configuration like semiconductor device 10, where the upper surface of the insulating layer 118 is in contact only with the lower surface of the semiconductor layer 108.

[0264] Regarding semiconductor device 10D, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0265] <Configuration Example 6> A plan view of a semiconductor device 10E, which is one embodiment of the present invention, is shown in Figure 16A. A cross-sectional view along the dashed line A1-A2 shown in Figure 16A is shown in Figure 16B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 16C.

[0266] The semiconductor device 10E includes a transistor 100E, an insulating layer 109, an insulating layer 110, and an insulating layer 116. The semiconductor device 10E mainly differs from the semiconductor device 10 shown in Figure 1B, etc., in that it does not have an insulating layer 118.

[0267] As shown in Figures 16B and 16C, the semiconductor device 10E has a configuration in which the region located outside the opening 145 of the semiconductor layer 108 is in contact with the upper surface of the insulating layer 116. Depending on the material used for the semiconductor layer 108, it may not always be necessary to provide an insulating layer 118, as in the semiconductor device 10E. For example, when silicon is used as the material for the semiconductor layer 108, the configuration of the semiconductor device 10E can be applied. Furthermore, even when a metal oxide is used as the material for the semiconductor layer 108, the original oxygen vacancies (V) in the metal oxide can be addressed. Ｏ ) and V Ｏ When the amount of H is extremely low and the material is close to a highly pure intrinsic state, the configuration of semiconductor device 10E can be applied. Since semiconductor device 10E has this configuration, there is no need to provide an insulating layer 118, thus reducing the number of manufacturing steps compared to semiconductor device 10.

[0268] Regarding semiconductor device 10E, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0269] <Configuration Example 7> A plan view of a semiconductor device 10F, which is one embodiment of the present invention, is shown in Figure 17A. A cross-sectional view along the dashed-dotted line A1-A2 shown in Figure 17A is shown in Figure 17B, and a cross-sectional view along the dashed-dotted line B1-B2 is shown in Figure 17C.

[0270] The semiconductor device 10F includes a transistor 100F, an insulating layer 109, an insulating layer 110, and an insulating layer 116. The semiconductor device 10F differs from the semiconductor device 10E shown in Figure 16B, etc., mainly in the shape of the semiconductor layer 108 in a plan view.

[0271] As shown in Figures 17A to 17C, in semiconductor device 10F, the semiconductor layer 108 does not cover the entire opening 145, and the semiconductor layer 108 has a smaller width in the Y direction compared to semiconductor device 10E. Therefore, in the Y direction, there is no region located outside the opening 145 of the semiconductor layer 108 (a region where oxygen supply from the insulating layer 110 may be insufficient), and thus leakage current between the source and drain of transistor 100F can be suppressed through this region.

[0272] Furthermore, in a plan view, the area of ​​the opening 145 that does not overlap with the semiconductor layer 108 has an exposed side surface of the insulating layer 110 (not covered by the insulating layer 116), so there is a possibility that some of the oxygen contained in the insulating layer 110 may diffuse from that area into the insulating layer 106. However, since the side surface of the insulating layer 110 excluding the above area is covered by the insulating layer 116, even if the above-mentioned oxygen diffusion occurs, its effect is extremely small. Therefore, even with a configuration like the semiconductor device 10F, it is sometimes possible to realize a transistor 100F that exhibits good electrical characteristics and is highly reliable. Also, as with the semiconductor device 10E described above, the material used for the semiconductor layer 108 is limited (originally oxygen vacancies in the metal oxide (V Ｏ ) and V Ｏ It is not necessary to use a material that has an extremely low H content and is close to a high-purity intrinsic state. Therefore, compared to semiconductor device 10E, this also has the effect of broadening the range of material selection for the semiconductor layer 108.

[0273] Regarding semiconductor device 10F, for details other than those described above, please refer to the descriptions provided for semiconductor device 10 and semiconductor device 10E, respectively.

[0274] <Configuration Example 8> Figure 18A shows a plan view of a semiconductor device 10G, which is one embodiment of the present invention. Figure 18B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 18A, and Figure 18C shows a cross-sectional view along the dashed line B1-B2.

[0275] The semiconductor device 10G includes a transistor 100G, an insulating layer 109, an insulating layer 110, and an insulating layer 116. The semiconductor device 10G differs from the semiconductor device 10E shown in Figure 16B, etc., and the semiconductor device 10F shown in Figure 17B, etc., mainly in the shape of the semiconductor layer 108 in a plan view.

[0276] As shown in Figures 18A to 18C, in the semiconductor device 10G, the semiconductor layer 108 does not cover the entire opening 145, and the semiconductor layer 108 has a smaller width in both the X and Y directions compared to the semiconductor device 10E. This configuration allows the semiconductor device 10G to reduce the area in contact between the semiconductor layer 108 and the insulating layer 116 compared to the semiconductor device 10E. Therefore, the area of ​​the region in the semiconductor layer 108 where oxygen is not supplied can be reduced compared to the semiconductor device 10E.

[0277] Furthermore, in semiconductor device 10G, the area of ​​the semiconductor layer 108 is smaller than that of semiconductor device 10F, and in a plan view, the semiconductor layer 108 is contained within the opening 145. Therefore, in semiconductor device 10G, unlike semiconductor devices 10E and 10F, there is no region where the semiconductor layer 108 overlaps the insulating layer 116. Consequently, the coverage of a film (such as the insulating layer 106) whose surface is the upper surface of the semiconductor layer 108 and the upper surface of the insulating layer 116 can be improved.

[0278] Regarding semiconductor device 10G, for details other than those described above, you can refer to the contents described for semiconductor device 10, semiconductor device 10E, and semiconductor device 10F, respectively.

[0279] <Configuration Example 9> Figure 19A shows a plan view of a semiconductor device 10H, which is one embodiment of the present invention. Figure 19B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 19A, and Figure 19C shows a cross-sectional view along the dashed line B1-B2.

[0280] The semiconductor device 10H includes a transistor 100H, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The semiconductor device 10H differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in the shape of the insulating layer 110 and the conductive layer 112b in a plan view.

[0281] As shown in Figures 19A to 19C, in the semiconductor device 10H, compared to the semiconductor device 10, the width of the island-shaped insulating layer 110 and conductive layer 112b in the Y direction is smaller, and in a plan view, the opening 145 and the semiconductor layer 108 are arranged to overlap with one corner of the insulating layer 110 and conductive layer 112b (a corner with an interior angle greater than 0 degrees and less than 180 degrees in a plan view). The above corner can also be rounded.

[0282] Because the semiconductor device 10H has the above-described configuration, the semiconductor layer 108 has a region that contacts two sides of the insulating layer 110 corresponding to the corners (i.e., the side shown in Figure 19B and the side on the B2 side shown in Figure 19C). Therefore, in the semiconductor device 10H, the region of the semiconductor layer 108 that contacts these two sides can function as a channel formation region for the transistor 100H.

[0283] In transistor 100H, in a plan view, the lengths of the two sides that overlap with the semiconductor layer 108 correspond to the channel width of the transistor. Therefore, the widths in the Y direction of the conductive layers 112a and 112b, which function as the source and drain electrodes of transistor 100H, can be made shorter than those of transistor 100 (Figure 19A shows a configuration where the width in the Y direction of conductive layer 112a is the same as in Figure 1A, and the width in the Y direction of conductive layer 112b is shorter than that of transistor 1A). Consequently, the area occupied in a plan view of a transistor with the same channel width can be reduced compared to transistor 100.

[0284] In semiconductor device 10H, the opening 145 and semiconductor layer 108 overlap with only one corner of the insulating layer 110 and conductive layer 112b in a plan view, but this is not limited to this configuration. In one embodiment of the present invention, the opening 145 and semiconductor layer 108 can also overlap with the adjacent corner on the Y-direction side of the aforementioned corner in a plan view. For example, the semiconductor layer 108 can be configured to be in contact with the side shown in Figure 19B, the side shown in Figure 19C on the B2 side, and the side shown in Figure 19C on the B1 side in a cross-sectional view. This makes it possible to increase the channel width of the transistor (i.e., increase the on-current of the transistor) without changing the size of each electrode constituting the transistor (source electrode, drain electrode, and gate electrode) in a plan view.

[0285] Regarding semiconductor device 10H, for details other than those described above, please refer to the information provided for semiconductor device 10.

[0286] <Configuration Example 10> A plan view of a semiconductor device 10I, which is one aspect of the present invention, is shown in Figure 20A. A cross-sectional view along the dashed line A1-A2 shown in Figure 20A is shown in Figure 20B, and a cross-sectional view along the dashed line B1-B2 is shown in Figure 20C.

[0287] The semiconductor device 10I includes a transistor 100I, an insulating layer 109, an insulating layer 110, an insulating layer 116, and an insulating layer 118. The semiconductor device 10I differs from the semiconductor device 10 shown in Figure 1B, etc., mainly in the shape of the insulating layer 110 and the conductive layer 112b in a plan view.

[0288] As shown in Figures 20A to 20C, the semiconductor device 10I has an island-like arrangement of insulating layer 110 and conductive layer 112b, which have a concave polygonal shape. In a plan view, the opening 145 and the semiconductor layer 108 are arranged to overlap with one corner of the insulating layer 110 and the conductive layer 112b, respectively (a corner with an interior angle greater than 180 degrees and less than 360 degrees in a plan view). The corner can also be rounded.

[0289] Because the semiconductor device 10I has the above-described configuration, the semiconductor layer 108 has a region that is in contact with two sides of the insulating layer 110 that correspond to the corners (i.e., the side shown in Figure 20B and the side closest to B1 shown in Figure 20C). Therefore, in the semiconductor device 10I, the region of the semiconductor layer 108 in contact with the two sides can function as a channel formation region for the transistor 100I.

[0290] In transistor 100I, in a plan view, the lengths of the two sides that overlap with the semiconductor layer 108 correspond to the channel width of the transistor. Therefore, the widths in the Y direction of the conductive layers 112a and 112b, which function as the source electrode and drain electrode of transistor 100I, can be made shorter than those of transistor 100 (Figure 20A shows a configuration in which both conductive layers 112a and 112b have the same width in the Y direction as in Figure 1A). Consequently, the area occupied in a plan view of a transistor with the same channel width can be reduced compared to transistor 100.

[0291] In semiconductor device 10I, the opening 145 and semiconductor layer 108 overlap with only one corner of the insulating layer 110 and conductive layer 112b in a plan view, but this is not limited to this configuration. In one embodiment of the present invention, similar to semiconductor device 10H described above, the opening 145 and semiconductor layer 108 can also overlap with the corner adjacent to the aforementioned corner in a plan view.

[0292] Regarding semiconductor device 10I, for details other than those described above, please refer to the content described for semiconductor device 10.

[0293] <Configuration Example 11> Figure 21A shows a plan view of a semiconductor device 10J, which is one embodiment of the present invention. Figure 21B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 21A, and Figure 21C shows a cross-sectional view along the dashed line B1-B2.

[0294] The semiconductor device 10J includes transistor 100J1, transistor 100J2, insulating layer 109, insulating layer 110, insulating layer 116, and insulating layer 118. The semiconductor device 10J differs from the semiconductor device 10B shown in Figure 9B, etc., in that it has two transistors.

[0295] As shown in Figures 21A and 21C, in semiconductor device 10J, the A1-side end of the conductive layer 112b extends further than that of semiconductor device 10B, and is provided to have a region that overlaps with the slit 137 in a plan view. As a result, in semiconductor device 10J, the regions in contact between the two opposing sides of the insulating layer 110 shown in Figure 21B and the semiconductor layer 108 can each function as channel formation regions for transistors. Of these, the transistor that uses the region of the semiconductor layer 108 in contact with the A2-side side of the insulating layer 110 as the channel formation region is shown as transistor 100J1, and the transistor that uses the region of the semiconductor layer 108 in contact with the A1-side side of the insulating layer 110 as the channel formation region is shown as transistor 100J2.

[0296] Transistors 100J1 and 100J2 are transistors that share various components, such as source electrodes, drain electrodes, semiconductor layers, gate insulating layers, and gate electrodes. That is, in semiconductor device 10J, conductive layer 112a functions as either the source electrode or the drain electrode of transistors 100J1 and 100J2. Conductive layer 112b functions as the other source electrode or drain electrode of transistors 100J1 and 100J2. Semiconductor layer 108 functions as a semiconductor layer having channel-forming regions for transistors 100J1 and 100J2. Insulating layer 106 functions as the gate insulating layer for transistors 100J1 and 100J2. Conductive layer 104 functions as the gate electrode for transistors 100J1 and 100J2.

[0297] In other words, the semiconductor device 10J, like the semiconductor device 10B, has a configuration in which the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are stacked in this order against the two sides (the side on the A1 side and the side on the A2 side) of the insulating layer 110 within the slit 137. However, in the semiconductor device 10B, only the region of the semiconductor layer 108 in contact with the side on the A2 side of the insulating layer 110 functions as the channel formation region of the transistor (transistor 100B), whereas in the semiconductor device 10J, both the region of the semiconductor layer 108 in contact with the side on the A1 side of the insulating layer 110 and the region of the semiconductor layer 108 in contact with the side on the A2 side of the insulating layer 110 function as the channel formation regions of the transistors (transistor 100J2 and transistor 100J1, respectively). Therefore, the on-current of the transistors in the semiconductor device 10J can be doubled compared to the semiconductor device 10B.

[0298] Regarding semiconductor device 10J, for details other than those described above, please refer to the descriptions provided for semiconductor device 10 and semiconductor device 10B, respectively.

[0299] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0300] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0301] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0302] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0303] The carrier concentration dependence of the hole (Hall) mobility of indium oxide, silicon, and IGZO is described. Figure 22A shows silicon (Si) and indium oxide (InO Ｘ Figure 22B is a schematic diagram of the carrier concentration dependence of hole mobility for IGZO.

[0304] First, as indicated by the arrows in Figure 22B, IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, as indicated by the arrows in Figure 22A, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases (see Non-Patent Literature 1). This trend is similar to that of silicon, where the lower the concentration of dopants (impurities) in the material, the less impurity scattering occurs and the higher the hole mobility. In other words, the higher the purity and intrinsic nature of indium oxide, the higher its hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that the properties of indium oxide shown in Figure 22A are assumed to be those of a single crystal. Therefore, when indium oxide is not a single crystal (for example, polycrystalline), the properties may differ from those shown in Figure 22A.

[0305] In Figure 22A, the low carrier concentration range R1 exhibits extremely high hole mobility, making it a suitable carrier concentration range for, for example, the channel formation region of a transistor. For example, in the case of indium oxide, the range R1 has a carrier concentration of 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0306] Furthermore, in indium oxide, the region where the carrier concentration is within the range R1 may contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Other elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0307] On the other hand, the range R2 with high carrier concentration has low electrical resistance and can be said to be a suitable range of carrier concentration for applications such as the source and drain regions of a transistor, or for resistors or transparent conductive films. The range R2 is when the carrier concentration value is 1 × 10⁻⁶. ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0308] Furthermore, in the indium oxide, the region where the carrier concentration is in the range R2 may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use elements in which the oxide is conductive or semiconducting.

[0309] In this way, indium oxide uses regions with low carrier concentrations for the transistor's channel formation region and regions with high carrier concentrations for the transistor's source and drain regions. In other words, indium oxide can be said to be an oxide in which valence electron control is possible. In contrast, with IGZO, strain may be formed in the source and drain regions due to stress on the electrodes in contact with IGZO, and an n-type region may be formed. On the other hand, unlike IGZO, indium oxide allows for valence electron control, so it does not require strain to be formed in the film as in IGZO. Less strain in the film is expected to improve reliability. For example, by creating regions with carrier concentrations in the range R1 and range R2 shown in Figure 22A within the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Valence electron control in silicon transistors is generally known. On the other hand, valence electron control in indium oxide transistors is a novel technological concept that would not normally be conceived.

[0310] By applying the above technical concept, the indium oxide transistor described herein has two or more, preferably three or more, more preferably four or more, and most preferably five of the following features (1) to (5): (1) High on-current (in other words, high mobility). (2) Low off-current. (3) Normally off is possible. (4) High reliability. (5) High cutoff frequency (fT). For example, the indium oxide transistor described herein has high mobility, low off-current, and is normally off. This transistor is different from a transistor that is high mobility and normally on.

[0311] Next, we will describe indium oxide films applied to transistors. Indium oxide films are preferably crystalline (i.e., they have crystal grains). Examples of films with crystal grains include single-crystal films, polycrystalline films, or amorphous films containing crystal grains (also called microcrystalline films). In particular, polycrystalline films are preferred for indium oxide films, and single-crystal films are more preferred. Single-crystal films do not have crystal grain boundaries. Impurities that inhibit carrier flow (typically insulating impurities, insulating oxides, etc.) tend to segregate at crystal grain boundaries. By using single-crystal films, carrier scattering at crystal grain boundaries can be suppressed, enabling the realization of transistors with high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by these crystal grain boundaries.

[0312] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline indium oxide film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which single-crystal indium oxide is applied.

[0313] The crystallinity of indium oxide can be analyzed, for example, by XRD, TEM, or ED. Alternatively, a combination of these methods may be used for analysis.

[0314] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel-forming region, a semiconductor layer in which the channel-forming region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel-forming region can be called a single crystal film. In addition, a semiconductor layer in which, within a single crystal grain in the channel-forming region, the direction of other crystal axes changes continuously with respect to a certain crystal axis or crystal orientation as the axis of rotation can be called a single crystal film.

[0315] The channel formation region refers to the region within the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0316] The indium oxide film in the channel-forming region is preferable to have a low impurity concentration. Impurities in the indium oxide film in the channel-forming region can act as a scattering source for carriers, and thus can cause a decrease in field-effect mobility. Furthermore, these impurities can also inhibit the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The concentration of these impurities in the indium oxide film is preferably 0.1% or less, and more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above-mentioned impurities.

[0317] Furthermore, the indium oxide film in the channel-forming region may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0318] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ It can be set to (V・s) or more.

[0319] As one of the characteristics of the indium oxide film, it can be mentioned that its oxygen permeability (diffusivity) is higher compared to the IGZO film. As shown in Fig. 22C, the oxygen (O) diffusing into the indium oxide film (denoted as InO Ｘ ) permeates through the indium oxide film and is released as oxygen molecules (O ２ ). Also, by reacting with the hydrogen contained in the film, it may be released as water molecules (H ２ O). When there is an oxygen deficiency (V Ｏ ) in the film, the diffusing oxygen atoms fill the oxygen deficiency. Since oxygen diffuses easily through the indium oxide film, it can be said that it is easier to fill oxygen deficiencies compared to the IGZO film. <�

[0320] Thus, since the indium oxide film is likely to reduce oxygen deficiencies in the film compared to the IGZO film, by applying such an indium oxide film to a transistor, a transistor showing extremely high reliability can be realized.

[0321] Also, as shown in Fig. 22C, the indium oxide film diffuses hydrogen. The hydrogen diffusing into the indium oxide film from the outside permeates through the indium oxide film and is released as hydrogen molecules (H ２ ). Or, by reacting with the oxygen contained in the film, it is released as water molecules.

[0322] A transistor using an indium oxide film is an accumulation-type transistor with electrons as the majority carriers. Assuming that the carrier relaxation time is a constant value, the smaller the effective mass of electrons (carriers), the higher the electron mobility. That is, by using indium oxide with a small effective mass of electrons in a transistor, the on-current or the field-effect mobility of the transistor can be increased. <00単0804> Table 1 shows single-crystal indium oxide (here, In ２ O ３)( ) and the effective masses of single-crystalline silicon (Si) are shown respectively. As shown in Table 1, indium oxide has the characteristics that the effective mass of electrons is small and the effective mass of holes is large. Also, the effective mass of electrons in indium oxide has the characteristic of hardly depending on the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with a high field-effect mobility and a transistor with high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with an extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm channel width is 1 fA (1×10 −１５ A) or less, or 1 aA (1×10 −１８ A) or less in an environment of 125°C, and 1 aA (1×10 −１８ A) or less, or 1 zA (1×10 −２１ A) or less in an environment of room temperature (25°C). Also, as shown in Table 1, since indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, there is a possibility of realizing a transistor with a higher field-effect mobility and a lower off-current than a transistor (hereinafter referred to as a Si transistor) using silicon in the semiconductor layer.

[0324]

[0325] It is preferable to provide a seed layer so as to contact at least a part of the crystalline indium oxide film. For the seed layer, it is preferable to use a material containing a crystal with a small difference in lattice constant (also called lattice mismatch) from indium oxide. Thereby, the crystallinity of the indium oxide film can be improved. Note that a substrate (for example, a single-crystalline substrate) may be used as one of the layers contacting at least a part of the crystalline indium oxide film.

[0326] As one method for evaluating the degree of lattice mismatch, there is a method using the value of lattice mismatch shown below. The lattice mismatch degree Δa [%] of the crystal of the forming film (here, the indium oxide film) with respect to the crystal of the seed layer is Δa = ((L １ −L ２ ) / L２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0327] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0328] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0329] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0330] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0331] (Embodiment 3) In this embodiment, a method for manufacturing a semiconductor device according to one aspect of the present invention will be described with reference to Figures 23A to 29B. Note that the description of the materials and formation methods of each element may be omitted if it is the same as that described in Embodiment 1.

[0332] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), atomic layer deposition (ALD), and other methods. CVD methods include plasma chemical vapor deposition (PECVD or plasma CVD) and thermal CVD. One type of thermal CVD is metal-organic chemical vapor deposition (MOCVD).

[0333] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, or knife coating.

[0334] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by film deposition methods using shielding masks such as metal masks.

[0335] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0336] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it enables extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0337] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0338] <Example of Manufacturing Method> Here, an example of a manufacturing method for the semiconductor device 10 shown in Figures 1A to 2A will be explained using Figures 23A to 29B. Figures 23A to 25D show a cross-sectional view between the dashed line A1 and A2 shown in Figure 1A. Figures 26A to 29B show perspective views corresponding to Figure 2A for each manufacturing step.

[0339] First, an insulating layer 109 is formed on the substrate 102. Sputtering or PECVD can be suitably used to form the insulating layer 109.

[0340] Next, a conductive film that will become the conductive layer 112a is formed on the insulating layer 109, and the conductive film is processed to form the conductive layer 112a (Figure 23A). A sputtering method can be suitably used to form the conductive film.

[0341] Next, an insulating film 110af, which will become the insulating layer 110a, and an insulating film 110bf, which will become the insulating layer 110b, are deposited on the conductive layer 112a in this order (Figure 23B).

[0342] Sputtering or PECVD methods can be suitably used to deposit the insulating film 110af and insulating film 110bf. It is preferable to deposit insulating film 110bf without exposing the surface of insulating film 110af to the atmosphere after depositing insulating film 110af. This suppresses the adhesion of airborne impurities to the surface of insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to deposit insulating film 110bf continuously using the same apparatus after depositing insulating film 110af.

[0343] The substrate temperature during the deposition of the insulating film 110af and insulating film 110bf is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. By setting the substrate temperature during the deposition of the insulating film 110af and insulating film 110bf within the above range, the amount of impurities (e.g., water and hydrogen) released from the film itself can be reduced, and the diffusion of impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be realized.

[0344] Furthermore, since the insulating film 110af and insulating film 110bf are formed before the semiconductor layer 108, there is no need to worry about oxygen being released from the semiconductor layer 108 due to the heat applied during the deposition of the insulating film 110af and insulating film 110bf.

[0345] After forming the insulating film 110af and insulating film 110bf, a heat treatment can be performed. By performing the heat treatment, impurities (e.g., water and hydrogen) can be removed from the insulating film 110af and from the insulating film 110bf and from its surface.

[0346] After the insulating film 110bf is formed, oxygen can be supplied to the insulating film 110bf. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As a plasma treatment, a device that turns oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that turn gas into plasma using high-frequency power include a PECVD device, a plasma etching device, and a plasma ashing device. Plasma treatment is preferably carried out in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: ), carbon monoxide, and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and processing time in the plasma treatment. In Figure 23C, the supply of oxygen (oxygen 180) to the insulating film 110bf is schematically shown by arrows.

[0347] After the insulating film 110bf is formed, nitrogen can be supplied to the insulating film 110bf. For the method of supplying nitrogen, refer to the description of the oxygen supply method described above. Plasma treatment in a nitrogen-containing atmosphere is suitably used as the nitrogen supply method. For example, nitrogen, nitrous oxide (N) ２ O), and nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following. The amount of nitrogen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0348] In the insulating layer (here, the insulating film 110bf or the subsequent insulating layer 110b), nitrogen oxides are produced by the reaction of nitrogen and oxygen. As nitrogen oxides, for example, N ２ O, NO, and NO ２ For example, in the insulating layer, nitrogen oxides form energy levels, which are located within the band gap of the metal oxide. ２ The transition level at which the charge of 0 transitions between the -1 state lies within the band gap of indium oxide. Therefore, nitrogen oxides (e.g., NO) ２When a negative charge (also called a negative fixed charge) diffuses to or near the interface between the insulating layer and the semiconductor layer having a metal oxide, that level traps electrons. As a result, a negative charge (also called a negative fixed charge) is formed at or near the interface between the insulating layer and the semiconductor layer, which can shift the threshold voltage of the transistor in the positive direction. This makes it possible to realize a normally-off transistor (in the case of an n-channel transistor) and a semiconductor device with low power consumption.

[0349] Increasing the amount of nitrogen oxides can shift the threshold voltage more towards the positive side. However, if the amount of nitrogen oxides is too high, the fluctuation in the threshold voltage when a positive potential (positive bias) is applied to the transistor gate will become large, which may reduce reliability. Therefore, it is preferable to use an amount of nitrogen oxides that does not affect reliability.

[0350] The amount of nitrogen oxides can be evaluated, for example, by the emission amount in thermal desorption spectroscopy (TDS) or by the electron spin amount in electron spin resonance (ESR). In TDS, NO (mass-to-charge ratio (also called m / z) = 30), N ２ O (m / z = 44), and NO ２ The amount of NO (m / z = 46) can be evaluated. ２ In some cases, it is difficult to quantify the amount of NO and N released. ２ By evaluating the amount of O released, NO ２ The amount of NO can be evaluated. ２ The ESR signal derived from NO can be used. Since N atoms have 7 electrons and O atoms have 8 electrons, NO ２ Molecules have an open-shell structure for electrons. Therefore, neutral NO ２ Because molecules have lone electrons, they can be measured using ESR. １４ Since N has a nuclear spin of 1, １４The peak of the ESR signal involving N splits into three. In this case, the split width of the ESR signal is the hyperfine coupling constant.

[0351] The order of supplying oxygen and supplying nitrogen is not particularly limited. Oxygen can be supplied after supplying nitrogen. Nitrogen can be supplied after supplying oxygen. Alternatively, oxygen and nitrogen can be supplied in the same process. For example, oxygen and nitrogen can be supplied by performing plasma treatment in an atmosphere containing nitrogen and oxygen. For example, nitrous oxide (N) ２ Plasma treatment using O) is preferable because it allows for efficient generation of nitrogen oxides.

[0352] Furthermore, after the insulating film 110bf is formed, the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the atmosphere. For example, when a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity. Specifically, after forming the insulating film 110bf in the PECVD apparatus, N ２ It can perform plasma processing.

[0353] Next, it is preferable to deposit a film 130 on the insulating film 110bf (Figure 23D). Sputtering can be suitably used to deposit the film 130. It is preferable to carry out the sputtering in an oxygen-containing atmosphere. By depositing the film 130 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf.

[0354] The conductivity of the film 130 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 130. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO) can be used as the film 130.

[0355] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the film 130. In particular, it is preferable to use an oxide semiconductor applicable to the semiconductor layer 108.

[0356] When forming the film 130, the higher the oxygen flow rate ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is preferably, for example, 50% or more and 100% or less, more preferably 60% or more and 100% or less, more preferably 70% or more and 100% or less, more preferably 80% or more and 100% or less, and more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and the oxygen partial pressure as close to 100% as possible.

[0357] In this way, by depositing the film 130 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during film formation, and oxygen can be prevented from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies (V) in the semiconductor layer 108 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, enabling the realization of a transistor that exhibits good electrical characteristics and high reliability.

[0358] After forming the film 130, a heat treatment can be performed. By performing a heat treatment after forming the film 130, oxygen can be effectively supplied from the film 130 to the insulating film 110bf.

[0359] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the atmosphere containing nitrogen or oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110af and insulating film 110bf as much as possible. For heat treatment, ovens, rapid thermal annealing (RTA) devices, etc., can be used. Using an RTA device can shorten the heat treatment time.

[0360] After the film 130 is formed, or after the aforementioned heat treatment, oxygen can be supplied to the insulating film 110bf via the film 130. For example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0361] Next, the film 130 is removed. There are no particular limitations on the method for removing the film 130, but a wet etching method can be suitably used. By using a wet etching method, etching of the insulating film 110bf during the removal of the film 130 can be suppressed. This prevents the thickness of the insulating film 110bf from becoming thinner, and the thickness of the insulating layer 110b can be made uniform.

[0362] The process of supplying oxygen to the insulating film 110bf is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, or oxygen molecular ions can be supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0363] Next, an insulating film 110cf, which will become the insulating layer 110c, is deposited on the insulating film 110bf (Figure 23E). For the deposition of the insulating film 110cf, refer to the description relating to the deposition of the insulating film 110af.

[0364] When an oxide or oxidized nitride is used for the insulating layer 110c, oxygen can be supplied to the insulating film 110bf by depositing the insulating film 110cf in an oxygen-containing atmosphere. Sputtering is suitably used for depositing the insulating film 110cf. For example, an aluminum oxide film can be deposited as the insulating film 110cf using an aluminum target in an oxygen-containing atmosphere by sputtering. When depositing the insulating film 110cf, the higher the oxygen flow rate ratio of the deposition gas introduced into the processing chamber of the deposition apparatus, or the higher the oxygen partial pressure in the processing chamber, the greater the amount of oxygen supplied to the insulating film 110bf. The oxygen flow rate ratio or oxygen partial pressure is preferably, for example, 50% or more and 100% or less, more preferably 60% or more and 100% or less, more preferably 70% or more and 100% or less, more preferably 80% or more and 100% or less, and more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and to bring the oxygen partial pressure as close to 100% as possible.

[0365] By depositing the insulating film 110cf in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110bf during the deposition of the insulating film 110cf, while preventing oxygen from being released from the insulating film 110bf. As a result, a large amount of oxygen can be trapped in the insulating film 110bf. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies (V) in the semiconductor layer 108 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, enabling the realization of a transistor that exhibits good electrical characteristics and high reliability.

[0366] After forming the insulating film 110cf, a heat treatment can also be performed. By performing a heat treatment after forming the insulating film 110cf, oxygen can be effectively supplied from the insulating film 110cf to the insulating film 110bf.

[0367] Next, a conductive film 112bf, which will become the conductive layer 112b, is deposited on the insulating film 110cf (Figure 24A). Sputtering can be suitably used to deposit the conductive film 112bf.

[0368] Next, the conductive film 112bf, insulating film 110cf, insulating film 110bf, and insulating film 110af are processed into island shapes to form conductive layer 112b, insulating layer 110c, insulating layer 110b, and insulating layer 110a, respectively (Figures 24B and 26A). This forms an insulating layer 110 having insulating layers 110a, insulating layer 110b, and insulating layer 110c. The insulating layer 110 and the conductive layer 112b are formed to have a region that overlaps with the conductive layer 112a. For example, a wet etching method can be suitably used to form the conductive layer 112b. For example, a dry etching method can be suitably used to form the insulating layer 110.

[0369] The conductive layer 112b and the insulating layer 110 can be formed, for example, using the same resist mask. After forming the insulating films (insulating film 110af, insulating film 110bf, and insulating film 110cf) that will become the insulating layer 110 and the conductive film 112bf, a resist mask is formed on the conductive film 112bf. By processing the conductive film 112bf and the insulating film using the resist mask as a mask, the conductive layer 112b and the insulating layer 110 can be formed respectively. By using the same resist mask for the formation of each of the conductive layer 112b and the insulating layer 110, productivity can be improved. Also, the upper surface shapes of each of the conductive layer 112b and the insulating layer 110 can be made to coincide or approximately coincide. Note that different resist masks can also be used for the formation of the conductive layer 112b and the formation of the insulating layer 110. In this case, for example, the semiconductor device 10A etc. described above can be manufactured.

[0370] Subsequently, an insulating film 116f that will become the insulating layer 116 is formed so as to cover the conductive layer 112a, the conductive layer 112b, and the insulating layer 110 (FIG. 26B). The insulating film 116f is provided in contact with the upper surface of the conductive layer 112a, the upper surface and side surfaces of the conductive layer 112b, and the side surface of the insulating layer 110 respectively.

[0371] Regarding the formation of the insulating film 116f, reference can be made to the description regarding the formation of the insulating film 110af and the insulating film 110cf.

[0372] Subsequently, an insulating film 118f that will become the insulating layer 118 is formed on the insulating film 116f (FIGS. 24C and 27A). The insulating film 118f is provided in contact with the upper surface of the insulating film 116f.

[0373] Regarding the formation of the insulating film 118f, reference can be made to the description regarding the formation of the insulating film 110bf.

[0374] Next, portions of the insulating film 118f and insulating film 116f are removed to form an opening (opening 145 shown in Figure 1A). This opening is formed so that, in plan view, it has a region that overlaps with the conductive layer 112a and conductive layer 112b, respectively. As a result, an insulating layer 118s is formed from the insulating film 118f, and an insulating layer 116 is formed from the insulating film 116f (Figures 24D and 27B). In the region overlapping with the opening, the upper surface of the conductive layer 112a, the side surface of the insulating layer 110, and the upper and side surfaces of the conductive layer 112b are exposed, respectively.

[0375] Next, a metal oxide film 108f, which will become the semiconductor layer 108, is formed to cover the insulating layer 118s, insulating layer 116, conductive layer 112a, insulating layer 110, and conductive layer 112b (Figures 25A and 28A). The metal oxide film 108f is provided in contact with the upper and side surfaces of the insulating layer 118s, the side surfaces of the insulating layer 116, the upper surface of the conductive layer 112a, the side surfaces of the insulating layer 110, and the upper and side surfaces of the conductive layer 112b.

[0376] The metal oxide film 108f is preferably deposited by sputtering using a metal oxide target. Alternatively, the metal oxide film 108f is preferably deposited by the ALD method. By using the ALD method, the metal oxide film 108f can be deposited with good coverage on the sides of the insulating layer 110 and the conductive layer 112b. Furthermore, since the deposition rate of the ALD method is easy to control, thin films can be deposited with good yield. Therefore, the ALD method is particularly suitable when the thickness of the metal oxide film 108f is thin. In addition, the CVD method can be used to deposit the metal oxide film 108f instead of the sputtering method and the ALD method.

[0377] It is preferable that the metal oxide film 108f be a dense film with as few defects as possible. Furthermore, it is preferable that the metal oxide film 108f has a high purity, with as few hydrogen-containing impurities as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film 108f.

[0378] It is preferable to use oxygen gas when forming the metal oxide film 108f. By using oxygen gas, oxygen can be suitably supplied to the insulating layer 110. For example, when an oxide or oxidoxide-nitride is used for the insulating layer 110b, oxygen can be suitably supplied to the insulating layer 110b.

[0379] By supplying oxygen to the insulating layer 110b, oxygen is supplied to the semiconductor layer 108 in a later process, and oxygen vacancies (V) in the semiconductor layer 108 are eliminated. Ｏ ) and V Ｏ H can be reduced.

[0380] When forming the metal oxide film 108f, a mixture of oxygen gas and an inert gas (e.g., helium gas, argon gas, xenon gas, etc.) can be used. The higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas used to form the metal oxide film, the higher the crystallinity of the metal oxide film can be, enabling the realization of a highly reliable transistor. Conversely, the lower the oxygen flow rate ratio or oxygen partial pressure, the lower the crystallinity and the higher the electrical conductivity of the metal oxide film, enabling the realization of a transistor with a large on-current.

[0381] Here, if the oxygen flow rate ratio or oxygen partial pressure is high, the metal oxide film may form a polycrystalline structure. In the case of a polycrystalline metal oxide film, the grain boundaries become recombination centers, trapping carriers and potentially reducing the on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure so that the metal oxide film 108f does not form a polycrystalline structure. Since the likelihood of forming a polycrystalline structure differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow rate ratio or oxygen partial pressure according to the composition of the metal oxide film 108f. However, the present invention is not limited to this, and a polycrystalline metal oxide can also be used. When the grain boundaries of a polycrystalline metal oxide film do not affect the transistor characteristics, a transistor using a polycrystalline metal oxide can be realized with higher reliability than a transistor using a metal oxide with low crystallinity.

[0382] The higher the substrate temperature during metal oxide film deposition, the higher the crystallinity and density of the resulting metal oxide film. This allows for the creation of highly reliable transistors. Conversely, the lower the substrate temperature, the lower the crystallinity and the higher the electrical conductivity of the resulting metal oxide film. This allows for the creation of transistors with high on-current.

[0383] The substrate temperature during the deposition of the metal oxide film 108f is preferably between room temperature and 250°C, more preferably between room temperature and 200°C, and even more preferably between room temperature and 140°C. For example, setting the substrate temperature to between room temperature and 140°C is preferable because it increases productivity. Furthermore, crystallinity can be reduced by depositing the metal oxide film at room temperature or without heating the substrate.

[0384] Furthermore, if the substrate temperature is high, the metal oxide film may develop a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.

[0385] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or the PEALD (Plasma Enhanced ALD) method. The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0386] Metal oxide films can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0387] For example, when forming an In-Ga-Zn oxide film, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and precursors containing both gallium and zinc.

[0388] Examples of indium precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.

[0389] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0390] Examples of tin-containing precursors include tin(IV) chloride and tetrakis(dimethylamide)tin.

[0391] Examples of zinc-containing precursors include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride.

[0392] Examples of oxidizing agents include ozone, oxygen, and water.

[0393] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration for which the raw material gases are flowed, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film 108f with a continuously changing composition.

[0394] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, organic matter, etc. adsorbed on the surface of the insulating layer 110, and a treatment to supply oxygen into the insulating layer 110. For example, a heat treatment can be performed in a reduced-pressure atmosphere at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Oxygen can be supplied to the insulating layer 110 by plasma treatment in an atmosphere containing an oxidizing gas such as 0). Plasma treatment containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 110 while supplying oxygen. After such treatment, it is preferable to continuously form a metal oxide film 108f without exposing the surface of the insulating layer 110 to the atmosphere.

[0395] Furthermore, when the semiconductor layer 108 is a stacked structure, it is preferable to deposit the metal oxide film to be deposited first, and then continuously deposit the next metal oxide film without exposing its surface to the atmosphere.

[0396] When the semiconductor layer 108 has a stacked structure, all layers constituting the semiconductor layer 108 can be deposited using the same method (for example, sputtering or ALD). Alternatively, different deposition methods can be used for each layer. For example, the first metal oxide layer can be deposited by sputtering, and the second metal oxide layer on the first metal oxide layer can be deposited by ALD.

[0397] Next, the metal oxide film 108f and the insulating layer 118s are processed into island shapes to form the semiconductor layer 108 and the insulating layer 118, respectively (Figures 25B and 28B). The semiconductor layer 108 and the insulating layer 118 are formed to have regions that overlap with the conductive layer 112a and the conductive layer 112b, respectively. The semiconductor layer 108 and the insulating layer 118 are formed to have regions that overlap with the aforementioned opening (opening 145 shown in Figure 1A). The semiconductor layer 108 and the insulating layer 118 are formed so that their respective edges coincide or roughly coincide in a plan view.

[0398] A wet etching method can be suitably used to form the semiconductor layer 108 and the insulating layer 118. In this case, a portion of the insulating layer 116 in areas that do not overlap with the semiconductor layer 108 and the insulating layer 118 may be etched and become thinner. However, when etching the metal oxide film 108f and the insulating layer 118s, using a material with a high selectivity ratio for the insulating layer 116 can suppress the thinning of the insulating layer 116.

[0399] It is preferable to perform a heat treatment after the metal oxide film 108f has been formed, or after the metal oxide film 108f has been processed into a semiconductor layer 108. The heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108, or adsorbed on the surface. In addition, the heat treatment may improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (for example, by reducing defects or improving crystallinity).

[0400] Heat treatment can also supply oxygen from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing the semiconductor layer 108. Since the heat treatment can be described in the previous section, a detailed explanation will be omitted.

[0401] Note that this heat treatment can be omitted if it is not necessary. Alternatively, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Furthermore, a heat treatment in a later step (for example, a film formation process) may also serve as this heat treatment.

[0402] Next, an insulating layer 106 is formed, covering the semiconductor layer 108, insulating layer 118, insulating layer 116, conductive layer 112b, insulating layer 110, and conductive layer 112a (Figures 25C and 29A). The insulating layer 106 is provided in contact with the upper and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 118, and the upper surface of the insulating layer 116. For forming the insulating layer 106, for example, the PECVD method, the sputtering method, or the ALD method can be suitably used.

[0403] When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses the diffusion of oxygen. Since the insulating layer 106 has a function of suppressing the diffusion of oxygen, the diffusion of oxygen into the conductive layer 104 through the insulating layer 106 is suppressed, and the oxidation of the conductive layer 104 can be suppressed. As a result, a transistor with good electrical characteristics and high reliability can be realized.

[0404] By increasing the temperature during the formation of the insulating layer 106 that functions as a gate insulating layer, an insulating layer with few defects can be obtained. However, when the temperature during the formation of the insulating layer 106 is high, oxygen desorbs from the semiconductor layer 108, and oxygen vacancies (V<00OO142>) and V Ｏ H may increase. The substrate temperature during the formation of the insulating layer 106 is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, still more preferably 250°C or higher and 450°C or lower, still more preferably 300°C or higher and 450°C or lower, and still more preferably 300°C or higher and 400°C or lower. By setting the substrate temperature during the formation of the insulating layer 106 within the above range, the defects of the insulating layer 106 can be reduced, and the desorption of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be realized.

[0405] Before forming the insulating layer 106, plasma treatment can be performed on the surface of the semiconductor layer 108. By this plasma treatment, impurities such as water adsorbed on the surface of the semiconductor layer 108 can be reduced. Therefore, the impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. In particular, it is suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere from the formation of the semiconductor layer 108 to the formation of the insulating layer 106. The plasma treatment can be performed, for example, in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, etc. Also, the plasma treatment and the formation of the insulating layer 106 are preferably performed continuously without exposure to the atmosphere.

[0406] Next, impurity elements (elements other than the main components constituting the semiconductor layer 108; for example, elements with a concentration of less than 0.1 atomic% in the semiconductor layer 108) can be supplied to the semiconductor layer 108 via the insulating layer 106. It is preferable to use impurity elements that can reduce the resistance of the source and drain regions of the transistor.

[0407] Examples of such impurity elements include one or more of the following: boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).

[0408] Furthermore, the impurity elements are not limited to the elements listed above, and may include one or more elements from among the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and rare earth elements.

[0409] Furthermore, the impurity element can be either the element mentioned above or hydrogen.

[0410] The concentration of the impurity element in the source and drain regions is, for example, 1 × 10⁻⁶ １９ atoms / cm ３ The above 1 x 10 ２３ atoms / cm ３ The following is preferably 5 × 10 １９ atoms / cm ３ The above 5 x 10 ２２ atoms / cm ３ More specifically, 1 x 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ It is preferable that the following region be included. If multiple impurity elements are included, it is preferable that the concentration of each impurity element be within the above range.

[0411] By supplying the aforementioned impurity elements to the source and drain regions, these impurity elements remove oxygen from these regions, creating oxygen deficiencies (V) in these regions. Ｏ This creates an oxygen vacancy. Then, when this oxygen vacancy combines with hydrogen in the film, a carrier is generated, which allows the source and drain regions to have lower resistance. As a result, the source and drain regions of the transistor can have lower resistance than the channel formation region. Therefore, the contact resistance between the source region and the source electrode, and the contact resistance between the drain region and the drain electrode of the transistor can be reduced, and the on-current of the transistor can be increased. Furthermore, by increasing the on-current of the transistor, the operating voltage of the transistor can be reduced, which can reduce the power consumption of the semiconductor device.

[0412] Furthermore, the aforementioned impurity elements may also be supplied to the channel formation region in the semiconductor layer 108. Alternatively, due to the effects of heat during the manufacturing process, some of the impurity elements contained in the source region and drain region may diffuse into the channel formation region.

[0413] The concentration of impurity elements contained in the semiconductor layer 108 can be analyzed by analytical methods such as SIMS or XPS. When using XPS analysis, the concentration distribution in the depth direction can be determined by combining ion sputtering from the surface or back side with XPS analysis.

[0414] Ion doping or ion implantation can be suitably used to supply the impurity elements.

[0415] Furthermore, there are no limitations on the method of supplying the impurity elements; for example, plasma treatment or treatment utilizing thermal diffusion by heating can also be used. In the case of plasma treatment, the impurity elements can be supplied by generating plasma in a gas atmosphere containing the impurity elements to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0416] Furthermore, it is preferable to perform the impurity element supply process while heating the substrate 102. This allows for the repair of damage to the semiconductor layer 108 that occurs when the impurity element is supplied. In other words, the supply of impurity elements to the semiconductor layer 108 and the repair of damage caused by such supply can be performed in parallel. In addition, damage to the insulating layer 106 that occurs when the impurity element is supplied can also be repaired.

[0417] The substrate temperature during the supply process of the impurity element is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C or higher and 500°C or lower, more preferably 200°C or higher and 450°C or lower, more preferably 250°C or higher and 400°C or lower, more preferably 250°C or higher and 350°C or lower, or more preferably 300°C or higher and 350°C or lower.

[0418] After supplying the impurity element, a heat treatment can also be performed. By performing this heat treatment, damage sustained by the semiconductor layer 108 and the insulating layer 106 during the impurity element supply process can be repaired.

[0419] The temperature of the heat treatment after supplying the impurity element is preferably 150°C or higher but below the strain point of the substrate, more preferably 200°C or higher but 500°C or lower, more preferably 200°C or higher but 450°C or lower, more preferably 250°C or higher but 400°C or lower, more preferably 250°C or higher but 350°C or lower, or more preferably 300°C or higher but 400°C or lower, and more preferably 300°C or higher but 350°C or lower.

[0420] Furthermore, if the source and drain regions of the semiconductor layer 108 have sufficiently low resistance, the supply of the impurity element to the semiconductor layer 108 may be omitted. This reduces the number of steps involved in the manufacturing of the semiconductor device.

[0421] Next, a conductive film 104f, which will become the conductive layer 104, is formed on the insulating layer 106 (Figures 25D and 29B). For forming the conductive film 104f, for example, sputtering, thermal CVD (including MOCVD), or ALD can be suitably used.

[0422] Next, the conductive film 104f is processed to form a conductive layer 104 (Figures 1B and 2A). The conductive layer 104 is formed to have a region that overlaps with the semiconductor layer 108 in a plan view. For example, a wet etching method can be suitably used to form the conductive layer 104.

[0423] By following the above steps, a semiconductor device 10 according to one aspect of the present invention can be manufactured.

[0424] This embodiment can be combined with other embodiments as appropriate.

[0425] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 30 to 38B.

[0426] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0427] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0428] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an Integrated Circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0429] The display device of this embodiment can also function as a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the proximity or contact of an object to be detected, such as a finger, can be applied to the display device.

[0430] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0431] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0432] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0433] <Display device 50A> Figure 30 shows a perspective view of the display device 50A.

[0434] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 30, substrate 152 is shown with a dashed line.

[0435] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 30 shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 30 can also be described as a display module having the display device 50A, an IC, and an FPC.

[0436] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There may be one or more connection portions 140. Figure 30 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The common electrode of the display element and the conductive layer are connected at the connection portion 140, and a potential can be supplied to the common electrode.

[0437] The circuit section 164 may include, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 may also include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0438] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from an external source via the FPC 172, or from the IC 173.

[0439] Figure 30 shows an example in which IC 173 is provided on the substrate 151 using the COG method or COF method, etc. For example, IC 173 can be an IC having one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method, etc.

[0440] A semiconductor device according to one aspect of the present invention can be applied, for example, to one or both of the display unit 162 and the circuit unit 164 of a display device 50A. Oxide semiconductors (OS) can preferably be used in the channel formation regions of the transistors in the display device. By using OS transistors, a display device with low power consumption can be achieved. Furthermore, the semiconductor device according to one aspect of the present invention can be used in both the display unit 162 and the circuit unit 164, meaning that all the transistors in the display device can be OS transistors. By making all the transistors in the display device OS transistors in this way, the manufacturing cost can be kept low.

[0441] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0442] The display unit 162 is the area in the display device 50A that displays images, and has a plurality of pixels 201 arranged periodically. Figure 30 shows a magnified view of one pixel 201.

[0443] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various arrangements can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0444] The pixel 201 shown in Figure 30 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. The number of sub-pixels that a single pixel has is not particularly limited.

[0445] Each sub-pixel 11R, sub-pixel 11G, and sub-pixel 11B includes a display element and a circuit that controls the driving of the display element.

[0446] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLED (Quantum-dot LED) using a light source and color conversion technology using quantum dot materials can also be used.

[0447] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0448] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and guest host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0449] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0450] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs, OLEDs (organic LEDs), and semiconductor lasers. Examples of LEDs that can be used include mini-LEDs and micro-LEDs.

[0451] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0452] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0453] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0454] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0455] Figure 31A shows an example of a cross-section obtained when a portion of the display device 50A is cut, including a portion of the area containing the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end.

[0456] The display device 50A shown in Figure 31A has transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, and 130B between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0457] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0458] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be arranged overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0459] Transistors 205D, 205R, 205G, and 205B are all formed on the substrate 151. These transistors can be manufactured using the same process. Note that transistors with different structures can also be used for each of transistors 205D, 205R, 205G, and 205B.

[0460] In this embodiment, an example is shown in which OS transistors are used for transistors 205D, 205R, 205G, and 205B. Transistors according to one aspect of the present invention can be used for transistors 205D, 205R, 205G, and 205B. In other words, the display device 50A has transistors according to one aspect of the present invention in both the display unit 162 and the circuit unit 164. By using transistors according to one aspect of the present invention in the display unit 162, the pixel size can be reduced, and high resolution can be achieved. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced, and a narrow bezel can be achieved. For details on transistors according to one aspect of the present invention, refer to the description of the previous embodiment.

[0461] Specifically, transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, conductive layers 112a and 112b that function as source and drain, and a semiconductor layer 108 having a metal oxide, respectively. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 110 is located between the conductive layer 112a and the conductive layer 112b. The insulating layer 106 is located between the conductive layer 104 and the semiconductor layer 108.

[0462] Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0463] The display device of this embodiment may have, for example, one or more of the following: planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be either top-gate or bottom-gate types. Alternatively, the device may have a configuration in which gates are provided above and below the semiconductor layer in which the channel is formed.

[0464] The display device of this embodiment may also have Si transistors.

[0465] To increase the luminescence brightness of a light-emitting element included in a pixel circuit, it is necessary to increase the amount of current flowing through the light-emitting element. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the drive transistor in the pixel circuit, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the light-emitting element.

[0466] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage. This allows for control of the current flowing to the light-emitting element, thereby increasing the number of grayscale levels in the pixel circuit.

[0467] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is changed, thus stabilizing the luminescence brightness of the light-emitting element.

[0468] The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 may all be the same or there may be two or more types. Similarly, the structures of the multiple transistors in the display unit 162 may all be the same or there may be two or more types.

[0469] All of the transistors in the display unit 162 can be OS transistors, all of the transistors in the display unit 162 can be Si transistors, and some of the transistors in the display unit 162 can be OS transistors and the rest can be Si transistors.

[0470] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0471] For example, one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. Either the source or the drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0472] On the other hand, the other transistor in the display unit 162 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and either the source or the drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly low (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0473] An insulating layer 218 is provided so as to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on top of the insulating layer 218.

[0474] The insulating layer 218 preferably functions as a protective layer for the transistor. It is preferable to use a material for the insulating layer 218 that does not easily absorb impurities such as water and hydrogen. This allows the insulating layer 218 to function as a barrier film. This configuration effectively suppresses the diffusion of impurities into the transistor from the outside, thereby improving the reliability of the display device.

[0475] The insulating layer 218 preferably has one or more inorganic insulating layers. The insulating layer 218 can be made of the same material that can be used for the insulating layer 110.

[0476] The insulating layer 235 preferably functions as a planarization layer, and an organic insulating film is preferred. Examples of materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. The insulating layer 235 can also be a laminated structure of an organic insulating film and an inorganic insulating film. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc. Alternatively, the insulating layer 235 can be configured to have recesses when processing the pixel electrodes 111R, 111G, 111B, etc. Note that the pixel electrodes 111R, 111G, and 111B may be collectively referred to as pixel electrode 111.

[0477] A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 235.

[0478] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Figure 31A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0479] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Figure 31A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0480] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Figure 31A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0481] In Figure 31A, EL layers 113R, 113G, and 113B are all shown to be the same thickness, but this is not the only option. The thicknesses of EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the thickness of EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each light-emitting element.

[0482] The pixel electrode 111R is connected to the conductive layer 112b of the transistor 205R at openings provided in the insulating layer 116, insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0483] The ends of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition. The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can be made of materials that can be used for the insulating layer 218 and materials that can be used for the insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other.

[0484] The insulating layer 237 is provided at least on the display unit 162. The insulating layer 237 can also be provided on the connection unit 140 and the circuit unit 164, not just the display unit 162. Furthermore, the insulating layer 237 can be provided up to the end of the display device 50A.

[0485] The common electrode 115 is a continuous film provided in common to the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed by the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B.

[0486] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0487] A conductive film that transmits visible light can also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can be reflected by the reflective layer and extracted from the display device.

[0488] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, other examples of such materials include aluminum-containing alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-magnesium alloys and silver-containing alloys such as silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0489] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0490] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0491] The EL layers 113R, 113G, and 113B are each provided in an island-like configuration. In Figure 31A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 31A, but this is not the only case. In other words, adjacent EL layers can not overlap and can be configured to be separated from each other. Furthermore, in a display device, it is possible to have a configuration in which both adjacent EL layers overlap and adjacent EL layers do not overlap and are separated from each other.

[0492] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0493] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0494] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of these organic compounds may be substances with high hole transport properties (hole transport materials) and / or substances with high electron transport properties (electron transport materials). Furthermore, one or more of these organic compounds may be bipolar substances (substances with high electron and hole transport properties) or TADF materials.

[0495] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0496] In addition to the light-emitting layer, the EL layer may have one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may also contain either or both a bipolar material and a TADF material.

[0497] The light-emitting element can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0498] A light-emitting element can be configured as either a single structure (a structure with only one light-emitting unit) or a tandem structure (a structure with multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. In a tandem structure, multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be created. Furthermore, compared to a single structure, a tandem structure can reduce the current required to obtain the same brightness, thus improving reliability. The tandem structure can also be called a stacked structure.

[0499] In Figure 31A, when a tandem light-emitting element is used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0500] A protective layer 131 is provided on the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 31A, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space can be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure can be applied. In this case, the adhesive layer 142 can be provided so as not to overlap with the light-emitting elements. Furthermore, the space can be filled with a resin different from the adhesive layer 142, which is provided in a frame shape.

[0501] The protective layer 131 is provided at least on the display section 162, and preferably so as to cover the entire display section 162. It is preferable that the protective layer 131 covers not only the display section 162, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 197, there is a portion where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 165.

[0502] By providing a protective layer 131 on the light-emitting element 130R, on the light-emitting element 130G, and on the light-emitting element 130B, the reliability of the light-emitting element can be improved.

[0503] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0504] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 115 and suppresses the intrusion of impurities (water, oxygen, etc.) into the light-emitting element, thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0505] The protective layer 131 preferably has one or more inorganic insulating layers. The protective layer 131 can be made of the same material that can be used for the insulating layer 110. In particular, it is preferable to use a nitride or nitride oxide for the protective layer 131, and it is more preferable to use a nitride.

[0506] The protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or aluminum oxide. The inorganic film is preferably highly resistive, specifically, more resistive than the common electrode 115. The inorganic film may also contain nitrogen.

[0507] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0508] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using this laminated structure, it is possible to suppress the penetration of impurities (water, oxygen, etc.) into the EL layer.

[0509] Furthermore, the protective layer 131 may also have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include organic insulating films that can be used for the insulating layer 235.

[0510] A connection portion 197 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. The conductive layer 165 is shown as an example of a conductive layer obtained by processing the same conductive film as conductive layer 112b. The conductive layer 166 is shown as an example of a conductive layer obtained by processing the same conductive film as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. The connection portion between conductive layer 165 and conductive layer 166 can be configured in the same way as the connection portion between pixel electrode 111 and conductive layer 112b. Specifically, Figure 31A shows an example in which an opening is provided in the upper layer of conductive layer 165, and conductive layer 166 is in contact with the upper surface of conductive layer 165 through this opening. On the upper surface of the connection portion 197, conductive layer 166 is exposed. This allows the connection part 197 and the FPC 172 to be connected via the connection layer 242.

[0511] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0512] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection parts 140, in circuit parts 164, etc.

[0513] A colored layer, such as a color filter, can also be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0514] A colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. One or more of the following can be used for each colored layer: metal materials, resin materials, pigments, and dyes. The colored layers are formed at the desired positions using methods such as printing, inkjet printing, or etching using lithography.

[0515] Various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. Surface protection layers such as an antistatic film to suppress dust adhesion, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and a shock-absorbing layer can also be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO₂) can be used as a surface protection layer. ｘProviding a protective layer is preferable as it can suppress surface contamination and scratching. Alternatively, DLC (diamond-like carbon), aluminum oxide, polyester-based materials, or polycarbonate-based materials can be used as the surface protective layer. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0516] Substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc., respectively. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate can be used as at least one of substrates 151 and 152.

[0517] As substrates 151 and 152, polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. can be used, respectively. Glass of a thickness sufficient to provide flexibility can also be used for at least one of substrates 151 and 152.

[0518] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0519] Various types of curing adhesives can be used as the adhesive layer 142, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins can also be used. Adhesive sheets can also be used.

[0520] As the connecting layer 242, an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), etc., can be used.

[0521] <Display Device 50B> Figure 31B shows an example of a cross-section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). The configuration shown in Figure 31B can be combined with the configuration of the region including the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection unit 140, and the end portion shown in Figure 31A. Note that in the following description of the display device, parts that are the same as those described earlier may be omitted.

[0522] The display device 50B shown in Figure 31B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, a colored layer 132B that transmits blue light, and the like.

[0523] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0524] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0525] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0526] The light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B each have a common EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0527] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 31B each emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0528] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers can be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Furthermore, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to create a configuration in which the entire light-emitting element emits white light.

[0529] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0530] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B, Y (yellow), a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R, Y, a two-layer structure of R, G, a two-layer structure of G, R, G, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. It is also possible to have a configuration in which other layers are provided between the two light-emitting layers.

[0531] Furthermore, by applying a microcavity structure, a light-emitting element that normally emits white light may also emit light of specific wavelengths, such as red, green, or blue, with increased intensity.

[0532] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 31B each emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by the light-emitting elements may be transmitted directly without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0533] <Display device 50C> The display device 50C shown in Figure 32 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0534] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0535] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 32 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, 205B, etc. are provided on the insulating layer 153. In addition, a colored layer 132R, a colored layer 132G, and a colored layer 132B are provided on the insulating layer 218, and an insulating layer 235 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B.

[0536] The light-emitting element 130R, which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0537] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0538] The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.

[0539] The pixel electrodes 111R, 111G, and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission type display device, a metal with low electrical resistivity can be used for the common electrode 115, thereby suppressing voltage drops caused by the electrical resistance of the common electrode 115 and achieving high display quality.

[0540] A transistor according to one aspect of the present invention can be miniaturized and have a reduced occupied area, which allows for an increase in the aperture ratio of pixels or a reduction in the size of pixels in a display device with a bottom emission structure.

[0541] <Display device 50D> The display device 50D shown in Figure 33A mainly differs from the display device 50A in that it has a light-receiving element 130S.

[0542] The display device 50D has a light-emitting element and a light-receiving element in each pixel. In the display device 50D, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element.

[0543] In a display device 50D having light-emitting and light-receiving elements in its pixels, the pixels have a light-receiving function, allowing for the detection of contact or proximity of an object while displaying an image. Therefore, the display unit 162 has, in addition to an image display function, one or both of an imaging function and a sensing function. For example, the display device 50D can not only display an image using all of its subpixels, but some subpixels can also emit light as a light source, some other subpixels can perform light detection, and the remaining subpixels can display an image.

[0544] Therefore, it is not necessary to provide a light receiving unit and a light source separately from the display device 50D, and the number of components in the electronic device can be reduced. For example, there is no need to separately provide a biometric authentication device or a capacitive touch panel for scrolling, etc., which are installed in the electronic device. Therefore, by using the display device 50D, it is possible to provide an electronic device with reduced manufacturing costs.

[0545] When a light-receiving element is used as an image sensor, the display device 50D can capture an image using the light-receiving element. For example, the image sensor can be used to capture images for personal authentication, such as fingerprints, palm prints, irises, pulse patterns (including vein patterns and arterial patterns), or faces.

[0546] The light-receiving element can be used in touch sensors (also called direct touch sensors) or non-contact sensors (also called hover sensors, hover touch sensors, or touchless sensors). A touch sensor can detect an object (such as a finger, hand, or pen) by making direct contact between the display device and the object. A non-contact sensor can detect an object even if the object does not come into contact with the display device.

[0547] The light-receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50D.

[0548] The pixel electrode 111S is connected to the conductive layer 112b of the transistor 205S at openings provided in the insulating layer 116, insulating layer 106, insulating layer 218, and insulating layer 235.

[0549] The ends of the pixel electrodes 111S are covered by an insulating layer 237.

[0550] The common electrode 115 is a continuous film provided in common to the light-receiving element 130S, the light-emitting element 130R (not shown), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 115, which is shared by the light-emitting element and the light-receiving element, is connected to the conductive layer 123 provided at the connection portion 140.

[0551] The functional layer 113S has at least an active layer (also called a photoelectric conversion layer). The active layer contains a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), and the manufacturing equipment can be standardized.

[0552] The functional layer 113S may further include layers other than the active layer, such as a material with high hole transport properties, a material with high electron transport properties, or a bipolar material. Furthermore, it may also further include layers containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For example, the functional layer 113S can be made from materials that can be used in the above-described light-emitting devices.

[0553] The photodetector can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the photodetector can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0554] The display device 50D shown in Figures 33B and 33C has a layer 353 with a light-receiving element, a circuit layer 355, and a layer 357 with an light-emitting element between the substrate 151 and the substrate 152.

[0555] Layer 353 has, for example, a light-receiving element 130S. Layer 357 has, for example, light-emitting elements 130R, 130G, and 130B.

[0556] The circuit layer 355 includes a circuit for driving a light-receiving element and a circuit for driving a light-emitting element. The circuit layer 355 includes, for example, transistors 205R, 205G, and 205B. In addition, the circuit layer 355 may be provided with one or more of the following: switches, capacitors, resistors, wiring, terminals, etc.

[0557] Figure 33B shows an example of using the light-receiving element 130S as a touch sensor. As shown in Figure 33B, the light emitted by the light-emitting element in layer 357 is reflected by the finger 352 that is in contact with the display device 50D, and the light-receiving element in layer 353 detects this reflected light. This makes it possible to detect that the finger 352 has come into contact with the display device 50D.

[0558] Figure 33C shows an example of using the light-receiving element 130S as a non-contact sensor. As shown in Figure 33C, the light emitted by the light-emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light-receiving element in layer 353 detects the reflected light.

[0559] <Display Device 50E> The display device 50E shown in Figure 34A is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50E has a light-emitting element that is manufactured without using a fine metal mask.

[0560] In a display device using an MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing a light-emitting layer onto one surface and then processing it using lithography. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality. For example, if the display device is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0561] Because MML (Multilayer Molded) devices can be manufactured without using a metal mask, they can exceed the resolution limits imposed by the precision required for metal mask alignment. Furthermore, when manufacturing devices without a metal mask, the equipment and cleaning processes associated with metal mask manufacturing are eliminated. Additionally, since the lithography process can utilize equipment common to or similar to that used for transistor manufacturing, there is no need to introduce special equipment for manufacturing MML devices. Thus, MML structures allow for lower manufacturing costs, making them suitable for mass production of devices.

[0562] In a display device to which an MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement. Therefore, a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) can be realized using a so-called stripe arrangement in which the R, G, and B subpixels are each arranged in one direction.

[0563] By providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0564] By employing a film deposition process using an area mask and a processing process using a resist mask, light-emitting elements can be fabricated using a relatively simple process.

[0565] Note that the laminated structure from substrate 151 to insulating layer 235, and the laminated structure from protective layer 131 to substrate 152 are the same as those of the display device 50A, so their explanation is omitted.

[0566] In Figure 34A, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0567] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in Figure 34A emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0568] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in Figure 34A emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0569] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in Figure 34A emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0570] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer common to multiple light-emitting elements is referred to as the common layer 114. In this specification, the common layer 114 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc. Furthermore, light-emitting elements manufactured without using a metal mask may have a configuration without a common layer, and all layers constituting the EL layer may be formed in an island-like manner.

[0571] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0572] Note that in Figure 34A, layers 133R, 133G, and 133B are all shown to be of the same thickness, but this is not the only option. The thicknesses of layers 133R, 133G, and 133B can also be different.

[0573] The conductive layer 124R is connected to the conductive layer 112b of transistor 205R at openings provided in the insulating layer 116, insulating layer 106, insulating layer 218, and insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 112b of transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of transistor 205B.

[0574] The conductive layer 124R, conductive layer 124G, and conductive layer 124B are each formed to cover the openings provided in the insulating layer 235. Layer 128 is embedded in the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively.

[0575] Layer 128 has the function of flattening the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B, which are connected to conductive layers 124R, 124G, and 124B, are provided on conductive layers 124R and 128, on conductive layers 124G and 128, and on conductive layers 124B and 128, respectively. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels. It is preferable to ...

Claims

It comprises a transistor, a first insulating layer, and a second insulating layer. The transistor has a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first insulating layer is located on the first conductive layer such that it has a region that overlaps with the first conductive layer. The second conductive layer is located on the first insulating layer, The second insulating layer is located on the first conductive layer, on the first insulating layer, and on the second conductive layer, and is in contact with the upper and side surfaces of the first conductive layer, the side surfaces of the first insulating layer, and the upper and side surfaces of the second conductive layer, The second insulating layer has a first opening that overlaps with the first conductive layer and the second conductive layer, The semiconductor layer is located on the second insulating layer such that it has a region overlapping with the first opening, and within the first opening, it is in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the upper and side surfaces of the second conductive layer, respectively. The third insulating layer is located on the semiconductor layer, The third conductive layer is located on the third insulating layer such that it has a region that overlaps with the semiconductor layer. Semiconductor equipment. 　 In claim 1, The semiconductor layer is an oxide semiconductor layer containing indium. The first insulating layer comprises a fourth insulating layer, a fifth insulating layer on the fourth insulating layer, and a sixth insulating layer on the fifth insulating layer. The fourth insulating layer and the sixth insulating layer each contain silicon and nitrogen, The fifth insulating layer comprises silicon and oxygen, The second insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 In claim 1 or claim 2, A seventh insulating layer is provided between the second insulating layer and the semiconductor layer. The seventh insulating layer is in contact with the upper surface of the second insulating layer and has a second opening in a region that overlaps with the first opening. The semiconductor layer is in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, and the upper and side surfaces of the second conductive layer, respectively, inside the first and second openings, and is in contact with the upper surface of the seventh insulating layer outside the first and second openings. The seventh insulating layer comprises silicon and oxygen. Semiconductor equipment. 　 In claim 3, The semiconductor layer and the seventh insulating layer have their edges coincide or roughly coincide when viewed in plan. Semiconductor equipment. 　 In claim 1 or claim 2, An eighth insulating layer is located beneath the first conductive layer. The upper surface of the eighth insulating layer is in contact with the first conductive layer. The eighth insulating layer is one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, aluminum nitride, silicon nitride, and silicon nitride oxide. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer is provided in an island-like manner, The first insulating layer and the second conductive layer have their respective edges coincide or approximately coincide when viewed in plan. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer is divided by a slit that reaches the first conductive layer. The region has a pair of opposing sides separated by the slit, in which the second insulating layer, the semiconductor layer, the third insulating layer, and the third conductive layer are stacked in this order. Semiconductor equipment. 　 In claim 1 or claim 2, The first insulating layer and the second conductive layer have a third opening that reaches the first conductive layer. Within the third opening, the region has a layer on the side surface of the first insulating layer in which the second insulating layer, the semiconductor layer, the third insulating layer, and the third conductive layer are stacked in this order. Semiconductor equipment. 　 In claim 1 or claim 2, The semiconductor layer has a configuration that, in a plan view, is contained within the first opening. Semiconductor equipment. 　 In claim 1 or claim 2, The first opening and the semiconductor layer each have a region that overlaps with the first corner of the first insulating layer and the second conductive layer in a plan view, The first corner is a corner whose interior angle in a plan view is greater than 0 degrees and less than 180 degrees. Semiconductor equipment. 　 In claim 1 or claim 2, The first opening and the semiconductor layer each have a region that overlaps with the second corner of the first insulating layer and the second conductive layer in a plan view, The second corner is a corner whose interior angle in a plan view is greater than 180 degrees and less than 360 degrees. Semiconductor equipment. 　 A first conductive layer is formed, A first insulating film and a first conductive film are formed on the first conductive layer in this order. The first conductive film and the first insulating film are processed to have a region that overlaps with the first conductive layer, thereby forming a second conductive layer and a first insulating layer, respectively. A second insulating film and a third insulating film are formed in this order, in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the upper surface of the second conductive layer, respectively. A portion of the second insulating film and the third insulating film is removed to form an opening that overlaps with the first conductive layer and the second conductive layer, respectively, and a second insulating layer and a third insulating layer are formed, respectively. A metal oxide film is formed in contact with the upper surface of the third insulating layer, the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the second conductive layer, and the upper surface of the second conductive layer. The metal oxide film and the third insulating layer are processed so that they have a region that overlaps with the opening, and so that their respective edges coincide or substantially coincide in a plan view, thereby forming a semiconductor layer and a fourth insulating layer, respectively. A fifth insulating layer is formed on the semiconductor layer. A third conductive layer is formed on the fifth insulating layer such that it has a region that overlaps with the semiconductor layer. Method for manufacturing semiconductor devices.

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