Input / output circuit

Abstract

An input / output circuit (1) is capable of receiving a second input signal (IN2) via an input / output terminal (INOUT) and outputting a first output signal (OUT1) that changes in accordance with a first input signal (IN1). The input / output circuit (1) is provided with: three P-type transistors (P1, P2, P3) connected in series between a first power supply and the input / output terminal (INOUT); three N-type transistors (N1, N2, N3) connected in series between the input / output terminal (INOUT) and a fourth power supply; an N-type transistor (N4) and a P-type transistor (P4) connected in series between a second power supply and a third power supply; and an N-type transistor (N5) and a P-type transistor (P5) connected in series between the second power supply and the third power supply.

Description

Input / output circuit

[0001] The present disclosure relates to an input / output circuit of an IO cell that outputs a signal to the outside of a semiconductor device (LSI (Large Scale Integration)) or inputs a signal from the outside of the semiconductor device.

[0002] In conventional semiconductor devices, a transistor with a thick film gate (high breakdown voltage transistor) and a transistor with a thin film gate (low breakdown voltage transistor) having a lower breakdown voltage than the thick film gate transistor have been prepared. Generally, a high breakdown voltage transistor has a high allowable voltage stress (breakdown voltage) and is used in an IO cell that communicates a high voltage signal with the outside of the LSI. A low breakdown voltage transistor is used in an internal cell (such as a memory cell or a standard cell) that handles a relatively low voltage signal.

[0003] In recent years, semiconductor devices without high breakdown voltage transistors have been studied due to manufacturing reasons associated with transistor miniaturization. In the future, since communication of relatively high voltage signals (such as 1.8 V) may occur, IO cells that handle high voltage signals using only low breakdown voltage transistors have been studied.

[0004] For example, Patent Document 1 discloses an output circuit of an IO cell that outputs a voltage signal several times the breakdown voltage of a transistor.

[0005] U.S. Patent No. 9,214,933

[0006] However, while further reduction of the transistor breakdown voltage due to the progress of miniaturization and a decrease in the operating voltage associated therewith are assumed, there is no input / output circuit that can flexibly and easily adapt to them.

[0007] In view of the above problems, an object of the present disclosure is to solve the above problems.

[0008] One aspect of the present disclosure relates to an input / output circuit that receives a first input signal, outputs an output signal that changes according to the first input signal from an input / output terminal, and receives a second input signal input to the input / output terminal. The input / output circuit includes a first P-type transistor whose source is connected to a first power supply, whose drain is connected to a first node, and whose gate receives a signal that changes according to the first input signal; a second P-type transistor whose source is connected to the first node, whose drain is connected to a second node, and whose gate is connected to a second power supply with a lower power supply voltage than the first power supply; a third P-type transistor whose source is connected to the second node, whose drain is connected to the input / output terminal, and whose gate is connected to a third node; a first N-type transistor whose drain is connected to the input / output terminal, whose source is connected to a fourth node, and whose gate is connected to the third node; and a second N-type transistor whose drain is connected to the fourth node, whose source is connected to a fifth node, and whose gate is connected to a third power supply with a lower power supply voltage than the second power supply. The device comprises: a transistor; a third N-type transistor whose drain is connected to the fifth node, whose source is connected to a fourth power supply having a lower power supply voltage than the third power supply, and whose gate receives a signal that changes according to the first input signal; a fourth N-type transistor whose drain is connected to the second power supply, whose source is connected to the third node, and whose gate is connected to the second node; a fourth P-type transistor whose source is connected to the third node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a fifth P-type transistor whose source is connected to the second power supply, whose drain is connected to the sixth node, and whose gate is connected to the third node; and a fifth N-type transistor whose source is connected to the third power supply, whose drain is connected to the sixth node, and whose gate is connected to the third node.

[0009] In this embodiment, the gate voltages of the third P-type transistor and the third N-type transistor are controlled according to the characteristics of the output signal, which fluctuate depending on the transistor's breakdown voltage and operating voltage. Similarly, the gate voltages of the third and fifth P-type transistors and the third and fifth N-type transistors are controlled according to the second input signal input from the input / output terminals. As a result, during the operation of the input / output circuit, the terminal voltages of the first to fifth P-type transistors and the first to fifth N-type transistors are maintained below the transistor's breakdown voltage. This makes it possible to effectively prevent the aging degradation of each transistor (first to fifth P-type transistors and first to fifth N-type transistors) constituting the input / output circuit compared to the conventional technology.

[0010] According to this disclosure, the voltage across each terminal of each transistor is maintained below the transistor's breakdown voltage during the operation of the input / output circuit, thereby effectively preventing the aging degradation of each transistor.

[0011] Circuit diagram of the input / output circuit according to the first embodiment Waveform diagram showing an example of operation in the output mode of the input / output circuit of Figure 1 Waveform diagram showing an example of operation in the input mode of the input / output circuit of Figure 1 Circuit diagram of the input / output circuit according to the second embodiment Circuit diagram of the input / output circuit according to the second embodiment

[0012] The embodiments will be described below with reference to the drawings.

[0013] In this disclosure, "connection" is a broad concept encompassing electrical connection, including not only direct connections but also indirect electrical connections via passive elements, etc. The circuit diagrams shown below are simplified illustrations focusing on the components relevant to this disclosure. Therefore, components shown as directly connected may, in actual circuit configurations, be indirectly connected due to other components being positioned between them. Furthermore, in this disclosure, "terminal" refers to an entry and exit point for current provided for the connection of an electrical circuit. For example, it is not intended to be limited to specific configurations such as semiconductor pads; wiring and vias connecting circuits and components may also qualify as terminals.

[0014] Furthermore, in the following explanation, common symbols or names may be used to describe the nodes and terminals of a circuit and the signals passing through those nodes and terminals, and common symbols may be used to describe the power supply name and the power supply voltage of that power supply. Also, regarding the voltage of terminals and nodes, only the symbol indicating the voltage may be used, and it may be written as "(terminal name or node name) = (symbol indicating voltage)". Specifically, for example, if the voltage of the input / output terminal INOUT is VDD (voltage of power supply VDD), it may be written as "INOUT = VDD".

[0015] <First Embodiment> Figure 1 is a circuit diagram of an input / output circuit according to the first embodiment. Specifically, the input / output circuit 1 receives a first input signal IN1 and outputs a first output signal OUT1, which changes according to the first input signal IN1, to the input / output terminal INOUT. The first input signal IN1 is, for example, a signal output from an internal circuit (not shown) of a semiconductor device (LSI). The input / output circuit 1 also receives a second input signal IN2 input to the input / output terminal INOUT and outputs a second output signal OUT2, which changes according to the second input signal IN2, to the internal output terminal C. The input / output circuit 1 is a circuit using a low-voltage transistor and is capable of inputting and outputting voltage signals approximately three times the transistor's breakdown voltage. The input / output circuit 1 is provided, for example, in the IO cell (signal input / output section) of an LSI. In this case, the input / output pad of the LSI corresponds to the input / output terminal INOUT.

[0016] The first input signal IN1 transitions between VSS and VDD, and the first output signal OUT1 transitions between VSS and 3VDD. VDD is the power supply voltage of power supply VDD (corresponding to the third power supply), 2VDD is the power supply voltage of power supply 2VDD (corresponding to the second power supply), 3VDD is the power supply voltage of power supply 3VDD (corresponding to the first power supply), and VSS is the power supply voltage of ground VSS (corresponding to the fourth power supply). The relative magnitudes of these power supply voltages are "VSS < VDD < 2VDD < 3VDD". For example, VDD is a low voltage of less than 1.0 [V], and typically decreases with the miniaturization of transistors. For example, 2VDD is twice the voltage of VDD, and 3VDD is three times the voltage of VDD.

[0017] [Configuration of Input / Output Circuit] As shown in Figure 1, the input / output circuit 1 comprises an output circuit 2 and an input circuit 3. The output circuit 2 comprises an output driver 10, a control circuit 20, and a buffer circuit 30. The input circuit 3 comprises an input buffer circuit 40 and a step-down circuit 50. Note that each transistor described below is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, there is no intention to limit it to MOSFETs, and alternative transistors or switching elements may be used.

[0018] The input / output circuit 1 is switched by a mode switching signal EN input from the mode switching terminal EN to operate in either an input mode that receives a second input signal IN2 from the input / output terminal INOUT, or an output mode that outputs a first output signal OUT1 from the input / output terminal INOUT.

[0019] -Output Driver- The output driver 10 is a circuit that outputs a first output signal OUT1 (amplitude: VSS to 3VDD), which changes according to a first input signal IN1 (amplitude: VSS to VDD) input to the internal input terminal IN1, to the input / output terminal INOUT. The specific operation of the output driver 10 will be explained later. The internal input terminal IN1 is, for example, a node that connects a circuit within the LSI (not shown) to the output driver 10.

[0020] The output driver 10 includes P-type transistors P1, P2, and P3 connected in series between the power supply 3VDD and the input / output terminal INOUT, and N-type transistors N3, N2, and N1 connected in series between the input / output terminal INOUT and the ground VSS. The P-type transistors P1, P2, P3, and P4 (described later) and the N-type transistors N1, N2, N3, and N4 (described later) are so-called low-voltage transistors. In the following, when P-type transistors P1 to P4 and N-type transistors N1 to N4 are described without distinction, they may be collectively referred to simply as "low-voltage transistors." In this example, low-voltage transistors are transistors that, when viewed individually, have a voltage rating of VDD + α. α is, for example, a value approximately equal to the threshold voltage of the transistor.

[0021] The P-type transistor P1 (corresponding to the first P-type transistor) has its source connected to power supply 3VDD and its drain connected to node n1 (corresponding to the first node). The gate of the P-type transistor P1 is connected to the output 31 of the buffer circuit 30 via node n6, and receives a signal from the buffer circuit 30 that changes according to the first input signal IN1. The P-type transistor P2 (corresponding to the second P-type transistor) has its source connected to node n1, its drain connected to node n2 (corresponding to the second node), and its gate connected to power supply 2VDD. The P-type transistor P3 (corresponding to the third P-type transistor) has its source connected to node n2, its drain connected to the input / output terminal INOUT, and its gate connected to node n3 (corresponding to the third node).

[0022] N-type transistor N3 (corresponding to the first N-type transistor) has its drain connected to the input / output terminal INOUT, its source connected to node n4 (corresponding to the fourth node), and its gate connected to node n3. N-type transistor N2 (corresponding to the second N-type transistor) has its drain connected to node n4, its source connected to node n5 (corresponding to the fifth node), and its gate connected to the power supply VDD. N-type transistor N1 (corresponding to the third N-type transistor) has its drain connected to node n5 and its source connected to ground VSS. The gate of N-type transistor N1 is connected to the output 32 of buffer circuit 30 via node n7, and receives a signal from buffer circuit 30 that changes according to the first input signal IN1.

[0023] -Control Circuit- The control circuit 20 is a circuit that controls the voltage of the gates of the P-type transistor P3 and the N-type transistor N3, i.e., the voltage amplitude of node n3, in the range of VDD to 2VDD, according to the voltages of nodes n2 and n4 of the output driver 10. Node n3 is also connected to the gates of the P-type transistor P5 and the N-type transistor N5 of the input buffer circuit 40, which will be described later. In other words, the control circuit 20 controls the voltage amplitude of the gate voltages of the P-type transistor P5 and the N-type transistor N5 in the range of VDD to 2VDD, according to the voltages of nodes n2 and n4 of the output driver 10.

[0024] The control circuit 20 includes an N-type transistor N4 (corresponding to a fourth N-type transistor) and a P-type transistor P4 (corresponding to a fourth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The drain of the N-type transistor N4 is connected to the power supply 2VDD, the source is connected to node n3, and the gate is connected to node n2. The source of the P-type transistor P4 is connected to node n3, the drain is connected to the power supply VDD, and the gate is connected to node n4.

[0025] - Buffer Circuit - The buffer circuit 30 propagates a signal that changes in response to the first input signal IN1 to nodes n6 and n7. Specifically, the buffer circuit 30 propagates a signal that changes between 3VDD and 2VDD as output 31 to node n6 in response to the change in the input signal from VSS to VDD. In other words, the buffer circuit 30 shifts (boosts) the input signal that changes between VSS and VDD to a signal that changes between 3VDD and 2VDD and propagates it to node n6. The buffer circuit 30 also propagates a signal that changes between VDD and VSS as output 32 to node n7 in response to the change in the input signal from VSS to VDD.

[0026] The buffer circuit 30 is equipped with a mode switching terminal EN for switching between input and output modes. As described above, the mode switching signal EN input to the mode switching terminal EN switches between operating in input mode and operating in output mode.

[0027] Note that the buffer circuit 30 is not an essential component of the input / output circuit 1. For example, the buffer circuit 30 may be provided outside of the input / output circuit 1.

[0028] -Input Buffer Circuit- The input buffer circuit 40 propagates the signal that changes between VDD and 2VDD to node n8 (corresponding to the sixth node) in response to the change from VDD to 2VDD at node n3.

[0029] The input buffer circuit 40 includes a P-type transistor P5 (corresponding to a fifth P-type transistor) and an N-type transistor N5 (corresponding to a fifth N-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The source of the P-type transistor P5 is connected to the power supply 2VDD, the drain is connected to node n8, and the gate is connected to node n3. The source of the N-type transistor N5 is connected to the power supply VDD, the drain is connected to node n8, and the gate is connected to node n3. Note that the configuration of the input buffer circuit 40 is not limited to the configuration shown in Figure 1. For example, a Schmitt circuit may be used as the input buffer circuit 40.

[0030] -Step-Down Circuit- The step-down circuit 50 steps down the Low potential from VDD to VSS and the High potential from 2VDD to VDD. In other words, the step-down circuit 50 outputs a signal that changes between VSS and VDD to the internal output terminal C in response to the change from VDD to 2VDD at node n8. The specific configuration of the step-down circuit 50 is not particularly limited, and a conventionally known general step-down circuit (level shift circuit) can be used.

[0031] [Operation of Input / Output Circuits] The operation of input / output circuit 1 will be explained below, focusing on the terminal voltages of the P-type transistor P3 and the N-type transistor N3. In the following explanation, the gate-drain voltage of a transistor will be simply referred to as Vgd. Similarly, the gate-source voltage will be simply referred to as Vgs, and the drain-source voltage will be simply referred to as Vds. In addition, the threshold voltage of the P-type transistor will be referred to as Vtp, and the threshold voltage of the N-type transistor will be referred to as Vtn.

[0032] (Operation Example 1) Output Mode Figure 2 shows the voltage of each node and the on / off state of each transistor in an example of operation in output mode. The mode switching signal EN is set to output mode.

[0033] (Operation Example 1-1) When IN1 = VSS and OUT1 = VSS, when IN1 = VSS, n7 = VDD, and N-type transistors N1 and N2 turn on, resulting in n4 = VSS. Then, P-type transistor P4 turns on, resulting in n3 = VDD, and N-type transistor N3 turns on, resulting in OUT1 = VSS. Also, when IN1 = VSS, n6 = 3VDD, and P-type transistor P1 turns off. As described above, n3 = VDD, so n2 = VDD + Vtp. VDD + Vtp < 2VDD, so N-type transistor N4 turns off.

[0034] Here, Vgd for the P-type transistor P3 and the N-type transistor N3 is the voltage between node n3 and the input / output terminal INOUT, and |Vgd| = VDD. This is below the breakdown voltage of a low-voltage transistor. Also, for the P-type transistor P3, Vgs = (VDD + Vtp) - VDD = Vtp and Vds = (VDD + Vtp) - VSS = VDD + Vtp, so both are below the breakdown voltage of a low-voltage transistor. Similarly, for the N-type transistor N3, Vgs = VDD - VSS = VDD and Vds = VSS - VSS = 0 [V], so both are below the breakdown voltage of a low-voltage transistor.

[0035] (Operation Example 1-2) When IN1 = VDD and OUT1 = 3VDD When IN1 = VDD, n6 = 2VDD, and P-type transistors P1 and P2 turn on, resulting in n2 = 3VDD. Then, N-type transistor N4 turns on, resulting in n3 = 2VDD, and P-type transistor P3 turns on, resulting in OUT1 = 3VDD. When IN1 = VDD, n7 = VSS, and N-type transistor N1 turns off. As described above, n3 = 2VDD, so n4 = 2VDD - Vtn. Since 2VDD - Vtn > VDD, P-type transistor P4 turns off.

[0036] Here, Vgd for the P-type transistor P3 and the N-type transistor N3 is the voltage between node n3 and the input / output terminal INOUT, and Vgd = 3VDD - 2VDD = VDD. This is below the breakdown voltage of a low-voltage transistor. Also, for the P-type transistor P3, Vgs = 3VDD - 2VDD = VDD and Vds = 3VDD - 3VDD = 0 [V], so both are below the breakdown voltage of a low-voltage transistor. Similarly, for the N-type transistor N3, Vgs = 2VDD - (2VDD - Vtn) = Vtn and Vds = 3VDD - (2VDD - Vtn) = VDD + Vtn, so both are below the breakdown voltage of a low-voltage transistor.

[0037] (Operation Example 1-3) IN1 = VSS → VDD, OUT1 = VSS → 3VDD The left side of Figure 2 shows an example of the operation waveform for IN1 = VSS → VDD, OUT1 = VSS → 3VDD. Here, we will explain the operation in which the first input signal IN1 transitions from Low to High and the first output signal OUT1 changes from Low to High. When the first input signal IN1 transitions from Low to High, the on / off state of each transistor transitions from the state of "Operation Example 1-1" described above to the state of "Operation Example 1-2". Here, we will explain the operation related to the terminal voltage of the P-type transistor P3 and the N-type transistor N3.

[0038] When the first input signal IN1 transitions from Low to High, P-type transistors P1, P2, and P3 turn on, and the voltage of the first output signal OUT1 and node n2 rises toward 3VDD. As the voltage of the first output signal OUT1 and node n2 rises, N-type transistor N4 turns on, and the voltage of node n3 rises toward 2VDD.

[0039] In this case, the start of the voltage rise at node n3 is delayed by the time T1 required for the N-type transistor N4 to turn on, which is delayed by the start of the rise of the first output signal OUT1. Therefore, the |Vgd| of the P-type transistor P3 and the N-type transistor N3 is maintained below VDD, even while the first output signal OUT1 changes from Low to High, and remains below the breakdown voltage of the low-voltage transistor. The same applies to the |Vgs| and |Vds| of the P-type transistor P3 and the N-type transistor N3; they are maintained at voltages below the breakdown voltage of the low-voltage transistor even while the first output signal OUT1 changes from Low to High.

[0040] (Operation Example 1-4) When IN1 = VDD → VSS, OUT1 = 3VDD → VSS, the right side of Figure 2 shows the waveform when IN1 = VDD → VSS, OUT1 = 3VDD → VSS, that is, when the first input signal IN1 transitions from High to Low and the first output signal OUT1 changes from High to Low.

[0041] When the first input signal IN1 transitions from High to Low, the on / off state of each transistor transitions from the state described in "Operation Example 1-2" to the state described in "Operation Example 1-1". Here, we will explain the operation related to the terminal voltage of the P-type transistor P3 and the N-type transistor N3.

[0042] When the first input signal IN1 transitions from High to Low, N-type transistors N1, N2, and N3 turn on, and the voltage of the first output signal OUT1 and node n4 decreases toward VSS. As the voltage of the first output signal OUT1 and node n4 decreases, P-type transistor P4 turns on, so the voltage of node n3 decreases from 2VDD toward VDD.

[0043] At this time, the start of the voltage drop of node n3 is delayed from the start of the voltage drop of the first output signal OUT1 by the time T2 until the P-type transistor P4 is turned on. Therefore, |Vgd| of the P-type transistor P3 and the N-type transistor N3 is maintained at or below VDD even while the first output signal OUT1 changes from High to Low, and becomes below the breakdown voltage of the low-voltage transistor. The same applies to |Vgs| and |Vds| of the P-type transistor P3 and the N-type transistor N3, and they are maintained at a voltage below the breakdown voltage of the low-voltage transistor even while the first output signal OUT1 changes from High to Low.

[0044] (Operation Example 2) Input Mode Figure 3 shows the voltages of each node and the on / off states of each transistor in the operation example of the input mode. The mode switching signal EN is set to the input mode. When the mode switching signal EN is set to the input mode, n6 = 3VDD and n7 = VSS. In FIG. 3, the waveform in the second row from the bottom shows the change in |Vgd| of the P-type transistor P3 and the N-type transistor N3. Also, the waveform in the first row from the bottom shows the change in |Vgd| of the P-type transistor P5 and the N-type transistor N5 with a solid line.

[0045] (Operation Example 2-1) When IN2 = VSS → 3VDD and OUT2 = VSS → VDD Here, the operation in which the second input signal IN2 input to the input / output terminal INOUT transitions from Low to High will be described. The left side of FIG. 3 is a waveform diagram related to the operation of IN2 = VSS → 3VDD and OUT2 = VSS → VDD.

[0046] During the process in which the second input signal IN2 transitions from Low to High (from VSS to 3VDD), the P-type transistor P3 turns on, and the voltage of node n2 rises toward 3VDD. During this process, the N-type transistor N4 turns on, and the voltage of node n3 rises from VDD to 2VDD. Also, the N-type transistor N3 and the P-type transistor P4 turn off. Here, the start of the rising of the voltage of node n3 is delayed from the start of the rising of the second input signal IN2 by the time T3 until the N-type transistor N4 turns on. Therefore, |Vgd| of the P-type transistor P3 and the N-type transistor N3 is maintained below VDD even while the second input signal IN2 changes from Low to High, and becomes below the breakdown voltage of the low breakdown voltage transistor. The same applies to |Vgs| and |Vds| of the P-type transistor P3 and the N-type transistor N3, and they are maintained at a voltage below the breakdown voltage of the low breakdown voltage transistor even while the input signal IN2 changes from Low to High.

[0047] The input buffer circuit 40 has the high potential side power supply connected to 2VDD and the low potential side power supply connected to VDD. Therefore, when the voltage of the input / output terminal INOUT transitions from Low to High, the input buffer circuit 40 outputs an output signal that transitions from High (2VDD) to Low (VDD) to node n8. Here, the input of the input buffer circuit 40 is connected to node n3. Therefore, similar to the P-type transistor P3 and the N-type transistor N3, |Vgd| of the P-type transistor P5 and the N-type transistor N5 is maintained below VDD while the voltage of the input / output terminal INOUT transitions from Low to High. The same applies to |Vgs| and |Vds| of the P-type transistor P5 and the N-type transistor N5, and they are maintained below VDD while the voltage of the input / output terminal INOUT transitions from Low to High.

[0048] As described above, the step-down circuit 50 steps down the Low potential from VDD to VSS and steps down the High potential from 2VDD to VDD. Specifically, when the voltage of the input / output terminal INOUT transitions from Low to High, the step-down circuit 50 outputs an output signal that transitions from Low (VSS) to High (VDD) to the internal output terminal C.

[0049] (Operation Example 2-2) IN2 = 3VDD → VSS, OUT2 = VDD → VSS Here, we will explain the operation in which the second input signal IN2, which is input to the input / output terminal INOUT, transitions from High to Low. The right side of Figure 3 is a waveform diagram related to the operation of IN2 = 3VDD → VSS, OUT2 = VDD → VSS.

[0050] As the second input signal IN2 transitions from High to Low (from 3VDD to VSS), the N-type transistor N3 turns on, and the voltage at node n4 decreases toward VSS. During this process, the P-type transistor P4 turns on, and the voltage at node n3 decreases toward VDD from 2VDD. Also, the P-type transistor P3 and the N-type transistor N4 turn off. Here, the start of the falling edge of the voltage at node n3 is delayed by the time T4 required for the P-type transistor P4 to turn on, which is delayed by the start of the falling edge of the second input signal IN2. Therefore, the |Vgd| of the P-type transistor P3 and the N-type transistor N3 remains below VDD even while the second input signal IN2 is changing from High to Low, and is below the breakdown voltage of the low-voltage transistors. The same applies to |Vgs| and |Vds| of the P-type transistor P3 and N-type transistor N3; even while the second input signal IN2 changes from High to Low, the voltage is maintained below the breakdown voltage of the low-voltage transistor.

[0051] As described above, the input of the input buffer circuit 40 is connected to node n3. The input buffer circuit 40 has a high-potential power supply connected to 2VDD and a low-potential power supply connected to VDD. Therefore, when the voltage of the input / output terminal INOUT transitions from High to Low, the input buffer circuit 40 outputs an output signal to node n8 that transitions from Low (VDD) to High (2VDD). The |Vgd|, |Vgs|, and |Vds| of the P-type transistor P5 and the N-type transistor N5 are maintained below VDD while the voltage of the input / output terminal INOUT transitions from Low to High.

[0052] As described above, the step-down circuit 50 steps down the Low potential from VDD to VSS and the High potential from 2VDD to VDD. Therefore, when the voltage at the input / output terminal INOUT transitions from High to Low, the step-down circuit 50 outputs an output signal that transitions from High (VDD) to Low (VSS) to the internal output terminal C.

[0053] [Effects of the First Embodiment] According to this embodiment, the control circuit 20 controls the gate voltages of P-type transistors P3, P5 and N-type transistors N3, N5 according to the characteristics of the output signal or input signal to the input / output terminal INOUT, which fluctuate depending on the breakdown voltage and operating voltage of the transistors. As a result, during the operation of the input / output circuit 1, the |Vgd|, |Vgs|, and |Vds| of the P-type transistors P1 to P5 and N-type transistors N1 to N5 are maintained at a state below the breakdown voltage of the low-breakdown transistors. As a result, compared to the conventional technology, the degradation of transistors over time can be effectively prevented.

[0054] Furthermore, the output driver 10 and control circuit 20 located in the output circuit 2 control the voltage amplitude which changes in accordance with the transition of the second input signal IN2 input from outside the LSI. This eliminates the need for a dedicated control circuit equivalent to the control circuit 20 in the input circuit 3, thereby simplifying the design and reducing the circuit area. In addition, since the control circuit 20 according to this embodiment has a very simple configuration consisting of two transistors, it is possible to simplify the design of the input / output circuit 1 and reduce the circuit area.

[0055] <Second Embodiment> Figures 4 and 5 are circuit diagrams of the input / output circuit according to the second embodiment. In Figures 4 and 5, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment.

[0056] [Configuration of Input / Output Circuits] The input / output circuits 1 in Figures 4 and 5 differ from the configuration in Figure 1 in that the internal configuration of the control circuit 20 is different. In other words, the configurations other than the control circuit 20 are the same in the input / output circuits of Figures 4 and 5.

[0057] Specifically, the control circuit 20 in Figure 4, in addition to the configuration in Figure 1, includes an N-type transistor N6 (corresponding to a sixth N-type transistor) and a P-type transistor P6 (corresponding to a sixth P-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The drain of the N-type transistor N6 is connected to the power supply 2VDD, and the source and gate are connected to node n3. The source and gate of the P-type transistor P6 are connected to node n3, and the drain is connected to the power supply VDD. The P-type transistor P6 and the N-type transistor N6 are the low-voltage transistors mentioned above.

[0058] The control circuit 20 in Figure 5, in addition to the configuration in Figure 1, includes a P-type transistor P6 (corresponding to a sixth P-type transistor) and an N-type transistor N6 (corresponding to a sixth N-type transistor) connected in series between the power supply 2VDD and the power supply VDD. The source and gate of the P-type transistor P6 are connected to the power supply 2VDD, and the drain is connected to node n3. The drain of the N-type transistor N6 is connected to node n3, and the source and gate are connected to the power supply VDD.

[0059] In Figures 4 and 5, the control circuit 20, similar to Figure 1, controls the gate voltages of the P-type transistor P3 and the N-type transistor N3, i.e., the voltage amplitude of node n3, within the range of VDD to 2VDD, according to the operation of the output driver 10.

[0060] Incidentally, when the first output signal OUT1 or the second input signal IN2 of the input / output terminal INOUT transitions, the voltage at node n3 may fluctuate unexpectedly due to the coupling of parasitic capacitance between the input / output terminal INOUT and node n3. For example, the voltage at node n3 may exceed 2VDD or fall below VDD. As shown in Figures 4 and 5, this voltage fluctuation can be suppressed by providing a P-type transistor P6 and an N-type transistor N6. Note that parasitic capacitance fluctuates due to factors such as the proximity of wiring within the circuit. Therefore, both the P-type transistor P6 and the N-type transistor N6 may be provided, or either the P-type transistor P6 or the N-type transistor N6 may be provided.

[0061] [Output Circuit Operation] In this embodiment as well, the basic operation of the input / output circuit 1 as a whole is the same as in the aforementioned "Operation Example 1" and "Operation Example 2". Here, we will mainly explain the configuration newly added in Figures 4 and 5.

[0062] In the input / output circuit 1 of Figure 4, when the voltage at node n3 rises above 2VDD, the N-type transistor N6 turns on during this process and acts to lower the voltage at node n3 to 2VDD. In the input / output circuit 1 of Figure 4, when the voltage at node n3 falls below VDD, the P-type transistor P6 turns on during this process and acts to raise the voltage at node n3 to VDD.

[0063] In the input / output circuit 1 of Figure 5, when the voltage at node n3 rises above 2VDD, the P-type transistor P6 turns on during this process and acts to lower the voltage at node n3 to 2VDD. In the input / output circuit 1 of Figure 5, when the voltage at node n3 falls below VDD, the N-type transistor N6 turns on during this process and acts to raise the voltage at node n3 to VDD.

[0064] [Effects of the Second Embodiment] According to this embodiment, even when the voltage of the parasitic capacitance coupling node n3 exceeds 2VDD or falls below VDD during the operation of the input / output circuit 1, the |Vgd|, |Vgs|, and |Vds| of the P-type transistors P1 to P6 and N-type transistors N1 to N6 are maintained at a state below the breakdown voltage of the low-voltage transistors. As a result, the degradation of transistors over time can be effectively prevented compared to the conventional technology.

[0065] Furthermore, the output driver 10 and control circuit 20 located in the output circuit 2 control the voltage amplitude which changes in accordance with the transition of the second input signal IN2 input from outside the LSI. This eliminates the need for a dedicated control circuit equivalent to the control circuit 20 in the input circuit 3, thereby simplifying the design and reducing the circuit area. In addition, since the control circuit 20 according to this embodiment has a very simple configuration consisting of four transistors, it is possible to simplify the design of the input / output circuit 1 and reduce the circuit area.

[0066] <Other Embodiments> The technology in this disclosure is not limited to the configurations described in the embodiments above, and many modifications, such as changes, substitutions, additions, and omissions, can be made as appropriate by a person with ordinary skill in the art within the technical concept of this disclosure. Furthermore, it is possible to combine the components described in the embodiments above to create new embodiments.

[0067] For example, in the above embodiment, the power supply voltage of power supply 3VDD is not limited to three times the voltage of VDD. In other words, the amplitude of the output signal voltage is not limited to three times VDD. For example, by adjusting the voltage of each node, voltages exceeding three times VDD or voltages below three times VDD can be output as the first output signal OUT1 from the input / output terminal INOUT, or input as the second input signal IN2 from the input / output terminal INOUT.

[0068] This disclosure effectively prevents the aging degradation of transistors, making it useful as an input / output circuit for LSIs.

[0069] 1 Input / Output Circuit IN1 First Input Signal INOUT Input / Output Terminal N1 N-type transistor (3rd N-type transistor) N2 N-type transistor (2nd N-type transistor) N3 N-type transistor (1st N-type transistor) N4 N-type transistor (4th N-type transistor) N5 N-type transistor (5th N-type transistor) N6 N-type transistor (6th N-type transistor) P1 P-type transistor (1st P-type transistor) P2 P-type transistor (2nd P-type transistor) P3 P-type transistor (3rd P-type transistor) P4 P-type transistor (4th P-type transistor) P5 P-type transistor (5th P-type transistor) P6 P-type transistor (6th P-type transistor) VDD Power supply (3rd power supply) 2VDD Power supply (2nd power supply) 3VDD Power supply (1st power supply) VSS Ground (4th power supply) n1 Node (1st node) n2 Node (2nd node) n3 Node (3rd node) n4 Node (4th node) n5 Node (5th node) n8 Node (6th node)

Claims

1. An input / output circuit that receives a first input signal, outputs an output signal that changes according to the first input signal from an input / output terminal, and receives a second input signal input to the input / output terminal, comprising: a first P-type transistor whose source is connected to a first power supply, whose drain is connected to a first node, and whose gate receives a signal that changes according to the first input signal; a second P-type transistor whose source is connected to the first node, whose drain is connected to a second node, and whose gate is connected to a second power supply with a lower power supply voltage than the first power supply; a third P-type transistor whose source is connected to the second node, whose drain is connected to the input / output terminal, and whose gate is connected to a third node; a first N-type transistor whose drain is connected to the input / output terminal, whose source is connected to a fourth node, and whose gate is connected to the third node; and a second N-type transistor whose drain is connected to the fourth node, whose source is connected to a fifth node, and whose gate is connected to a third power supply with a lower power supply voltage than the second power supply. An input / output circuit comprising: a third N-type transistor whose drain is connected to the fifth node, whose source is connected to a fourth power supply having a lower power supply voltage than the third power supply, and whose gate receives a signal that changes according to the first input signal; a fourth N-type transistor whose drain is connected to the second power supply, whose source is connected to the third node, and whose gate is connected to the second node; a fourth P-type transistor whose source is connected to the third node, whose drain is connected to the third power supply, and whose gate is connected to the fourth node; a fifth P-type transistor whose source is connected to the second power supply, whose drain is connected to the sixth node, and whose gate is connected to the third node; and a fifth N-type transistor whose source is connected to the third power supply, whose drain is connected to the sixth node, and whose gate is connected to the third node.

2. An input / output circuit according to claim 1, comprising: a sixth N-type transistor whose drain is connected to the second power supply and whose source and gate are connected to the third node; and a sixth P-type transistor whose source and gate are connected to the third node and whose drain is connected to the third power supply.

3. An input / output circuit according to claim 1, comprising: a sixth P-type transistor whose source and gate are connected to the second power supply and whose drain is connected to the third node; and a sixth N-type transistor whose source and gate are connected to the third power supply and whose drain is connected to the third node.

Images