Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device according to the present invention comprises: first lower layer wiring which is connected to upper layer wiring formed in an upper layer wiring layer and is formed in a lower layer wiring layer; and second lower layer wiring which is not connected to the upper layer wiring and is formed in the lower layer wiring layer. This semiconductor device comprises: an air gap formed in contact with the first lower layer wiring and the second lower layer wiring; and a lower layer insulating layer in contact with the second lower layer wiring on the opposite side from the air gap.

Description

Semiconductor device and method for manufacturing the same

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002] As semiconductor devices are miniaturized, a technique for replacing the insulating layer between wirings with an air gap is used to reduce the capacitance between interconnects and improve the switching speed. As a method for forming an air gap, for example, a method of forming an insulating film with poor embedding properties after forming the wiring has been proposed. Also, a method of removing the insulating film by wet etching after forming the wiring has been proposed (see, for example, Patent Document 1 and Patent Document 2).

[0003] U.S. Patent Application Publication No. 2010 / 38797, U.S. Patent Application Publication No. 2018 / 76082

[0004] However, in the method of forming an insulating film with poor embedding properties, the shape of the air gap is likely to vary depending on the distance between the wirings. Therefore, in this method, an insulating film is formed in part of the space between the wirings, and a complete air gap cannot be formed. Also, the method of removing the insulating film by wet etching has a problem in controlling the penetration range of the chemical solution. In particular, in the method of removing the insulating film by wet etching, when there is a wide area without wiring, the chemical solution may penetrate into the insulating film more than necessary.

[0005] In order to solve the above problems, the present invention provides a semiconductor device capable of forming a highly accurate air gap and a method for manufacturing the same.

[0006] The semiconductor device of the present invention includes a lower wiring layer and an upper wiring layer. The lower wiring includes a first lower wiring and a second lower wiring. The first lower wiring is formed in the lower wiring layer and is connected to an upper wiring formed in the upper wiring layer. Also, the second lower wiring is formed in the lower wiring layer and is not connected to the upper wiring. Further, the semiconductor device includes an air gap formed in contact with the first lower wiring and the second lower wiring, and a lower insulating layer formed in contact with the second lower wiring on the side opposite to the air gap.

[0007] Furthermore, the present invention relates to a method for manufacturing a semiconductor device comprising a lower wiring layer and an upper wiring layer. The method for manufacturing a semiconductor device includes the steps of forming a first lower wiring connected to an upper wiring formed on the upper wiring layer, a second lower wiring not connected to the upper wiring, and a lower insulating layer in the area excluding the first and second lower wirings on the lower wiring layer. The method for manufacturing a semiconductor device also includes the steps of forming a third upper insulating layer and a first upper insulating layer on the lower wiring layer, and forming wiring grooves in the third upper insulating layer and the first upper insulating layer that expose the upper surface of the first lower wiring. The method for manufacturing a semiconductor device also includes the steps of removing the lower insulating layer from the wiring grooves between the first lower wirings and between the first and second lower wirings to form an air gap. The method for manufacturing a semiconductor device also includes the steps of forming a second upper insulating layer that closes the upper part of the air gap and forming upper wiring connected to the first lower wiring.

[0008] According to the present invention, it is possible to provide a semiconductor device capable of forming a highly accurate air gap, and a method for manufacturing a semiconductor device.

[0009] This is a schematic diagram of a semiconductor device according to the first embodiment. This is a diagram showing an example of a wiring structure applied to a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a schematic diagram of a semiconductor device according to the third embodiment. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a manufacturing process diagram of a semiconductor device. This is a schematic diagram of a modified semiconductor device. This is a schematic diagram of a modified semiconductor device.

[0010] The following describes examples of embodiments for carrying out the present invention, but the present invention is not limited to these examples. The description will be in the following order: 1. Configuration of a semiconductor device (first embodiment) 2. Manufacturing method of a semiconductor device (second embodiment) 3. Configuration of a semiconductor device (third embodiment) 4. Manufacturing method of a semiconductor device (fourth embodiment)

[0011] <1. Configuration of the Semiconductor Device (First Embodiment)> The following describes a specific embodiment of the semiconductor device of the present invention. Figure 1 shows a schematic configuration diagram of the semiconductor device of the first embodiment. The semiconductor device 100 shown in Figure 1 is a cross-sectional view of a part of the wiring structure of the semiconductor device. Figure 1 shows only the wiring structure of the semiconductor device 100.

[0012] As shown in Figure 1, the wiring structure of the semiconductor device 100 is formed on an insulating layer 111. The insulating layer 111 is formed on, for example, a semiconductor substrate (silicon substrate) on which semiconductor elements such as transistors and diodes that constitute an integrated circuit are formed. The semiconductor elements formed on the semiconductor device 100 are not particularly limited.

[0013] The semiconductor device 100 has a wiring region 110 and a dummy wiring region 150. The semiconductor device 100 also has a wiring layer of the lower layer 120 (lower wiring layer) and a wiring layer of the upper layer 130 (upper wiring layer). In Figure 1, the interface between the wiring layer of the lower layer 120 and the wiring layer of the upper layer 130 in the semiconductor device 100 is shown by a dashed line 160. The wiring formed in the wiring region 110 and the dummy wiring region 150 is made of, for example, copper, ruthenium, molybdenum, or cobalt. In the case of copper wiring, a Co cap layer may be present on the copper wiring to prevent oxidation.

[0014] The wiring region 110 has wirings 102, 103, 104, and 105 (first lower layer wirings) in the lower layer 120. An air gap 101 is placed between the wirings 102, 103, 104, and 105 formed in the lower layer 120. Here, an air gap refers to a vacuum or air layer provided between the wirings to achieve a low dielectric constant. Furthermore, the vacuum is not limited to a perfect vacuum. Vacuum means that substantially no other materials are contained, and does not exclude cases where small amounts of unavoidable impurities may be present. The wiring region 110 has an air gap 101 between the wiring 102 formed closest to the dummy wiring region 150 and the wiring 151 (second lower layer wiring) formed in the dummy wiring region 150. With this structure, the semiconductor device 100 is surrounded by the air gap 101 around the wirings 102, 103, 104, and 105 formed in the lower layer 120 of the wiring region 110 in the direction of the substrate surface.

[0015] In the wiring region 110, wiring 106 and 107 (upper layer wiring) is formed on the upper layer 130. In addition, insulating layers 112, 113, 114, and 157 (first upper insulating layer) are formed on the upper layer 130 of the wiring region 110 and the dummy wiring region 150. In the wiring region 110, insulating layers 112, 113, and 114 are formed between wiring 106 and 107. Furthermore, in the upper layer 130 of the wiring region 110 and the dummy wiring region 150, insulating layers 115, 116, 117, 118, and 119 (second upper insulating layer) are formed between wiring 106 and 107 and insulating layers 112, 113, 114, and 157. Between wiring 106 and insulating layer 112, insulating layers 115 and 116 are formed, except for the upper part of insulating layer 112. An insulating layer 117 is formed between the wiring 106 and 107 and the insulating layer 113. An insulating layer 118 is formed between the wiring 107 and the insulating layer 114. Furthermore, on the dummy wiring region 150 side of the wiring 106, an insulating layer 119 is formed between it and the insulating layer 157 formed on top of the dummy wiring region 150. The insulating layers 115, 116, 117, 118, and 119 are made of, for example, SiO ２ They are formed from SiC and SiN. Note that wiring 106 and 107 may be vias connecting the upper and lower layers of wiring, not just wiring.

[0016] Furthermore, insulating layers 115, 116, 117, 118, and 119 are formed not only between the wiring 106, 107 and insulating layers 112, 113, 114, and 157, but also on the lower layer 120 side, on a portion of the upper side of the sides of the wiring 102, 103, 104, and 105. Moreover, insulating layers 115, 116, 117, 118, and 119 are continuously formed from the upper side of the sides of the wiring 102, 103, 104, and 105 to the lower side of insulating layers 112, 113, 114, and 157. In other words, insulating layers 115, 116, 117, 118, and 119 are formed above the air gap 101 and between insulating layers 112, 113, 114, and 157.

[0017] The dummy wiring region 150 has wirings 151 and 152 on the lower layer 120. An insulating layer 155 (lower insulating layer) is placed between the wirings 151 and 152 formed on the lower layer 120. The dummy wiring region 150 has an insulating layer 156 (third upper insulating layer) on the upper layer 130 above the insulating layer 155. The insulating layer 156 is made of, for example, aluminum oxide (AlO Ｘ The insulating layer 156 is formed from materials such as AlN, SiCN, SiOC, SiON, and SiwCxOyNz-based materials. The insulating layer 156 is selectively formed on the insulating layer 155. The insulating layer 156 is formed as a thin film directly in contact with the insulating layer 155. The insulating layer 156 serves as a pathway for the chemical solution to penetrate during wet etching in the wiring region 110. After wet etching, it is necessary to seal the formed penetration pathway. For this reason, the thickness of the insulating layer 156 is preferably 2 nm or more and 4 nm or less. If the thickness of the insulating layer 156 is less than 2 nm, the chemical solution will not penetrate easily during wet etching, and the etching process will likely be insufficient. Also, if the thickness of the insulating layer 156 is less than 2 nm, the etching process will take longer. Furthermore, if the thickness of the insulating layer 156 exceeds 4 nm, it will be difficult to seal the penetration pathway after wet etching. In other words, by setting the thickness of the insulating layer 156 to 2 nm or more and 4 nm or less, it is easier to form a highly accurate air gap.

[0018] Furthermore, the dummy wiring area 150 has an insulating layer 157 on the upper layer 130. The insulating layer 157 is formed over the entire upper layer 130, except for the insulating layer 156. The insulating layer 157 is in contact with the wiring 151 and 152 formed on the lower layer 120 of the dummy wiring area 150. In addition, an insulating layer 119 is formed between the insulating layer 157 and the upper part of the air gap 101. The insulating layer 157 is exposed to the air gap 101 from between the insulating layer 119 and the wiring 151.

[0019] In the wiring region 110, the wirings 102, 103, 104, and 105 formed in the lower layer 120 are connected to the wirings 106 and 107 formed in the upper layer 130. In the configuration shown in Figure 1, the wirings 102 and 104 of the lower layer 120 are commonly connected to the wiring 106 of the upper layer 130. The wiring 105 of the lower layer 120 is connected to the wiring 107 of the upper layer 130. In addition, the wiring 103 of the lower layer 120 is connected to other wirings of the upper layer 130 that are not shown.

[0020] On the other hand, in the dummy wiring area 150, no wiring is formed on the upper layer 130. Therefore, the dummy wiring area 150 is a so-called dummy wiring, in which the wiring 151 and 152 formed on the lower layer 120 are not connected to the wiring on the upper layer 130.

[0021] In the semiconductor device 100, the air gap 101 is formed by wet etching the insulating layer formed on the lower layer 120. That is, the insulating layer positioned to form the air gap 101 is a so-called sacrificial layer that is removed in a later process. In the semiconductor device 100, the insulating layer (sacrificial layer) removed by wet etching is formed simultaneously with the formation of the insulating layer 155. For this reason, the insulating layer 155 is formed from the same material as the sacrificial layer used to form the air gap 101.

[0022] The insulating layer 111 is formed of a material that has higher resistance to wet etching chemicals than the insulating layer 155. Similarly, the insulating layers 113, 114, and 157 are also formed of materials that have higher resistance to wet etching chemicals than the insulating layer 155. For example, it is preferable that the etching rate of insulating layer 111 and insulating layers 113, 114, and 157 is 1 / 100 or less than that of insulating layer 155. As a specific example, insulating layer 155 having the same composition as the sacrificial layer is made of SiO ２ When forming the material and using dilute hydrogen fluoride (DHF) as the wet etching solution, it is preferable that the insulating layer 111 is made of SiCN and the insulating layers 113, 114, and 157 are made of SiCO.

[0023] The semiconductor device 100 has an air gap 101 between the wirings 102, 103, 104, and 105 of the lower layer 120, thereby suppressing parasitic capacitance between the wirings 102, 103, 104, and 105. Furthermore, the semiconductor device 100 has an insulating layer 111 with high etching resistance located below the air gap 101. Therefore, when the sacrificial layer is removed by wet etching to form the air gap 101, the insulating layer 111 functions as an etching stopper. In addition, the semiconductor device 100 has wiring 151, which is a dummy wiring of the dummy wiring region 150, located in contact with the air gap 101. Therefore, when the sacrificial layer is removed by wet etching to form the air gap 101, the dummy wiring 151 functions as an etching stopper. As a result, it is possible to prevent the sacrificial layer from being etched more than necessary during the process of removing the sacrificial layer by wet etching to form the air gap 101. Thus, the semiconductor device 100 has a highly accurate air gap in its miniaturized wiring structure.

[0024] Furthermore, the upper layer 130 has a lower wiring density compared to the lower layer 120, and is less affected by capacitance between wires. For this reason, insulating layers 113 and 114 may be placed between wires 106 and 107 in the upper layer 130. Also, since the dummy wires 151 and 152 are not connected to other wires, they do not carry current. Therefore, even if an insulating layer 155 is formed between wires 151 and 152, parasitic capacitance between wires does not occur. Consequently, it is not necessary to form an air gap between the dummy wires 151 and 152.

[0025] [Example of Wiring Arrangement] Next, Figure 2 shows an example of a wiring structure applied to the semiconductor device 100. The wiring structure example shown in Figure 2 is a plan view mainly showing the arrangement of wiring and air gaps in the lower layer 120. In the semiconductor device 100, an insulating layer 201 (lower insulating layer) is formed over the entire surface of the lower layer 120. The insulating layer 201 has the same configuration as the insulating layer 155 shown in Figure 1 above, and is formed between dummy wirings in the dummy wiring area. In addition, the insulating layer 201 is also formed in the wiring area at positions that do not affect the capacitance between wirings. In the semiconductor device 100, air gaps 202, 203, 204, 205, 206, and 207 are formed in the wiring area of ​​the lower layer 120.

[0026] The air gap 202 is formed within a region surrounded by dummy wiring 210 (second lower layer wiring). The region surrounded by wiring 210 is the wiring region. Wiring 221 (first lower layer wiring) is formed within this wiring region. The area around wiring 221 is surrounded by the air gap 202. Upper layer wiring 231 is connected to wiring 221. The area on the outer periphery of wiring 210 is the dummy wiring region. In this dummy wiring region, an insulating layer 201 is formed in contact with wiring 210. When fine wiring is densely packed and the wiring spacing is small, as with wiring 221, it is preferable to surround the area with dummy wiring 210 and form the air gap 202 over the entire inner circumference of wiring 210. By surrounding the air gap 202 with wiring 210, it is possible to suppress the air gap 202 from expanding more than necessary and to form the air gap 202 only in the desired location.

[0027] The air gap 203 is formed in the region sandwiched between dummy wirings 211 (second lower layer wirings). The wirings 211 are not formed to continuously enclose a single region like wiring 210. The wirings 211 are formed linearly in one direction and arranged at equal intervals. Between the wirings 211 are wirings 222 (first lower layer wirings) formed linearly in the same direction as the wirings 211. The area around the wirings 222 is surrounded by the air gap 203. The upper layer wiring 232 is connected to the wirings 222. Dummy wirings 211 are arranged on both sides of the air gap 203 in one direction, and no wiring is formed on both sides of the air gap 203 in the other direction. In this way, by forming the wirings 211 in at least one direction of the air gap 203, it is possible to suppress the air gap 203 from expanding more than necessary in that direction. The direction in which the wirings 211 are formed is preferably, for example, the direction in which the distance to adjacent wirings is large. This configuration eliminates the problem of the chemical solution seeping into the insulating film more than necessary when there are large areas without wiring, and allows the air gap 203 to be formed only in the desired locations.

[0028] Air gaps 204, 205, 206, and 207 are formed in the region between the dummy wirings 212 (second lower layer wiring) and 213 (second lower layer wiring). The area between wiring 212 and 213 is the wiring region, and the outer periphery between wiring 212 and 213 is the dummy wiring region. Multiple wirings 223 (first lower layer wiring) are formed in the wiring region. Also, wiring 224 (first lower layer wiring) is formed in the wiring region. Wiring 223 extends in the same direction as wiring 212 and 213 between wiring 212 and 213. Furthermore, wiring 223 is formed in multiple columns and multiple rows within the wiring region. Wiring 224 extends in a direction perpendicular to wiring 212 and 213 and is positioned between the wirings 223 arranged in the column direction. Upper layer wiring 233 is connected to each wiring 223. The upper wiring 234 is connected to wiring 224.

[0029] The wiring region formed between wiring 212 and wiring 213 has a large area. Therefore, if an air gap is formed throughout the entire wiring region, the strength of the lower wiring layer tends to decrease. For this reason, an insulating layer 209 is also formed within the wiring region. The insulating layer 209 is formed continuously in the direction of the three rows of wiring 223, near the center.

[0030] Furthermore, between wiring 212 and wiring 213, dummy wirings 214, 215, and 216 are formed adjacent to wiring 224. The strength of the wiring layer tends to decrease if there is a large area where no wiring is formed. For example, if the distance between wirings is 40 nm or more, the strength of the wiring layer tends to decrease. For this reason, in order to ensure the strength of the wiring layer, it is preferable to have a structure in which dummy wirings 214, 215, and 216 are formed in wiring areas where wiring connected to the upper layer is not formed (for example, areas where the distance between wirings is 40 nm or more). Wiring 214 is arranged between wirings 223. Wiring 214 extends in a direction perpendicular to wiring 223 and parallel to wiring 224. Between wirings 214, an insulating layer 201 is formed in part, and an air gap 206 is formed in the other area. Wirings 215 and 216 are arranged between wirings 223. Wiring 215 is formed to surround the periphery of wiring 216. Within the area of ​​wiring 215, wiring 216 and an insulating layer 201 are formed, and no air gap is formed.

[0031] Furthermore, dummy wiring 217 is formed in the dummy wiring region. If the area without wiring is large in the dummy wiring region, the strength of the underlying wiring layer tends to decrease. For this reason, even in the dummy wiring region, dummy wiring is formed in wiring areas where wiring is not formed (for example, areas where the distance between wirings is 40 nm or more) in order to ensure the strength of the wiring layer.

[0032] A wiring 225 (third lower layer wiring) is formed outside the wiring region surrounded by the dummy wiring 210, and the wiring region sandwiched by wirings 211, 212, and 213. The upper layer wiring 235 is connected to wiring 225. Wiring 225 is wider and longer than wirings 221, 222, 223, and 224 formed within the wiring region. In the case of wiring that is not miniaturized, such as wiring 225, if it has a width that is 4 nm or more greater than the width of the upper layer wiring (e.g., connecting via), an air gap does not need to be formed. Thus, wiring that connects to the upper layer wiring in the lower layer wiring does not need to be in contact with an air gap. For example, miniaturized wiring such as wirings 221, 222, 223, and 224 is preferably in contact with an air gap. Also, wiring that is formed to a sufficient size, such as wiring 225, does not need to be in contact with an air gap.

[0033] Furthermore, in the configuration shown in Figure 2 above, the air gap is surrounded by dummy wiring or in contact with dummy wiring in at least two directions. However, the air gap only needs to be in contact with dummy wiring in at least one direction. The air gap can suppress the excessive expansion of the etching area by the chemical solution during wet etching in the direction in which it is in contact with the dummy wiring. Therefore, it is possible to suppress the expansion of the air gap beyond what is necessary and to form a highly accurate air gap.

[0034] <2. Method for Manufacturing a Semiconductor Device (Second Embodiment)> Next, the method for manufacturing the semiconductor device described above will be explained. Figures 3 to 11 show the manufacturing process diagram of the semiconductor device 100. First, semiconductor elements such as transistors and diodes are formed on a semiconductor substrate to form an integrated circuit, etc. Then, as shown in Figure 3, an insulating layer 111 is formed on the substrate on which the semiconductor elements are formed. The insulating layer 111 is formed of, for example, SiCN. Then, as shown in Figure 3, an insulating layer 155 and wirings 102, 103, 104, 105, 151, 152 are formed on the insulating layer 111 using a conventionally known method, for example, the damascene method. For example, the insulating layer 155 is formed over the entire surface of the insulating layer 111. The insulating layer 155 is, for example, SiO ２The insulating layer 155 is formed using a photolithography exposure and development process to create a predetermined pattern for forming the wirings 102, 103, 104, 105, 151, and 152. Furthermore, after forming a conductive layer on the insulating layers 111 and 155, the surface is flattened, and the wirings 102, 103, 104, 105, 151, and 152 are formed between the insulating layers 155.

[0035] Next, as shown in Figure 4, an insulating layer 156 is selectively formed on the insulating layer 155 using aluminum oxide (AlO) or the like. For example, to form the insulating layer 156, a growth layer is selectively formed on the wiring 102, 103, 104, 105, 151, and 152. Next, a precursor layer for the insulating layer 156 (for example, an Al layer) is grown between the growth layers formed on the wiring 102, 103, 104, 105, 151, and 152. Then, using hydrogen plasma or the like, the growth layers formed on the wiring 102, 103, 104, 105, 151, and 152 are removed, and the precursor growth layer is thermally oxidized to form the insulating layer 156.

[0036] Next, as shown in Figure 5, an insulating layer 158 is formed on the wiring 102, 103, 104, 105, 151, 152 and on the insulating layer 156. The insulating layer 158 is formed of, for example, SiCO. Furthermore, the insulating layer 158 is processed into a predetermined pattern by exposure and development using photolithography. As a result, as shown in Figure 6, grooves 141, which will become wiring grooves and via holes, are formed in the insulating layers 112, 113, 114, 157, exposing the upper surfaces of the wiring 102, 103, 104, 105 of the wiring region 110. At this time, the insulating layer 158 is removed so that the width of the grooves 141 is greater than the width of the upper surfaces of the wiring 102, 103, 104, 105, so that the grooves 141 can contact the insulating layer 156 even if misalignment occurs. For example, the width of the groove 141 is preferably 1.5 nm or more, and more preferably 3.0 nm or more, than the width of the upper surface of the wiring 102, 103, 104, and 105. In addition, the insulating layer 157 is left on the wiring 151, 152 of the dummy wiring area 150 and on the insulating layers 155, 156.

[0037] Next, the insulating layer 156 exposed between insulating layers 112, 113, and 114, and the insulating layer 155 below insulating layer 156 are removed. This creates an air gap 101 between wirings 102, 103, 104, and 105, and between wiring 102 and wiring 151, as shown in Figure 7. The removal of insulating layers 156 and 155 is performed, for example, by isodirectional etching using wet etching. In etching of insulating layers 156 and 155, insulating layer 111 acts as an etching stopper on the lower side of the air gap 101. Also, the wiring 151 closest to the wiring area 110 in the dummy wiring area 150 acts as an etching stopper.

[0038] Furthermore, as shown in Figure 7, the lower parts of the insulating layers 113 and 114 formed on the air gap 101 and the lower parts of the insulating layer 112 formed on the wiring 103 are at different heights from the substrate surface. The insulating layers 113 and 114 are formed on insulating layer 156, and both insulating layer 155 and insulating layer 156 are removed. On the other hand, insulating layer 112 is formed on the wiring 103. Insulating layer 155 and wiring 103 are formed at the same height. Therefore, the lower parts of the insulating layers 113 and 114 formed on the air gap 101 are formed at a higher position than the lower parts of insulating layer 112 by the amount that insulating layer 156 is removed. Also, in insulating layer 112, a step is formed between the part on wiring 103 and the part on air gap 101. The portion of insulating layer 112 that is on air gap 101 is formed on insulating layer 155 and insulating layer 156. Therefore, as both the insulating layer 155 and the insulating layer 156 are removed, the lower part of the insulating layer 112 above the air gap 101 is formed at a higher position than the lower part of the insulating layer 112 above the wiring 103, by the amount of the insulating layer 156.

[0039] Figure 8 shows the three-dimensional structure of region 140, indicated by the dashed line in Figure 7. The cross-sectional view along line A-A in Figure 8 corresponds to region 140 shown in Figure 7. As shown in Figure 8, wirings 104 and 105 and an air gap 101 between the wirings 104 and 105 are formed on the insulating layer 111. Furthermore, an insulating layer 113 is formed on the wirings 104 and 105 and the air gap 101. Grooves 141 for forming wirings 106 and 107 are formed in the insulating layer 113. Note that Figure 8 shows the position of the etched insulating layer 156. In this process, the position of the insulating layer 156 is a cavity, similar to the groove 141. In Figure 7, the insulating layers 113 and 114 are shown separated from the wirings 104 and 105 of the lower layer 120 and floating from the substrate. However, as shown in Figure 8, the insulating layers 113 and 114 are actually formed continuously from above the wirings 104 and 105. Furthermore, for the sake of explanation, the insulating layers 112, 113, 114, and 157 are each assigned different reference numerals, but the insulating layers 112, 113, 114, and 157 may be continuously formed as a single layer. Similarly, the insulating layers 115, 116, 117, 118, and 119 are each assigned different reference numerals, but the insulating layers 115, 116, 117, 118, and 119 may be continuously formed as a single layer.

[0040] Next, as shown in Figure 9, an insulating layer 131 (second upper insulating layer) is formed on insulating layers 112, 113, 114, 157 and on wiring 102, 103, 104, 105. The insulating layer 131 is formed using ALD (Atomic Layer Deposition), etc. The insulating layer 131 is formed using, for example, SiO ２, SiC, and SiN are used. In forming the insulating layer 131, the space above the air gap 101 is blocked by controlling the coating property. By controlling the coating property, the insulating layer 131 is continuously formed from the lower parts of the insulating layers 112, 113, 114, 157 to the upper parts of the wirings 102, 103, 104, 105 and the upper side surfaces of the wirings 102, 103, 104, 105. Thereby, without forming the insulating layer 131 on the side surfaces other than the upper parts of the wirings 102, 103, 104, 105, the space above the air gap 101 is blocked while leaving the space of the air gap 101. Thus, by adjusting the film formation conditions, the materials used, etc., the coating property of the insulating layer 131 is controlled to form the insulating layer 131 that blocks the space above the air gap 101.

[0041] Next, isotropic etching is performed in the vertical direction with respect to the insulating layer 131. Thereby, as shown in FIG. 10, the upper parts of the wirings 102, 104, 105 are exposed to form the insulating layers 115, 116, 117, 118, 119.

[0042] Then, as shown in FIG. 11, the wirings 106, 107 are formed on the upper layer 130. The wiring 106 is commonly connected to the wirings 102, 104 of the lower layer 120. The wiring 107 is connected to the wiring 105 of the lower layer 120. Since the space above the air gap 101 is blocked by the insulating layers 115, 116, 117, 118, 119, the inside of the air gap 101 is not filled with the wiring material even in the process of forming the wirings 106, 107. Therefore, the wirings 106, 107 can be formed on the upper layer 130 while maintaining the air gap 101 formed in the desired shape in the lower layer 120. Through the above processes, the semiconductor device 100 shown in FIG. 1 above can be manufactured.

[0043] <3. Configuration of Semiconductor Device (Third Embodiment)> Next, the third embodiment of the above-described semiconductor device will be described. FIG. 12 shows a schematic configuration diagram of the semiconductor device of the third embodiment. The semiconductor device 200 shown in FIG. 12 is a cross-sectional view of a part of the wiring structure of the semiconductor device. Note that, for the semiconductor device of the third embodiment below, only the shape of the wiring and the shape of the insulating layer are different from the configuration of the above-described semiconductor device (first embodiment). Therefore, hereinafter, for the configurations similar to those of the above-described semiconductor device (first embodiment), the same reference numerals are given and detailed descriptions are omitted.

[0044] The semiconductor device 200 shown in FIG. 12 has different configurations of the insulating layers 112, 113, 114, the insulating layer 159, and the insulating layers 115, 116, 117, 118, 119 compared to the semiconductor device 100 shown in FIG. 1 above.

[0045] In the wiring region 110, the semiconductor device 200 includes an insulating layer 159 (third upper insulating layer) below the insulating layers 112, 113, 114. In the wiring region 110, the insulating layer 159 is formed over the entire lower surface of the insulating layers 112, 113, 114. The insulating layers 112, 113, 114 have the same height from the substrate surface of the lower surface. Also, the insulating layer 112 has the same height from the substrate surface of the lower surface both on the wiring 103 and on the air gap 101.

[0046] In the dummy wiring region 150, the semiconductor device 200 includes an insulating layer 159 below the insulating layer 157. In the dummy wiring region 150, the insulating layer 159 is formed over the entire lower surface of the insulating layer 157. Therefore, the insulating layer 159 is also formed on the wirings 151, 152.

[0047] Furthermore, by interposing insulating layer 159 between wiring 102, 103, 104, 105 and insulating layers 112, 113, 114, insulating layers 115, 116, 117, 118, 119 are continuously formed from the lower surface of insulating layer 159 to the upper sides of wiring 102, 103, 104, 105. Insulating layers 115, 116, 117, 118, 119 formed on the lower surface of insulating layer 159 are formed on the lower layer 120 side. And because insulating layers 115, 116, 117, 118, 119 formed on the lower surface of insulating layer 159 are formed on the lower layer 120 side, the height of the air gap 101 becomes smaller than that of the semiconductor device 100 shown in Figure 1 above.

[0048] <4. Method for Manufacturing a Semiconductor Device (Fourth Embodiment)> Next, another embodiment of the above-described method for manufacturing a semiconductor device will be explained. Figures 13 to 21 show the manufacturing process diagrams for the semiconductor device 200. In the following explanation of the method for manufacturing a semiconductor device, only the form of the insulating layer formed on the upper wiring layer differs. For this reason, in the following explanation, components similar to those in the above-described semiconductor device configuration (first embodiment) and semiconductor device manufacturing method (second embodiment) are denoted by the same reference numerals and detailed explanations are omitted.

[0049] First, semiconductor elements such as transistors and diodes are formed on a semiconductor substrate to form an integrated circuit, etc. Then, as shown in Figure 13, an insulating layer 111 is formed on the substrate on which the semiconductor elements are formed. Then, as shown in Figure 13, an insulating layer 155 and wirings 102, 103, 104, 105, 151, and 152 are formed on the insulating layer 111. Furthermore, as shown in Figure 13, an insulating layer 159 is formed over the entire surface of the insulating layer 155 and the wirings 102, 103, 104, 105, 151, and 152. The insulating layer 159 is formed of, for example, SiCN. The thickness of the insulating layer 159 is formed to be about the same as the thickness of the insulating layer 156 in the second embodiment described above. Then, an insulating layer 158 is formed on the insulating layer 159.

[0050] Next, the insulating layer 158 and insulating layer 159 are processed into a predetermined pattern by exposure and development using photolithography to form grooves 141. As a result, insulating layers 112, 113, 114, and 157 are formed as shown in Figure 14, and insulating layer 159 is left remaining only beneath insulating layers 112, 113, 114, and 157.

[0051] Next, as shown in Figure 15, the upper surfaces of the wirings 102, 104, and 105 that are exposed between the insulating layers 112, 113, 114, and 157 are etched. This reduces the height of the upper surfaces of the wirings 102, 104, and 105 by about 2-3 nm. As a result, a step 161 is formed between the upper surfaces of the wirings 102, 104, and 105 and the upper surface of the insulating layer 155. In the area where the step 161 is formed, the side surfaces of the insulating layer 155, which is positioned between the wirings 102, 103, 104, and 105, are exposed. The etching of the upper surfaces of the wirings 102, 104, and 105 is performed, for example, by wet etching using a chemical solution. At this time, the upper surface of wiring 103, which has insulating layers 112 and 159 formed on its upper surface, is not etched. Therefore, the upper surfaces of the wirings 102, 104, and 105 and the upper surface of wiring 103 are at different heights from the substrate surface.

[0052] Next, the insulating layer 155 exposed between insulating layers 112, 113, and 114 is removed. As a result, as shown in Figure 16, the etching of the insulating layer 155 forms an air gap 101 between wirings 102, 103, 104, and 105, and between wiring 102 and wiring 151. The removal of the insulating layer 155 is performed, for example, by isodirectional etching using wet etching. At this time, the insulating layer 111 acts as an etching stopper on the lower side of the air gap 101. Also, the wiring 151 closest to the wiring area 110 in the dummy wiring area 150 acts as an etching stopper for the air gap 101.

[0053] As shown in Figure 16, in this embodiment of semiconductor device manufacturing method, unlike the semiconductor device manufacturing method (second embodiment) described above, the lower part of the insulating layers 113 and 114 formed on the air gap 101 and the lower part of the insulating layer 112 formed on the wiring 103 are at the same height from the substrate surface. Also, in the insulating layer 112, no step is formed between the wiring 103 and the air gap 101. In the semiconductor device manufacturing method (second embodiment) described above, an insulating layer 156 (see Figure 6) is formed on the insulating layer 155 below the insulating layer 112, and no insulating layer 156 is formed on the wiring 103. Therefore, by removing the insulating layer 156 together with the insulating layer 155, a step is formed between the wiring 103 and the air gap 101 below the insulating layer 112 (see Figure 7). However, in this embodiment of semiconductor device manufacturing method, an insulating layer 159 is formed over the entire lower surface of the insulating layer 112, and the insulating layer 112 is not in direct contact with the wiring 103. Furthermore, in the process of removing the insulating layer 155 shown in Figure 16, the insulating layer 159 below the insulating layer 112 is not removed. Therefore, no step is formed on the lower surface of the insulating layer 112 between the wiring 103 and the air gap 101.

[0054] Next, as shown in Figure 17, insulating layers 115, 116, 117, 118, 119 and wiring 106, 107 of the upper layer 130 are formed. The insulating layers 115, 116, 117, 118, 119 are formed using the methods shown in Figures 9 and 10 above. The wiring 106, 107 of the upper layer 130 are formed using the method shown in Figure 11 above.

[0055] Figure 18 shows a cross-sectional view along line A-A as shown in Figure 17. As shown in Figure 18, in the cross-sectional view along line A-A of wiring including wiring 102 and wiring 106, wiring 106 is connected to wiring 102. The dashed line 162 shown in Figure 18 indicates the connection position between wiring 102 and wiring 106. The connection position between wiring 102 and wiring 106, indicated by the dashed line 162, is formed lower than the upper surface of the surrounding wiring 102 by the amount of the step 161 that occurs when the upper part of wiring 102 is etched from the opening in the insulating layer 112. Furthermore, for example, if a barrier metal different from the bulk wiring material is used for the upper layer wiring, the connection position between wiring 102 in the lower layer 120 and wiring 106 in the upper layer 130 is the position of the barrier metal. In addition, the insulating layer 112 is formed on wiring 102 and on the side surface of wiring 106. Wiring 102 is in contact with the insulating layer 112 in all areas except for the portion in contact with wiring 106 and the portion in contact with the insulating layer 115. Wiring 106 is in contact with the insulating layer 112 on the side surface of the portion in contact with the insulating layer 115.

[0056] The insulating layer 115 is the portion remaining after the process of exposing the upper parts of insulating layers 115, 116, 117, 118, and 119 (see Figure 10). Figures 19-21 show the manufacturing process of the wiring structure shown in Figure 18.

[0057] First, as shown in Figure 19, the upper surface of the wiring 102 exposed from between the insulating layers 112 is etched. This step corresponds to the step of etching the upper surfaces of the wirings 102, 104, and 105 shown in Figure 15. When etching the upper surface of the wiring 102, not only the area directly below the opening in the insulating layer 112 is etched, but also the wiring 102 directly below the insulating layer 112, close to the opening in the insulating layer 112, is etched due to the leakage of the chemical solution at the interface between the wiring 102 and the insulating layer 112. As a result, a gap 163 is formed between the wiring 102 and the insulating layer 112, continuous from the opening in the insulating layer 112.

[0058] Next, as shown in Figure 20, an insulating layer 131 is formed on the openings of the insulating layer 112 and on the upper surface of the wiring 102. This step corresponds to the step of forming an insulating layer 131 on the insulating layers 112, 113, 114, 157 and on the wirings 102, 103, 104, 105 shown in Figure 9. In this step, the gaps 163 are filled by the insulating layer 131, and the insulating layer 131 is formed.

[0059] Next, as shown in Figure 21, the insulating layer 131 on the upper surface of the wiring 102 is removed. This step corresponds to the etching step of the insulating layer 131 that exposes the upper parts of the wirings 102, 103, 104, and 105 shown in Figure 10. In this step, by removing the insulating layer 131, the insulating layer 115 remains on the side surface of the insulating layer 112. At this time, the insulating layer 115 also remains in the gap 163 between the insulating layer 112 and the wiring 102.

[0060] Next, wiring 106 is formed on the upper layer 130. This step corresponds to the step of forming wiring 106 and 107 shown in Figure 11. By forming wiring 106, a wiring structure can be realized in which the insulating layer 115 remains between the wiring 102 and 106 and the insulating layer 112, as shown in Figure 18. Through the above steps, the semiconductor device 200 shown in Figure 12 can be manufactured.

[0061] [Modifications] Next, modifications of the semiconductor device will be described. Figures 22 and 23 show the schematic configuration of modifications of the semiconductor device. Figure 22 is a semiconductor device 100A, which is a modification of the semiconductor device 100 shown in Figure 1 above. Figure 23 is a semiconductor device 200A, which is a modification of the semiconductor device 200 shown in Figure 12 above.

[0062] As shown in Figure 22, in semiconductor device 100A, insulating layers 115, 116, 117, 118, and 119 cover the entire sides of the wirings 102, 103, 104, 105, and 151. Therefore, the sides and top of the air gap 101 are covered with insulating layers 115, 116, 117, 118, and 119. As shown in Figure 23, in semiconductor device 200A, insulating layers 115, 116, 117, 118, and 119 cover the entire sides of the wirings 102, 103, 104, 105, and 151. Therefore, the sides and top of the air gap 101 are covered with insulating layers 115, 116, 117, 118, and 119. The configurations of the semiconductor devices 100A and 200A shown in Figures 22 and 23 above can be achieved by applying conditions that provide high coverage as the film deposition conditions using ALD or the like in the process of forming the insulating layer 131 shown in Figure 9 above.

[0063] It should be noted that the present invention is not limited to the configuration described in the above-described embodiments, and various modifications and changes are possible without departing from the configuration of the present invention.

[0064] 100, 100A, 200, 200A Semiconductor device, 101, 202, 203, 204, 205, 206, 207 Air gap, 102, 103, 104, 105, 106, 107, 151, 152, 210, 211, 212, 213, 214, 215, 216, 217, 221, 222, 223, 224, 225, 231, 232, 233, 234, 235 Wiring, 110 Wiring area, 111, 112, 113, 114, 115, 116, 117, 118, 119, 131, 155, 156, 157, 158, 159, 201, 209 Insulating layer, 120 Lower layer, 130 Upper layer, 140 area, 141 groove, 150 dummy wiring area, 160, 162 dashed line, 161 step, 163 void

Claims

1. A semiconductor device comprising a lower wiring layer and an upper wiring layer, the semiconductor device comprising: a first lower wiring formed in the lower wiring layer and connected to an upper wiring formed in the upper wiring layer; a second lower wiring formed in the lower wiring layer and not connected to the upper wiring; an air gap formed in contact with the first lower wiring and the second lower wiring; and a lower insulating layer in contact with the second lower wiring on the side opposite to the air gap.

2. The semiconductor device according to claim 1, wherein the first lower wiring and the air gap are formed in a region sandwiched between a plurality of second lower wirings.

3. The semiconductor device according to claim 1, wherein the first lower wiring and the air gap are formed within a region surrounded by a plurality of second lower wirings.

4. The semiconductor device according to claim 1, comprising the first lower wiring surrounded by the air gap.

5. The semiconductor device according to claim 4, comprising a third lower wiring connected to the upper wiring, having a width 4 nm or more greater than the width of the upper wiring, and not in contact with the air gap.

6. The semiconductor device according to claim 1, further comprising: a first upper insulating layer formed between the upper wirings in the upper wiring layer; and a second upper insulating layer formed between the upper wiring and the first upper insulating layer, wherein the second upper insulating layer is provided around the connection point between the first lower wiring and the upper wiring.

7. The semiconductor device according to claim 1, wherein the connection position between the first lower wiring and the upper wiring is formed at a position lower than the height of the first lower wiring other than the connection position.

8. A method for manufacturing a semiconductor device comprising a lower wiring layer and an upper wiring layer, comprising the steps of: forming a first lower wiring connected to an upper wiring formed on the upper wiring layer, a second lower wiring not connected to the upper wiring, and a lower insulating layer in the area excluding the first and second lower wirings on the lower wiring layer; forming a third upper insulating layer and a first upper insulating layer on the lower wiring layer; forming a wiring groove in the third upper insulating layer and the first upper insulating layer that exposes the upper surface of the first lower wiring; removing the lower insulating layer from the wiring groove between the first lower wirings and between the first and second lower wirings to form an air gap; forming a second upper insulating layer that closes the upper part of the air gap; and forming an upper wiring connected to the first lower wiring.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the width of the wiring groove is formed to be 1.5 nm or more greater than the width of the upper surface of the first lower layer wiring.

10. A method for manufacturing a semiconductor device according to claim 8, comprising the steps of selectively growing the third upper insulating layer only on the lower insulating layer, forming the wiring groove, and then removing the third upper insulating layer whose surface is exposed from the wiring groove and the lower insulating layer below the third upper insulating layer.

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