Semiconductor module

Abstract

This semiconductor module comprises a semiconductor device and a control unit. The semiconductor device comprises an n-type first semiconductor region, a p-type body region, an n-type second semiconductor region, a first gate electrode, and a second gate electrode. The control unit executes: a preliminary ON operation of applying a gate ON voltage to the first gate electrode and applying a gate OFF voltage to the second gate electrode; an ON operation of applying the gate ON voltage to the second gate electrode while maintaining a state in which the gate ON voltage is applied to the first gate electrode when a short circuit of a load is not detected during execution of the preliminary ON operation; and a current cutoff operation of applying the gate OFF voltage to the first gate electrode while maintaining a state in which the gate OFF voltage is applied to the second gate electrode when a short circuit of the load is detected during execution of the preliminary ON operation.

Description

Semiconductor Module

[0001] (Cross - reference to related applications) This application is a related application of Japanese Patent Application No. 2024 - 167903 filed on September 26, 2024. It claims the priority based on this Japanese patent application, and all the contents described in this Japanese patent application are incorporated herein by reference as constituting this specification.

[0002] The technology disclosed in this specification relates to a semiconductor module.

[0003] Japanese Patent Application Laid - Open No. 2005 - 191221 discloses a semiconductor device including a semiconductor substrate provided with a plurality of trenches on its upper surface, a gate insulating film and a gate electrode disposed in each trench, an emitter electrode provided on the upper surface of the semiconductor substrate, and a collector electrode provided on the lower surface of the semiconductor substrate. In this semiconductor device, the semiconductor substrate has an n - type source layer exposed on the upper surface of the semiconductor substrate and in contact with the gate insulating film, a p - type base layer in contact with the gate insulating film below the n - type source layer, an n - type base layer in contact with the gate insulating film below the p - type base layer and separated from the n - type source layer by the p - type base layer, and a p - type emitter layer disposed below the n - type base layer and in contact with the emitter electrode.

[0004] In Japanese Patent Application Laid - Open No. 2005 - 191221, when turning on the semiconductor device, a gate - on voltage is first applied to the first gate electrode (i.e., some of the gate electrodes) among the plurality of gate electrodes, and then a gate - on voltage is applied to the second gate electrode (i.e., the remaining gate electrodes). It is described that this can reduce the negative capacitance and stabilize the turn - on operation.

[0005] In the technical field of semiconductor devices, a high tolerance to load short - circuit is required. However, it is difficult to improve the tolerance while maintaining a large output of the semiconductor device. In this specification, a technology is proposed that can improve the output of the entire semiconductor device while controlling the tolerance required for the semiconductor device in a semiconductor device where gate - on voltages are applied to the first gate electrode and the second gate electrode at different timings.

[0006] The semiconductor module disclosed herein comprises a semiconductor device and a control unit. The semiconductor device comprises an n-type first semiconductor region, a p-type body region in contact with the first semiconductor region, an n-type second semiconductor region in contact with the body region and separated from the first semiconductor region by the body region, a first gate electrode facing the body region via a first gate insulating film, and a second gate electrode facing the body region via a second gate insulating film. The control unit performs a pre-on operation in which a gate-on voltage is applied to the first gate electrode and a gate-off voltage is applied to the second gate electrode, an on operation in which, if no short circuit of the load is detected during the execution of the pre-on operation, a gate-on voltage is applied to the second gate electrode while maintaining the state in which a gate-on voltage is applied to the first gate electrode, and a current interruption operation in which, if a short circuit of the load is detected during the execution of the pre-on operation, a gate-off voltage is applied to the first gate electrode while maintaining the state in which a gate-off voltage is applied to the second gate electrode.

[0007] In this semiconductor module, the control unit performs a preliminary ON operation by applying a gate-on voltage to the first gate electrode and a gate-off voltage to the second gate electrode, and then determines whether the load is short-circuited. If the control unit does not detect a short circuit in the load, it performs an ON operation by applying a gate-on voltage to both the first and second gate electrodes. On the other hand, if the control unit detects a short circuit in the load, it performs a current-cutting operation by applying a gate-off voltage to both the first and second gate electrodes. In the preliminary ON operation, since the gate-off voltage is applied to the second gate electrode, the current flowing through the semiconductor device is smaller than in the ON operation. Therefore, even if the load is short-circuited, the current flowing through the semiconductor device is relatively small, and the subsequent current-cutting operation can suppress damage to the semiconductor device. On the other hand, if the load is not short-circuited, it performs an ON operation by applying a gate-on voltage to the second gate electrode. This allows the output of the semiconductor device to be increased.

[0008] Cross-sectional view of a semiconductor device. Graph showing the measured value of the allowable current density of the semiconductor device as a function of the integral concentration in the collector region under a short-circuit load. Graph showing the measured value of the allowable energy per unit volume of the semiconductor device as a function of the temperature of the semiconductor substrate under a short-circuit load.

[0009] In one example semiconductor module disclosed herein, the current density flowing through the semiconductor device during the pre-on operation and while the load is short-circuited may be lower than the allowable current density of the semiconductor device.

[0010] In this specification, the allowable current density refers to the upper limit of the current density that can flow through the semiconductor device without damaging it, from the start of the pre-on operation to the execution of the current cutoff operation, when the load is short-circuited. With the above configuration, even when a gate-on voltage is applied to the first gate electrode when the load is short-circuited, the density of the saturation current flowing through the semiconductor device is lower than the allowable current density, thus further suppressing damage to the semiconductor device. If a short circuit in the load is not detected during the execution of the pre-on operation, an on operation is performed in which a gate-on voltage is applied to both the first and second gate electrodes, so that a high output can be obtained for the semiconductor device as a whole.

[0011] In one example semiconductor module disclosed herein, the energy generated by the semiconductor device while the load is short-circuited between the start of the pre-on operation and the start of the current cutoff operation may be lower than the allowable energy of the semiconductor device.

[0012] In this specification, "allowable energy" refers to the upper limit of energy that can be generated in a semiconductor device without causing damage to the device. With the above configuration, even when a gate-on voltage is applied to the first gate electrode while the load is short-circuited, the energy generated in the semiconductor device before the current interruption operation begins is lower than the allowable energy, thus further suppressing damage to the semiconductor device. If a short circuit in the load is not detected during the pre-on operation, an on operation is performed in which a gate-on voltage is applied to both the first and second gate electrodes, so that a high output can be obtained for the semiconductor device as a whole.

[0013] In one example semiconductor module disclosed herein, the semiconductor device may have a p-type collector region in contact with the second semiconductor region and separated from the body region by the second semiconductor region, and an n-type cathode region adjacent to the collector region and in contact with the second semiconductor region and separated from the body region by the second semiconductor region.

[0014] With this configuration, in a so-called RC-IGBT (Reverse-conducting Insulated-Gate Bipolar Transistor), it is possible to control the required tolerance of the semiconductor device while improving the overall output of the semiconductor device.

[0015] (Example) An example of a semiconductor module 1 will be described with reference to the drawings. As shown in Figure 1, the semiconductor module 1 comprises a semiconductor device 10 and a control unit 80. The semiconductor device 10 is composed of a semiconductor substrate 12 and electrodes, insulating films, etc., provided on the upper surface 12a and lower surface 12b of the semiconductor substrate 12. The semiconductor substrate 12 has an IGBT region 16 on which an IGBT (Insulated-Gate Bipolar Transistor) is formed and a diode region 18 on which a diode is formed. In other words, the semiconductor device 10 is a so-called RC-IGBT (Reverse-conducting IGBT). The semiconductor substrate 12 is composed of a semiconductor material such as Si (silicon) or SiC (silicon carbide).

[0016] Multiple trenches 40 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 40 extends parallel to each other along a direction perpendicular to the plane of the paper in Figure 1. Multiple trenches 40 are provided in both the IGBT region 16 and the diode region 18.

[0017] The inner surface of each trench 40 within the IGBT region 16 is covered with a gate insulating film 42. A gate electrode 44 is located inside each trench 40 within the IGBT region 16. The gate electrode 44 is insulated from the semiconductor substrate 12 by the gate insulating film 42. The upper surface of the gate electrode 44 is covered with an interlayer insulating film 48.

[0018] The gate electrode 44 has a first gate electrode 44a and a second gate electrode 44b. In this embodiment, the first gate electrode 44a and the second gate electrode 44b are alternately arranged in the trench 40 along the arrangement direction of the trench 40. The potentials of the first gate electrode 44a and the second gate electrode 44b are independently controlled by the control unit 80. Note that the potentials of some of the first gate electrode 44a and the second gate electrode 44b do not need to be controlled by the control unit 80, and may be fixed at the same potential as the upper electrode 70, for example.

[0019] The inner surface of each trench 40 within the diode region 18 is covered with an insulating film 52. A control electrode 54 is positioned inside each trench 40 within the diode region 18. The control electrode 54 is insulated from the semiconductor substrate 12 by the insulating film 52. The potential of the control electrode 54 is controlled by the control unit 80. The potential of the control electrode 54 may be independent of the potential of the gate electrode 44, or it may be at the same potential as either gate electrode 44a or 44b. The upper surface of the control electrode 54 is covered with an interlayer insulating film 56. Note that the potential of the control electrode 54 does not necessarily have to be controlled by the control unit 80; for example, it may be fixed at the same potential as the upper electrode 70.

[0020] An upper electrode 70 is provided on the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 covers the upper surface 12a of the semiconductor substrate 12 in areas where the interlayer insulating film 48 and interlayer insulating film 56 are not provided. The upper electrode 70 is insulated from the gate electrode 44 by the interlayer insulating film 48 and from the control electrode 54 by the interlayer insulating film 56. A lower electrode 72 is provided on the lower surface 12b of the semiconductor substrate 12.

[0021] Inside the IGBT region 16, an emitter region 20, a body region 22, a drift region 24, and a collector region 28 are formed.

[0022] The emitter region 20 is an n-type region and is exposed on the upper surface 12a of the semiconductor substrate 12. The emitter region 20 is in contact with the gate insulating film 42. A portion of the emitter region 20 is in contact with the upper electrode 70.

[0023] The body region 22 has a body contact region 22a and a main body region 22b. The body contact region 22a is a p-type region containing a high concentration of p-type impurities. The body contact region 22a is exposed on the upper surface 12a of the semiconductor substrate 12. The body contact region 22a is adjacent to the emitter region 20. The body contact region 22a is in contact with the upper electrode 70. The main body region 22b is a p-type region containing a lower concentration of p-type impurities than the body contact region 22a. The main body region 22b is located below the emitter region 20 and the body contact region 22a. The main body region 22b is in contact with the gate insulating film 42 below the emitter region 20.

[0024] The drift region 24 has a low-concentration drift region 25 and a buffer region 26. The low-concentration drift region 25 is an n-type region containing n-type impurities at a lower concentration than the emitter region 20 and the buffer region 26. The low-concentration drift region 25 is located below the main body region 22b. The low-concentration drift region 25 is separated from the emitter region 20 by the main body region 22b. The low-concentration drift region 25 is in contact with the gate insulating film 42 near the lower end of the trench 40 below the main body region 22b. The buffer region 26 is an n-type region containing n-type impurities at a higher concentration than the low-concentration drift region 25. The buffer region 26 is located below the low-concentration drift region 25.

[0025] The collector region 28 is a p-type region containing a high concentration of p-type impurities. The collector region 28 is located below the buffer region 26. The collector region 28 is separated from the body region 22 by the drift region 24. The collector region 28 is exposed on the lower surface 12b of the semiconductor substrate 12. The collector region 28 is in contact with the lower electrode 72.

[0026] Within the IGBT region 16, an IGBT is formed by an emitter region 20, a body region 22, a drift region 24, a collector region 28, and a gate electrode 44, etc., connected between the upper electrode 70 and the lower electrode 72. When the semiconductor device 10 operates as an IGBT, the upper electrode 70 functions as the emitter electrode and the lower electrode 72 functions as the collector electrode.

[0027] Inside the diode region 18, an anode region 30, a low-concentration drift region 35, a buffer region 36, and a cathode region 37 are formed.

[0028] The anode region 30 has an anode contact region 30a and a main anode region 30b. The anode contact region 30a is a p-type region containing a high concentration of p-type impurities. The anode contact region 30a is exposed on the upper surface 12a of the semiconductor substrate 12. The anode contact region 30a is in contact with the upper electrode 70. The main anode region 30b is a p-type region containing a lower concentration of p-type impurities than the anode contact region 30a. The main anode region 30b is provided around the anode contact region 30a. At the location where the anode contact region 30a is located, the anode contact region 30a and the main anode region 30b are arranged alternately along the direction perpendicular to the plane of Figure 1. That is, the anode contact region 30a is arranged intermittently along the direction perpendicular to the plane of Figure 1. The main anode region 30b is in contact with the insulating film 52.

[0029] The low-concentration drift region 35 is an n-type region and is connected to the low-concentration drift region 25 within the IGBT region 16. The low-concentration drift region 35 is located below the main anode region 30b. The low-concentration drift region 35 is in contact with the insulating film 52 near the lower end of the trench 40 below the main anode region 30b. The buffer region 36 is an n-type region containing a higher concentration of n-type impurities than the low-concentration drift region 35. The buffer region 36 is connected to the buffer region 26 within the IGBT region 16. The buffer region 36 is located below the low-concentration drift region 35. The cathode region 37 is an n-type region containing a higher concentration of n-type impurities than the buffer region 36. The cathode region 37 is located below the buffer region 36. The cathode region 37 is adjacent to the collector region 28. The cathode region 37 is exposed on the lower surface 12b of the semiconductor substrate 12. The cathode region 37 is in contact with the lower electrode 72.

[0030] Within the diode region 18, a diode is formed by connecting the upper electrode 70 and the lower electrode 72 via an anode region 30 and a cathode region 37, etc. When the semiconductor device 10 operates as a diode, the upper electrode 70 functions as the anode electrode and the lower electrode 72 functions as the cathode electrode. In other words, the diode is connected in antiparallel to the IGBT.

[0031] Next, the operation of the semiconductor device 10 will be described. When the semiconductor device 10 is in use, the semiconductor device 10, a load (for example, a motor), and a power supply are connected in series. The power supply voltage is applied to the series circuit of the semiconductor device 10 and the load.

[0032] First, the operation of the IGBTs within the IGBT region 16 will be explained. When turning on the IGBTs, the control unit 80 performs a pre-on operation. In the pre-on operation, the control unit 80 applies a gate-on voltage (potential above the gate threshold) to the first gate electrode 44a and a gate-off voltage (potential below the gate threshold) to the second gate electrode 44b. As a result, a channel is formed in the main body region 22b adjacent to the gate insulating film 42 surrounding the first gate electrode 44a. Since a gate-off voltage is applied to the second gate electrode 44b, no channel is formed in the main body region 22b adjacent to the gate insulating film 42 surrounding the second gate electrode 44b. When a potential is applied such that the lower electrode 72 is at a higher potential than the upper electrode 70, if a channel is formed, electrons flow from the upper electrode 70 to the lower electrode 72 via the emitter region 20, the channel in the main body region 22b, the drift region 24, and the collector region 28. Furthermore, holes flow from the lower electrode 72 through the collector region 28, the drift region 24, the main body region 22b, and the body contact region 22a to the upper electrode 70. In other words, a current path is formed in a part of the IGBT region 16, and the IGBT is turned on.

[0033] Next, the control unit 80 determines whether a short circuit in the load has been detected during the pre-ON operation. For example, the control unit 80 can determine that a short circuit has occurred in the load if the voltage applied between the lower electrode 72 and the upper electrode 70 is higher than the reference voltage. Alternatively, the control unit 80 may determine that a short circuit has occurred in the load if the current flowing through the IGBT is higher than the reference current. If no short circuit has been detected in the load, the control unit 80 performs the ON operation.

[0034] In ON operation, the control unit 80 applies a gate-on voltage to the second gate electrode 44b while maintaining the state in which a gate-on voltage is applied to the first gate electrode 44a. That is, in ON operation, the control unit 80 raises the potential of the second gate electrode 44b from the gate-off potential to the gate-on potential without changing the potential applied to the first gate electrode 44a. As a result, a channel is formed in the main body region 22b adjacent to the gate insulating film 42 surrounding the second gate electrode 44b. In other words, current flows throughout almost the entire IGBT region 16.

[0035] Subsequently, the control unit 80 performs an off operation. In the off operation, the control unit 80 lowers the potentials of the first gate electrode 44a and the second gate electrode 44b from the gate-on potential to the gate-off potential. As a result, the channel disappears and the IGBT is turned off.

[0036] On the other hand, if a short circuit in the load is detected while the pre-on operation is being performed, the control unit 80 performs a current cutoff operation. In the current cutoff operation, the gate-off voltage is applied to the first gate electrode 44a while maintaining the state in which the gate-off voltage is applied to the second gate electrode 44b. That is, in the current cutoff operation, the control unit 80 lowers the potential of the first gate electrode 44a from the gate-on voltage to the gate-off voltage without raising the potential applied to the second gate electrode 44b to the gate-on voltage. As a result, the channel disappears and the IGBT is forcibly turned off.

[0037] When the load is short-circuited, applying a gate-on voltage to the gate electrode 44 causes an overcurrent (saturation current) to flow through the semiconductor device 10. If the density of this current exceeds the allowable current density of the semiconductor device, the semiconductor device 10 may be destroyed. In this embodiment, a pre-on operation is performed first when operating the IGBT. In the pre-on operation, the gate-on voltage is applied only to the first gate electrode 44a, so the current path within the IGBT region 16 is narrower compared to when the gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b. Therefore, the saturation current flowing through the semiconductor device 10 during the pre-on operation when the load is short-circuited is small. In particular, in this embodiment, the density of the current flowing through the semiconductor device 10 during the pre-on operation when the load is short-circuited is set to be lower than the allowable current density of the semiconductor device 10. Therefore, in this semiconductor device 10, when the load is short-circuited, the destruction of the semiconductor device 10 due to overcurrent can be suppressed, and the semiconductor device 10 can be protected from destruction by performing a subsequent current interruption operation. Furthermore, if the load is not short-circuited during the pre-ON operation, an ON operation is performed in which a gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b, allowing a large output current to flow through the semiconductor device 10.

[0038] Furthermore, when the load is short-circuited, the electric field applied to the semiconductor substrate 12 is distributed such that a peak occurs within the buffer region 26. This is because there are fewer holes injected from the collector region 28 into the lower end portion of the buffer region 26 (the portion in contact with the lower electrode 72), resulting in an excess of electrons. When a peak in the electric field occurs within the buffer region 26, avalanche breakdown can occur, potentially destroying the semiconductor device 10. In other words, the allowable current density has a strong correlation with the p-type impurity concentration in the collector region 28. Figure 2 shows the results of plotting the measured allowable current density against the integrated concentration (collector integrated concentration) obtained by integrating the p-type impurity concentration in the thickness direction of the semiconductor substrate. Line A1 represents the approximate straight line for each plot, where y = 3.3 × 10 －１２It can be expressed by x. In this embodiment, the relationship between the current density flowing through the semiconductor device 10 when the pre-on operation is performed and the collector integral concentration is y < 3.3 × 10 －１２ The current density when a gate-on voltage is applied only to the first gate electrode 44a and the p-type impurity concentration in the collector region 28 are set to satisfy the relationship x (i.e., within the hatched region in Figure 2). Note that the measurements in Figure 2 were performed under typical environmental conditions at the start of operation of the semiconductor device. The specific measurement conditions were an ambient temperature of 40°C and a power supply voltage of 740V.

[0039] Furthermore, when the load is short-circuited, an overvoltage equivalent to the power supply voltage is applied to the semiconductor device 10, generating energy equal to the saturation current multiplied by the power supply voltage per unit time in the semiconductor device 10, causing the semiconductor substrate 12 to heat up according to its thermal capacity. When the semiconductor device 10 reaches a predetermined temperature, it may be destroyed. In other words, if the energy generated in the semiconductor device 10 exceeds the allowable energy of the semiconductor device 10, it may be destroyed. In the pre-on operation, the gate-on voltage is applied only to the first gate electrode 44a, so the energy generated in the semiconductor device 10 before the current cutoff operation is performed is lower compared to when the gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b. In particular, in this embodiment, the energy generated from the start of the pre-on operation to the start of the current cutoff operation when the load is short-circuited is set to be lower than the allowable energy. Therefore, in this semiconductor device 10, when the load is short-circuited, the destruction of the semiconductor device 10 due to the energy generated in the semiconductor device 10 can be suppressed, and the semiconductor device 10 can be protected from destruction by performing the subsequent current cutoff operation. Furthermore, if the load is not short-circuited during the pre-ON operation, an ON operation is performed in which a gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b, allowing a large output current to flow through the semiconductor device 10.

[0040] Since the specific heat of the semiconductor substrate 12 is an eigenvalue, the temperature of the semiconductor substrate 12, which rises due to the energy generated in the semiconductor device 10, has a strong correlation with the volume of the semiconductor substrate 12. Figure 3 shows the results of plotting the measured allowable energy per unit volume of the semiconductor substrate 12 against the temperature of the semiconductor substrate at the timing when the gate-on voltage is applied to the gate electrode. Line A2 represents the approximate straight line for each plot and can be expressed as y = -0.0016x + 0.5948. In this embodiment, the initial temperature and volume of the semiconductor substrate 12 are set such that the relationship between the temperature of the semiconductor substrate 12 at the timing when the pre-on operation starts and the energy generated per unit volume of the semiconductor substrate 12 satisfies the relationship y < -0.0016x + 0.5948 (i.e., within the hatched region of Figure 3). Note that the measurements in Figure 3 were performed under typical environmental conditions at the start of operation of the semiconductor device. The specific measurement conditions are that the power supply voltage is 740V.

[0041] As described above, in the semiconductor device 10 of this embodiment, the control unit 80 performs a preliminary ON operation by applying a gate ON voltage to the first gate electrode 44a and a gate OFF voltage to the second gate electrode 44b, and then determines whether or not the load is short-circuited. If the control unit 80 does not detect a short circuit in the load, it performs an ON operation by applying a gate ON voltage to both the first gate electrode 44a and the second gate electrode 44b. On the other hand, if the control unit 80 detects a short circuit in the load, it performs a current interruption operation by applying a gate OFF voltage to both the first gate electrode 44a and the second gate electrode 44b. In the preliminary ON operation, since a gate OFF voltage is applied to the second gate electrode 44b, the current flowing through the semiconductor device 10 is smaller than in the ON operation. Therefore, even if the load is short-circuited, the current flowing through the semiconductor device 10 is relatively small, and the subsequent current interruption operation can suppress damage to the semiconductor device 10. On the other hand, if the load is not short-circuited, the control unit 80 performs an ON operation by applying a gate ON voltage to the second gate electrode 44b. This makes it possible to increase the output of the semiconductor device 10.

[0042] (Corresponding relationship) The emitter region 20 and the drift region 24 are each an example of a "first semiconductor region" and a "second semiconductor region". The gate insulating film 42 is an example of a "first gate insulating film" and a "second gate insulating film".

[0043] In the above-described embodiment, in a state where the load is short-circuited, if a gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b, the density of the current flowing through the semiconductor device 10 may exceed the allowable current density. As described above, the gate-on voltage is applied to the second gate electrode 44b only when it is detected that the load is not short-circuited in the pre-on operation. That is, if it is detected that the load is short-circuited, the gate-on voltage is not applied to the second gate electrode 44b. Therefore, even if the density of the current flowing through the semiconductor device 10 is set to exceed the allowable current density when a gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b in a state where the load is short-circuited, it does not affect the operation of the semiconductor device 10 at all. By setting it in this way, a larger output can be obtained as a whole for the semiconductor device 10. Similarly, in a short-circuited state, if a gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b, the energy generated in the semiconductor device 10 before starting the current blocking operation may exceed the allowable energy.

[0044] Also, in the above-described embodiment, the density of the current flowing through the semiconductor device 10 in the pre-on operation during load short-circuit may be higher than the allowable current density of the semiconductor device 10. Even with such a configuration, the density of the current flowing through the semiconductor device 10 is lower compared to the case where a gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b (i.e., the on operation). Therefore, in the pre-on operation, the short-circuit tolerance of the semiconductor device 10 is improved compared to the on operation, and the tolerance required for the semiconductor device 10 can be reduced.

[0045] Also, in the above-described embodiments, the energy generated from the start of the pre-on operation to the start of the current cutoff operation during a load short circuit may be higher than the allowable energy. Even with such a configuration, compared to the case where the gate-on voltage is applied to both the first gate electrode 44a and the second gate electrode 44b (i.e., the on operation), the energy generated in the semiconductor device 10 until the current is cutoff is lower. Therefore, in the pre-on operation, the short-circuit withstand capacity of the semiconductor device 10 is improved compared to the on operation, so the required withstand capacity of the semiconductor device 10 can be reduced.

[0046] Also, in the above-described embodiments, the RC-IGBT has been described as an example of the semiconductor device 10. However, the semiconductor device 10 may be, for example, an IGBT or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Further, the semiconductor device 10 does not have to be a trench gate type, and may be, for example, a planar type.

[0047] Also, in the above-described embodiments, the first gate electrode 44a and the second gate electrode 44b are alternately arranged along the arrangement direction of the trenches 40. However, for example, a plurality of first gate electrodes 44a may be adjacent to each other in the arrangement direction, and a plurality of second gate electrodes 44b may be arranged adjacent to each other in the arrangement direction. Further, the ratio of the number of the first gate electrodes 44a to the number of the second gate electrodes 44b in the entire semiconductor device 10 can be appropriately set according to the desired performance.

[0048] The configurations of the semiconductor modules disclosed herein are listed below. (Configuration 1) A semiconductor module comprising: a semiconductor device; a control unit; wherein the semiconductor device comprises: an n-type first semiconductor region; a p-type body region in contact with the first semiconductor region; an n-type second semiconductor region in contact with the body region and separated from the first semiconductor region by the body region; a first gate electrode facing the body region via a first gate insulating film; and a second gate electrode facing the body region via a second gate insulating film; wherein the control unit performs: a pre-on operation which applies a gate-on voltage to the first gate electrode and a gate-off voltage to the second gate electrode; an on operation which, if no short circuit of the load is detected during the execution of the pre-on operation, applies a gate-on voltage to the second gate electrode while maintaining the state in which the gate-on voltage is applied to the first gate electrode; and a current interruption operation which, if a short circuit of the load is detected during the execution of the pre-on operation, applies a gate-off voltage to the first gate electrode while maintaining the state in which the gate-off voltage is applied to the second gate electrode. (Configuration 2) The semiconductor module according to Configuration 1, wherein the current density flowing through the semiconductor device while the pre-on operation is being performed and the load is short-circuited is lower than the allowable current density of the semiconductor device. (Configuration 3) The semiconductor module according to Configuration 1 or 2, wherein the energy generated in the semiconductor device while the load is short-circuited from the start of the pre-on operation to the start of the current cutoff operation is lower than the allowable energy of the semiconductor device. (Configuration 4) The semiconductor module according to any one of Configurations 1 to 3, wherein the semiconductor device has a p-type collector region in contact with the second semiconductor region and separated from the body region by the second semiconductor region, and an n-type cathode region in contact with the second semiconductor region and separated from the body region by the second semiconductor region.

[0049] Although specific examples of the present invention have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness.

Claims

1. A semiconductor module (1) comprising a semiconductor device (10) and a control unit (80), wherein the semiconductor device comprises an n-type first semiconductor region (20), a p-type body region (22) in contact with the first semiconductor region, an n-type second semiconductor region (24) in contact with the body region and separated from the first semiconductor region by the body region, a first gate electrode (44a) facing the body region via a first gate insulating film (42), and a second gate electrode (44b) facing the body region via a second gate insulating film (42), wherein the control unit performs a preliminary on operation which applies a gate on voltage to the first gate electrode and a gate off voltage to the second gate electrode, and an on operation which, if a short circuit in the load is not detected during the execution of the preliminary on operation, maintains the state in which a gate on voltage is applied to the first gate electrode while applying a gate on voltage to the second gate electrode, A semiconductor module that, when a short circuit in the load is detected during the execution of the aforementioned pre-on operation, performs a current interruption operation in which a gate-off voltage is applied to the first gate electrode while maintaining the state in which a gate-off voltage is applied to the second gate electrode.

2. The semiconductor module according to claim 1, wherein the current density flowing through the semiconductor device during the execution of the pre-on operation and while the load is short-circuited is lower than the allowable current density of the semiconductor device.

3. The semiconductor module according to claim 1, wherein the energy generated by the semiconductor device when the load is short-circuited between the start of the pre-on operation and the start of the current interruption operation is lower than the allowable energy of the semiconductor device.

4. The semiconductor module according to any one of claims 1 to 3, wherein the semiconductor device has a p-type collector region (28) in contact with the second semiconductor region and separated from the body region by the second semiconductor region, and an n-type cathode region (37) in contact with the second semiconductor region and separated from the body region by the second semiconductor region.

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