Substrate for mounting semiconductor element

Abstract

This substrate for mounting a semiconductor element comprises: a base material; an electrode to be connected to a semiconductor element; and an insulating layer disposed between the base material and the electrode. The insulating layer includes an insulating film having a Knoop hardness of at least 14.7 GPa HK 0.4903 N.

Description

Substrate for mounting semiconductor device

[0001] The present invention relates to a substrate for mounting a semiconductor device.

[0002] Conventionally, a substrate for mounting a semiconductor device having an electrode connected to a semiconductor element has been known (for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2010-73742

[0004] However, even with the prior art such as Patent Document 1, there is still room for improvement in the technology for improving the heat resistance of the insulating layer in the substrate for mounting a semiconductor device.

[0005] An object of the present invention is to provide a technology for improving the heat resistance of an insulating layer in a substrate for mounting a semiconductor device.

[0006] The present invention has been made to solve at least a part of the above-described problems and can be realized in the following forms.

[0007] (1) According to one aspect of the present invention, a substrate for mounting a semiconductor device is provided. This substrate for mounting a semiconductor device includes a base material, an electrode connected to a semiconductor element, and an insulating layer disposed between the base material and the electrode, and the insulating layer has an insulating film having a Knoop hardness of 14.7 GPa HK0.4903 N or more.

[0008] According to this configuration, the insulating layer has an insulating film having a Knoop hardness of 14.7 GPa HK0.4903 N or more. Thereby, for example, since the resistance to thermal stress generated in the insulating layer due to temperature changes in the manufacture of the substrate for mounting a semiconductor device can be improved, it is possible to suppress the occurrence of defects such as cracks in the insulating layer. Therefore, the heat resistance of the insulating layer can be improved.

[0009] (2) In the semiconductor element mounting substrate of the above form, the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film, wherein the first insulating film and the second insulating film may have the same composition. According to this configuration, the insulating layer comprises a first insulating film and a second insulating film having a Knoop hardness lower than that of the first insulating film. Since the first insulating film and the second insulating film have the same composition, when forming the insulating layer in the manufacturing of the semiconductor element mounting substrate, the material used when forming the first insulating film and the material used when forming the second insulating film are basically the same. As a result, the time required to switch materials when forming the insulating layer is eliminated, and the time required to form the insulating layer can be shortened. Therefore, the production efficiency of the semiconductor element mounting substrate can be improved.

[0010] (3) In the semiconductor element mounting substrate of the above form, the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film, wherein the first insulating film may be positioned on the substrate side of the insulating layer than the second insulating film. With this configuration, the insulating layer comprises a first insulating film and a second insulating film having a Knoop hardness lower than that of the first insulating film. In this way, by making a part of the insulating layer a second insulating film with a relatively low Knoop hardness, it is possible to suppress warping of the semiconductor element mounting substrate while maintaining the overall thickness of the insulating layer.

[0011] (4) In the semiconductor element mounting substrate of the above embodiment, the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or more, and a second insulating film having a Knoop hardness smaller than that of the first insulating film, wherein the second insulating film may be positioned on the substrate side of the insulating layer than the first insulating film. According to this configuration, the insulating layer comprises a first insulating film and a second insulating film having a Knoop hardness smaller than that of the first insulating film. In the insulating layer, the second insulating film is positioned on the substrate side of the first insulating film. By positioning the second insulating film, which has a relatively small Knoop hardness, on the substrate side in this way, stress can be relieved so that thermal stress generated in the substrate is not transmitted to the first insulating film, which has a relatively large Knoop hardness. This makes it possible to suppress the occurrence of defects such as cracks in the insulating layer, and thus improve the heat resistance of the insulating layer.

[0012] (5) In the semiconductor element mounting substrate of the above configuration, the insulating layer may be formed of aluminum nitride. With this configuration, the aluminum nitride forming the insulating layer has relatively high thermal conductivity and relatively high electrical insulation properties. This makes it possible to efficiently dissipate heat generated in the semiconductor element connected to the electrode through the substrate while maintaining insulation between the electrode and the substrate.

[0013] (6) In the semiconductor element mounting substrate of the above configuration, the substrate may be made of a material mainly composed of copper or aluminum. With this configuration, the substrate is made of copper or aluminum, which have relatively high thermal conductivity. This makes it possible to efficiently dissipate the heat generated in the semiconductor element connected to the electrode through the substrate.

[0014] (7) The semiconductor element mounting substrate of the above configuration may further include an adhesion layer disposed between the substrate and the insulating layer. With this configuration, an adhesion layer is formed between the substrate and the insulating layer to improve the adhesion between the substrate and the insulating layer. This improves resistance to stress caused by differences in thermal expansion between the substrate and the insulating layer due to temperature changes, for example, and thus suppresses the occurrence of cracks in the insulating layer. Therefore, the heat resistance of the insulating layer can be further improved.

[0015] Furthermore, the present invention can be realized in various forms, for example, in the form of a substrate having an insulating layer, a product including a substrate for mounting semiconductor elements, a semiconductor package including a substrate for mounting semiconductor elements, a method for manufacturing the substrate for mounting semiconductor elements and the semiconductor package.

[0016] This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the first embodiment. This is the first figure illustrating the results of an evaluation test regarding bias voltage. This is the second figure illustrating the results of an evaluation test regarding bias voltage. This is the third figure illustrating the results of an evaluation test regarding bias voltage. This is the fourth figure illustrating the results of an evaluation test regarding bias voltage. This is the fifth figure illustrating the results of an evaluation test regarding bias voltage. This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the second embodiment. This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the third embodiment. This is a schematic cross-sectional view of a semiconductor element mounting substrate according to the fourth embodiment.

[0017] <First Embodiment> Figure 1 is a schematic cross-sectional view of a semiconductor element mounting substrate 1 according to the first embodiment. The semiconductor element mounting substrate 1 of this embodiment supports optical semiconductors such as light-emitting diodes (LEDs) and semiconductor lasers (LDs) as semiconductor elements 5 via electrodes 40, and functions as a heat dissipation substrate that releases heat generated during light emission to the outside. The semiconductor element mounting substrate 1 comprises a base material 10, an adhesion layer 20, an insulating layer 30, and electrodes 40. Note that the thickness relationships of the base material 10, the adhesion layer 20, the insulating layer 30, and the electrodes 40 in Figure 1 are shown differently from the actual thickness relationships for the sake of explanation.

[0018] The base material 10 is a flat plate-shaped member that serves as the base for the semiconductor element mounting substrate 1. In this embodiment, the thickness of the base material 10 is, for example, 1 mm. The base material 10 is made of metal. In this embodiment, the base material 10 is made of copper (Cu). The base material 10 may be formed from a material mainly composed of copper, aluminum (Al), or a material mainly composed of aluminum. Here, "main component" refers to a component that accounts for more than 50% by mass in the material in question. The base material 10 may be made of an alloy of copper and aluminum. By forming the base material 10 from these metals, the heat generated in the semiconductor element 5 can be efficiently released to the outside through the base material 10.

[0019] The adhesion layer 20 is positioned between the substrate 10 and the insulating layer 30. In this embodiment, the adhesion layer 20 is made of titanium (Ti). The thickness of the adhesion layer 20 is, for example, 0.5 μm. The adhesion layer 20 adheres the substrate 10 and the insulating layer 30 to each other and suppresses the occurrence of cracks in the insulating layer 30 due to the difference in thermal expansion coefficients between the substrate 10 and the insulating layer 30. The material forming the adhesion layer 20 is not limited to titanium, and may be chromium (Cr), molybdenum (Mo), copper, etc., which have good adhesion to both the insulating layer and the substrate. It is desirable that the material forming the adhesion layer 20 has a thermal expansion coefficient value between the thermal expansion coefficient of the material forming the substrate 10 and the thermal expansion coefficient of the material forming the insulating layer 30.

[0020] The insulating layer 30 is positioned between the substrate 10 and the electrode 40, more specifically, between the adhesion layer 20 and the electrode 40. The insulating layer 30 has a single-layer structure formed of aluminum nitride (AlN). The thickness of the insulating layer 30 is 3 to 4 μm, and in this embodiment, the thickness of the insulating layer 30 is 3.4 μm. The insulating layer 30 insulates the metal substrate 10 from the electrode 40. Note that the material forming the insulating layer 30 is not limited to aluminum nitride, but may also be silicon nitride (SiN).

[0021] The insulating layer 30 of this embodiment has a Knoop hardness of 14.7 GPa HK 0.4903 N (= 1500 HK 0.05) or higher. In other words, the insulating layer 30 has an insulating film with a Knoop hardness of 14.7 GPa HK 0.4903 N or higher. The insulating layer 30 of this embodiment has a Knoop hardness of 23.34 GPa HK 0.4903 N (= 2380 HK 0.05), and in particular, to improve heat resistance, it has a more preferable Knoop hardness of 19.57 GPa HK 0.4903 N (= 2000 HK 0.05) or higher. The Knoop hardness of the insulating layer 30 is measured by the Knoop hardness test method described in JIS Z 2251:2009. Furthermore, the Knoop hardness of the insulating layer 30 may be determined by converting the measurement results of the Vickers hardness test described in JIS B7725:2010, or the Vickers hardness measurement results measured using a nanoindenter, into Knoop hardness.

[0022] The electrode 40 is positioned on the surface of the insulating layer 30 opposite to the substrate 10. The electrode 40 is connected to the semiconductor element 5. The electrode 40 is made of gold (Au). The thickness of the electrode 40 is, for example, 3.0 μm. The electrode 40 has a predetermined pattern shape so as to connect to a predetermined location on the semiconductor element 5 on which it is mounted. Note that the material forming the electrode 40 is not limited to gold, but may be made of copper.

[0023] Next, the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment will be described. In the manufacturing of the semiconductor element mounting substrate 1, first, the material that will become the base material 10 is pre-treated. Specifically, a plate-shaped rolled copper is prepared. After the surface of the prepared rolled copper is mirror-polished, nickel or the like, which has resistance to gold etching solution, is plated onto the mirror-polished surface. As a result, the manufactured base material 10 becomes less susceptible to oxidation and its corrosion resistance is improved. An adhesion layer 20 made of titanium is formed on the surface of the manufactured base material 10. The adhesion layer 20 is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Note that chemical polishing may be used instead of mirror polishing for the surface treatment of the prepared rolled copper.

[0024] Next, an insulating layer 30 is formed on the adhesion layer 20. In the manufacturing method of the semiconductor element mounting substrate 1 of this embodiment, the insulating layer 30 is formed by reactive sputtering. The insulating layer 30 is formed with Al as the target, while maintaining the temperature of the substrate 10 at 100 to 300°C, and under a vacuum of 0.1 to 0.8 Pa, using argon (Ar) and nitrogen (N) ２ By passing a solution through it, the film is formed on the surface of the adhesion layer 20. In the formation of the insulating layer 30 in this embodiment, aluminum nitride is formed while applying a bias voltage of 125 (V) to the substrate 10.

[0025] Next, an electrode 40 is formed on the insulating layer 30. Specifically, first, an adhesion layer to improve adhesion with the insulating layer 30 and a seed layer to improve the bonding strength between the gold film that will become the electrode 40 and the adhesion layer are formed on the surface 31 of the insulating layer 30 as a base for the electrode 40. In this embodiment, the adhesion layer is formed of titanium using sputtering, and the seed layer is formed of palladium (Pd) using sputtering. Next, a gold film that will become the electrode 40 is formed on the seed layer, for example, by electroplating. The gold film may also be formed by sputtering or vapor deposition. Next, after the gold film is formed on the seed layer, electrode patterning is performed. Specifically, for example, the gold film is coated with a resist by forming a dry film resist with a laminator, and a resist pattern is formed by exposure and development. Next, using the resist as a mask, the gold film, seed layer, and a part of the adhesion layer are removed by etching, and the resist is peeled off with a stripping solution to form the electrode 40. This process manufactures a semiconductor element mounting substrate 1. However, the manufacturing method of the semiconductor element mounting substrate 1 is not limited to these methods.

[0026] Next, an evaluation test relating to the semiconductor element mounting substrate 1 of this embodiment will be described. In this evaluation test, the effect of the bias voltage in the process of forming the insulating layer was evaluated. Specifically, a sample for the evaluation test was prepared by fabricating the insulating layer using a method similar to the manufacturing method of the semiconductor element mounting substrate 1 described above. At this time, multiple samples with insulating layers having different film formation conditions were prepared by changing the bias voltage applied to the substrate during the deposition of the insulating layer by reactive sputtering. The prepared samples were subjected to Knoop hardness measurement and a heat resistance test (ambient temperature: 350°C, ambient gas: air, test time: 10 minutes), after which the surface of the sample was observed to confirm the effect of the bias voltage.

[0027] Figure 2 is the first figure illustrating the results of the evaluation test related to bias voltage. Figure 2 shows the "bias voltage" applied to the substrate when forming the insulating layer, the "Knoop hardness" of the insulating layer, and an image of the surface of the insulating layer after the heat resistance test for each of the four types of samples 1 to 4 used in this evaluation test. In this evaluation test, the bias voltages applied to the substrate were 125 (V), 94 (V), 40 (V), and 0 (V). The Knoop hardness shown in Figure 2 was measured using the Knoop hardness test method described in JIS Z 2251:2009, similar to the semiconductor element mounting substrate 1 in this embodiment. As shown in Figure 2, it was confirmed that the Knoop hardness of the insulating layer increases as the bias voltage applied to the substrate increases.

[0028] Figure 2 shows images of the insulating layer surface after the heat resistance test. For each of samples 1 to 4, images P10, P20, P30, and P40 were taken using a microscope at 400x magnification of a 740 μm × 560 μm area of ​​the insulating layer surface after the heat resistance test at an ambient temperature of 350°C. The images in Figure 2 were taken using oblique light mode. No cracks or other defects were visually observed on the surface of the insulating layer of the samples from the images in Figure 2.

[0029] Figure 3 is a second diagram illustrating the results of the evaluation test regarding the bias voltage. Figure 3 shows a magnified image P11 of a portion of image P10 of sample 1 shown in Figure 2. In sample 1, where the bias voltage was 125 (V), no cracks were observed on the surface of the insulating layer, as shown in image P11.

[0030] Figure 4 is a third figure illustrating the results of the evaluation test regarding the bias voltage. Figure 4 shows a magnified image P21 of a portion of image P20 of sample 2 shown in Figure 2. Even in sample 2, where the bias voltage was 94 (V), no cracks were observed on the surface of the insulating layer, as shown in image P21.

[0031] Figure 5 is the fourth figure illustrating the results of the evaluation test regarding the bias voltage. Figure 5 shows a magnified image P31 of a portion of image P30 of sample 3 shown in Figure 2. In sample 3, where the bias voltage was 40 (V), it was confirmed that a crack CK was formed on the surface of the insulating layer, as shown in image P31.

[0032] Figure 6 is the fifth figure illustrating the results of the evaluation test related to bias voltage. Figure 6 shows a magnified image P41 of a portion of image P40 of sample 4 shown in Figure 2. In sample 4, where the bias voltage was 0 (V), i.e., no bias voltage was applied to the substrate, it was confirmed that more cracks CK were formed on the surface of the insulating layer than in sample 3, as shown in image P41. Thus, it was confirmed that applying a bias voltage of a certain value or higher to the substrate during the deposition of the insulating layer by reactive sputtering increases the Knoop hardness. As a result, it was confirmed that the formation of cracks on the surface of the insulating layer is suppressed under the heat resistance test conditions.

[0033] As described above, the semiconductor element mounting substrate 1 of this embodiment has an insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 30 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 1, thereby suppressing defects such as cracks in the insulating layer 30. Therefore, the heat resistance of the insulating layer 30 can be improved.

[0034] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, the insulating layer 30 is formed of aluminum nitride. Aluminum nitride has relatively high thermal conductivity and relatively high electrical insulation properties. This allows for efficient dissipation of heat generated in the semiconductor element 5 connected to the electrode 40 via the substrate 10, while maintaining insulation between the electrode 40 and the substrate 10.

[0035] Furthermore, according to the semiconductor element mounting substrate 1 of this embodiment, the base material 10 is made of copper, which has relatively high thermal conductivity. This allows heat generated in the semiconductor element 5 connected to the electrode 40 to be efficiently released through the base material 10.

[0036] Furthermore, in the semiconductor element mounting substrate 1 of this embodiment, an adhesion layer 20 is formed between the base material 10 and the insulating layer 30 to improve the adhesion between the base material 10 and the insulating layer 30. This improves resistance to stress caused by, for example, the difference in thermal expansion between the base material 10 and the insulating layer 30 due to temperature changes, thereby suppressing the occurrence of cracks in the insulating layer 30. Therefore, the heat resistance of the insulating layer 30 can be further improved.

[0037] <Second Embodiment> Figure 7 is a cross-sectional view of the semiconductor element mounting substrate 2 of the second embodiment. The semiconductor element mounting substrate 2 of the second embodiment has a different insulating layer configuration compared to the semiconductor element mounting substrate 1 of the first embodiment (Figure 1).

[0038] The semiconductor element mounting substrate 2 of the second embodiment comprises a base material 10, an adhesion layer 20, an insulating layer 50, and an electrode 40. Note that the thickness relationships of the base material 10, the adhesion layer 20, the insulating layer 50, and the electrode 40 in Figure 7 are illustrated differently from the actual thickness relationships for the sake of explanation.

[0039] The insulating layer 50 is positioned between the adhesion layer 20 formed on the substrate 10 and the electrode 40. The insulating layer 50 has a first insulating film 51 with a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, and a second insulating film 52 with a Knoop hardness lower than that of the first insulating film 51. The first insulating film 51 and the second insulating film 52 have the same composition. Both the first insulating film 51 and the second insulating film 52 are made of aluminum nitride. The insulating layer 50 insulates the substrate 10 from the electrode 40.

[0040] Next, the manufacturing method of the semiconductor element mounting substrate 2 of this embodiment will be described. The manufacturing method of the semiconductor element mounting substrate 2 is similar to the manufacturing method of the semiconductor element mounting substrate 1 of the first embodiment, but the method of forming the insulating layer is different. Here, the differences between the manufacturing method of the semiconductor element mounting substrate 2 and the manufacturing method of the semiconductor element mounting substrate 1 will be explained.

[0041] In the manufacturing of the substrate 2 for mounting semiconductor elements, when depositing an insulating layer 50 on the adhesion layer 20, the bias voltage applied to the substrate 10 is changed. Specifically, when depositing the insulating layer 50 on the adhesion layer 20, first, the bias voltage is set to, for example, 125 (V) to deposit the first insulating film 51. After depositing the first insulating film 51, the bias voltage is set to a lower voltage than the bias voltage used when depositing the first insulating film 51, for example, 94 (V), to deposit the second insulating film 52. As a result, an insulating layer 50 is deposited consisting of a first insulating film 51 and a second insulating film 52 that have the same composition but different Knoop hardness. In the deposition of the insulating layer 50, the target used in reactive sputtering is aluminum for both the first insulating film 51 and the second insulating film 52. That is, when depositing the insulating layer 50, there is no need to change the sputtering target.

[0042] According to the substrate 2 for mounting semiconductor elements of the present embodiment described above, the insulating layer 50 has a first insulating film 51 with a Knoop hardness of 14.7 GPa HK0.4903 N or more. Thereby, for example, since the resistance to thermal stress generated in the insulating layer 50 due to temperature changes in the manufacture of the substrate 2 for mounting semiconductor elements can be improved, the heat resistance of the insulating layer 50 can be improved.

[0043] Moreover, according to the substrate 2 for mounting semiconductor elements of the present embodiment, a part of the insulating layer 50 is a second insulating film 52 having a relatively small Knoop hardness. Thereby, while maintaining the film thickness of the insulating layer 50, the stress in the insulating layer 50 can be reduced, so that the warpage of the substrate 2 for mounting semiconductor elements can be suppressed.

[0044] Moreover, according to the substrate 2 for mounting semiconductor elements of the present embodiment, the insulating layer 50 has a first insulating film 51 and a second insulating film 52 having a Knoop hardness smaller than that of the first insulating film 51. Since both the first insulating film 51 and the second insulating film 52 are formed of aluminum nitride, when forming the insulating layer 50 in the manufacture of the substrate 2 for mounting semiconductor elements, the target used when forming the first insulating film 51 and the target used when forming the second insulating film 52 are the same. Thereby, since the time for switching the target when forming the insulating layer 50 becomes unnecessary, the time required for forming the insulating layer 50 can be shortened. Therefore, the production efficiency of the substrate 2 for mounting semiconductor elements can be improved.

[0045] Moreover, according to the substrate 2 for mounting semiconductor elements of the present embodiment, the insulating layer 50 is formed in a state where a bias voltage is applied to the base material 10. Thereby, since the covering property of the surface of the base material 10 by the insulating layer 50 is improved, the unevenness of the base material 10 can be absorbed. [[ID=*]] [[ID=*]]

[0046] <Third Embodiment> FIG. 8 is a cross-sectional view of a substrate 3 for mounting semiconductor elements of the third embodiment. The substrate 3 for mounting semiconductor elements of the third embodiment has a different configuration of the insulating layer as compared with the substrate 1 for mounting semiconductor elements of the first embodiment (FIG. 1). [[ID=1*]]

[0047] The substrate 3 for mounting a semiconductor element according to the third embodiment includes a base material 10, an adhesion layer 20, an insulating layer 60, and an electrode 40. Note that, in FIG. 8, the relationship between the thicknesses of the base material 10, the adhesion layer 20, the insulating layer 60, and the electrode 40 is illustrated to be different from the actual thickness relationship for convenience of explanation.

[0048] The insulating layer 60 is disposed between the adhesion layer 20 formed on the base material 10 and the electrode 40. The insulating layer 60 has a first insulating film 61 having a Knoop hardness of 14.7 GPa HK0.4903 N or more, and a second insulating film 62 having a Knoop hardness smaller than that of the first insulating film 61. The first insulating film 61 is disposed closer to the base material 10 side than the second insulating film 62 in the insulating layer 60. In the present embodiment, the first insulating film 61 is formed of silicon nitride (SiN), and the second insulating film 62 is formed of aluminum nitride. The insulating layer 60 insulates the base material 10 and the electrode 40.

[0049] Next, a method for manufacturing the substrate 3 for mounting a semiconductor element according to the present embodiment will be described. The method for manufacturing the substrate 3 for mounting a semiconductor element is in accordance with the method for manufacturing the substrate 1 for mounting a semiconductor element of the first embodiment, and the method for forming the insulating layer is different. Here, in the method for manufacturing the substrate 3 for mounting a semiconductor element, the portions different from the method for manufacturing the substrate 1 for mounting a semiconductor element will be described.

[0050] When forming the insulating layer 60 on the adhesion layer 20 in the manufacture of the substrate 3 for mounting a semiconductor element, the target in reactive sputtering is changed. Specifically, when forming the insulating layer 60 on the adhesion layer 20, first, the target is set to Si, and the first insulating film 61 is formed. After forming the first insulating film 61, the target is changed to Al, and the second insulating film 62 is formed. Thereby, the insulating layer 60 composed of the first insulating film 61 and the second insulating film 62 is formed. Note that the point of applying a bias voltage to the base material 10 during film formation is the same as the method for manufacturing the substrate 1 for mounting a semiconductor element.

[0051] As described above, the semiconductor element mounting substrate 3 of this embodiment has a first insulating film 61 in the insulating layer 60 having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 60 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 3, thereby improving the heat resistance of the insulating layer 60.

[0052] Furthermore, in the semiconductor element mounting substrate 3 of this embodiment, a portion of the insulating layer 60 is a second insulating film 62 with relatively low Knoop hardness. This makes it possible to reduce stress in the insulating layer 60 while maintaining the thickness of the insulating layer 60, thereby suppressing warping of the semiconductor element mounting substrate 3.

[0053] <Fourth Embodiment> Figure 9 is a cross-sectional view of the semiconductor element mounting substrate 4 of the fourth embodiment. The semiconductor element mounting substrate 4 of the fourth embodiment has a different insulating layer configuration compared to the semiconductor element mounting substrate 1 of the first embodiment (Figure 1).

[0054] The semiconductor element mounting substrate 4 of the fourth embodiment comprises a base material 10, an adhesion layer 20, an insulating layer 70, and an electrode 40. Note that the thickness relationships of the base material 10, the adhesion layer 20, the insulating layer 70, and the electrode 40 in Figure 9 are illustrated differently from the actual thickness relationships for the sake of explanation.

[0055] The insulating layer 70 is positioned between the adhesion layer 20 formed on the substrate 10 and the electrode 40. The insulating layer 70 has a first insulating film 71 having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, and a second insulating film 72 having a Knoop hardness lower than that of the first insulating film 71. The second insulating film 72 is positioned on the substrate 10 side of the insulating layer 70 than the first insulating film 71. In this embodiment, the first insulating film 71 is made of silicon nitride, and the second insulating film 72 is made of aluminum nitride. The insulating layer 70 insulates the substrate 10 from the electrode 40.

[0056] Next, the manufacturing method of the semiconductor element mounting substrate 4 of this embodiment will be described. The manufacturing method of the semiconductor element mounting substrate 4 is similar to the manufacturing method of the semiconductor element mounting substrate 1 of the first embodiment, but the method of forming the insulating layer is different. Here, we will explain the parts of the manufacturing method of the semiconductor element mounting substrate 4 that differ from the manufacturing method of the semiconductor element mounting substrate 1.

[0057] In the manufacturing of the semiconductor device mounting substrate 4, when depositing an insulating layer 70 on the adhesion layer 20, the target in reactive sputtering is changed. Specifically, when depositing the insulating layer 70 on the adhesion layer 20, first, the target is set to Si and a second insulating film 72 is deposited. After depositing the second insulating film 72, the target is changed to Al and the first insulating film 71 is deposited. As a result, an insulating layer 70 consisting of the first insulating film 71 and the second insulating film 72 is deposited. Note that the point of depositing the film while applying a bias voltage to the substrate 10 is the same as in the manufacturing method of the semiconductor device mounting substrate 1.

[0058] As described above, the semiconductor element mounting substrate 4 of this embodiment has a first insulating film 71 in the insulating layer 70 having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher. This improves the resistance to thermal stress generated in the insulating layer 70 due to temperature changes during the manufacturing of the semiconductor element mounting substrate 4, thereby improving the heat resistance of the insulating layer 60.

[0059] Furthermore, according to the semiconductor element mounting substrate 4 of this embodiment, the insulating layer 70 has a first insulating film 71 and a second insulating film 72 having a lower Knoop hardness than the first insulating film 71. In the insulating layer 70, the second insulating film 72 is positioned closer to the substrate 10 than the first insulating film 71. By positioning the second insulating film 72, which has a relatively low Knoop hardness, closer to the substrate 10, the stress can be relieved so that thermal stress generated in the substrate 10 is not transmitted to the first insulating film 71, which has a relatively high Knoop hardness. This suppresses the occurrence of defects such as cracks in the insulating layer 70, and thus improves the heat resistance of the insulating layer 70.

[0060] Furthermore, in the semiconductor element mounting substrate 4 of this embodiment, a first insulating film 71 with relatively high Knoop hardness is arranged on the side of the insulating layer 70 opposite to the base material 10. As a result, the surface 70a of the insulating layer 70 is relatively hard, making it less susceptible to scratches during the manufacturing process of the semiconductor element mounting substrate 4. Therefore, it is possible to suppress the occurrence of defects in the semiconductor element mounting substrate 4, such as insulation defects in the insulating layer 70.

[0061] <Modifications of this Embodiment> The present invention is not limited to the above-described embodiments, and can be implemented in various forms without departing from the spirit of the invention. For example, the following modifications are also possible.

[0062] [Modification 1] In the above embodiment, the substrate for mounting semiconductor elements had an insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher. A Knoop hardness of 19.57 GPaHK 0.4903 N or higher is more preferable because it can further suppress the occurrence of cracks in the insulating properties.

[0063] [Modification 2] In the second, third, and third embodiments, the insulating layer has a plurality of insulating films with different Knoop hardnesses. The Knoop hardness in the insulating layer may change continuously in the lamination direction between the substrate and the insulating layer. Such an insulating layer can be formed by, for example, continuously changing the bias voltage applied to the substrate when forming the insulating layer.

[0064] [Modification 3] In the above embodiment, the heat resistance of the insulating layer was described as a characteristic of temperature changes during the manufacturing of the semiconductor element mounting substrate. The temperature changes that can be accommodated are not limited to those during the manufacturing of the semiconductor element mounting substrate.

[0065] [Modification 4] In the above embodiment, the semiconductor element 5 mounted on the substrate for mounting semiconductor elements was described as a light-emitting diode or a semiconductor laser, but it is not limited to these. It may also be a power semiconductor or the like, which generates a relatively large amount of heat.

[0066] [Modification 5] In the above embodiment, the substrate for mounting semiconductor elements is provided with an adhesion layer placed between the substrate and the insulating layer. The adhesion layer is not required, but by providing it, resistance to stress caused by the difference in thermal expansion between the substrate and the insulating layer due to temperature changes can be improved.

[0067] [Modification 6] In the second to fourth embodiments, the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film. The configuration of the insulating layer is not limited to these. The insulating layer may also have films other than the first insulating film and the second insulating film. That is, the insulating layer may be formed by laminating three or more films, including the first insulating film and the second insulating film.

[0068] The embodiments of this specification have been described above based on the embodiments and modifications described above. The embodiments described above are for the purpose of facilitating understanding of this specification and do not limit it. This specification may be modified and improved without departing from its spirit and the scope of the claims, and equivalents thereof are included in this specification. Furthermore, any technical features that are not described as essential in this specification may be deleted as appropriate.

[0069] (Application Example 1) A semiconductor element mounting substrate comprising: a base material; electrodes connected to a semiconductor element; and an insulating layer disposed between the base material and the electrodes, wherein the insulating layer has an insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher. (Application Example 2) The semiconductor element mounting substrate according to Application Example 1, wherein the insulating layer comprises: a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher; and a second insulating film having a Knoop hardness lower than that of the first insulating film, wherein the first insulating film and the second insulating film have the same composition. (Application Example 3) A semiconductor element mounting substrate according to claim 1 or claim 2, wherein the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or more, and a second insulating film having a Knoop hardness less than that of the first insulating film, and the first insulating film is positioned on the substrate side of the insulating layer than the second insulating film. (Application Example 4) A semiconductor element mounting substrate according to any one of Application Examples 1 to 3, wherein the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or more, and a second insulating film having a Knoop hardness less than that of the first insulating film, and the second insulating film is positioned on the substrate side of the insulating layer than the first insulating film. (Example 5) A semiconductor element mounting substrate according to any one of Examples 1 to 4, wherein the insulating layer is formed of aluminum nitride. (Example 6) A semiconductor element mounting substrate according to any one of Examples 1 to 5, wherein the base material is formed of a material mainly composed of copper or aluminum. (Example 7) A semiconductor element mounting substrate according to any one of Examples 1 to 6, further comprising an adhesion layer disposed between the base material and the insulating layer.

[0070] 1, 2, 3, 4... Substrate for mounting semiconductor elements 10... Base material 20... Adhesion layer 30, 50, 60, 70... Insulating layer 40... Electrode 51, 61, 71... First insulating film 52, 62, 72... Second insulating film

Claims

1. A substrate for mounting semiconductor elements, comprising: a base material; electrodes connected to a semiconductor element; and an insulating layer disposed between the base material and the electrodes, wherein the insulating layer has an insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher.

2. A semiconductor element mounting substrate according to claim 1, wherein the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or higher, and a second insulating film having a Knoop hardness lower than that of the first insulating film, and the first insulating film and the second insulating film have the same composition.

3. A semiconductor element mounting substrate according to claim 1, wherein the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or more, and a second insulating film having a Knoop hardness less than that of the first insulating film, and the first insulating film is positioned on the substrate side of the insulating layer than the second insulating film.

4. A semiconductor element mounting substrate according to claim 1, wherein the insulating layer comprises a first insulating film having a Knoop hardness of 14.7 GPaHK 0.4903 N or more, and a second insulating film having a Knoop hardness less than that of the first insulating film, and the second insulating film is positioned on the substrate side of the insulating layer than the first insulating film.

5. A semiconductor element mounting substrate according to any one of claims 1 to 4, wherein the insulating layer is formed of aluminum nitride.

6. A semiconductor element mounting substrate according to any one of claims 1 to 4, wherein the substrate is formed of a material mainly composed of copper or aluminum.

7. A semiconductor element mounting substrate according to any one of claims 1 to 4, further comprising an adhesion layer disposed between the substrate and the insulating layer.

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