Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device including an active part and an edge termination structure part provided on the outer periphery of the active part. The semiconductor device may include a first-conductivity-type drift region provided in a semiconductor substrate, and a second-conductivity-type region that is of a second conductivity type provided above the drift region in the active part. The edge termination structure part may have a second-conductivity-type first channel stop region provided above the drift region. The edge termination structure part may include a first-conductivity-type second channel stop region provided below the first channel stop region and having a doping concentration higher than that of the drift region. The edge termination structure part may include a first-conductivity-type third channel stop region connected to the second channel stop region, provided close to the active part relative to the first channel stop region, and having a doping concentration higher than that of the drift region.

Description

Semiconductor device and method for manufacturing a semiconductor device

[0001] This invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Semiconductor devices having a P-type channel stop region in the edge termination structure are known (see, for example, Patent Documents 1 and 2). Patent Document 1: Japanese Unexamined Patent Publication No. 2014-138182 Patent Document 2: Japanese Unexamined Patent Publication No. 2023-135674 General disclosure

[0003] In a first embodiment of the present invention, a semiconductor device is provided comprising an active portion and an edge termination structure provided on the outer periphery of the active portion. The semiconductor device may comprise a drift region of a first conductivity type provided on a semiconductor substrate, and a second conductivity type region of a second conductivity type provided above the drift region in the active portion. The edge termination structure may have a first channel stop region of a second conductivity type provided above the drift region. The edge termination structure may have a second channel stop region of a first conductivity type provided below the first channel stop region and having a doping concentration higher than that of the drift region. The edge termination structure may have a third channel stop region of a first conductivity type connected to the second channel stop region, provided closer to the active portion than the first channel stop region, and having a doping concentration higher than that of the drift region. The lower end of the third channel stop region may be shallower than the lower end of the second channel stop region in the depth direction of the semiconductor substrate.

[0004] In any of the semiconductor devices described above, the third channel stop region may extend from the second channel stop region in the direction from which the active portion is provided.

[0005] In any of the semiconductor devices described above, the second channel stop region may cover the lower end and side of the active portion side of the first channel stop region.

[0006] In any of the semiconductor devices described above, the distance between the active portion side end of the first channel stop region and the active portion side end of the third channel stop region may be greater than the difference between the depth position of the lower end of the first channel stop region and the depth position of the lower end of the second channel stop region.

[0007] In any of the semiconductor devices described above, the thickness of the first channel stop region may be smaller than the thickness of the second channel stop region below the first channel stop region.

[0008] In any of the above semiconductor devices, the thickness of the first channel stop region may be greater than or equal to the thickness of the second channel stop region below the first channel stop region.

[0009] In any of the above-described semiconductor devices, the doping concentration in the first channel stop region may be the same as the doping concentration in the second conductivity type region.

[0010] In any of the above semiconductor devices, the depth position of the lower end of the first channel stop region may be the same as the depth position of the lower end of the second conductivity type region.

[0011] The first channel stop region may be provided on the front surface of the semiconductor substrate.

[0012] In any of the semiconductor devices described above, the first channel stop region may be provided on the side surface of the semiconductor substrate.

[0013] In any of the above-described semiconductor devices, the maximum doping concentration of the second conductivity type dopant in the first channel stop region may be smaller than the maximum doping concentration of the first conductivity type dopant in the second channel stop region.

[0014] In any of the semiconductor devices described above, the second channel stop region may have multiple peaks of doping concentration in the depth direction of the semiconductor substrate.

[0015] In any of the above-described semiconductor devices, the dopant in the second channel stop region may be phosphorus.

[0016] Any of the above semiconductor devices may have a non-formed region at the corner of the semiconductor substrate where the second channel stop region is not provided. The outer periphery of the non-formed region may be covered by the second channel stop region when viewed from above.

[0017] In any of the semiconductor devices described above, the second channel stop region may be provided on the side surface of the semiconductor substrate.

[0018] In any of the above-described semiconductor devices, the thickness of the third channel stop region may be 1.0 μm or more and 5.0 μm or less in the depth direction of the semiconductor substrate.

[0019] In any of the above-described semiconductor devices, the dopant in the third channel stop region may be phosphorus.

[0020] Any of the above semiconductor devices may include a stopper metal layer provided above the semiconductor substrate and connected to the first channel stop region.

[0021] In any of the semiconductor devices described above, the end of the stopper metal layer on the active portion side may be provided closer to the active portion than the end of the third channel stop region on the active portion side.

[0022] In any of the above semiconductor devices, the third channel stop region may be provided below the stopper metal layer.

[0023] Any of the above semiconductor devices may include a storage region of a first conductivity type having a higher doping concentration than the drift region, located above the drift region.

[0024] In any of the semiconductor devices described above, the storage region may have multiple peaks of doping concentration in the depth direction of the semiconductor substrate. The third channel stop region may have multiple peaks of doping concentration in the depth direction of the semiconductor substrate.

[0025] In any of the above semiconductor devices, the doping concentration in the storage region may be the same as the doping concentration in the second channel stop region.

[0026] In any of the semiconductor devices described above, the magnitude of the peak doping concentration in the accumulation region may be the same as the magnitude of the peak doping concentration in the third channel stop region.

[0027] Any of the above semiconductor devices may include a base insulating film provided above the third channel stop region.

[0028] In any of the above semiconductor devices, the thickness of the basic insulating film may be 100 nm or more and 3 μm or less.

[0029] In any of the semiconductor devices described above, the edge termination structure may have a plurality of guard ring portions located inside the semiconductor substrate beyond the third channel stop region when viewed from above. The distance from the third channel stop region to the outermost guard ring portion among the plurality of guard ring portions may be 10 μm or more and 100 μm or less.

[0030] In any of the above semiconductor devices, if α is the distance from the edge of the basic insulating film on the semiconductor substrate side to the active side of the third channel stop region, and β is the distance from the third channel stop region to the outermost guard ring portion, then 0 < α / β ≤ 10 may be satisfied.

[0031] In any of the above semiconductor devices, α and β may satisfy 0.001 ≤ α / β ≤ 10.

[0032] Any of the above semiconductor devices may include a transistor section. The transistor section may include a plurality of trench sections extended in a predetermined trench stretching direction on the front surface of the semiconductor substrate, an emitter section of a first conductivity type having a higher doping concentration than the drift section, and a plurality of contact sections of a second conductivity type having a higher doping concentration than the second conductivity section, provided above the drift section. The second conductivity section may be the base section of the transistor section.

[0033] Any of the above semiconductor devices may include a diode section. The second conductivity type region may be the anode region of the diode section.

[0034] Any of the above semiconductor devices may include a stopper metal layer provided above the semiconductor substrate and connected to the first channel stop region. Any of the above semiconductor devices may include a guard ring portion provided inside the semiconductor substrate beyond the third channel stop region when viewed from above. Any of the above semiconductor devices may include an edge metal layer provided above the semiconductor substrate and connected to the guard ring portion. The third channel stop region may extend from the edge side of the semiconductor substrate, beyond the end of the stopper metal layer on the active portion side, toward the active portion side. The amount of extension of the end of the third channel stop region on the active portion side toward the direction in which the active portion is provided from the end of the stopper metal layer on the active portion side may be 50% or less of the distance between the end of the stopper metal layer on the active portion side and the end of the edge metal layer on the semiconductor substrate side.

[0035] Any of the above semiconductor devices may include a stopper metal layer provided above the semiconductor substrate and connected to the first channel stop region. Any of the above semiconductor devices may include, in the edge termination structure portion, a guard ring portion provided inside the semiconductor substrate with respect to the third channel stop region in a top view. Any of the above semiconductor devices may include an edge metal layer provided above the semiconductor substrate and connected to the guard ring portion. The third channel stop region may terminate from the edge side of the semiconductor substrate without exceeding the end portion on the active portion side of the stopper metal layer. The separation distance from the end portion on the active portion side of the third channel stop region to the end portion on the active portion side of the stopper metal layer may be 50% or less of the distance between the end portion on the active portion side of the stopper metal layer and the end portion on the edge side of the semiconductor substrate of the edge metal layer.

[0036] In any of the above semiconductor devices, the distance L1 between the end portion on the active portion side of the first channel stop region and the end portion on the active portion side of the third channel stop region may be 5 μm or more.

[0037] In a second aspect of the present invention, there is provided a semiconductor device including an active portion and an edge termination structure portion provided on the outer periphery of the active portion. The semiconductor device may include a drift region of a first conductivity type provided in a semiconductor substrate, a second conductivity type region of a second conductivity type provided above the drift region in the active portion, and an accumulation region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region. The edge termination structure portion may have a first channel stop region of a second conductivity type provided above the drift region. The edge termination structure portion may have a second channel stop region of a first conductivity type provided below the first channel stop region and having a higher doping concentration than the drift region. The magnitude of the peak of the doping concentration of the accumulation region may be equal to the magnitude of the peak of the doping concentration of the second channel stop region.

[0038] A third aspect of the present invention provides a semiconductor device comprising an active portion and an edge termination structure provided on the outer periphery of the active portion. The semiconductor device may include a drift region of a first conductivity type provided on a semiconductor substrate, a second conductivity type region of a second conductivity type provided above the drift region in the active portion, and a storage region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region. The edge termination structure may have a second channel stop region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region. The edge termination structure may have a third channel stop region of a first conductivity type connected to the second channel stop region, provided closer to the active portion than the second channel stop region, and having a higher doping concentration than the drift region. The edge termination structure may have a base insulating film provided above the third channel stop region. The dopants of the second channel stop region and the third channel stop region may be the same as the dopants of the storage region. The lower end of the third channel stop region may be shallower than the lower end of the second channel stop region in the depth direction of the semiconductor substrate. The base insulating film does not need to be provided above the second channel stop region.

[0039] In any of the semiconductor devices described above, the third channel stop region may extend from the second channel stop region in the direction from which the active portion is provided.

[0040] In a fourth aspect of the present invention, a semiconductor device is provided which includes an active portion and an edge termination structure portion provided on the outer periphery of the active portion. The semiconductor device may include a drift region of a first conductivity type provided on a semiconductor substrate, a second conductivity type region of a second conductivity type provided above the drift region in the active portion, and an accumulation region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region. The edge termination structure portion may be provided above the drift region and may have a first conductivity type channel stop portion of a first conductivity type having a higher doping concentration than the drift region. The dopant of the first conductivity type channel stop portion may be the same as the dopant of the accumulation region. The maximum value of the doping concentration of the first conductivity type channel stop portion may be the same as the maximum value of the doping concentration of the accumulation region.

[0041] Any of the above semiconductor devices may include a base insulating film provided above the first conductivity type channel stop portion.

[0042] In a fifth aspect of the present invention, a method for manufacturing a semiconductor device including an active portion and an edge termination structure portion provided on the outer periphery of the active portion is provided. The method for manufacturing the semiconductor device may include forming a second conductivity type region of a second conductivity type above a drift region of a first conductivity type provided on a semiconductor substrate in the active portion, forming a first channel stop region of a second conductivity type above the drift region in the edge termination structure portion, forming a second channel stop region of a first conductivity type having a higher doping concentration than the drift region below the first channel stop region, and forming a third channel stop region of a first conductivity type having a higher doping concentration than the drift region, which is connected to the second channel stop region and closer to the active portion than the first channel stop region. The lower end of the third channel stop region may be shallower than the lower end of the second channel stop region in the depth direction of the semiconductor substrate. [[ID=�]]

[0043] In the above-described method for manufacturing a semiconductor device, the step of forming the third channel stop region may include the step of implanting ions into the semiconductor substrate via a base insulating film provided above the semiconductor substrate.

[0044] Any of the above methods for manufacturing a semiconductor device may include a step of forming a storage region on the semiconductor substrate. Ion implantation of the third channel stop region may be performed simultaneously with ion implantation of the storage region in the same process.

[0045] Any of the above methods for manufacturing a semiconductor device may include a step of forming a stopper metal layer connected to the first channel stop region above the semiconductor substrate. Any of the above methods for manufacturing a semiconductor device may include a step of forming a guard ring portion inside the semiconductor substrate beyond the third channel stop region in a top view. Any of the above methods for manufacturing a semiconductor device may include a step of forming an edge metal layer connected to the guard ring portion above the semiconductor substrate. The third channel stop region may extend from the edge side of the semiconductor substrate, beyond the end of the stopper metal layer on the active portion side, toward the active portion side. The amount of extension of the end of the third channel stop region on the active portion side from the end of the stopper metal layer on the active portion side toward the direction in which the active portion is provided may be 50% or less of the distance between the end of the stopper metal layer on the active portion side and the end of the edge metal layer on the semiconductor substrate side.

[0046] Any of the above methods for manufacturing a semiconductor device may include a step of forming a stopper metal layer connected to the first channel stop region above the semiconductor substrate. Any of the above methods for manufacturing a semiconductor device may include a step of forming a guard ring portion inside the semiconductor substrate beyond the third channel stop region in a top view. Any of the above methods for manufacturing a semiconductor device may include a step of forming an edge metal layer connected to the guard ring portion above the semiconductor substrate. The third channel stop region may terminate without extending beyond the active portion side end of the stopper metal layer from the edge side of the semiconductor substrate. The distance between the active portion side end of the third channel stop region and the active portion side end of the stopper metal layer may be 50% or less of the distance between the active portion side end of the stopper metal layer and the edge portion of the edge metal layer from the semiconductor substrate.

[0047] In any of the above methods for manufacturing a semiconductor device, the distance L1 between the active portion side end of the first channel stop region and the active portion side end of the third channel stop region may be 5 μm or more.

[0048] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention.

[0049] An example of a top view of the semiconductor device 100 is shown. This is an enlarged view of region A in Figure 1. This is a diagram showing an example of an XZ cross section including the b-b' cross section in Figure 2A. This is a diagram showing an example of an XZ cross section including the c-c' cross section in Figure 2A. This is an enlarged view of an XZ cross section passing through the mesa portion 71. This is a diagram showing an example of an XZ cross section including the a-a' cross section in Figure 1. This is a flowchart showing the manufacturing method of the semiconductor device 100 in Figure 3A. This is a diagram for explaining the manufacturing process of the semiconductor device 100 in Figure 3A. This is a diagram showing a modified example of the XZ cross section including the a-a' cross section in Figure 1. An example of simulation results for the semiconductor device 100 and semiconductor device 500 is shown. An example of the electrical characteristics of the semiconductor device is shown. This shows the dependence of the dose amount of the first conductivity type channel stop portion 260 on BVCES. This is a diagram showing a modified example of the XZ cross section including the a-a' cross section in Figure 1. This is a flowchart showing the manufacturing method of the semiconductor device 100 in Figure 5A. This is a diagram for explaining the manufacturing process of the semiconductor device 100 in Figure 5A. This is a diagram showing a modified example of the XZ cross section including the a-a' cross section in Figure 1. This is a flowchart showing the manufacturing method of the semiconductor device 100 in Figure 6A. This is a diagram illustrating the manufacturing process of the semiconductor device 100 shown in Figure 6A. This is a diagram showing a modified XZ cross section including the a-a' cross section in Figure 1. This is a flowchart illustrating the manufacturing method of the semiconductor device 100 shown in Figure 7A. This is a diagram illustrating the manufacturing process of the semiconductor device 100 shown in Figure 7A. This is an example of the edge breakdown structure of the edge termination structure 170. This is a modified example of the edge breakdown structure of the edge termination structure 170. This is a modified example of the edge breakdown structure of the edge termination structure 170. This shows an example of the corner R shown in Figure 1. This shows a modified example of the corner R shown in Figure 1. This is an example of a top view of the semiconductor device 100. This is an example of a cross-sectional view of the semiconductor device 100. This is a diagram showing a modified XZ cross section including the a-a' cross section in Figure 1. This is a diagram showing a modified XZ cross section including the a-a' cross section in Figure 1. This shows an example of the electrical characteristics of the semiconductor device. This shows an example of the electrical characteristics of the semiconductor device. This shows an example of the electrical characteristics of the semiconductor device. This shows an example of the electrical characteristics of the semiconductor device.

[0050] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0051] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "upper," and the other side as "lower." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the upper surface, and the other surface as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0052] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z axis and the -Z axis.

[0053] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction.

[0054] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0055] In this specification, the conductivity type of a doped region containing impurities is described as either P-type or N-type. In this specification, impurities may specifically refer to either N-type donors or P-type acceptors, and may be referred to as dopants. In this specification, doping means introducing donors or acceptors into a semiconductor substrate to make it a semiconductor exhibiting either an N-type conductivity or a P-type conductivity.

[0056] In this specification, doping concentration means the concentration of the donor or acceptor at thermal equilibrium. In this specification, net doping concentration means the net concentration obtained by adding up the charge polarity, with the donor concentration being the concentration of positive ions and the acceptor concentration being the concentration of negative ions. As an example, the donor concentration is N Ｄ , the acceptor concentration is N Ａ Therefore, the net doping concentration at any given position is N Ｄ -N Ａ In this specification, net doping concentration may sometimes be simply referred to as doping concentration.

[0057] In this specification, when P+ type or N+ type is mentioned, it means a higher doping concentration than P type or N type, and when P- type or N- type is mentioned, it means a lower doping concentration than P type or N type. Furthermore, when P++ type or N++ type is mentioned in this specification, it means a higher doping concentration than P+ type or N+ type.

[0058] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electrical activation state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by voltage-capacitance (CV) spectroscopy. Alternatively, the carrier concentration measured by broadened resistance (SR) spectroscopy may be used as the net doping concentration. A carrier refers to an electron or hole charge carrier. The carrier concentration measured by CV or SR spectroscopy may be the value at thermal equilibrium. Furthermore, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier concentration in that region may be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in that region may be used as the acceptor concentration. In this specification, the doping concentration in the N-type region may be referred to as the donor concentration, and the doping concentration in the P-type region may be referred to as the acceptor concentration.

[0059] Furthermore, if the concentration distribution of donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of donor, acceptor, or net doping in that region. In cases where the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping.

[0060] The carrier concentration measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value in the crystalline state within the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc. The reason for the decrease in carrier concentration is as follows: In the SR method, spreading resistance is measured, and the carrier concentration is converted from the measured value of spreading resistance. At this time, the carrier mobility of the crystalline state is used. On the other hand, at locations where lattice defects are introduced, the carrier concentration is calculated using the carrier mobility of the crystalline state, even though the carrier mobility is reduced. Therefore, it will be a lower value than the actual carrier concentration, i.e., the donor or acceptor concentration.

[0061] The donor or acceptor concentrations calculated from carrier concentrations measured by the CV or SR method may be lower than the chemical concentrations of the elements that represent the donor or acceptor. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentrations of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen, which is a donor in silicon semiconductors, is approximately 0.1% to 10% of the hydrogen chemical concentration. The SI unit system is used in this specification. In this specification, units of distance and length may be expressed in cm (centimeters). In this case, calculations may be performed by converting to m (meters). Regarding the numerical representation of powers of 10, for example, the representation of 1E+16 is 1 × 10⁻¹⁶. １６ This indicates that the 1E-16 designation is 1 × 10 －１６ This indicates.

[0062] Figure 1 shows an example of a top view of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some components of the semiconductor device 100 are shown, and some components are omitted. The semiconductor device 100 is a semiconductor chip comprising a transistor section 70 and a diode section 80.

[0063] The transistor section 70 includes a transistor such as an IGBT (Insulated Gate Bipolar Transistor). The diode section 80 includes a diode such as a freewheel diode (FWD). The semiconductor device 100 in this example is a reverse conducting IGBT (RC-IGBT) having the transistor section 70 and the diode section 80 on the same chip.

[0064] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate, a silicon carbide substrate, a diamond substrate, a nitride semiconductor substrate such as gallium nitride, an inorganic compound semiconductor substrate such as gallium oxide, or an organic compound semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. The semiconductor ingot may be manufactured by any of the following methods: the Czochralski method (CZ method), the magnetic field applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0065] The semiconductor substrate 10 has edges 102 when viewed from above. In this specification, "viewed from above" simply means viewing the semiconductor substrate 10 from the top side. The semiconductor substrate 10 in this example has two pairs of edges 102 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to one of the edges 102. The Z axis is perpendicular to the top surface of the semiconductor substrate 10. The semiconductor substrate 10 has an active portion 160 and an edge termination structure portion 170.

[0066] The active region 160 is the area between the upper and lower surfaces of the semiconductor substrate 10 where the main current flows in the depth direction during operation of the semiconductor device 100. An emitter electrode is provided above the active region 160, but it is omitted in Figure 1.

[0067] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10.

[0068] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have a longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0069] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode portion 80. In other words, the diode portion 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided in the area other than the cathode region on the lower surface of the semiconductor substrate 10.

[0070] The transistor section 70 has a P+ type collector region in the area that is in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N type emitter region, a P type base region, a gate conductive portion, and a gate insulating film.

[0071] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is located near the edge 102. The vicinity of the edge 102 may refer to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0072] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 includes gate wiring 130 that connects the gate pad 112 and the gate trench.

[0073] The gate wiring 130 is electrically connected to the gate conductive part of the transistor section 70 and applies a gate voltage to the transistor section 70. The gate wiring 130 is provided so as to surround the outer circumference of the active section 160 when viewed from above. The gate wiring 130 is electrically connected to the gate pad 112 provided on the edge termination structure 170.

[0074] Furthermore, the semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0075] In this example, the semiconductor device 100 includes an edge termination structure 170 between the active portion 160 and the edge 102 when viewed from above. The edge termination structure 170 in this example is positioned between the gate wiring 130 and the edge 102. The edge termination structure 170 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 170 may include at least one of a guard ring, a field plate, and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0076] Figure 2A is an enlarged view of region A in Figure 1. Region A is the region that includes the transistor section 70, the diode section 80, and the gate wiring 130. In this example, the gate wiring 130 includes the gate metal layer 50 and the gate runner section 51.

[0077] The transistor section 70 has a main region 75 and a boundary region 90. On the front surface 21 of the semiconductor substrate 10, a boundary region 90 is provided between the main region 75 of the transistor section 70 and the diode section 80. The front surface 21 of the semiconductor substrate 10 refers to one of the two opposing main surfaces of the semiconductor substrate 10. The front surface 21 will be described later.

[0078] The semiconductor device 100 in this example includes a gate trench 40, a dummy trench 30, a well region 17, an emitter region 12, a base region 14, and a contact region 15 formed inside the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example also includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0079] An interlayer insulating film is formed between the emitter electrode 52 and the gate metal layer 50 and the front surface 21 of the semiconductor substrate 10, but this interlayer insulating film is omitted in Figure 2A. In this example, contact holes 54, 55, and 56 are formed through the interlayer insulating film.

[0080] The emitter electrode 52 is electrically connected to the emitter region 12, contact region 15, and base region 14 on the front surface 21 of the semiconductor substrate 10 through a contact hole 54 opened in the interlayer insulating film. The emitter electrode 52 is also connected to a dummy conductive portion in the dummy trench portion 30 through a contact hole 56. A connection portion 25 made of a conductive material such as polysilicon doped with impurities may be provided between the emitter electrode 52 and the dummy conductive portion.

[0081] The gate metal layer 50 contacts the gate runner portion 51 through the contact hole 55. The gate runner portion 51 is formed of a semiconductor such as polysilicon doped with impurities. The gate runner portion 51 is connected to the gate conductive portion in the gate trench portion 40 on the front surface 21 of the semiconductor substrate 10.

[0082] The emitter electrode 52 and the gate metal layer 50 are formed from a metal-containing material. At least a portion of the emitter electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). At least a portion of the gate metal layer 50 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed from titanium or a titanium compound in the layer below the region formed from aluminum or the like. Each electrode may further have a plug portion formed by embedding tungsten or the like in contact with the barrier metal and aluminum or the like within the contact hole.

[0083] The well region 17 is provided overlapping the gate metal layer 50 and the gate runner portion 51. The well region 17 is also provided extending to a predetermined width in areas that do not overlap the gate metal layer 50 and the gate runner portion 51. In this example, the well region 17 is provided away from the Y-axis end of the contact hole 54 towards the gate metal layer 50. The well region 17 is a second conductivity type region provided on the semiconductor substrate 10. The doping concentration of the well region 17 may be higher than the doping concentration of the base region 14. In this example, the base region 14 is P-type and the well region 17 is P+ type.

[0084] Each of the transistor section 70 and the diode section 80 has multiple trenches arranged in the trench arrangement direction on the front surface 21 of the semiconductor substrate 10. In this example, the transistor section 70 has one or more gate trenches 40 and one or more dummy trenches 30 alternately provided along the trench arrangement direction. In this example, the diode section 80 has multiple dummy trenches 30 provided along the trench arrangement direction. In this example, the diode section 80 does not have gate trenches 40. The trench arrangement direction may be the same as or different from the arrangement direction of the transistor section 70 and the diode section 80. In this example, the trench arrangement direction is the same as the arrangement direction of the transistor section 70 and the diode section 80.

[0085] The transistor section 70 has one or more gate trench sections 40 arranged at predetermined intervals along the trench arrangement direction. The gate conductive portion inside the gate trench section 40 is electrically connected to the gate metal layer 50, and the gate potential is applied. The transistor section 70 may also have one or more dummy trench sections 30 arranged at predetermined intervals along the trench arrangement direction. A potential different from the gate potential is applied to the dummy conductive portion inside the dummy trench section 30. In this example, the dummy conductive portion is electrically connected to the emitter electrode 52, and the emitter potential is applied.

[0086] In the transistor section 70, one or more gate trench sections 40 and one or more dummy trench sections 30 may be alternately formed along a predetermined trench arrangement direction. The dummy trench sections 30 are arranged at predetermined intervals along a predetermined trench arrangement direction in the diode section 80 and the boundary region 90. The transistor section 70 may also consist only of gate trench sections 40 without any dummy trench sections 30.

[0087] The gate trench section 40 in this example may have two extended portions 41 (the trench sections that are linear along the extension direction) that extend along the trench extension direction perpendicular to the trench arrangement direction, and a connecting portion 43 that connects the two extended portions 41. In Figure 2A, the trench extension direction is the Y-axis direction. The trench extension direction may be the same as or different from the extension direction of the transistor section 70 and the diode section 80. In this example, the trench extension direction is the same as the extension direction of the transistor section 70 and the diode section 80.

[0088] Preferably, at least a portion of the connecting portion 43 is provided in a curved shape when viewed from above. By connecting the ends of the two extended portions 41 in the Y-axis direction with the connecting portion 43, electric field concentration at the ends of the extended portions 41 can be mitigated.

[0089] The dummy trench section 30 in this example may have two extending portions 31 (the trench portion which is linear along the extending direction) that extend along the trench extending direction perpendicular to the trench arrangement direction, and a connecting portion 33 that connects the two extending portions 31. The dummy trench section 30 may have a linear shape that extends in a predetermined trench extending direction. The semiconductor device 100 may include both a linear dummy trench section 30 without a connecting portion 33 and a dummy trench section 30 with a connecting portion 33. The dummy trench section 30 may be provided in the transistor section 70 between each extending portion 41 of the gate trench section 40. Between each extending portion 41, one dummy trench section 30 may be provided, or multiple dummy trench sections 30 may be provided.

[0090] The longitudinal direction of the trench portion may be the direction in which the extended portion 41 of the gate trench portion 40 or the extended portion 31 of the dummy trench portion 30 extends. The longitudinal direction of the trench portion may coincide with the extension direction of the transistor portion 70 and the diode portion 80. In this example, the longitudinal direction of the trench portion is the Y-axis direction.

[0091] The short direction of the trench section may be the trench arrangement direction in which multiple extended portions 41 of the gate trench section 40 or extended portions 31 of the dummy trench section 30 are arranged. The short direction of the trench section may coincide with the arrangement direction of the transistor section 70 and the diode section 80. The short direction of the trench section may also be perpendicular to the longitudinal direction of the trench section. In this example, the short direction of the trench section is the X-axis direction.

[0092] At the connection portion 43 at the tip of the gate trench portion 40, the gate conductive portion within the gate trench portion 40 and the gate runner portion 51 are connected. The gate trench portion 40 may be provided so as to protrude toward the gate runner portion 51 side from the dummy trench portion 30 in the trench extension direction (Y-axis direction). This protruding portion of the gate trench portion 40 is connected to the gate runner portion 51.

[0093] The lower end of the well region 17 may be deeper than the lower ends of the gate trench portion 40 and the dummy trench portion 30. The Y-axis ends of the gate trench portion 40 and the dummy trench portion 30 are located in the well region 17 when viewed from above. In other words, at the Y-axis end of each trench portion, the bottom in the depth direction of each trench portion is covered by the well region 17. This makes it possible to mitigate electric field concentration at the bottom of each trench portion.

[0094] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to the region within the semiconductor substrate 10 that is sandwiched between two adjacent trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench portion in the trench extension direction (Y-axis direction).

[0095] The main region 75 is the region in the transistor section 70 where the main current flows in the depth direction. The main region 75 includes an emitter region 12 and a contact region 15. The area of ​​the main region 75 may be larger than the area of ​​the boundary region 90.

[0096] The boundary region 90 is provided in the transistor portion 70 closer to the diode portion 80 than to the main portion 75. The boundary region 90 may have a dummy trench portion 30 and be a region on the back side of the semiconductor substrate 10 where the collector region 22 is provided. Both ends of the mesa portion of the boundary region 90 in the trench arrangement direction may be in contact with the dummy trench portion 30. All of the trench portions of the boundary region 90 may be dummy trench portions 30. The boundary region 90 may include a gate trench portion 40. In this example, the boundary region 90 does not have an emitter region 12 of the first conductivity type in the mesa portion on the front surface 21 side of the semiconductor substrate 10. The boundary region 90 may have a base region 14 on the front surface 21. The boundary region 90 may have an emitter region 12 or a contact region 15 on the front surface 21. In this example, the boundary region 90 has a base region 14 and a contact region 15 on the front surface 21.

[0097] Mesa portion 71 is a mesa portion provided in the main region 75 of the transistor portion 70. Mesa portion 81 is a mesa portion provided in the diode portion 80. Mesa portion 91 is a mesa portion provided in the boundary region 90. In this specification, when simply referred to as a mesa portion, it may refer to mesa portion 71, mesa portion 81, or mesa portion 91, respectively. The extended portion of each trench portion may be considered as a single trench portion. The region sandwiched between two extended portions may be considered as a mesa portion.

[0098] Each mesa portion may be provided with a base region 14. Of the base regions 14 exposed on the front surface 21 of the semiconductor substrate 10 in the mesa portion, the region closest to the gate metal layer 50 is defined as base region 14-e. In Figure 2A, the base region 14-e is shown located at one end of each mesa portion in the trench extension direction, but a base region 14-e may also be located at the other end of each mesa portion. In each mesa portion, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 may be provided in the region sandwiched between the base regions 14-e in a top view. In this example, the emitter region 12 is N+ type and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 may be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0099] The mesa portion 71 of the transistor portion 70 has an emitter region 12 exposed on the front surface 21 of the semiconductor substrate 10. The emitter region 12 is provided in contact with the gate trench portion 40. The mesa portion 71 may also have a contact region 15 exposed on the front surface 21 of the semiconductor substrate 10.

[0100] The emitter region 12 is located on the front surface 21 of the semiconductor substrate 10 and is a first-conductivity region with a higher doping concentration than the drift region 18. The drift region 18 will be described later. The doping concentration of the emitter region 12 is 1E21cm². －３ Above 1E22cm －３ The following is also possible: In this example, the emitter region 12 extends in the trench arrangement direction from one trench portion in contact with the mesa portion 71 to the other opposing trench portion.

[0101] An anode region 19 is provided in the mesa portion 81 of the diode portion 80. Base regions 14-e may be provided at both ends of the anode region 19 in the trench extension direction. An emitter region 12 is not provided on the front surface 21 of the mesa portion 81, but an emitter region 12 may be provided. A contact region 15 may be provided on the front surface 21 of the mesa portion 81.

[0102] The anode region 19 is a second conductivity type region provided in the mesa between the multiple trench sections. In this example, the anode region 19 is provided in the diode section 80, but it may be provided in the boundary region 90, or in both the diode section 80 and the boundary region 90. In this example, the anode region 19 is P-type, but is not limited to this.

[0103] A contact hole 54 is provided above each mesa portion. The contact hole 54 is located in the region sandwiched between the base region 14-e along the trench extension direction. In this example, the contact hole 54 is provided above the emitter region 12, the contact region 15, the base region 14, and the anode region 19. The contact hole 54 does not need to be provided in the region corresponding to the base region 14-e and the well region 17. The contact hole 54 may be located in the center of the mesa portion in the trench arrangement direction (X-axis direction).

[0104] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. The doping concentration of the cathode region 82 is higher than that of the drift region 18. In the region on the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the back surface 23 of the semiconductor substrate 10 and the buffer region 20, which will be described later. The back surface 23 will be described later.

[0105] In Figure 2A, the positions of the collector region 22 and cathode region 82, which are located on the back side of the semiconductor substrate 10, are shown when projected onto the front side 21. In Figure 2A, the boundary 78 between the cathode region 82 and the collector region 22 is shown by a dashed line.

[0106] The cathode region 82 is positioned away from the well region 17 in the trench extension direction. This ensures a distance between the cathode region 82 and the P-type region (well region 17), which has a relatively high doping concentration and is formed to a deep position, thereby improving pressure resistance and suppressing the injection of holes from the well region 17. In this example, the end of the cathode region 82 in the trench extension direction is positioned further from the well region 17 than the end of the contact hole 54 in the trench extension direction. In other examples, the end of the cathode region 82 in the trench extension direction may be positioned between the well region 17 and the contact hole 54.

[0107] A base region 14 is provided in the mesa portion 91 of the boundary region 90. The boundary region 90 may have multiple mesa portions 91. Contact regions 15 may be provided in the mesa portions 91. In this example, the mesa portion 91 has a contact region 15 around the end of the contact hole 54 in the trench extension direction.

[0108] The trench contact portion 58 is provided in the mesa portion between two adjacent trench portions among a plurality of trench portions. The trench contact portion 58 extends from the front surface 21 of the semiconductor substrate 10 in the depth direction of the semiconductor substrate 10. The trench contact portion 58 may be provided extending from the upper end of the interlayer insulating film 38 to the inside of the semiconductor substrate 10. In this example, the trench contact portion 58 is provided in the contact hole 54. By providing the trench contact portion 58, the semiconductor device 100 in this example can reduce the base resistance during turn-off and improve the latch-up tolerance.

[0109] The second conductivity region 26 is a second conductivity region located above the drift region 18 in the active portion 160. The base region 14 and the anode region 19 are examples of the second conductivity region 26. That is, the second conductivity region 26 may be the base region 14 of the transistor portion 70 or the anode region 19 of the diode portion 80. The second conductivity region 26 may be formed simultaneously with the first channel stop region 61, which will be described later, in the same process.

[0110] Figure 2B shows an example of an XZ cross-section including the b-b' cross-section in Figure 2A. The XZ cross-section including the b-b' cross-section is the XZ plane that passes through the emitter region 12 in the main region 75. The semiconductor device 100 in this example has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the XZ cross-section including the b-b' cross-section. The emitter electrode 52 is provided above the semiconductor substrate 10 and the interlayer insulating film 38.

[0111] The drift region 18 is a region of a first conductivity type provided on the semiconductor substrate 10. In this example, the drift region 18 is N-type. The drift region 18 may be a region remaining on the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0112] The buffer region 20 is a first conductivity type region located on the back surface 23 side of the semiconductor substrate 10, closer to the back surface 23 than the drift region 18. In this example, the buffer region 20 is located closer to the back surface 23 of the semiconductor substrate 10 than to the center of the semiconductor substrate 10 in the depth direction. In this example, the buffer region 20 is N-type as an example. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0113] The collector region 22 and the cathode region 82 are provided on the back surface 23 of the semiconductor substrate 10. The collector region 22 is provided below the buffer region 20 in the transistor section 70. The cathode region 82 is provided below the buffer region 20 in the diode section 80. The boundary 78 between the collector region 22 and the cathode region 82 may be the boundary between the transistor section 70 and the diode section 80.

[0114] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. At least a part of the region of the collector electrode 24 may be formed of a metal such as aluminum (Al), or a metal alloy such as aluminum - silicon alloy (AlSi), aluminum - silicon - copper alloy (AlSiCu).

[0115] The base region 14 is a region of the second conductivity type provided above the drift region 18 in the mesa portion 71. The base region 14 may also be provided in the mesa portion 91. The base region 14 is provided in contact with the gate trench portion 40. The base region 14 may be provided in contact with the dummy trench portion 30.

[0116] The accumulation region 16 is provided above the drift region 18. That is, the accumulation region 16 is provided on the front surface 21 side of the semiconductor substrate 10 rather than the drift region 18. The accumulation region 16 is a region of the first conductivity type with a higher doping concentration than the drift region 18. The accumulation region 16 in this example is N + type as an example. The doping concentration of the accumulation region 16 is 1E16 cm －３ or more and 1E18 cm －３ or less. The depth position of the lower end of the accumulation region 16 may be 2.0 μm or more and 8.0 μm or less. The accumulation region 16 is provided in the mesa portion 71. The accumulation region 16 may be provided in the mesa portions 81 and 91.

[0117] Also, the accumulation region 16 is provided in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than the doping concentration of the drift region 18. By providing the accumulation region 16, the carrier injection promotion effect (IE effect) can be enhanced and the on - voltage of the transistor portion 70 can be reduced.

[0118] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the front surface 21. Each trench extends from the front surface 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, storage region 16, and anode region 19 is provided, each trench penetrates these regions as well and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to those manufactured in the order of forming the doping region before forming the trenches. Even when doping regions are formed between trenches after the trenches have been formed, the trenches are still considered to penetrate the doping region.

[0119] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front surface 21 by an interlayer insulating film 38.

[0120] The gate conductive portion 44 includes a region facing the base region 14 across the gate insulating film 42. When a predetermined voltage is applied to the gate conductive portion 44, an electron channel is formed by an inversion layer on the surface layer of the interface in contact with the gate trench within the base region 14.

[0121] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 may be covered with an interlayer insulating film 38 on the front surface 21.

[0122] The interlayer insulating film 38 is provided above the semiconductor substrate 10. In this example, the interlayer insulating film 38 is provided on the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or more contact holes 54 for electrically connecting the emitter electrode 52 and the semiconductor substrate 10. Similarly, contact holes 55 and 56 may be provided through the interlayer insulating film 38.

[0123] The front electrode portion 200 is provided above the front surface 21 of the semiconductor substrate 10. The front electrode portion 200 has an emitter electrode 52, a barrier metal portion 220, and a plug portion 230. The front electrode portion 200 may have a silicide layer 210, which will be described later. The front electrode portion 200 may have a trench contact portion 58. The front electrode portion 200 may be in ohmic contact with the plug region 13, which will be described later.

[0124] The barrier metal portion 220 is provided on the side walls and bottom surface of the contact hole 54. The barrier metal portion 220 may be provided over the entire bottom surface of the contact hole 54. The material of the barrier metal portion 220 may be titanium (Ti) and / or a titanium compound. The barrier metal portion 220 may contain Ti and may contain titanium nitride (TiN). TiN is a compound of titanium and nitrogen.

[0125] The plug portion 230 is provided inside the barrier metal portion 220 in the contact hole 54. The material of the plug portion 230 may be tungsten. The material of the plug portion 230 may be the same as the material of the emitter electrode 52. That is, the plug portion 230 may be the portion of the emitter electrode 52 that is embedded in the contact hole 54.

[0126] The semiconductor device 100 in this example does not have a lifetime control unit with a lifetime killer, but it may have a lifetime control unit. The semiconductor device 100 may have a lifetime killer region closer to the front surface 21 than to the center in the depth direction of the semiconductor substrate 10, and may also have a lifetime killer region closer to the back surface 23 than to the center in the depth direction of the semiconductor substrate 10.

[0127] The anode region 19 is a second conductivity type region located above the drift region 18. The anode region 19 is located in the mesa portion 81. The anode region 19 may be in contact with the dummy trench portion 30. In this example, the anode region 19 is located in the mesa portion 81, extending in the trench arrangement direction from one adjacent dummy trench portion 30 to the other dummy trench portion 30. The anode region 19 may be located in contact with the gate trench portion 40. The depth of the anode region 19 may be deeper than, shallower than, or equal to the depth of the base region 14 in the depth direction of the semiconductor substrate 10. In this example, the depth of the anode region 19 is the same as the depth of the base region 14.

[0128] The doping concentration in the anode region 19 may be the same as or different from the doping concentration in the base region 14. The doping concentration in the anode region 19 may be less than or greater than the doping concentration in the base region 14. The maximum value of the doping concentration in the anode region 19 may be less than, greater than, or equal to the maximum value of the doping concentration in the base region 14. In this example, the maximum value of the doping concentration in the anode region 19 is the same as the maximum value of the doping concentration in the base region 14. The integral value obtained by integrating the doping concentration in the anode region 19 along the depth direction of the semiconductor substrate 10 may be less than, greater than, or equal to the integral value obtained by integrating the doping concentration in the base region 14. In this example, the integral value of the doping concentration in the anode region 19 in the depth direction is the same as the integral value of the doping concentration in the base region 14 in the depth direction. The depth direction is the direction from the front surface 21 to the back surface 23, and in this example, it is the -Z axis direction. In this example, the anode region 19 is P-type.

[0129] The plug region 13 is located above the drift region 18 and is a second conductivity type region with a higher doping concentration than the base region 14 and the anode region 19. The plug region 13 may have a higher doping concentration than the contact region 15. In this example, the plug region 13 is of the P++ type, but is not limited to this.

[0130] The plug region 13 is provided on the semiconductor substrate 10 and may be in contact with the front electrode portion 200. In this example, the plug region 13 is provided below the trench contact portion 58. The plug region 13 may be in contact with the trench contact portion 58. In this example, the plug region 13 is in contact with the bottom surface of the trench contact portion 58. The plug region 13 may be in contact with the side surface of the trench contact portion 58. The emitter region 12 may be in contact with the side surface of the trench contact portion 58 on the front surface 21 side of the plug region 13.

[0131] The plug region 13 may be provided continuously on the bottom surface of the trench contact portion 58, extending in the direction of trench extension. The plug region 13 may be provided across the entire bottom surface of the trench contact portion 58. The plug region 13 may be provided discretely on the bottom surface of the trench contact portion 58, in the direction of trench extension. The plug region 13 may be provided in at least one of the main region 75, the diode portion 80, or the boundary region 90. In this example, the plug region 13 is provided in the main region 75, the diode portion 80, and the boundary region 90, respectively.

[0132] The plug region 13 may be in contact with the anode region 19 in the mesa portion 81. The lower end of the plug region 13 may be shallower than the lower end of the anode region 19. The plug region 13 may be in contact with the emitter region 12 and the base region 14 in the mesa portion 71. The lower end of the plug region 13 may be deeper than the lower end of the emitter region 12 and shallower than the lower end of the base region 14. The plug region 13 may be in contact with the base region 14 in the mesa portion 91.

[0133] The lower end of the trench contact portion 58 may be deeper than the lower end of the emitter region 12. The lower end of the trench contact portion 58 may be shallower than the lower end of the base region 14. The lower end of the trench contact portion 58 may be shallower than the upper end of the storage region 16. The shape of the trench contact portion 58 may be the same or different in the main region 75, the diode portion 80, and the boundary region 90.

[0134] Figure 2C shows an example of an XZ cross-section including the c-c' cross-section in Figure 2A. The XZ cross-section including the c-c' cross-section is the XZ plane that passes through the contact region 15 in the main region 75. In this example, the differences from the b-b' cross-section in Figure 2B that passes through the emitter region 12 will be explained in particular. Other points may be the same as the b-b' cross-section in Figure 2B.

[0135] The lower end of the contact region 15 may be deeper than the lower end of the emitter region 12. The contact region 15 may be in contact with the plug region 13 and the base region 14 in the mesa region 71. The contact region 15 may be in contact with the side surface of the trench contact region 58 on the front surface 21 side of the plug region 13.

[0136] The plug region 13 may be in contact with the contact region 15 and the base region 14 in the mesa portion 71. The lower end of the plug region 13 may be deeper than the lower end of the contact region 15 and shallower than the lower end of the base region 14.

[0137] The lower end of the trench contact portion 58 may be deeper than the lower end of the contact region 15. The lower end of the trench contact portion 58 may be shallower than the lower end of the base region 14. The lower end of the trench contact portion 58 may be shallower than the upper end of the accumulation region 16. The shape of the trench contact portion 58 in the XZ cross section that penetrates the contact region 15 may be the same as, for example, the shape of the trench contact portion 58 in the XZ cross section that penetrates the emitter region 12 in Figure 2B.

[0138] The mesa portion 81 may be the same as the mesa portion 81 in the b-b' section of Figure 2B. The mesa portion 91 may be the same as the mesa portion 91 in the b-b' section of Figure 2B.

[0139] Figure 2D is an enlarged view of the XZ cross-section passing through the mesa portion 71. This figure illustrates the mesa portion 71 sandwiched between two adjacent dummy trench portions 30. The front electrode portion 200 has a silicide layer 210, a barrier metal portion 220, a plug portion 230, and an emitter electrode 52.

[0140] The silicide layer 210 is in contact with the semiconductor substrate 10. If the semiconductor substrate 10 is silicon, the silicide layer 210 may be a layer that reacts with the semiconductor substrate 10 to silicide the barrier metal portion 220. The silicide layer 210 is provided on both the bottom and side surfaces of the trench contact portion 58. In this example, the silicide layer 210 is in contact with the emitter region 12 and the plug region 13. The silicide layer 210 does not need to be provided in areas that are not in contact with the semiconductor substrate 10. In this example, the material of the silicide layer 210 is a compound of titanium (Ti) and silicon (Si). ｘ Si ｙ However, it is not limited to this. Here, x and y are numerical values ​​indicating the stoichiometry of the titanium-silicon compound. In this specification, the material of the silicide layer 210 may be simply referred to as TiSi.

[0141] The barrier metal portion 220 is in contact with the silicide layer 210. The barrier metal portion 220 may contain a material that reacts with the Si of the semiconductor substrate 10 to form a silicide. The barrier metal portion 220 may contain Ti. In this example, the barrier metal portion 220 has a first barrier metal layer 221 and a second barrier metal layer 222.

[0142] The first barrier metal layer 221 is provided on the side surface of the trench contact portion 58. The first barrier metal layer 221 may be in contact with the silicide layer 210 provided on the side surface and bottom surface of the trench contact portion 58. A portion of the first barrier metal layer 221 may be in contact with the interlayer insulating film 38 on the side surface of the trench contact portion 58. In this example, the material of the first barrier metal layer 221 is Ti.

[0143] The second barrier metal layer 222 is provided inside the first barrier metal layer 221 in the trench contact portion 58. The second barrier metal layer 222 is provided in close proximity to the bottom and side surfaces of the trench contact portion 58. The second barrier metal layer 222 may be in contact with the first barrier metal layer 221. In this example, the material of the second barrier metal layer 222 is TiN, a compound of titanium (Ti) and nitrogen (N). Note that the stoichiometry of the titanium-nitrogen compound is omitted.

[0144] The plug portion 230 is provided inside the barrier metal portion 220 in the trench contact portion 58. In this example, the plug portion 230 is provided inside the second barrier metal layer 222 in the trench contact portion 58. In this example, the plug portion 230 is in contact with the second barrier metal layer 222. The plug portion 230 may be formed using a method and material that can fill the inside of the contact hole 54. In this example, the material of the plug portion 230 is tungsten (W).

[0145] Thus, the semiconductor device 100 may have a laminated structure comprising a semiconductor substrate 10, a silicide layer 210, a first barrier metal layer 221, a second barrier metal layer 222, and a plug portion 230. In one example, the semiconductor device 100 has a laminated structure comprising a Si substrate, a TiSi layer, a Ti layer, a TiN layer, and a W layer.

[0146] As explained in Figure 2B, the emitter region 12 may be in contact with the side surface of the trench contact portion 58 on the front surface 21 side of the plug region 13. That is, the emitter region 12 may be in contact with the silicide layer 210 on the front surface 21 side of the plug region 13. This allows the emitter region 12 to be electrically connected to the emitter electrode 52 and prevents latch-up of the transistor portion 70.

[0147] The depth D58 represents the distance from the front surface 21 to the lower end of the trench contact portion 58 in the depth direction of the semiconductor substrate 10. Increasing the depth D58 makes it easier to reduce the reverse recovery loss Err by suppressing the amount of holes injected from the transistor portion 70 to the diode portion 80.

[0148] The mesa width Wm is the width of the mesa section in the direction of trench arrangement. In this example, the mesa width Wm represents the mesa width of mesa section 71. The trench width Wt is the width of any trench section in the direction of trench arrangement among the multiple trench sections. In this example, the trench width Wt represents the trench width of dummy trench section 30. In this example, the mesa width Wm is greater than the trench width Wt, but may be less than the trench width Wt, or may be the same as the trench width Wt.

[0149] Figure 3A shows an example of the XZ cross-section including the a-a' cross-section in Figure 1. This figure shows an example of the configuration of the edge termination structure 170. The edge termination structure 170 in this example has an edge pressure-resistant structure and a channel stop structure.

[0150] The edge breakdown structure promotes the expansion of the depletion layer extending from the active portion 160, thereby improving the breakdown voltage of the semiconductor device 100. The edge breakdown structure may have a guard ring structure. The edge breakdown structure in this example has a guard ring portion 176 and an edge metal layer 178. The edge breakdown structure will be described later.

[0151] The channel stop structure suppresses the expansion of the depletion layer extending from the active portion 160 at the edge, thereby suppressing reach-through current. The channel stop structure may have at least one of a first channel stop region 61, a second channel stop region 62, or a third channel stop region 63. In this example, the channel stop structure has a first channel stop region 61, a second channel stop region 62, and a third channel stop region 63.

[0152] The first channel stop region 61 is a region of the second conductivity type located above the drift region 18. The doping concentration of the first channel stop region 61 may be the same as the doping concentration of the second conductivity type region 26. The doping concentration of the first channel stop region 61 may be the same as the doping concentration of the base region 14, or it may be the same as the doping concentration of the anode region 19. The first channel stop region 61 may be formed simultaneously with the second conductivity type region 26 in the same process. The doping concentrations being the same means that, as mentioned above, if there are errors due to manufacturing variations, such as those mentioned above, such errors may be within 10%. Alternatively, the doping concentrations being the same means, as an example, that the ratio of the maximum doping concentration of the first channel stop region 61 to the maximum doping concentration of the second conductivity type region 26 may be 0.8 or more, 0.9 or more, 0.95 or more, 1.2 or less, 1.1 or less, or 1.05 or less.

[0153] The depth position Z61 at the lower end of the first channel stop region 61 may be the same as the depth position at the lower end of the second conductive region 26. In other words, the depth position Z61 at the lower end of the first channel stop region 61 may be the same as the depth position at the lower end of the base region 14, or it may be the same as the depth position at the lower end of the anode region 19. For example, if the depth positions are the same, the ratio of the depth position at the lower end of the base region 14 to the depth position Z61 at the lower end of the first channel stop region 61 may be 0.8 or more, 0.9 or more, 0.95 or more, 1.2 or less, 1.1 or less, or 1.05 or less.

[0154] The first channel stop region 61 may be provided on the front surface 21 of the semiconductor substrate 10. In other words, the first channel stop region 61 may be exposed on the front surface 21 of the semiconductor substrate 10. However, above the first channel stop region 61, a region of a first conductivity type may be provided, or a region of a second conductivity type with a different doping concentration from the first channel stop region 61 may be provided.

[0155] In this case, if a region formed with an N-type dopant such as arsenic (As) is exposed on the surface 21, the insulating film may be prone to peeling. In this example, the semiconductor device 100 makes it easier to prevent peeling by exposing the first channel stop region 61 of the second conductivity type.

[0156] The first channel stop region 61 may be provided on the side surface of the semiconductor substrate 10. In other words, the first channel stop region 61 may be exposed on the side surface of the semiconductor substrate 10. The side surface of the semiconductor substrate 10 may be the edge 102 of the semiconductor substrate 10.

[0157] The second channel stop region 62 is a first-conductivity region located above the drift region 18. The second channel stop region 62 is located below the first channel stop region 61. The upper surface of the second channel stop region 62 may be in contact with the lower surface of the first channel stop region 61. The doping concentration of the second channel stop region 62 may be higher than the doping concentration of the drift region 18. The doping concentration of the second channel stop region 62 is 1E16cm². －３Above, 1E18cm －３ The following is possible: The second channel stop region 62 may be exposed on the side surface of the semiconductor substrate 10. The side surface of the semiconductor substrate 10 may be the edge 102 of the semiconductor substrate 10.

[0158] The dopant in the second channel stop region 62 may be the same as or different from the dopant in the storage region 16. When the second channel stop region 62 is formed simultaneously with the storage region 16 in the same process, the dopant in the second channel stop region 62 will be the same as the dopant in the storage region 16. The dopant in the second channel stop region 62 may be phosphorus (P). In this case, the dopant in the storage region 16 may also be phosphorus (P). By avoiding dopants such as arsenic (As) used in the emitter region 12 as the dopant in the second channel stop region 62, concerns about delamination of the insulating film can be reduced.

[0159] The doping concentration in the accumulation region 16 may be the same as the doping concentration in the second channel stop region 62. The dose amount during ion implantation in the accumulation region 16 may be the same as the dose amount during ion implantation in the second channel stop region 62. The magnitude of the peak doping concentration in the accumulation region 16 may be the same as the magnitude of the peak doping concentration in the second channel stop region 62. For example, "the dose amounts are the same" means that the ratio of the dose amount during ion implantation in the accumulation region 16 to the dose amount during ion implantation in the second channel stop region 62 may be 0.8 or greater, 0.9 or greater, 0.95 or greater, 1.2 or less, 1.1 or less, or 1.05 or less.

[0160] The maximum doping concentration of the second conductivity type dopant in the first channel stop region 61 may be the same as or different from the maximum doping concentration of the first conductivity type dopant in the second channel stop region 62. In this example, the maximum doping concentration of the second conductivity type dopant in the first channel stop region 61 is smaller than the maximum doping concentration of the first conductivity type dopant in the second channel stop region 62.

[0161] The thickness D62 of the second channel stop region 62 is the thickness of the second channel stop region 62 in the depth direction of the semiconductor substrate 10. The thickness D62 of the second channel stop region 62 may be the distance from the front surface 21 to the lower end of the second channel stop region 62. The thickness D62 of the second channel stop region 62 may be greater than the thickness D61 of the first channel stop region 61.

[0162] The third channel stop region 63 is a region of the first conductivity type with a higher doping concentration than the drift region 18. The third channel stop region 63 is located above the drift region 18. The third channel stop region 63 may be located on the front surface 21.

[0163] The dopant in the third channel stop region 63 may be the same as or different from the dopant in the storage region 16. The dopant in the third channel stop region 63 may be the same as or different from the dopant in the second channel stop region 62. Ion implantation of the third channel stop region 63 may be performed simultaneously with ion implantation of the storage region 16 in the same process. In this case, the dopant in the third channel stop region 63 will be the same as the dopant in the storage region 16. The dopant in the third channel stop region 63 may be phosphorus (P). In this case, the dopant in the storage region 16 may also be phosphorus (P). By avoiding dopants such as arsenic (As) used in the emitter region 12 as the dopant in the third channel stop region 63, concerns about delamination of the insulating film can be reduced.

[0164] The magnitude of the doping concentration peak in the third channel stop region 63 may be the same as the magnitude of the doping concentration peak in the accumulation region 16. The magnitude of the doping concentration peak in the third channel stop region 63 may be the same as the magnitude of the doping concentration peak in the second channel stop region 62.

[0165] The thickness D63 of the third channel stop region 63 may be smaller than the thickness D62 of the second channel stop region 62. The thickness D63 of the third channel stop region 63 may be smaller than the thickness D62 of the second channel stop region 62 by ion implantation through the base insulating film 74. In other words, the upper part of the third channel stop region 63 may be covered with the base insulating film 74. The thickness D63 of the third channel stop region 63 may be 1.0 μm or more and 5.0 μm or less in the depth direction of the semiconductor substrate 10. Here, the base insulating film 74 may be an insulating film formed by thermal oxidation of the semiconductor substrate 10, such as a thermal oxide film or a LOCOS film, or it may be an insulating film formed by chemical vapor deposition (CVD) such as HTO, LTO, BPSG, or PSG. The base insulating film 74 may be in contact with the front surface 21 of the semiconductor substrate 10. In this example, the base insulating film 74 is a thermal oxide film formed by thermal oxidation.

[0166] The third channel stop region 63 is connected to the second channel stop region 62. The connection between the second channel stop region 62 and the third channel stop region 63 may mean that the second channel stop region 62 and the third channel stop region 63 are in direct contact. The second channel stop region 62 and the third channel stop region 63 may be formed simultaneously by ion implantation using the same ion implantation process.

[0167] The third channel stop region 63 is provided closer to the active portion 160 than the first channel stop region 61. That is, the third channel stop region 63 is provided further away from the edge 102 of the semiconductor substrate 10 than the first channel stop region 61. In this example, the third channel stop region 63 is provided between the first channel stop region 61 and the guard ring portion 176. By providing the third channel stop region 63 closer to the active portion 160 than the first channel stop region 61, it becomes easier to suppress the expansion of the depletion layer.

[0168] The lower end of the third channel stop region 63 may be shallower than the lower end of the second channel stop region 62 in the depth direction of the semiconductor substrate 10. In this example, the third channel stop region 63 extends from the second channel stop region 62 in the direction in which the active portion 160 is provided. By providing the third channel stop region 63 extending from the second channel stop region 62 in the direction of the active portion 160, it becomes easier to suppress the depletion layer.

[0169] The first conductive channel stop portion 260 may cover the lower end and side of the active portion 160 side of the first channel stop region 61. In this example, the second channel stop region 62 covers the lower end and side of the active portion 160 side of the first channel stop region 61. As a result, the channel stop region of the edge termination structure 170 may function substantially as the first conductive channel stop region.

[0170] Distance L62 is the distance from the edge of the base insulating film 74 on the semiconductor substrate 10 side to the edge of the second channel stop region 62 on the active portion 160 side. The size of distance L62 is determined by the conditions during ion implantation of the second channel stop region 62 and the taper angle of the edge of the base insulating film 74. Distance L62 may be between 1 μm and 20 μm. In one example, distance L62 is 5 μm.

[0171] Distance L1 is the distance between the end of the first channel stop region 61 on the active portion 160 side and the end of the third channel stop region 63 on the active portion 160 side. Thickness T62 is the difference between the depth position of the lower end of the first channel stop region 61 and the depth position of the lower end of the second channel stop region 62. That is, thickness T62 indicates the thickness of the second channel stop region 62 below the first channel stop region 61. Thickness T62 may be the same as or different from the thickness of the storage region 16 in the depth direction of the semiconductor substrate 10. Distance L1 may be greater than thickness T62.

[0172] The thickness D61 of the first channel stop region 61 may be the same as or different from the thickness T62 of the second channel stop region 62 located below the first channel stop region 61. The thickness D61 of the first channel stop region 61 may be smaller than the thickness T62 of the second channel stop region 62 located below the first channel stop region 61. Alternatively, the thickness D61 of the first channel stop region 61 may be greater than or equal to the thickness T62 of the second channel stop region 62 located below the first channel stop region 61.

[0173] The base insulating film 74 is provided above the semiconductor substrate 10. The base insulating film 74 may be provided above the first conductivity type channel stop portion 260. In this example, the base insulating film 74 is provided above the third channel stop region 63. The base insulating film 74 may be patterned after being formed over the entire surface of the front surface 21 of the semiconductor substrate 10. In this example, the base insulating film 74 is formed by thermal oxidation of the front surface 21 of the semiconductor substrate 10, but is not limited to this.

[0174] The thickness of the base insulating film 74 may be greater than the thickness of the interlayer insulating film 38. The thickness of the base insulating film 74 may be greater than the thickness of the dummy insulating film 32 and greater than the thickness of the gate insulating film 42. The thickness of the base insulating film 74 may be 100 nm or more and 3 μm or less. In one example, the thickness of the base insulating film 74 is 1500 nm. If the thickness of the base insulating film 74 is too thick, it may not be possible to form the third channel stop region 63 by ion implantation through the base insulating film 74. The thickness of the insulating film above the first channel stop region 61 may be different from the thickness of the insulating film above the third channel stop region 63. The thickness of the insulating film above the first channel stop region 61 may be thinner than the thickness of the insulating film above the third channel stop region 63. In this example, the insulating film above the first channel stop region 61 may be the interlayer insulating film 38. The insulating film above the first channel stop region 61 does not need to include the protective layer 180 formed of polyimide or the like, which will be described later. The insulating film above the third channel stop region 63 may be the interlayer insulating film 38 and the base insulating film 74. The insulating film above the third channel stop region 63 does not need to include the protective layer 180 formed of polyimide or the like, which will be described later.

[0175] Here, when ions are implanted through the base insulating film 74, whether or not the dopant reaches the semiconductor substrate 10 depends on the ion implantation conditions. Whether or not the dopant reaches the semiconductor substrate 10 depends on the type of dopant and conditions such as the acceleration energy during ion implantation. Arsenic (As), which is an N-type dopant, is less likely to penetrate the base insulating film 74 than phosphorus (P), which is also an N-type dopant. When boron (B), which is a P-type dopant, is ion-implanted through the base insulating film 74, a P-type region may not be formed below the base insulating film 74.

[0176] The stopper metal layer 172 is provided above the semiconductor substrate 10 and is connected to the first channel stop region 61. The material of the stopper metal layer 172 may be the same as the material of the gate metal layer 50 and the emitter electrode 52. The potential of the stopper metal layer 172 may be floating. That is, the stopper metal layer 172 does not need to be set to the emitter potential, collector potential, and gate potential. The stopper metal layer 172 may be formed simultaneously in the same process as the gate metal layer 50 and the emitter electrode 52. In this example, the stopper metal layer 172 is connected to the first channel stop region 61 via a contact portion 173 provided in the interlayer insulating film 38.

[0177] The contact portion 173 connects the stopper metal layer 172 and the first channel stop region 61. The contact portion 173 is provided in the interlayer insulating film 38. The contact portion 173 may be made of the same material as the stopper metal layer 172. The contact portion 173 may have the same material as the trench contact portion 58. That is, the contact portion 173 may have a silicide layer 210, a barrier metal portion 220, and a plug portion 230.

[0178] The end of the stopper metal layer 172 on the active portion 160 side may be provided closer to the active portion 160 than the end of the third channel stop region 63 on the active portion 160 side. In other words, the stopper metal layer 172 may be provided extending beyond the third channel stop region 63 towards the active portion 160. By providing the stopper metal layer 172 on the active portion 160 side, it becomes easier to suppress the expansion of the depletion layer. The third channel stop region 63 may be provided below the stopper metal layer 172.

[0179] The edge termination structure 170 may have a plurality of guard ring portions 176 located inside the semiconductor substrate 10 beyond the third channel stop region 63 when viewed from above. The plurality of guard ring portions 176 improve the withstand voltage of the edge termination structure 170.

[0180] The guard ring portion 176 is a second conductivity type region provided on the front surface 21 of the semiconductor substrate 10. The doping concentration of the guard ring portion 176 may be greater than the doping concentrations of the first channel stop region 61 and the second conductivity type region 26. The doping concentration of the guard ring portion 176 may be the same as or different from the doping concentration of the well region 17.

[0181] The thickness D176 of the guard ring portion 176 may be thicker than the thickness D61 of the first channel stop region 61, thicker than the thickness D62 of the second channel stop region 62, and thicker than the thickness D63 of the third channel stop region 63. The thickness D176 of the guard ring portion 176 may be 10 μm or more and 100 μm or less, and 20 μm or more and 50 μm or less in the depth direction of the semiconductor substrate 10.

[0182] The edge metal layer 178 is provided above the semiconductor substrate 10. The edge metal layer 178 may be connected to the guard ring portion 176. The material of the edge metal layer 178 may be the same as the material of the gate metal layer 50 and the emitter electrode 52. The potential of the edge metal layer 178 may be floating. That is, the edge metal layer 178 does not need to be set to the emitter potential, collector potential, and gate potential.

[0183] The contact portion 175 connects the edge metal layer 178 and the guard ring portion 176. The contact portion 175 is provided in the interlayer insulating film 38. The contact portion 175 may be made of the same material as the edge metal layer 178. The contact portion 175 may have the same material as the trench contact portion 58. That is, the contact portion 175 may have a silicide layer 210, a barrier metal portion 220, and a plug portion 230.

[0184] The second channel stop region 62 may have one doping concentration peak or multiple peaks in the depth direction of the semiconductor substrate 10. The number of doping concentration peaks in the second channel stop region 62 may be the same as or different from the number of doping concentration peaks in the accumulation region 16. When the second channel stop region 62 is formed simultaneously with the accumulation region 16 in the same process, the number of doping concentration peaks in the second channel stop region 62 may be the same as the number of doping concentration peaks in the accumulation region 16.

[0185] The third channel stop region 63 may have one doping concentration peak or multiple peaks in the depth direction of the semiconductor substrate 10. The number of doping concentration peaks in the third channel stop region 63 may be the same as or different from the number of doping concentration peaks in the accumulation region 16 and the second channel stop region 62. When the third channel stop region 63 is formed simultaneously with the accumulation region 16 and the second channel stop region 62 in the same process, the number of doping concentration peaks in the third channel stop region 63 may be the same as the number of doping concentration peaks in the accumulation region 16 and the second channel stop region 62.

[0186] Distance α is the distance from the edge side of the semiconductor substrate 10 of the base insulating film 74 to the active portion 160 side of the third channel stop region 63. Distance β is the distance from the third channel stop region 63 to the outermost guard ring portion 176. Distance α may be the same as or different from distance β. Distance α may be smaller than or larger than distance β. Distances α and β may satisfy 0 < α / β ≤ 10. Also, distances α and β may satisfy 0.001 ≤ α / β ≤ 10. Distance β may be 10 μm or more and 100 μm or less.

[0187] The semiconductor device 100 in this example has a first conductivity type channel stop portion 260, which suppresses the expansion of the depletion layer in the direction perpendicular to the depth direction of the semiconductor substrate 10. The semiconductor device 100 in this example can reduce the inactive region by narrowing the area required for the edge termination structure portion 170. As a result, the chip area of ​​the semiconductor substrate 10 may be reduced, or the area of ​​the active portion 160 on the chip may be increased. In addition, the negative charge resistance is improved by using the first conductivity type channel stop portion 260.

[0188] Figure 3B is a flowchart showing a method for manufacturing the semiconductor device 100 shown in Figure 3A. The flowchart in this example is just one example of a method for manufacturing the semiconductor device 100 shown in Figure 3A, and the method for manufacturing the semiconductor device 100 shown in Figure 3A is not limited to this.

[0189] In step S100, a semiconductor substrate 10 having a drift region 18 is prepared. The drift region 18 may be a region of the semiconductor substrate 10 that remains without ion implantation. In other words, the drift region 18 may be a region of the semiconductor substrate 10 that has not been ion implanted after it has been cut out.

[0190] In step S102, a base insulating film 74 is formed on top of the semiconductor substrate 10 and then patterned. The base insulating film 74 may be formed by thermal oxidation of the semiconductor substrate 10.

[0191] In step S104, a second conductivity type region 26 of the second conductivity type is formed above the drift region 18. The second conductivity type region 26 is formed in the active portion 160.

[0192] In step S106, a first channel stop region 61 of the second conductivity type is formed above the drift region 18. The first channel stop region 61 is formed in the edge termination structure 170. The first channel stop region 61 may be formed using the base insulating film 74 as a mask. The first channel stop region 61 may be formed in a region not covered by the base insulating film 74. In the ion implantation process for the first channel stop region 61, ion implantation may be performed under conditions such that the first channel stop region 61 is not formed through the base insulating film 74.

[0193] Steps S104 and S106 may be performed simultaneously. That is, the first channel stop region 61 may be formed simultaneously with the second conductivity type region 26 in the same process.

[0194] In step S108, a second channel stop region 62 and a third channel stop region 63 are formed as the first conductivity type channel stop portion 260. Ion implantation of the first conductivity type channel stop portion 260 may be performed after ion implantation of the first channel stop region 61, or it may be performed before ion implantation of the first channel stop region 61.

[0195] The second channel stop region 62 is formed below the first channel stop region 61 and above the drift region 18. The third channel stop region 63 is formed closer to the active region 160 than the first channel stop region 61. The second channel stop region 62 and the third channel stop region 63 may be formed integrally by forming them simultaneously in the same process. The step of forming the third channel stop region 63 may include the step of implanting ions into the semiconductor substrate 10 via a base insulating film 74 provided above the semiconductor substrate 10.

[0196] In step S110, the stopper metal layer 172 and the edge metal layer 178 are formed. The stopper metal layer 172 and the edge metal layer 178 may be formed simultaneously in the same process as the gate metal layer 50 and the emitter electrode 52.

[0197] Figure 3C is a diagram illustrating the manufacturing process of the semiconductor device 100 shown in Figure 3A. Each step in this figure corresponds to each step in the flowchart of Figure 3B. In step S102, a basic insulating film 74 is formed on the semiconductor substrate 10 and patterned. Any structure, such as a guard ring portion 176, may be formed on the front surface 21 of the semiconductor substrate 10. However, the order in which the guard ring portion 176 is formed is not limited to this example.

[0198] In steps S104 and S106, the second conductivity region 26 and the first channel stop region 61 are formed. The second conductivity region 26 and the first channel stop region 61 may be formed using the base insulating film 74 as a mask. The second conductivity region 26 and the first channel stop region 61 may be formed simultaneously in the same process, or they may be formed in separate processes. The first channel stop region 61 does not need to be formed below the base insulating film 74.

[0199] In step S108, a second channel stop region 62 and a third channel stop region 63 are formed. In the step of forming the second channel stop region 62 and the third channel stop region 63, the resist 190 may be provided above the base insulating film 74. The second channel stop region 62 may be formed in an area where the base insulating film 74 and the resist 190 are not provided. The third channel stop region 63 may be formed in an area where the resist 190 is not provided but the base insulating film 74 is provided. The third channel stop region 63 does not need to be formed in an area where the resist 190 is provided. Therefore, the areas in which the second channel stop region 62 and the third channel stop region 63 are formed can be adjusted according to the pattern of the base insulating film 74 and the resist 190.

[0200] The second channel stop region 62 and the third channel stop region 63 may be formed simultaneously in the same process as the storage region 16. The emitter region 12 and the contact region 15 may be formed before the formation of the second channel stop region 62 and the third channel stop region 63, or they may be formed after the formation of the second channel stop region 62 and the third channel stop region 63. In step S108, the interlayer insulating film 38 does not need to be formed above the base insulating film 74.

[0201] In step S110, an interlayer insulating film 38 may be formed above the base insulating film 74. A stopper metal layer 172 and an edge metal layer 178 may be formed above the semiconductor substrate 10. The stopper metal layer 172 and the edge metal layer 178 may be formed simultaneously in the same process as the gate metal layer 50 and the emitter electrode 52.

[0202] In the manufacturing method of the semiconductor device 100 in this example, the second channel stop region 62 and the third channel stop region 63 are formed simultaneously in the same process as the accumulation region 16, thereby enabling the formation of an N-type channel stop region without increasing the number of steps. Furthermore, in the manufacturing method of the semiconductor device 100 in this example, even when the first channel stop region 61 is formed by irradiating the entire surface of the semiconductor substrate 10 with ion implantation of the second conductivity type region 26, the side and lower end of the active portion 160 side of the first channel stop region 61 can be covered with the first conductivity type channel stop portion 260. This eliminates the need to mask the region where the channel stop structure is formed to prevent the formation of a P-type region, and enables the formation of a channel stop structure having the first conductivity type channel stop portion 260 without increasing the number of photolithography steps.

[0203] Figure 3D shows a modified example of the XZ cross-section including the a-a' cross-section in Figure 1. In the semiconductor device 100 of this example, the positional relationship between the third channel stop region 63 and the stopper metal layer 172 differs from that of the semiconductor device 100 in Figure 3A. In this example, the differences from the semiconductor device 100 in Figure 3A will be explained in particular, and other aspects may be the same as those of the semiconductor device 100 in Figure 3A.

[0204] The third channel stop region 63 may extend further toward the active portion 160 than the stopper metal layer 172. That is, the end of the third channel stop region 63 toward the active portion 160 may be closer to the active portion 160 than the end of the stopper metal layer 172 toward the active portion 160. The third channel stop region 63 may be provided continuously from below the stopper metal layer 172, beyond the end of the stopper metal layer 172 toward the active portion 160, and extending toward the active portion 160.

[0205] Figure 4A shows an example of simulation results for semiconductor device 100 and semiconductor device 500. In this example, the degree of depletion layer expansion when a reverse bias is applied to semiconductor device 100 and semiconductor device 500 is compared. The symbol Ed in the figure indicates the edge of the depletion layer.

[0206] The semiconductor device 500 has a P-type channel stop portion 561. The P-type channel stop portion 561 is a P-type channel stop region provided at the edge of the semiconductor substrate 10. In the comparative example semiconductor device 500, when ion implantation of the base region is performed on the entire surface of the semiconductor substrate without using a resist mask, the P-type channel stop portion 561 may be formed in areas where the basic insulating film does not exist. In the comparative example semiconductor device 500, when the depletion layer reaches the P-type channel stop portion 561, a reach-through current may flow, causing a decrease in breakdown voltage.

[0207] The semiconductor device 100 has a first conductivity type channel stop portion 260. In this example, the first conductivity type channel stop portion 260 is N-type. Other structures may be the same for semiconductor device 100 and semiconductor device 500. By having the first conductivity type channel stop portion 260, semiconductor device 100 can suppress the expansion of the depletion layer at the edge more effectively than semiconductor device 500. This reduces the inactive region of semiconductor device 100. Furthermore, in this example, semiconductor device 100 can reduce the area of ​​the semiconductor substrate 10 compared to semiconductor device 500 while maintaining the area of ​​the active portion 160.

[0208] Figure 4B shows an example of the electrical characteristics of a semiconductor device. The vertical axis represents the collector current IC [A], and the horizontal axis represents the collector-emitter voltage (VCE) [V]. In this figure, the collector-emitter breakdown voltage (BVCES) at room temperature can be determined by observing the rise time of the collector current IC.

[0209] Comparative Example 1 is a semiconductor device 500 having a P-type channel stop portion 561. The area of ​​the inactive region in Comparative Example 1 may be the same as the area of ​​the inactive region in the other embodiments. In Comparative Example 1, the expansion of the depletion layer cannot be sufficiently suppressed, and reach-through current flows, resulting in a decrease in withstand voltage.

[0210] Example 1 is a semiconductor device 100 in which an N-type first conductivity channel stop portion 260 is formed by ion implanting arsenic (As) under the same conditions as the emitter region 12. Examples 2 to 5 are semiconductor devices 100 in which an N-type first conductivity channel stop portion 260 is formed by ion implanting phosphorus (P) under the same conditions as the storage region 16. Examples 2 to 5 are semiconductor devices 100 in which the protruding distance L1 is 15 μm, 18 μm, 20 μm, and 25 μm, respectively.

[0211] In Example 1, the BVCES was the largest, and as the distance L1 increased, the BVCES gradually decreased. In Comparative Example 1, leakage occurred in the region around 400V, and the BVCES was smaller than in any of the examples.

[0212] Figure 4C shows the dependence of the dose amount of the first conductivity type channel stop portion 260 on BVCES. The vertical axis shows BVCES [V] when the collector current IC is 1 μA, and the horizontal axis shows the dose amount of the first conductivity type channel stop portion 260.

[0213] As the dose of the first conductive channel stop portion 260 increases, BVCES tends to decrease. Also, as the overhang distance L1 of the first conductive channel stop portion 260 increases, the withstand voltage gradually decreases. Therefore, the overhang distance L1 and dose of the first conductive channel stop portion 260 may be adjusted taking BVCES into consideration.

[0214] Figure 5A shows a modified example of the XZ cross-section including the a-a' cross-section in Figure 1. The semiconductor device 100 in this example differs from the semiconductor device 100 in Figure 3A in that it does not have a third channel stop region 63. In this example, the differences from the semiconductor device 100 in Figure 3A will be explained in particular, and other aspects may be the same as the semiconductor device 100 in Figure 3A.

[0215] The semiconductor device 100 in this example does not have a third channel stop region 63, but it does have a first channel stop region 61 and a second channel stop region 62.

[0216] The first channel stop region 61 is provided on the front surface 21 of the edge termination structure 170. The first channel stop region 61 may be provided in an area not covered by the base insulating film 74. That is, the base insulating film 74 may function as a mask for forming the first channel stop region 61. However, a part of the first channel stop region 61 may be provided diffusely below the base insulating film 74. In this example, the first channel stop region 61 may be formed simultaneously with the second conductivity type region 26 in the same process.

[0217] The second channel stop region 62 is provided below the first channel stop region 61. The upper surface of the second channel stop region 62 may be in contact with the lower surface of the first channel stop region 61. The second channel stop region 62 may cover the lower end and side surface of the active portion 160 side of the first channel stop region 61. Even if the third channel stop region 63 is not provided, by covering the first channel stop region 61 with the second channel stop region 62, the first channel stop region 61 and the second channel stop region 62 can substantially function as a channel stop region of the first conductivity type. In this example, the second channel stop region 62 is spaced apart from the side surface of the semiconductor substrate 10, but it may be in contact with the side surface of the semiconductor substrate 10.

[0218] The thickness D61 of the first channel stop region 61 may be the same as or different from the thickness T62 of the second channel stop region 62 located below the first channel stop region 61. In this example, the thickness D61 is smaller than the thickness T62, but is not limited to this.

[0219] The base insulating film 74 may function as a mask for forming the second channel stop region 62. In this example, the base insulating film 74 has a thickness such that the third channel stop region 63 is not formed below it. This makes it possible to omit the third channel stop region 63 even when the second channel stop region 62 is formed using the base insulating film 74 as a mask.

[0220] Figure 5B is a flowchart showing the method for manufacturing the semiconductor device 100 shown in Figure 5A. Steps S200 to S206 may be the same as steps S100 to S106 in Figure 3B. Step S210 may be the same as step S110.

[0221] In step S208, the second channel stop region 62 is formed. In step S208, the area where the third channel stop region 63 is not to be formed may be covered with the base insulating film 74 and / or another mask such as a resist, so that the third channel stop region 63 is not to be formed. In this example, the second channel stop region 62 may be formed simultaneously with the storage region 16 in the same process. In the manufacturing method of this example, the second channel stop region 62 can be formed without additional steps compared to a semiconductor device 500 that does not have the second channel stop region 62.

[0222] Figure 5C is a diagram illustrating the manufacturing process of the semiconductor device 100 shown in Figure 5A. Each step in this figure corresponds to each step in the flowchart in Figure 5B. This example explains the differences between the manufacturing process steps in Figure 3C and those in Figure 5C.

[0223] In step S202, a basic insulating film 74 is formed on the semiconductor substrate 10 and patterned. The thickness of the basic insulating film 74 may be such that the third channel stop region 63 is not formed.

[0224] In steps S204 and S206, the second conductivity type region 26 and the first channel stop region 61 may be formed in the same manner as in steps S104 and S106.

[0225] In step S208, a second channel stop region 62 is formed. In the step of forming the second channel stop region 62, it is not necessary to form the resist 190 above the base insulating film 74. The second channel stop region 62 may be formed in a region where the base insulating film 74 is not provided. The second channel stop region 62 may also be provided diffusely below the base insulating film 74. The second channel stop region 62 may be selectively formed using a mask such as the resist 190. The second channel stop region 62 may be formed simultaneously with the accumulation region 16 in the same process.

[0226] In step S210, a stopper metal layer 172 and an edge metal layer 178 may be formed above the semiconductor substrate 10, similar to step S110. The stopper metal layer 172 and the edge metal layer 178 may be formed simultaneously in the same process as the gate metal layer 50 and the emitter electrode 52.

[0227] Figure 6A shows a modified example of the XZ cross-section including the a-a' cross-section in Figure 1. The semiconductor device 100 in this example differs from the semiconductor device 100 in Figure 3A in that it does not have a first channel stop region 61. In this example, the differences from the semiconductor device 100 in Figure 3A will be explained in particular, and other aspects may be the same as the semiconductor device 100 in Figure 3A.

[0228] The semiconductor device 100 in this example does not have a first channel stop region 61, but it does have a second channel stop region 62 and a third channel stop region 63. That is, the channel stop structure in this example is composed only of regions of the first conductivity type.

[0229] The second channel stop region 62 is provided on the front surface 21 of the edge termination structure 170. The base insulating film 74 does not need to be provided above the second channel stop region 62. However, the base insulating film 74 may be present above a part of the second channel stop region 62 as the second channel stop region 62 diffuses below the base insulating film 74. The depth position of the lower end of the second channel stop region 62 may be the same as the depth position of the lower end of the storage region 16.

[0230] The second channel stop region 62 is provided on the side surface of the semiconductor substrate 10. That is, in this example, the second channel stop region 62 is provided on the edge 102. This makes it easier to suppress the depletion layer that extends toward the side surface of the semiconductor substrate 10.

[0231] The dopant in the second channel stop region 62 may be phosphorus. This makes the insulating film less likely to peel off than when a region formed with an N-type dopant such as arsenic (As) is exposed on the surface 21.

[0232] The third channel stop region 63 is provided on the front surface 21 of the semiconductor substrate 10, below the base insulating film 74. In this example, the third channel stop region 63 is in contact with the side surface of the end of the second channel stop region 62 on the active portion 160 side. The third channel stop region 63 protrudes from the second channel stop region 62 in the direction from which the active portion 160 is provided. The lower end of the third channel stop region 63 may be shallower than the lower end of the second channel stop region 62 in the depth direction of the semiconductor substrate 10.

[0233] Figure 6B is a flowchart showing the manufacturing method of the semiconductor device 100 shown in Figure 6A. Steps S300 to S304 may be the same as steps S100 to S104 in Figure 3B.

[0234] In step S306, the second channel stop region 62 and the third channel stop region 63 are formed. The manufacturing method in this example does not include a step for forming the first channel stop region 61. The second channel stop region 62 may be formed simultaneously with the third channel stop region 63 in the same process. The second channel stop region 62 and the third channel stop region 63 may be formed simultaneously with the storage region 16 in the same process. The dopants of the second channel stop region 62 and the third channel stop region 63 may be the same as the dopant of the storage region 16. Step S308 may be the same as step S110.

[0235] Figure 6C is a diagram illustrating the manufacturing process of the semiconductor device 100 shown in Figure 6A. Each step in this figure corresponds to each step in the flowchart of Figure 6B. In this example, we will explain the differences from each step of the manufacturing process shown in Figure 3C. Step S302 may be the same as step S102.

[0236] In step S304, a second conductivity type region 26 (not shown) may be formed on top of the semiconductor substrate 10 with the resist 192 formed thereon. The resist 192 may be provided in a region of the edge termination structure 170 where the base insulating film 74 is not formed. This prevents the formation of the first channel stop region 61 by ion implantation of the second conductivity type region 26. In this example, the formation of the first channel stop region 61 was avoided using the resist 192, but the formation of the first channel stop region 61 may also be avoided by covering it with the base insulating film 74.

[0237] In step S306, a second channel stop region 62 and a third channel stop region 63 are formed. The second channel stop region 62 and the third channel stop region 63 may be formed according to the pattern of the base insulating film 74 and the resist 190. The second channel stop region 62 may be formed in an area not covered by the base insulating film 74. A part of the second channel stop region 62 may be covered by the base insulating film 74. The third channel stop region 63 may be formed in an area covered by the base insulating film 74 but not covered by the resist 190. Step S308 may be the same as step S110.

[0238] Figure 7A shows a modified example of the XZ cross-section including the a-a' cross-section in Figure 1. The semiconductor device 100 in this example differs from the semiconductor device 100 in Figure 6A in that it does not have a third channel stop region 63. In this example, the differences from the semiconductor device 100 in Figure 6A will be explained in particular, and other aspects may be the same as the semiconductor device 100 in Figure 6A.

[0239] The semiconductor device 100 in this example includes a second channel stop region 62, but does not include a first channel stop region 61 or a third channel stop region 63. In other words, the channel stop structure in this example consists only of regions of the first conductivity type.

[0240] The second channel stop region 62 is provided on the front surface 21 of the edge termination structure 170. The base insulating film 74 does not need to be provided above the second channel stop region 62. However, the base insulating film 74 may be present above a part of the second channel stop region 62 as the second channel stop region 62 diffuses below the base insulating film 74. The depth position of the lower end of the second channel stop region 62 may be the same as the depth position of the lower end of the storage region 16. In this example, the second channel stop region 62 is provided in contact with the side surface of the semiconductor substrate 10. The second channel stop region 62 may be connected to the stopper metal layer 172 via a contact portion 173.

[0241] The dopant in the first conductive channel stop portion 260 may be the same as the dopant in the accumulation region 16. The maximum doping concentration in the first conductive channel stop portion 260 may be the same as the maximum doping concentration in the accumulation region 16.

[0242] Distance γ is the distance from the second channel stop region 62 to the outermost guard ring portion 176. The magnitude of distance γ may be determined according to the withstand voltage of the semiconductor device 100. Distance γ may be 10 μm or more and 100 μm or less.

[0243] Figure 7B is a flowchart showing the manufacturing method of the semiconductor device 100 shown in Figure 7A. Steps S400 to S404 may be the same as steps S300 to S304 in Figure 6B.

[0244] In step S406, the second channel stop region 62 is formed. The manufacturing method in this example does not include the steps of forming the first channel stop region 61 and the third channel stop region 63. The second channel stop region 62 may be formed simultaneously with the storage region 16 in the same process. The dopant of the second channel stop region 62 may be the same as the dopant of the storage region 16. Step S408 may be the same as step S308.

[0245] Figure 7C is a diagram illustrating the manufacturing process of the semiconductor device 100 shown in Figure 7A. Steps S402 to S408 differ from steps S302 to S308 in Figure 6C in that the region where the base insulating film 74 is formed is different.

[0246] In step S402, a base insulating film 74 is formed. The base insulating film 74 may be formed while avoiding the region where dopants for forming the second channel stop region 62 are ion-implanted. The thickness of the base insulating film 74 may be such that dopants ion-implanted through the base insulating film 74 do not form the third channel stop region 63.

[0247] In step S404, a second conductivity type region 26 (not shown) may be formed on top of the semiconductor substrate 10 with the resist 192 formed thereon. The resist 192 may be provided in a region of the edge termination structure 170 where the base insulating film 74 is not formed. This prevents the formation of the first channel stop region 61 by ion implantation of the second conductivity type region 26.

[0248] In step S406, the ion-implanted dopant diffuses into the region where the base insulating film 74 is not formed, forming a second channel stop region 62. Step S408 may be the same as step S308.

[0249] Figure 8A shows an example of the edge pressure-resistant structure of the edge termination structure 170. This figure shows the edge termination structure 170 and a part of the active section 160 adjacent to the edge termination structure 170. The edge pressure-resistant structure may have a plurality of guard ring sections 176 and a plurality of edge metal layers 178.

[0250] Multiple guard ring portions 176 may be arranged to surround the active portion 160 when viewed from above. The edge breakdown structure in this example includes five guard ring portions 176, but the number of guard ring portions 176 is not limited thereto. The edge breakdown structure may have the function of extending the depletion layer extending from the active portion 160 to the outside of the semiconductor substrate 10. This can alleviate electric field concentration in the semiconductor substrate 10 and suppress a decrease in breakdown voltage of the semiconductor device 100.

[0251] Multiple guard ring portions 176 are electrically insulated from each other by an interlayer insulating film 38. The depth position of the lower end of the guard ring portion 176 may be the same as the depth position of the lower end of the well region 17 and the outer peripheral well region 165. The depth position of the lower end of the guard ring portion 176 may be deeper than the depth position of the lower end of the gate trench portion 40 and the dummy trench portion 30.

[0252] Multiple edge metal layers 178 may be arranged corresponding to multiple guard ring portions 176. Multiple edge metal layers 178 may be connected to multiple guard ring portions 176. Multiple edge metal layers 178 may be arranged to surround the active portion 160 when viewed from above. The edge pressure-resistant structure in this example includes five edge metal layers 178, but the number of edge metal layers 178 is not limited thereto. Multiple edge metal layers 178 may function as field plate electrodes.

[0253] The channel stop structure has a first conductive channel stop portion 260. The channel stop structure may be any of the structures disclosed herein. The depth of the lower end of the second channel stop region 62 may be the same as the depth of the lower end of the storage region 16.

[0254] The outer periphery well region 165 is an example of the well region 17. The outer periphery well region 165 may be provided such that the distance between the innermost guard ring portion 176 of the edge termination structure 170 and the outer end of the outer periphery well region 165 is close. Above the outer periphery well region 165, an oxide film 39 may be provided between the contact region 15 and the gate runner portion 51. The oxide film 39 may be formed simultaneously with the dummy insulating film 32 or the gate insulating film 42 in the same process.

[0255] The protective layer 180 covers the top of the semiconductor substrate 10. The protective layer 180 may also be provided above the gate metal layer 50, the emitter electrode 52, the stopper metal layer 172, and the edge metal layer 178. At least a portion of the pad electrodes, such as the emitter electrode 52, may be exposed and not covered by the protective layer 180. The protective layer 180 may be made of an insulating material such as polyimide.

[0256] Figure 8B shows a modified example of the edge pressure-resistant structure of the edge termination structure 170. The edge pressure-resistant structure in this example differs from the edge pressure-resistant structure in Figure 8A in that it has a polysilicon layer 177. In this example, the differences from the edge pressure-resistant structure in Figure 8A will be explained in particular.

[0257] The polysilicon layer 177 is provided above the guard ring portion 176. The polysilicon layer 177 may function as a field plate layer. The polysilicon layer 177 may be connected to the guard ring portion 176. The edge pressure-resistant structure of this example has a plurality of polysilicon layers 177. The plurality of polysilicon layers 177 may each be connected to a plurality of guard ring portions 176. The polysilicon layers 177 may be formed simultaneously in the same process as the polysilicon of the dummy conductive portion 34 and the gate conductive portion 44, or they may be formed in different processes. The plurality of polysilicon layers 177 may be covered with an interlayer insulating film 38.

[0258] The edge metal layer 178 is provided above the interlayer insulating film 38. The edge metal layer 178 may be connected to the polysilicon layer 177. The edge metal layer 178 may be formed simultaneously in the same process as the gate metal layer 50, the emitter electrode 52, and the stopper metal layer 172. The thickness of the edge metal layer 178 may be greater than the thickness of the polysilicon layer 177.

[0259] Figure 8C shows a modified example of the edge pressure-resistant structure of the edge termination structure 170. This example differs from the edge pressure-resistant structure of Figure 8A in that it has a resurf structure 179 instead of a guard ring 176. This example will be explained in detail in terms of the differences from the edge pressure-resistant structure of Figure 8A.

[0260] The Resurf structure 179 is a region of a second conductivity type provided on the front surface 21 of the semiconductor substrate 10. In this example, the Resurf structure 179 is of the P+ type. The doping concentration of the Resurf structure 179 may be greater than the doping concentrations of the first channel stop region 61 and the second conductivity type region 26. The doping concentration of the Resurf structure 179 may be the same as or different from the doping concentrations of the well region 17 and the outer well region 165.

[0261] The resurf structure 179 may have a structure that gradually becomes shallower from the active portion 160 side toward the edge 102 side. The depth of the resurf structure 179 may be changed toward the edge 102 side by ion implanting a second conductivity type dopant under different conditions for each region. The upper surface of the resurf structure 179 may be covered with an interlayer insulating film 38. One or more edge metal layers 178 may be provided above the resurf structure 179.

[0262] Figure 9A shows an example of a corner portion R in Figure 1. Corner portion R is a region in the vicinity of the corner 11 of the semiconductor substrate 10 where the edge breakdown structure is formed in a curved shape. The semiconductor device 100 in this example has the channel stop structure shown in Figure 3A.

[0263] The first channel stop region 61 may be provided in a corner R, in contact with the corner 11 and the edge 102. The first channel stop region 61 may also be provided in contact with the edge 102 other than the corner R. The first channel stop region 61 may extend along the edge 102 from one corner 11 to the other corner 11 of the semiconductor substrate 10.

[0264] The stopper metal layer 172 may be provided above the first channel stop region 61 at the corner portion R. The stopper metal layer 172 extends in a curved shape at the corner portion R. The stopper metal layer 172 may extend in a curved shape with the same width at the corner portion R, or it may extend in a curved shape with different widths. In this example, the stopper metal layer 172 has a greater width at the corner portion R than the straight portion. The stopper metal layer 172 is connected to the first channel stop region 61 via the contact portion 173.

[0265] The edge metal layer 178 is provided above the guard ring portion 176. The edge metal layer 178 is connected to the guard ring portion 176 via the contact portion 175. The guard ring portion 176 and the edge metal layer 178 extend in a curved shape at the corner portion R. In a top view, the guard ring portion 176 and the edge metal layer 178 are provided inside the stopper metal layer 172. Multiple guard ring portions 176 and multiple edge metal layers 178 extend in a curved, parallel manner at the corner portion R.

[0266] Figure 9B shows a modified example of the corner portion R in Figure 1. The semiconductor device 100 in this example differs from the corner portion R in Figure 9A in that it has a non-formed region 265. In this example, the differences from the corner portion R in Figure 9A will be explained in particular. The semiconductor device 100 in this example has the channel stop structure of Figure 7A. However, the non-formed region 265 may also be applied to the semiconductor device 100 of other embodiments.

[0267] The second channel stop region 62 may be provided in a corner R, adjacent to the corner 11 and the edge 102. The second channel stop region 62 may also be provided adjacent to the edge 102 other than the corner R. The second channel stop region 62 may extend along the edge 102 from one corner 11 of the semiconductor substrate 10 to another adjacent corner 11.

[0268] The non-formed region 265 is a region in the corner R of the semiconductor substrate 10 where the second channel stop region 62 is not provided. The outer periphery of the non-formed region 265 is covered by the second channel stop region 62 when viewed from above. The non-formed region 265 in this example has a substantially triangular shape, but is not limited thereto. Providing the non-formed region 265 makes it easier to suppress delamination of the interlayer insulating film 38 and the like. The front surface 21 of the non-formed region 265 may be provided with a first channel stop region 61 which is a second conductivity type, and a drift region 18 may also be provided.

[0269] Figure 10 is an example of a top view of a semiconductor device 100. In this example, the semiconductor device 100 includes a transistor section 70 but does not include a diode section 80.

[0270] The transistor section 70 may have the same basic structure as the transistor section 70 of a semiconductor device 100 that also includes a diode section 80. That is, the transistor section 70 may be an IGBT. The gate trench section 40 may be connected to the gate metal layer 50 using a connection section 25 and a contact hole 55. The transistor section 70 may also be a MOSFET (metal-oxide-semiconductor field-effect transistor). Thus, the semiconductor device 100 is not limited to an RC-IGBT. In a semiconductor device 100 that does not include a diode section 80, structures disclosed in other embodiments may be applied. That is, the semiconductor device 100 in this example may include a channel stop structure having a first conductivity type channel stop section 260, and may include an edge breakdown voltage structure disclosed in other embodiments.

[0271] Figure 11 is an example of a cross-sectional view of a semiconductor device 100. This example of a semiconductor device 100 includes a diode section 80 but does not include a transistor section 70. The diode section 80 in this example has the same basic structure as the diode section 80 in a semiconductor device 100 that also includes a transistor section 70. This example will specifically explain the differences between the diode section 80 in this example and the diode section 80 in a semiconductor device 100 that also includes a transistor section 70.

[0272] The semiconductor device 100 in this example includes an anode region 19 and an anode electrode 53. The anode region 19 is an example of a second conductivity type region 26. The anode region 19 may be formed simultaneously with the first channel stop region 61 in the same process.

[0273] The anode electrode 53 is connected to the anode region 19 via a contact hole 54. The anode electrode 53 is formed from a material containing metal. At least a portion of the anode electrode 53 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi), aluminum-silicon-copper alloy (AlSiCu), or aluminum-copper alloy (AlCu). The anode electrode 53 may have a barrier metal formed from titanium or a titanium compound, cobalt or a cobalt compound, nickel or a nickel compound, etc., in the layer below the region formed from aluminum or the like. The anode electrode 53 may be formed simultaneously with the stopper metal layer 172 and the edge metal layer 178 in the same process.

[0274] Even in semiconductor devices 100 that do not have a transistor section 70, structures disclosed in other embodiments may be applied. That is, the semiconductor device 100 in this example may have a channel stop structure having a first conductivity type channel stop section 260, and may have an edge breakdown voltage structure disclosed in other embodiments.

[0275] Figure 12A shows a modified example of the XZ cross-section including the a-a' cross-section in Figure 1. In the semiconductor device 100 of this example, the positional relationship between the third channel stop region 63 and the stopper metal layer 172 differs from that of the semiconductor device 100 in Figure 3A. In this example, the differences from the semiconductor device 100 in Figure 3A will be explained in particular, and other aspects may be the same as those of the semiconductor device 100 in Figure 3A.

[0276] End portion E172 indicates the position of the end portion of the stopper metal layer 172 on the active portion 160 side. In this example, end portion E172 indicates the position of the end portion of the stopper metal layer 172 on the active portion 160 side in the X-axis direction.

[0277] End portion E63 indicates the position of the end portion of the third channel stop region 63 on the active portion 160 side. In this example, end portion E63 indicates the position of the end portion of the third channel stop region 63 on the active portion 160 side in the X-axis direction.

[0278] The third channel stop region 63 may extend further toward the active portion 160 than the stopper metal layer 172. That is, the end E63 of the third channel stop region 63 toward the active portion 160 may be closer to the active portion 160 than the end E172 of the stopper metal layer 172 toward the active portion 160, and may protrude toward the active portion 160. In this example, the third channel stop region 63 extends from the edge side of the semiconductor substrate 10, beyond the end E172 of the stopper metal layer 172 toward the active portion 160, toward the active portion 160.

[0279] Distance L2 is the amount of overhang of the end E63 of the third channel stop region 63 on the active portion 160 side from the end E172 of the stopper metal layer 172 on the active portion 160 side in the direction in which the active portion 160 is provided. Distance γ is the distance between the end E172 of the stopper metal layer 172 on the active portion 160 side and the edge metal layer 178 on the semiconductor substrate 10 side. Distance γ may be the shortest distance between the end E172 and the edge metal layer 178 on the semiconductor substrate 10 side. Distance L2 may be 50% or less of distance γ. If distance L2 becomes too large, it may become easier to connect with the depletion layer on the active portion 160 side, which may reduce the avalanche tolerance.

[0280] Distance L1 is the distance between the end of the first channel stop region 61 on the active portion 160 side and the end E63 of the third channel stop region 63 on the active portion 160 side. Distance L1 may be 5 μm or more. Distance L1 may be 10 μm or more and may be 50 μm or less. Increasing distance L1 makes it easier to reduce leakage current, as will be described later. Increasing distance L1 makes it easier to suppress deterioration of static breakdown voltage characteristics, as will be described later.

[0281] Figure 12B shows a modified example of the XZ cross-section including the a-a' cross-section in Figure 1. In the semiconductor device 100 of this example, the positional relationship between the third channel stop region 63 and the stopper metal layer 172 differs from that of the semiconductor device 100 in Figure 12A. In this example, the differences from the semiconductor device 100 in Figure 12A will be explained in particular, while other aspects may be the same as those of the semiconductor device 100 in Figure 12A.

[0282] The third channel stop region 63 terminates from the edge side of the semiconductor substrate 10 without exceeding the end E172 of the stopper metal layer 172 on the active portion 160 side. In other words, the end E63 of the third channel stop region 63 on the active portion 160 side is closer to the edge of the semiconductor substrate 10 than the end E172 of the stopper metal layer 172 on the active portion 160 side.

[0283] Distance L3 is the distance between the end E63 on the active portion 160 side of the third channel stop region 63 and the end E172 on the active portion 160 side of the stopper metal layer 172. Distance L3 may be 50% or less of distance γ. However, even if distance L3 is 50% or less of distance γ, it may be set to a size such that distance L1 is 5 μm or more. If distance L3 becomes too large, the leakage current may increase.

[0284] Figure 13A shows an example of the electrical characteristics of a semiconductor device. The vertical axis represents the collector current IC [A], and the horizontal axis represents the collector-emitter voltage (VCE) [V]. This figure shows the electrical characteristics of a semiconductor device at room temperature. In this figure, the collector-emitter breakdown voltage (BVCES) at room temperature can be determined by observing the rise time of the collector current IC.

[0285] Comparative Example 2 is a semiconductor device with L1 = 12 μm. Examples 6 to 9 are semiconductor devices 100 with distances L1 of 15 μm, 20 μm, 25 μm, and 30 μm, respectively. In Comparative Example 2, leakage current is generated from a VCE of approximately 400 V.

[0286] Figure 13B shows an example of the electrical characteristics of a semiconductor device. The vertical axis represents the collector current IC [A], and the horizontal axis represents the collector-emitter voltage (VCE) [V]. This figure shows the electrical characteristics of the semiconductor device under high-temperature conditions (e.g., 150°C). The structure of the semiconductor devices in Comparative Example 2 and Examples 6-9 is the same as in Figure 13A. In this example as well, leakage current occurs in Comparative Example 2 at a VCE of approximately 400V. Furthermore, under high-temperature conditions, avalanche breakdown occurs at a VCE of approximately 800V.

[0287] Figure 14A shows an example of the electrical characteristics of a semiconductor device. The vertical axis shows the collector-emitter breakdown voltage BVCES [V] at room temperature, and the horizontal axis shows the overhang position [%] of the end E63 on the active portion 160 side of the third channel stop region 63, relative to the end E172 on the active portion 160 side of the stopper metal layer 172.

[0288] A positive value for the overhang position [%] indicates that the third channel stop region 63 overhangs the active portion 160 side beyond the end E172. For example, a 50% overhang position indicates that the third channel stop region 63 overhangs the active portion 160 side by 50% of the distance γ beyond the end E172.

[0289] If the overhang position [%] is a negative value, it indicates that the third channel stop region 63 terminates on the edge side of the semiconductor substrate 10, beyond the end E172. For example, if the overhang position is -50%, it indicates that the end E63 is located 50% of the distance γ toward the edge of the semiconductor substrate 10 compared to the end E172.

[0290] The overhang position of the semiconductor device 100 may be between -50% and 50%. However, even within this range, if L1 is less than 5 μm, the collector-emitter breakdown voltage BVCES may decrease.

[0291] Comparative Example 1 is a semiconductor device 500 having a P-type channel stop portion 561. In Comparative Example 1, a lower collector-emitter breakdown voltage BVCES is obtained than in the example.

[0292] Comparative Example 3 is a semiconductor device in which an N-type channel stop region is formed by ion implantation of arsenic (As). In Comparative Example 3, an excellent collector-emitter breakdown voltage BVCES is obtained, but there is a concern about delamination of the insulating film.

[0293] Figure 14B shows an example of the electrical characteristics of a semiconductor device. The vertical axis shows the collector-emitter breakdown voltage BVCES [V] at 150°C, and the horizontal axis shows the overhang position [%] of the end E63 on the active portion 160 side of the third channel stop region 63, relative to the end E172 on the active portion 160 side of the stopper metal layer 172.

[0294] As shown in Figure 14A, similar to the data for room temperature, the overhang position of the semiconductor device 100 may be between -50% and 50%. However, even within this range, if L1 is smaller than 5 μm, the collector-emitter breakdown voltage BVCES may decrease.

[0295] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0296] It should be noted that the execution order of operations, procedures, steps, and stages in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be performed in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, this does not mean that it is mandatory to perform the operations in that order.

[0297] 10... Semiconductor substrate, 11... Corner, 12... Emitter region, 13... Plug region, 14... Base region, 15... Contact region, 16... Accumulation region, 17... Well region, 18... Drift region, 19... Anode region, 20... Buffer region, 25... Connection region, 26... Second conductivity region, 21... Front surface, 22... Collector region, 23... Back surface, 24... Collector electrode, 30... Dummy trench region, 31... Extended portion, 32... Dummy insulating film, 33... Connection portion, 3 4... Dummy conductive part, 38... Interlayer insulating film, 39... Oxide film, 40... Gate trench part, 41... Stretched part, 42... Gate insulating film, 43... Connection part, 44... Gate conductive part, 50... Gate metal layer, 51... Gate runner part, 52... Emitter electrode, 53... Anode electrode, 54... Contact hole, 55... Contact hole, 56... Contact hole, 58... Trench contact part, 61... First channel stop region, 62... Second channel stop region, 63... Third channel stop region, 70...transistor section, 71...mesa section, 74...basic insulating film, 75...main region, 78...boundary, 80...diode section, 81...mesa section, 82...cathode region, 90...boundary region, 91...mesa section, 100...semiconductor device, 102...edge, 112...gate pad, 130...gate wiring, 160...active section, 165...outer well region, 170...edge termination structure, 172...stopper metal layer, 173...contact section, 175...contour 176...Guard ring section, 177...Polysilicon layer, 178...Edge metal layer, 179...Resurf structure section, 180...Protective layer, 190...Resist, 200...Front electrode section, 192...Resist, 210...Silicide layer, 220...Barrier metal section, 221...First barrier metal layer, 222...Second barrier metal layer, 230...Plug section, 260...First conductive channel stop section, 265...Non-formed region, 500...Semiconductor device, 561...P-type channel stop section

Claims

1. A semiconductor device comprising an active portion and an edge termination structure provided on the outer periphery of the active portion, wherein the semiconductor substrate comprises a drift region of a first conductivity type provided on the semiconductor substrate, and a second conductivity type region of a second conductivity type provided above the drift region in the active portion, the edge termination structure having a first channel stop region of a second conductivity type provided above the drift region, a second channel stop region of a first conductivity type provided below the first channel stop region and having a higher doping concentration than the drift region, and a third channel stop region of a first conductivity type connected to the second channel stop region, provided closer to the active portion than the first channel stop region and having a higher doping concentration than the drift region, the lower end of the third channel stop region being shallower than the lower end of the second channel stop region in the depth direction of the semiconductor substrate.

2. The semiconductor device according to claim 1, wherein the third channel stop region extends from the second channel stop region in the direction in which the active portion is provided.

3. The semiconductor device according to claim 1, wherein the second channel stop region covers the lower end and side surface of the active portion side of the first channel stop region.

4. The semiconductor device according to claim 1, wherein the distance between the active portion side end of the first channel stop region and the active portion side end of the third channel stop region is greater than the difference between the depth position of the lower end of the first channel stop region and the depth position of the lower end of the second channel stop region.

5. The semiconductor device according to claim 1, wherein the thickness of the first channel stop region is smaller than the thickness of the second channel stop region below the first channel stop region.

6. The semiconductor device according to claim 1, wherein the thickness of the first channel stop region is greater than or equal to the thickness of the second channel stop region below the first channel stop region.

7. The semiconductor device according to claim 1, wherein the doping concentration in the first channel stop region is the same as the doping concentration in the second conductivity type region.

8. The semiconductor device according to claim 1, wherein the depth position of the lower end of the first channel stop region is the same as the depth position of the lower end of the second conductivity type region.

9. The semiconductor device according to claim 1, wherein the first channel stop region is provided on the front surface of the semiconductor substrate.

10. The semiconductor device according to claim 1, wherein the first channel stop region is provided on the side surface of the semiconductor substrate.

11. The semiconductor device according to claim 1, wherein the maximum doping concentration of the second conductivity type dopant in the first channel stop region is smaller than the maximum doping concentration of the first conductivity type dopant in the second channel stop region.

12. The semiconductor device according to claim 1, wherein the second channel stop region has a plurality of peaks of doping concentration in the depth direction of the semiconductor substrate.

13. The semiconductor device according to claim 1, wherein the dopant of the second channel stop region is phosphorus.

14. The semiconductor device according to claim 1, wherein the corner portion of the semiconductor substrate has a non-formed region in which the second channel stop region is not provided, and the outer periphery of the non-formed region is covered by the second channel stop region when viewed from above.

15. The semiconductor device according to claim 1, wherein the second channel stop region is provided on the side surface of the semiconductor substrate.

16. The semiconductor device according to claim 1, wherein the thickness of the third channel stop region is 1.0 μm or more and 5.0 μm or less in the depth direction of the semiconductor substrate.

17. The semiconductor device according to claim 1, wherein the dopant in the third channel stop region is phosphorus.

18. The semiconductor device according to any one of claims 1 to 17, comprising a stopper metal layer provided above the semiconductor substrate and connected to the first channel stop region.

19. The semiconductor device according to claim 18, wherein the end of the stopper metal layer on the active portion side is provided closer to the active portion than the end of the third channel stop region on the active portion side.

20. The semiconductor device according to claim 18, wherein the third channel stop region is provided below the stopper metal layer.

21. The semiconductor device according to any one of claims 1 to 17, comprising a first conductivity type storage region provided above the drift region and having a doping concentration higher than that of the drift region.

22. The semiconductor device according to claim 21, wherein the accumulation region has a plurality of doping concentration peaks in the depth direction of the semiconductor substrate, and the third channel stop region has a plurality of doping concentration peaks in the depth direction of the semiconductor substrate.

23. The semiconductor device according to claim 21, wherein the doping concentration of the accumulation region is the same as the doping concentration of the second channel stop region.

24. The semiconductor device according to claim 21, wherein the magnitude of the peak doping concentration in the accumulation region is the same as the magnitude of the peak doping concentration in the third channel stop region.

25. The semiconductor device according to any one of claims 1 to 17, further comprising a base insulating film provided above the third channel stop region.

26. The semiconductor device according to claim 25, wherein the thickness of the basic insulating film is 100 nm or more and 3 μm or less.

27. The semiconductor device according to claim 25, wherein, in a top view, the edge termination structure has a plurality of guard ring portions located inside the semiconductor substrate beyond the third channel stop region, and the distance from the third channel stop region to the outermost guard ring portion among the plurality of guard ring portions is 10 μm or more and 100 μm or less.

28. The semiconductor device according to claim 27, wherein when the distance from the edge side of the semiconductor substrate of the basic insulating film to the active side of the third channel stop region is α, and the distance from the third channel stop region to the outermost guard ring portion is β, the device satisfies 0 < α / β ≤ 10.

29. The semiconductor device according to claim 28, wherein α and β satisfy 0.001 ≤ α / β ≤ 10.

30. A semiconductor device comprising a transistor, wherein the transistor has: a plurality of trenches extended in a predetermined trench stretching direction on the front surface of the semiconductor substrate; an emitter region of a first conductivity type having a higher doping concentration than the drift region, provided on the front surface of the semiconductor substrate; and a plurality of contact regions of a second conductivity type having a higher doping concentration than the second conductivity type region, wherein the second conductivity type region is the base region of the transistor.

31. A semiconductor device comprising a diode portion, wherein the second conductivity type region is the anode region of the diode portion, according to any one of claims 1 to 17.

32. A semiconductor device according to any one of claims 1 to 17, comprising: a stopper metal layer provided above the semiconductor substrate and connected to the first channel stop region; a guard ring portion provided in a top view to be inside the semiconductor substrate beyond the third channel stop region; and an edge metal layer provided above the semiconductor substrate and connected to the guard ring portion, wherein the third channel stop region extends from the edge side of the semiconductor substrate, beyond the end of the stopper metal layer on the active portion side, toward the active portion side, and the amount of overhang of the end of the third channel stop region on the active portion side toward the direction in which the active portion is provided from the end of the stopper metal layer on the active portion side is 50% or less of the distance between the end of the stopper metal layer on the active portion side and the end of the edge metal layer on the semiconductor substrate side.

33. A semiconductor device according to any one of claims 1 to 17, comprising: a stopper metal layer provided above the semiconductor substrate and connected to the first channel stop region; a guard ring portion provided in the edge termination structure portion, in a top view, inside the semiconductor substrate beyond the third channel stop region; and an edge metal layer provided above the semiconductor substrate and connected to the guard ring portion, wherein the third channel stop region terminates from the edge side of the semiconductor substrate without exceeding the active side end of the stopper metal layer, and the distance between the active side end of the third channel stop region and the active side end of the stopper metal layer is 50% or less of the distance between the active side end of the stopper metal layer and the edge side end of the edge metal layer on the semiconductor substrate.

34. The semiconductor device according to any one of claims 1 to 17, wherein the distance L1 between the active portion side end of the first channel stop region and the active portion side end of the third channel stop region is 5 μm or more.

35. A semiconductor device comprising an active portion and an edge termination structure provided on the outer periphery of the active portion, wherein the semiconductor device comprises: a drift region of a first conductivity type provided on a semiconductor substrate; a second conductivity type region of a second conductivity type provided above the drift region in the active portion; and an accumulation region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region, wherein the edge termination structure comprises: a first channel stop region of a second conductivity type provided above the drift region; and a second channel stop region of a first conductivity type provided below the first channel stop region and having a higher doping concentration than the drift region, wherein the magnitude of the peak doping concentration in the accumulation region is equal to the magnitude of the peak doping concentration in the second channel stop region.

36. A semiconductor device comprising an active portion and an edge termination structure provided on the outer periphery of the active portion, wherein the semiconductor substrate comprises: a drift region of a first conductivity type provided on a semiconductor substrate; a second conductivity type region of a second conductivity type provided above the drift region in the active portion; and an accumulation region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region, the edge termination structure comprises: a second channel stop region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region; a third channel stop region of a first conductivity type connected to the second channel stop region, provided closer to the active portion than the second channel stop region and having a higher doping concentration than the drift region; and a base insulating film provided above the third channel stop region, wherein the dopants of the second channel stop region and the third channel stop region are the same as the dopants of the accumulation region, and the lower end of the third channel stop region is shallower than the lower end of the second channel stop region in the depth direction of the semiconductor substrate. A semiconductor device in which the basic insulating film is not provided above the second channel stop region.

37. The semiconductor device according to claim 36, wherein the third channel stop region extends from the second channel stop region in the direction in which the active portion is provided.

38. A semiconductor device comprising an active portion and an edge termination structure provided on the outer periphery of the active portion, wherein the semiconductor device comprises: a drift region of a first conductivity type provided on a semiconductor substrate; a second conductivity type region of a second conductivity type provided above the drift region in the active portion; and a storage region of a first conductivity type provided above the drift region and having a higher doping concentration than the drift region, wherein the edge termination structure is provided above the drift region and has a first conductivity type channel stop portion of a first conductivity type having a higher doping concentration than the drift region, the dopant of the first conductivity type channel stop portion is the same as the dopant of the storage region, and the maximum doping concentration of the first conductivity type channel stop portion is the same as the maximum doping concentration of the storage region.

39. The semiconductor device according to claim 38, further comprising a base insulating film provided above the first conductive channel stop portion.

40. A method for manufacturing a semiconductor device comprising an active portion and an edge termination structure provided on the outer periphery of the active portion, comprising: a step of forming a second conductivity type region of a second conductivity type above a drift region of a first conductivity type provided on a semiconductor substrate in the active portion; a step of forming a first channel stop region of a second conductivity type above the drift region in the edge termination structure; a step of forming a second channel stop region of a first conductivity type having a higher doping concentration than the drift region below the first channel stop region; and a step of forming a third channel stop region of a first conductivity type having a higher doping concentration than the drift region, connected to the second channel stop region and closer to the active portion than the first channel stop region, wherein the lower end of the third channel stop region is shallower than the lower end of the second channel stop region in the depth direction of the semiconductor substrate.

41. The method for manufacturing a semiconductor device according to claim 40, wherein the step of forming the third channel stop region is to implant ions into the semiconductor substrate via a base insulating film provided above the semiconductor substrate.

42. A method for manufacturing a semiconductor device according to claim 40 or 41, comprising the step of forming an accumulation region on the semiconductor substrate, wherein ion implantation of the third channel stop region is performed simultaneously in the same process as ion implantation of the accumulation region.

43. A method for manufacturing a semiconductor device according to claim 40 or 41, comprising the steps of: forming a stopper metal layer connected to the first channel stop region above the semiconductor substrate; forming a guard ring portion inside the semiconductor substrate beyond the third channel stop region in a top view; and forming an edge metal layer connected to the guard ring portion above the semiconductor substrate, wherein the third channel stop region extends from the edge side of the semiconductor substrate, beyond the end of the stopper metal layer on the active portion side, toward the active portion side, and the amount of overhang of the end of the third channel stop region on the active portion side from the end of the stopper metal layer on the active portion side toward the direction toward the active portion is 50% or less of the distance between the end of the stopper metal layer on the active portion side and the end of the edge metal layer on the semiconductor substrate side.

44. A method for manufacturing a semiconductor device according to claim 40 or 41, comprising the steps of: forming a stopper metal layer connected to the first channel stop region above the semiconductor substrate; forming a guard ring portion inside the semiconductor substrate beyond the third channel stop region in a top view; and forming an edge metal layer connected to the guard ring portion above the semiconductor substrate, wherein the third channel stop region terminates from the edge side of the semiconductor substrate without exceeding the active portion side end of the stopper metal layer, and the distance between the active portion side end of the third channel stop region and the active portion side end of the stopper metal layer is 50% or less of the distance between the active portion side end of the stopper metal layer and the edge portion side end of the edge metal layer on the semiconductor substrate.

45. The method for manufacturing a semiconductor device according to claim 40 or 41, wherein the distance L1 between the end of the first channel stop region on the active portion side and the end of the third channel stop region on the active portion side is 5 μm or more.

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