Semiconductor device and control method

Abstract

This semiconductor device comprises: a substrate (101); a first nitride semiconductor layer (103) provided on the substrate (101); a second nitride semiconductor layer (104) provided on the first nitride semiconductor layer (103); a two-dimensional electron gas layer (105) provided in the vicinity of a boundary between the first nitride semiconductor layer (103) and the second nitride semiconductor layer (104); a source electrode (301) and a drain electrode (302) each electrically connected to the first nitride semiconductor layer (103); and a gate electrode (401) provided to be spaced apart from the source electrode (301) and the drain electrode (302). The device has an active region (701) on the substrate (101), and further comprises a first temperature detection resistor (601) for detecting a first temperature of the gate electrode (401) in the active region (701), and a second temperature detection resistor (602) for detecting a second temperature between the gate electrode (401) and the drain electrode (302) in the active region (701).

Description

Semiconductor device and control method

[0001] This disclosure relates to a semiconductor device and a control method.

[0002] Group III-V semiconductors, particularly arsenic-based GaAs or AlGaAs, or nitride-based GaN or AlGaN, can easily form heterostructures such as AlGaAs / GaAs and AlGaN / GaN. In the case of Group III nitride semiconductors, in addition to the difference in band gaps, fixed charges due to spontaneous polarization caused by differences in ionic radii or piezoelectric polarization generated from the difference in lattice constants between AlGaN and GaN can generate high-mobility, high-concentration electron channels (two-dimensional electron gas: 2DEG (Dimensional Electron Gas)) on the GaAs side of AlGaAs / GaAs and on the GaN layer side of the AlGaN / GaN interface. By controlling this two-dimensional electron gas as a channel, it becomes possible to form high-electron-mobility transistors (HEMTs). Field-effect transistors (FETs), which take advantage of this high mobility and resulting high-speed operation, are seeing expanding applications as high-frequency devices such as amplifiers and switching elements.

[0003] In recent years, semiconductor devices have been increasingly put into practical use as high-frequency amplifiers, particularly for mobile phone base stations. With the evolution of mobile phone communication generations, further increases in operating frequency and output power are expected. Increasing the operating frequency or output power leads to an increase in the amount of heat generated by the device itself (e.g., a transistor) used as a high-frequency amplifier.

[0004] Therefore, measuring the heat generated by the semiconductor device itself is being considered. For example, Patent Document 1 discloses a technique for measuring the temperature of a transistor element.

[0005] U.S. Patent Application Publication No. 2020 / 0144970

[0006] Incidentally, in FETs, the temperature tends to be highest near the gate electrode, but heat generation can also occur in other regions. However, since Patent Document 1 uses a floating gate plate for temperature measurement, it is difficult to accurately detect the temperature if heat is generated in regions other than near the gate electrode.

[0007] Therefore, this disclosure provides a semiconductor device and a control method that can improve the accuracy of temperature detection.

[0008] A semiconductor device according to one aspect of the present disclosure includes a substrate, a first nitride semiconductor layer provided on the substrate, a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer, a two-dimensional electron gas layer provided near the boundary between the first nitride semiconductor layer and the second nitride semiconductor layer, a source electrode and a drain electrode provided on the second nitride semiconductor layer at intervals and each electrically connected to the first nitride semiconductor layer, and a gate electrode provided on the second nitride semiconductor layer at intervals from the source electrode and the drain electrode, wherein the substrate has an active region and an inactive region, and further includes a first temperature sensing resistor for sensing a first temperature near the gate electrode in the active region, and a second temperature sensing resistor for sensing a second temperature between the gate electrode and the drain electrode in the active region.

[0009] A control method according to one aspect of the present disclosure converts the resistance value of the first temperature sensing resistor provided in the semiconductor device to a first temperature, converts the resistance value of the second temperature sensing resistor provided in the semiconductor device to a second temperature, increases the gate voltage if the representative temperature based on the first and second temperatures is less than or equal to a first threshold, increases the gate voltage and increases the drive current of the cooling fan if the representative temperature is greater than or equal to the first threshold and less than or equal to a second threshold higher than the first threshold, and turns off the gate voltage if the representative temperature is greater than or equal to the second threshold.

[0010] According to one aspect of this disclosure, it is possible to realize a semiconductor device that can improve the accuracy of temperature detection.

[0011] Figure 1 is a plan view showing the configuration of a semiconductor device according to Embodiment 1. Figure 2 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1 along line II-II in Figure 1. Figure 3 is a diagram showing the relationship between the temperature between the gate and drain and the resistor detection temperature according to Embodiment 1. Figure 4 is a plan view showing the configuration of a semiconductor device for single-finger temperature detection according to Embodiment 1. Figure 5 is a diagram showing the relationship between the gate temperature and the electrical resistance of the first temperature-sensing resistor according to Embodiment 1. Figure 6 is a diagram showing the relationship between the resistor width and the electrical resistance / volume resistivity of the first temperature-sensing resistor according to Embodiment 1. Figure 7 is a plan view showing the configuration of a semiconductor device according to Embodiment 2. Figure 8 is a diagram showing the relationship between the gate temperature and the electrical resistance of the first temperature-sensing resistor according to Embodiment 2. Figure 9 is a plan view showing the configuration of a semiconductor device according to Embodiment 3. Figure 10 is a diagram showing the relationship between the gate temperature and the electrical resistance of the first temperature-sensing resistor according to Embodiment 3. Figure 11 is a diagram showing the relationship between the resistor width and the rate of change of resistance according to Embodiment 3. Figure 12 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 4, corresponding to line II-II in Figure 1. Figure 13 is a diagram showing the configuration of the semiconductor module according to Embodiment 5. Figure 14 is a flowchart showing the operation of the semiconductor module according to Embodiment 5.

[0012] (Background to this disclosure) In FETs, it is known that the temperature is highest near the gate electrode. However, if there are abnormalities such as Mg diffusion or dielectric film interface, current can flow and the temperature can rise between the gate and drain. Therefore, it is desirable to detect the temperature between the gate and drain in order to detect abnormalities between the gate and drain.

[0013] However, since Patent Document 1 uses a floating gate plate for temperature detection, it is difficult to accurately monitor temperature changes between the gate and drain. In other words, with the technology of Patent Document 1, it is difficult to accurately detect the temperature (temperature change) between the gate and drain.

[0014] Therefore, the inventors of this application have diligently studied semiconductor devices that can accurately detect the temperature (temperature change) between the gate and drain, that is, devices that can improve the accuracy of temperature detection, and have devised the following semiconductor devices.

[0015] Furthermore, in semiconductor devices, FETs are sometimes formed in an array. In such a semiconductor device, if, for example, only one temperature-sensing resistor is placed, only the representative temperature of one or more transistors can be monitored, which may lead to missing an anomaly.

[0016] Therefore, the inventors of this application are also diligently studying semiconductor devices that can suppress the oversight of abnormalities by monitoring the entire array of FETs.

[0017] The embodiments will be described in detail below with reference to the drawings.

[0018] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0019] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0020] Furthermore, in this specification and the drawings, the X, Y, and Z axes represent the three axes of a right-handed three-dimensional Cartesian coordinate system. In each embodiment, the Z-axis direction is the stacking direction (thickness direction) of each layer of the semiconductor device. Also, in this specification, "plan view" means viewing the semiconductor device along the thickness direction of the semiconductor device.

[0021] Furthermore, in this specification, terms indicating relationships between elements such as orthogonal and parallel, terms indicating the shape of elements such as rectangles, and numerical values ​​and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, for example, differences of a few percent (or about 10%).

[0022] Furthermore, in this specification, the terms "on (e.g., on a substrate)" and "above" do not refer to an upward direction (vertically upward) in absolute spatial perception, but rather are used as terms defined by relative positional relationships based on the stacking order in a stacked structure. In addition, the terms "on (e.g., on a substrate)" and "above" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in contact with each other.

[0023] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., do not indicate the number or order of components unless otherwise specified, but are used to avoid confusion and to distinguish similar components.

[0024] (Embodiment 1) The semiconductor device according to this embodiment will be described below with reference to Figures 1 to 6.

[0025] [1-1. Configuration of the Semiconductor Device] First, the configuration of the semiconductor device according to this embodiment will be described with reference to Figures 1 and 2. Figure 1 is a plan view showing the configuration of the semiconductor device 1 according to this embodiment. Figure 2 is a cross-sectional view showing the configuration of the semiconductor device 1 according to this embodiment along line II-II in Figure 1. Note that in Figure 1, the substrate, nitride semiconductor layer, insulating layer, etc., are omitted from the illustration.

[0026] In Figure 1, the source electrode 301, drain electrode 302, source / drain electrode connection opening 801a, gate electrode connection opening 801c, first temperature sensing resistor connection opening 801d, and second temperature sensing resistor connection opening 801e, all located beneath the first wiring layer 801, are shown with solid lines rather than dashed lines to facilitate recognition of their relative positions. Furthermore, in Figure 1, for identification purposes, the source field plate electrode 501 is shown with dot hatching, the first temperature sensing resistor 601 with a downward-sloping diagonal hatching, the second temperature sensing resistor 602 with a downward-sloping diagonal hatching, while the first wiring layer 801 and other components are shown without hatching. The same applies to the plan views of Embodiment 2 and subsequent embodiments.

[0027] As shown in Figures 1 and 2, the semiconductor device 1 includes a substrate 101, a buffer layer 102, a first nitride semiconductor layer 103, a second nitride semiconductor layer 104, a third nitride semiconductor layer 106, a first insulating layer 201, a second insulating layer 202, a third insulating layer 203, a fourth insulating layer 204, a source electrode 301, a drain electrode 302, a gate electrode 401, a source field plate electrode 501, a first temperature sensing resistor 601, a second temperature sensing resistor 602, and an active region. The circuit includes 701, an inactive region 704, a first wiring layer 801, an opening 801a for source and drain electrode connection, an opening 801b for source field plate electrode connection, an opening 801c for gate electrode connection, an opening 801d for first temperature sensing resistor connection, an opening 801e for second temperature sensing resistor connection, a source via hole 802, a drain terminal 803, a gate terminal 804, first connection terminals 805 and 806, and second connection terminals 807 and 808. For convenience, the outer circumference of the active region 701 is shown with a thick line. The same applies to Figures 4, 7, and 9.

[0028] Furthermore, in semiconductor device 1, a two-dimensional electron gas layer 105 is formed on the first nitride semiconductor layer 103 side of the heterointerface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103.

[0029] Furthermore, the semiconductor device 1 may be used, for example, as a power amplification semiconductor device (sometimes called a power amplification semiconductor chip or simply a chip). For example, the semiconductor device 1 may be used as a power semiconductor device.

[0030] The semiconductor device 1 configured as described above is a resistor for directly measuring the temperature of a transistor, and is characterized by comprising a first temperature sensing resistor 601 and a second temperature sensing resistor 602, which are provided separately. Each component will be described below.

[0031] In the example described, the semiconductor device 1 includes a source electrode 301, a drain electrode 302, a gate electrode 401, and a source field plate electrode 501, all of which are arranged in an array (aligned in the X-axis direction). However, it is sufficient to have at least one FET.

[0032] The substrate 101 is, for example, a substrate containing Si (e.g., a silicon substrate). However, the substrate 101 is not limited to a substrate containing Si, but may also be a substrate containing sapphire, SiC, GaN, AlN, etc.

[0033] The buffer layer 102 is formed on the substrate 101. The buffer layer 102 is, for example, a nitride semiconductor layer having a stacked structure of multiple AlN and AlGaN with a thickness of 2 μm. The buffer layer 102 may also be composed of a single layer or multiple layers of a group III nitride semiconductor such as GaN, AlGaN, AlN, InGaN, or AlInGaN.

[0034] The first nitride semiconductor layer 103 is formed on the substrate 101. In this embodiment, the first nitride semiconductor layer 103 is formed on the buffer layer 102. The first nitride semiconductor layer 103 is composed of, for example, undoped (i-type) GaN with a thickness of 200 nm. Undoped (i-type) means that impurities are not intentionally doped during epitaxial growth. In addition to GaN, the first nitride semiconductor layer 103 may be composed of a group III nitride semiconductor such as AlGaN, InGaN, or AlInGaN. Furthermore, the first nitride semiconductor layer 103 may contain not only undoped (i-type) impurities but also n-type impurities such as Si.

[0035] The second nitride semiconductor layer 104 is formed on the first nitride semiconductor layer 103. The second nitride semiconductor layer 104 is composed of, for example, undoped (i-type) AlGaN with a thickness of 20 nm and an Al composition ratio of 25%. The second nitride semiconductor layer 104 is not limited to AlGaN, but may also be composed of a group III nitride semiconductor such as AlN, InGaN, or AlInGaN. Furthermore, the second nitride semiconductor layer 104 may contain n-type impurities.

[0036] Furthermore, a cap layer may be provided on the second nitride semiconductor layer 104, such as a semiconductor layer containing GaN with a thickness of approximately 1 to 2 nm, or a protective insulating layer containing SiN with a thickness of approximately 2 to 5 nm.

[0037] In this embodiment, the band gap of the second nitride semiconductor layer 104 is larger than the band gap of the first nitride semiconductor layer 103. Furthermore, the second nitride semiconductor layer 104 containing undoped (i-type) AlGaN and the first nitride semiconductor layer 103 containing undoped (i-type) GaN have a heterostructure. In other words, the interface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103 is a heterojunction, and a heterobarrier is formed at the interface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103.

[0038] As a result, a two-dimensional electron gas layer 105 is formed near the boundary between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104, for example, on the first nitride semiconductor layer 103 side of the heterointerface between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103 (in other words, on the second nitride semiconductor layer 104 side within the first nitride semiconductor layer 103). For example, the two-dimensional electron gas layer 105 is provided on the first nitride semiconductor layer 103 side of the interface between the first nitride semiconductor layer 103 and the second nitride semiconductor layer 104.

[0039] Note that a semiconductor layer having a thickness of about 1 to 2 nm containing, for example, AlN may be provided as a spacer layer between the second nitride semiconductor layer 104 and the first nitride semiconductor layer 103.

[0040] The third nitride semiconductor layer 106 is a contact layer containing a p-type nitride semiconductor. In the present embodiment, the third nitride semiconductor layer 106 is formed of p-type GaN. Further, a part of the third nitride semiconductor layer 106 is formed in a recess obtained by removing a part of the second nitride semiconductor layer 104 and / or the first nitride semiconductor layer 103.

[0041] Note that the third nitride semiconductor layer 106 may not be provided. A semiconductor device without the third nitride semiconductor layer 106 will be described later while referring to FIG. 12.

[0042] The source electrode 301 and the drain electrode 302 are provided on the second nitride semiconductor layer 104 with a space therebetween so as to face each other. The source electrode 301 and the drain electrode 302 are each electrically connected to the first nitride semiconductor layer 103. The source electrode 301 and the drain electrode 302 are, for example, multilayer electrode films having a laminated structure in which a Ti film and an Al film are laminated in this order, but are not limited thereto. Further, the source electrode 301 and the drain electrode 302 are electrically connected (for example, ohmically connected) to the two-dimensional electron gas layer 105.

[0043] Further, the drain electrode 302 is located on a drain finger extending in the Y-axis direction in a plan view.

[0044] Furthermore, beneath the source electrode 301 and the drain electrode 302, a contact layer containing n-type impurities including a donor such as Si may be provided in a recess obtained by removing a portion of the second nitride semiconductor layer 104 and / or the first nitride semiconductor layer 103. The contact layer containing n-type impurities may also be formed by plasma treatment, ion implantation, regrowth, or the like.

[0045] The gate electrode 401 is located on the second nitride semiconductor layer 104 (in this embodiment, on the third nitride semiconductor layer 106) between the source electrode 301 and the drain electrode 302. The gate electrode 401 is spaced apart from the source electrode 301 and the drain electrode 302. The distance between the gate electrode 401 and the drain electrode 302 in the X-axis direction may be longer than, for example, the distance between the gate electrode 401 and the source electrode 301 in the X-axis direction. In other words, the electrode that is farther away from the gate electrode 401 in the X-axis direction may be the drain electrode 302.

[0046] The gate electrode 401 is, for example, a multilayer electrode film having a stacked structure in which a TiN film and an Al film are stacked in sequence, but is not limited to this. The gate electrode 401 may also be electrically connected to the two-dimensional electron gas layer 105 using a Schottky connection. Furthermore, an MIS (Metal-Insulator-Semiconductor) structure may be formed in which an insulating layer is sandwiched between the gate electrode 401 and the second nitride semiconductor layer 104 to electrically insulate the gate electrode 401 and the second nitride semiconductor layer 104.

[0047] The gate electrode 401 is provided extending in the Y-axis direction in a plan view. The gate electrode 401 is rectangular in a plan view, with its longer side parallel to the Y-axis direction. The Y-axis direction is an example of a first direction. Furthermore, the gate electrode 401 is located on a gate finger extending in the Y-axis direction in a plan view.

[0048] The gate electrode 401 may be an alloy containing, for example, any or at least one of Ni, Ta, Ti, W, TaN, TiN, Pt, Pd, Al, Au, Cu, or Ag. Furthermore, the gate electrode 401 may be composed of a single layer (single-layer film) or a multilayer (multilayer film).

[0049] The first insulating layer 201 is provided on the source electrode 301, the drain electrode 302, and the gate electrode 401. The first insulating layer 201 is made of SiN, SiO ２ , SiON, AlN, Al ２ O ３ It is composed of at least one of SiC and C (diamond), and in this embodiment, it is composed of SiN with a thickness of 150 nm. The first insulating layer 201 may be a single layer or a laminated layer.

[0050] The source field plate electrode 501 is at the same potential as the source electrode 301, has an end on the drain electrode 302 side between the gate electrode 401 and the drain electrode 302, and is provided above the second nitride semiconductor layer 104. Specifically, the source field plate electrode 501 is provided on the first insulating layer 201 such that it is on the drain electrode 302 side of the gate electrode 401's end on the source electrode 301 side, and has an end on the drain electrode 302 side between the gate electrode 401 and the drain electrode 302. Furthermore, the source field plate electrode 501 is provided parallel to the long side direction of the gate electrode 401 in a plan view. For example, the source field plate electrode 501 is a multilayer electrode film having a laminated structure in which a Ti film and an Al film are stacked in order, but is not limited to this.

[0051] The source field plate electrode 501 is connected to the source electrode 301 via a first wiring layer 801 through a source / drain electrode connection opening 801a, and via a source field plate electrode connection opening 801b. The source field plate electrode 501 is an example of a field plate.

[0052] The source field plate electrode 501 may be an alloy containing, for example, Ni, Ta, Ti, W, TaN, TiN, Pt, Pd, Al, Au, Cu, or Ag, or at least one of them. The source field plate electrode 501 may be composed of a single layer or a laminate. Cu and Ag are high thermal conductivity materials having a thermal conductivity of a predetermined value or higher.

[0053] The second insulating layer 202 is provided on the first insulating layer 201 and the source field plate electrode 501. The second insulating layer 202 is made of SiN, SiO ２ , SiON, AlN, Al ２ O ３ It is composed of at least one of SiC and C (diamond), and in this embodiment, it is composed of SiN with a thickness of 100 nm. The second insulating layer 202 may be a single layer or a laminated layer.

[0054] The first temperature sensing resistor 601 is located within the active region 701 in a plan view and is provided on the second nitride semiconductor layer 104 (Z-axis positive side) in a cross-sectional view. It is a temperature sensing resistor for detecting the temperature of the transistor (FET), which will be described later, as a change in resistance. The first temperature sensing resistor 601 is a resistor for detecting the first temperature of a region near the gate electrode 401 (gate region: a region that is substantially the same temperature as the semiconductor in contact with the gate electrode 401, or a region formed in the direction of the drain electrode 302 from the end of the gate electrode 401 or the drain electrode 302 side (X-axis positive side) of the third nitride semiconductor layer 106, and having a length equal to or less than the width of the gate electrode 401 (length in the X-axis direction), or a region that overlaps with the source field plate electrode 501 in a plan view and includes at least a part of the region to the side of the gate electrode 401). The gate region is a heat-generating region around the gate electrode 401, and may include, for example, the region to the side of the gate electrode 401 in a cross-sectional view (e.g., the region on the positive X-axis side), or it may include the region below the gate electrode 401.

[0055] In this embodiment, the first temperature sensing resistor 601 is provided on the second insulating layer 202. Also in this embodiment, the first temperature sensing resistor 601 is provided on the source field plate electrode 501. For example, in a plan view, the first temperature sensing resistor 601 may overlap with the source field plate electrode 501 in at least a portion of it, or it may not overlap with the source field plate electrode 501. In this embodiment, the first temperature sensing resistor 601 overlaps with the gate electrode 401 in at least a portion of it in a plan view. For example, in a plan view, the first temperature sensing resistor 601 may overlap with the region where the source field plate electrode 501 and the gate electrode 401 overlap in at least a portion of it. Note that the first temperature sensing resistor 601 may not be provided in a region of the active region 701 that does not overlap with the source field plate electrode 501 and / or the gate electrode 401 in a plan view.

[0056] Furthermore, the end of the first temperature sensing resistor 601 on the source electrode 301 side (X-axis negative side) may be positioned closer to the drain electrode 302 side (X-axis positive side) than the end of the source field plate electrode 501 on the source electrode 301 side (X-axis negative side). Also, the end of the first temperature sensing resistor 601 on the drain electrode 302 side (X-axis positive side) may be positioned closer to the source electrode 301 side (X-axis negative side) than the end of the source field plate electrode 501 on the drain electrode 302 side (X-axis positive side). This can suppress the increase in parasitic capacitance caused by the first temperature sensing resistor 601. Note that the end of the first temperature sensing resistor 601 on the drain electrode 302 side (X-axis positive side) may be positioned closer to the source electrode 301 than the end of the second temperature sensing resistor 602 on the source electrode 301 side (X-axis negative side).

[0057] As shown in Figure 1, the first temperature sensing resistor 601 has a first temperature sensing portion 601a and a first connecting portion 601b so as to cover each of the multiple gate electrodes 401.

[0058] The first temperature sensing unit 601a has a rectangular shape that is elongated in the Y-axis direction so as to cover each of the multiple gate electrodes 401, with the direction of its longest side parallel to the Y-axis direction. For example, in a plan view, the direction of the longest side of the first temperature sensing unit 601a is parallel to the direction of the longest side (extension direction) of the gate electrode 401. Also, the plan view shape of the first temperature sensing resistor 601 is, for example, a rectangular shape that is elongated in the Y-axis direction. However, the plan view shape of the first temperature sensing resistor 601 is not limited to this.

[0059] The Y-axis negative end of the first temperature sensing unit 601a extends to the Y-axis negative end of the active region 701 (the boundary between the active region 701 and the inactive region 704). Furthermore, the Y-axis length of the first temperature sensing unit 601a is shorter than the Y-axis length L2 of the active region 701.

[0060] The first connecting portion 601b connects the ends of adjacent first temperature sensing units 601a. ​​The first connecting portion 601b is formed, for example, in an elongated shape in the X-axis direction, and connects a plurality of first temperature sensing units 601a in series.

[0061] The width (length in the X-axis direction) of the first temperature sensing resistor 601 is, for example, less than or equal to the width (length in the X-axis direction) of the source field plate electrode 501 and / or the width (length in the X-axis direction) of the gate electrode 401, but is not limited thereto. Also, the thickness (length in the Z-axis direction) of the first temperature sensing resistor 601 is, for example, less than or equal to the thickness (length in the Z-axis direction) of the source field plate electrode 501 and / or the thickness (length in the Z-axis direction) of the gate electrode 401, but is not limited thereto.

[0062] For example, the first temperature sensing resistor 601 is a single-layer electrode film containing Cu, but it is not limited to Cu; it may also be a single-layer electrode film containing one metal such as Ti, Al, Cu, Ni, Au, Pt, Pd, Ta, W, Si, Hf, or a multilayer electrode film composed of two or more of these metals, or an electrode film alloyed with these metals, or a conductive compound obtained by nitriding or oxidizing these metals, or a combination of these conductive compounds and the aforementioned electrode film. Furthermore, the first temperature sensing resistor 601 may be composed of the same metal as the electrodes such as the gate electrode 401, or it may be composed of a different metal.

[0063] The second temperature sensing resistor 602 is located within the active region 701 in a plan view and is provided on the second nitride semiconductor layer 104 (Z-axis positive side) in a cross-sectional view. It is a temperature sensing resistor used to detect the temperature of the transistor (FET), described later, as a change in resistance. The second temperature sensing resistor 602 detects the second temperature between the gate electrode 401 and the drain electrode 302. This makes it possible to determine, for example, whether or not abnormal heat generation is occurring due to Mg diffusion, dielectric film interface, etc., based on the second temperature. The transistor may also be a high-frequency amplification transistor.

[0064] In this embodiment, the second temperature sensing resistor 602 is provided on the second insulating layer 202, similar to the first temperature sensing resistor 601. The second temperature sensing resistor 602 is also positioned to measure the temperature (e.g., heat generation) between the gate electrode 401 and the drain electrode 302. The second temperature sensing resistor 602 is positioned, for example, between the gate electrode 401 and the drain electrode 302 in a plan view. The second temperature sensing resistor 602 is positioned, for example, in a region including the center between the gate electrode 401 and the drain electrode 302 in a plan view. The second temperature sensing resistor 602 does not have to overlap with the drain electrode 302 in a plan view, or it may have an overlapping portion. The second temperature sensing resistor 602 may also be positioned between the first temperature sensing resistor 601 and the drain electrode 302 in a plan view, or between the source field plate electrode 501 and the drain electrode 302. For example, the second temperature sensing resistor 602 may be positioned so as not to overlap with the first temperature sensing resistor 601 and the drain electrode 302 in a plan view, or so as not to overlap with the source field plate electrode 501 and the drain electrode 302. Alternatively, the second temperature sensing resistor 602 may be positioned so that, in a plan view, a portion of at least one of the source field plate electrode 501 and the drain electrode 302 overlaps with it.

[0065] The end of the second temperature sensing resistor 602 on the source electrode 301 side (X-axis negative side) may be positioned closer to the drain electrode 302 side (X-axis positive side) than the end of the source field plate electrode 501 on the drain electrode 302 side (X-axis positive side). Alternatively, the end of the second temperature sensing resistor 602 on the drain electrode 302 side (X-axis positive side) may be positioned closer to the source electrode 301 side (X-axis negative side) than the end of the drain electrode 302 on the source electrode 301 side (X-axis negative side).

[0066] The second temperature sensing resistor 602 has a second temperature sensing portion 602a and a second connecting portion 602b, which cover each of the spaces between the plurality of gate electrodes 401 and drain electrodes 302.

[0067] The second temperature sensing unit 602a has a rectangular shape that is elongated in the Y-axis direction, so as to cover each of the spaces between the multiple gate electrodes 401 and drain electrodes 302, with its longest side parallel to the Y-axis direction. For example, in a plan view, the longest side of the second temperature sensing unit 602a is parallel to the longest side (extension direction) of the gate electrode 401. The plan view shape of the second temperature sensing resistor 602 is, for example, a rectangular shape that is elongated in the Y-axis direction. However, the plan view shape of the second temperature sensing resistor 602 is not limited to this.

[0068] The Y-axis positive end of the second temperature sensing unit 602a extends to the Y-axis positive end of the active region 701 (the boundary between the active region 701 and the inactive region 704). Furthermore, the length of the second temperature sensing unit 602a in the Y-axis direction is shorter than the length L2.

[0069] The second connecting portion 602b connects the ends of adjacent second temperature sensing units 602a. The second connecting portion 602b is formed, for example, in an elongated shape in the X-axis direction, and connects a plurality of second temperature sensing units 602a in series.

[0070] The width (length in the X-axis direction) of the second temperature sensing resistor 602 is, for example, less than or equal to the width (length in the X-axis direction) of the source field plate electrode 501 and / or the width (length in the X-axis direction) of the gate electrode 401, but is not limited thereto. Also, the thickness (length in the Z-axis direction) of the second temperature sensing resistor 602 is, for example, less than or equal to the thickness (length in the Z-axis direction) of the source field plate electrode 501 and / or the thickness (length in the Z-axis direction) of the gate electrode 401, but is not limited thereto. For example, the width and thickness of the second temperature sensing resistor 602 may be the same as or different from the width and thickness of the first temperature sensing resistor 601.

[0071] For example, the second temperature sensing resistor 602 is a single-layer electrode film containing Cu, but it is not limited to Cu; it may also be a single-layer electrode film containing one metal such as Ti, Al, Cu, Ni, Au, Pt, Pd, Ta, W, Si, Hf, or a multilayer electrode film composed of two or more of these metals, or an electrode film alloyed with these metals, or a conductive compound obtained by nitriding or oxidizing these metals, or a combination of these conductive compounds and the aforementioned electrode film. Furthermore, the second temperature sensing resistor 602 may be composed of the same metal as the electrodes such as the gate electrode 401, or it may be composed of a different metal. Also, the second temperature sensing resistor 602 may be composed of the same metal as the first temperature sensing resistor 601, or it may be composed of a different metal.

[0072] Furthermore, the length of the second temperature detection unit 602a in the Y-axis direction is shorter than the length L2. Also, the width of the second temperature detection unit 602a in the X-axis direction may be equal to or different from the width of the first temperature detection unit 601a in the X-axis direction. Furthermore, the width of the second connection unit 602b in the Y-axis direction may be equal to or different from the width of the first connection unit 601b in the Y-axis direction.

[0073] Thus, the first temperature sensing resistor 601 and the second temperature sensing resistor 602 are each formed in a rectangular wave shape in a plan view. Furthermore, although the first temperature sensing resistor 601 and the second temperature sensing resistor 602 are arranged so as not to overlap in a plan view, they may be arranged so that a portion of them overlaps (for example, intersects in three dimensions) within the active region 701.

[0074] Although Figure 1 illustrates an example in which the first temperature detection unit 601a is provided for all of the multiple gate electrodes 401, the example is not limited to this, and it is sufficient if the first temperature detection unit 601a is provided for two or more gate electrodes 401. For example, the first temperature detection unit 601a may be provided for each of more than half of the multiple gate electrodes 401.

[0075] Note that in FIG. 1, an example is illustrated in which the second temperature detection unit 602a is disposed between each of the plurality of gate electrodes 401 and drain electrodes 302, but the present invention is not limited to this example, and it is sufficient that the second temperature detection unit 602a is disposed between two or more of them. For example, the second temperature detection unit 602a may be disposed between each of more than half of the plurality of them.

[0076] The third insulating layer 203 is provided on the second insulating layer 202, the first temperature detection resistor 601, and the second temperature detection resistor 602. The third insulating layer 203 is composed of at least one of SiN, SiO ２ , SiON, AlN, Al ２ O ３ , SiC, and C (diamond), and in the present embodiment, it is composed of SiN having a thickness of 200 nm. Further, the third insulating layer 203 may be composed of a single layer (single-layer film) or a laminate (laminated film).

[0077] The fourth insulating layer 204 is provided on the third insulating layer 203. The fourth insulating layer 204 is composed of at least one of SiN, SiO ２ , SiON, AlN, Al ２ O ３ , SiC, and C (diamond), and in the present embodiment, it is composed of SiN having a thickness of 200 nm. Further, the fourth insulating layer 204 may be composed of a single layer (single-layer film) or a laminate (laminated film).

[0078] The active region 701 is a region (a region on the substrate 101) where the two-dimensional electron gas layer 105 exists in a plan view. When the direction orthogonal to the long side direction of the gate electrode 401 is defined as the X-axis direction, the length of the active region 701 in the X-axis direction is L1. When the direction parallel to the long side direction of the gate electrode 401 is defined as the Y-axis direction, the length of the active region 701 in the Y-axis direction is L2. The X-axis direction is a direction orthogonal to the first direction in a plan view and is an example of the second direction.

[0079] Within the active region 701, an FET (for example, a high-frequency amplification transistor) is formed, which includes at least a source electrode 301, a drain electrode 302, and a gate electrode 401. In this embodiment, the FET is formed to include a source field plate electrode 501 in addition to the source electrode 301, drain electrode 302, and gate electrode 401.

[0080] The inactive region 704 is a region on the substrate 101 outside the active region 701 in a plan view, and is a region where the two-dimensional electron gas layer 105 does not exist. The inactive region 704 may be formed, for example, by implanting molecules containing any of He, B, H, F, and Fe, or by removing a portion of the second nitride semiconductor layer 104, the first nitride semiconductor layer 103, and the buffer layer 102, and implanting molecules containing any of He, B, H, F, and Fe into the remaining region. Alternatively, the inactive region 704 may be formed by removing a portion of the second nitride semiconductor layer 104, the first nitride semiconductor layer 103, and the buffer layer 102. Note that the absence of the two-dimensional electron gas layer 105 includes not only the complete absence of electrons, but also the substantially complete absence of electrons.

[0081] Thus, in a plan view, the substrate 101 is divided into an active region 701 having a two-dimensional electron gas layer 105 and an inactive region 704 lacking the two-dimensional electron gas layer 105. For example, in a plan view, the inactive region 704 is arranged in a frame shape surrounding the active region 701.

[0082] The first wiring layer 801 is provided on the fourth insulating layer 204. The first wiring layer 801 is a multilayer metal layer having a laminated structure in which Au layers are sequentially stacked on Ti layers, but is not limited to this.

[0083] The electrical connection between the source electrode 301 and the drain electrode 302 and the first wiring layer 801 is achieved by the first wiring layer 801 covering the source / drain electrode connection openings 801a, which are provided in the fourth insulating layer 204, the third insulating layer 203, the second insulating layer 202, and the first insulating layer 201, and which reach the source electrode 301 and the drain electrode 302.

[0084] The electrical connection between the source field plate electrode 501 and the source electrode 301 is achieved by the first wiring layer 801 covering the source field plate electrode connection opening 801b, which is provided in the fourth insulating layer 204, the third insulating layer 203, and the second insulating layer 202 and reaches the source field plate electrode 501. In a plan view, the source field plate electrode connection opening 801b is formed in the region outside the active region 701 (inactive region 704) on the Y-axis side.

[0085] The source electrode 301 and the source field plate electrode 501 are connected to a back metal (not shown) provided on the back surface of the substrate 101 via a source via hole 802 that reaches the back surface of the substrate 101, which is formed in the fourth insulating layer 204, third insulating layer 203, second insulating layer 202, first insulating layer 201, second nitride semiconductor layer 104, first nitride semiconductor layer 103, buffer layer 102, and substrate 101, in a plan view, on the Y-axis side outside the active region 701, and have a reference potential.

[0086] In a plan view, a drain terminal 803 is formed by the first wiring layer 801 in the Y-axis direction region of the inactive region 704, and this drain terminal 803 is connected to the drain electrode 302.

[0087] The electrical connection between the gate electrode 401 and the first wiring layer 801 (gate terminal 804) is achieved by the first wiring layer 801 covering the gate electrode connection opening 801c, which reaches the gate electrode 401 and is provided in the fourth insulating layer 204, the second insulating layer 202, and the first insulating layer 201, which are formed outside the Y-axis side (up-down direction on the plane of the paper) of the active region 701 in a plan view.

[0088] In a plan view, a gate terminal 804 is formed by the first wiring layer 801 in the region of the inactive region 704 that is opposite to the drain terminal 803 in the Y-axis direction of the active region 701 (the negative Y-axis side), and this gate terminal 804 is connected to the gate electrode 401.

[0089] The drain terminal 803 is connected to the drain electrode 302 via a source / drain electrode connection opening 801a in the Y-axis direction region of the region outside the active region 701 (inactive region 704). The drain terminal 803 is implemented as part of the first wiring layer 801.

[0090] The gate terminal 804 is connected to the gate electrode 401 via the gate electrode connection opening 801c. The gate terminal 804 is implemented as part of the first wiring layer 801.

[0091] The drain terminal 803 and gate terminal 804 are points that are electrically connected to the outside of the chip (for example, a mounting substrate or semiconductor package) by connecting wires or the like, and are connected, for example, to the drain electrode 302 or the gate electrode 401. Furthermore, the drain terminal 803 and gate terminal 804 are located, for example, in the inactive region 704, in a region that is aligned with the active region 701 in the direction of extension of the gate electrode 401 (Y-axis direction).

[0092] The source via hole 802 connects the first wiring layer 801, which is connected to the source electrode 301, to the back metal via the source / drain electrode connection opening 801a.

[0093] The first connection terminals 805 and 806 are located in the inactive region 704 and are connected to both ends of the first temperature sensing resistor 601. They are also connected by wires or the like to a temperature sensing processing unit (for example, the temperature sensing circuit 1210 shown in Figure 13, which will be described later) or electronic component outside the semiconductor device 1 (outside the chip, for example, on a mounting substrate or semiconductor package).

[0094] The electrical connection between the first connection terminals 805 and 806 and the first temperature sensing resistor 601 is achieved in the inactive region 704 by the first wiring layer 801 (for example, the first connection terminals 805 and 806) covering the opening 801d for connecting the first temperature sensing resistor, which is provided in the insulating layer between the first connection terminals 805 and 806 and the first temperature sensing resistor 601 and reaches the first temperature sensing resistor 601.

[0095] Furthermore, in this embodiment, no other elements (for example, electronic components) are connected between the first connection terminals 805 and 806 and the first temperature sensing resistor 601. The first connection terminals 805 and 806 and the first temperature sensing resistor 601 are directly connected without the use of other electronic components.

[0096] The second connection terminals 807 and 808 are located in the inactive region 704 and are connected to both ends of the second temperature sensing resistor 602, and are also connected by wires or the like to an external temperature sensing processing unit (for example, the temperature sensing circuit 1210 shown in Figure 13, which will be described later) or electronic component of the semiconductor device 1.

[0097] The electrical connection between the second connection terminals 807 and 808 and the second temperature sensing resistor 602 is achieved in the inactive region 704 by the first wiring layer 801 (for example, the second connection terminals 807 and 808) covering the opening 801e for connecting the second temperature sensing resistor, which reaches the second temperature sensing resistor 602 and is provided in the insulating layer between the second connection terminals 807 and 808 and the second temperature sensing resistor 602.

[0098] The first connection terminals 805 and 806 and the second connection terminals 807 and 808 are implemented, for example, as part of the first wiring layer 801. The first connection terminals 805 and 807 are arranged side by side in the Y-axis direction, and the first connection terminals 806 and 808 are arranged side by side in the Y-axis direction.

[0099] Furthermore, in this embodiment, no other elements (for example, electronic components) are connected between the second connection terminals 807 and 808 and the second temperature sensing resistor 602. The second connection terminals 807 and 808 and the second temperature sensing resistor 602 are directly connected without the use of other electronic components.

[0100] In this way, the first connection terminals 805 and 806 and the second connection terminals 807 and 808 are positioned on the X-axis side of the inactive region 704, relative to the gate terminal 804 and drain terminal 803 which are positioned in the Y-axis direction of the inactive region 704. This makes it possible to detect changes in the resistance values ​​of the first temperature sensing resistor 601 and the second temperature sensing resistor 602 with good responsiveness without interfering with the input signal from the gate terminal 804 and the output signal from the drain terminal 803 during high-frequency operation.

[0101] [1-2. Temperature Detection Characteristics] Next, the temperature detection characteristics of the semiconductor device 1 configured as described above will be explained with reference to Figures 3 to 6. Figure 3 is a diagram showing the relationship between the temperature between the gate and drain and the resistor detection temperature according to this embodiment. The temperature between the gate and drain is the temperature detected by the second temperature detection resistor 602. The detection on the gate shown in Figure 3 indicates the temperature detected by the first temperature detection resistor 601 (first temperature), and the detection between the gate and drain indicates the temperature detected by the second temperature detection resistor 602 (second temperature). The horizontal axis of Figure 3 shows the temperature between the gate and drain, and the vertical axis shows the resistor detection temperature, which is the temperature detected by the temperature detection resistor.

[0102] Generally, the first temperature in the gate region is said to be about 5 degrees higher than the second temperature between the gate and drain. However, if the temperature between the gate and drain is uniformly set to 5 degrees lower than the temperature detected by the first temperature sensing resistor 601, for example, the measurement accuracy is low because it is not the actual temperature.

[0103] On the other hand, in this embodiment, as shown in Figure 3, by newly providing a second temperature sensing resistor 602, the actual temperature between the gate and drain can be detected, thereby improving measurement accuracy.

[0104] Next, the materials of the first temperature sensing resistor 601 and the second temperature sensing resistor 602 will be described with reference to Figures 4 and 5. First, the configuration of the semiconductor device for single-finger temperature detection to compare the electrical resistance (resistance value) of the temperature sensing resistors will be described with reference to Figure 4. Figure 4 is a plan view showing the configuration of the semiconductor device 2 for single-finger temperature detection according to this embodiment. Note that the semiconductor device in this disclosure may be a semiconductor device 2 for single-finger temperature detection. In other words, the semiconductor device 2 is included in this disclosure. Single-finger means having one first temperature sensing unit 611a and one second temperature sensing unit 612a as temperature sensing resistors.

[0105] As shown in Figure 4, the semiconductor device 2 includes a first temperature sensing resistor 611 and a second temperature sensing resistor 612 as temperature sensing resistors. Specifically, the semiconductor device 2 includes one first temperature sensing unit 611a, a first connection unit 611b connecting both ends of the first temperature sensing unit 611a to first connection terminals 805 and 806, one second temperature sensing unit 612a, and a second connection unit 612b connecting both ends of the second temperature sensing unit 612a to second connection terminals 807 and 808.

[0106] In this case, the length of the first temperature detection unit 611a and the second temperature detection unit 612a in the Y-axis direction may be length L2. For example, the first temperature detection unit 611a and the second temperature detection unit 612a may be arranged from one end to the other in the Y-axis direction of the active region 701.

[0107] Figure 5 is a diagram showing the relationship between the gate temperature and the electrical resistance of the first temperature sensing resistor 601 according to this embodiment. The horizontal axis of Figure 5 shows the gate temperature (first temperature) detected by the first temperature sensing resistor 601, and the vertical axis shows the electrical resistance of the first temperature sensing resistor 601. The resistance value range and other specifications shown below are the same for the second temperature sensing resistor 602.

[0108] The detection point in the first temperature sensing resistor 601 shown in Figure 1 is indicated by "●", and the detection point in the first temperature sensing resistor 611 shown in Figure 4 is indicated by "□". Furthermore, the results when the first temperature sensing resistor is formed using Cu are shown by a solid line, the results when it is formed using Al are shown by a dashed line, and the results when it is formed using Pt are shown by a dotted line. In addition, in order to accurately detect temperature, the electrical resistance of the temperature sensing resistor should be 100Ω or more. Furthermore, the upper limit of the electrical resistance of a temperature sensing resistor that can be measured by current adjustment, etc., is approximately 3000Ω. For this reason, in this specification, the electrical resistance that can be used as a temperature sensing resistor is 100Ω or more and 3000Ω or less.

[0109] Furthermore, the volume resistivity (μΩcm) of Cu, Al, and Pt is set to 1.55, 2.5, and 9.81, and the temperature coefficient (1 / °C) within the active region 701 of Cu, Al, and Pt is set to 0.00393, 0.00390, and 0.00300. The temperature coefficient outside the active region 701 (i.e., the inactive region 704) is calculated at 80% of the above values. In addition, the width xa1 of the first temperature sensing portion 601a of the first temperature sensing resistor 601 of the semiconductor device 1 is set to 1.6 μm and the length ya1 to 1.35 mm, and the width yb1 of the first connecting portion 601b is set to 1.6 μm and the length xb1 to 0.65 mm. The width xa3 of the first temperature detection section 611a and the width xa4 of the second temperature detection section 612a of the semiconductor device 2 are set to 1.6 μm, and the length ya3 of the first temperature detection section 611a and the length ya4 of the second temperature detection section 612a are set to 1.5 mm. The thickness of each temperature detection resistor is set to 450 nm.

[0110] As shown in Figure 5, in semiconductor device 2, of Cu, Al, and Pt, only Pt satisfies the electrical resistance requirement of 100 Ω to 3000 Ω. On the other hand, in semiconductor device 1, the electrical resistance can be increased by connecting multiple first temperature sensing units 601a in series, so all of Cu, Al, and Pt satisfy the electrical resistance requirement of 100 Ω to 3000 Ω.

[0111] Thus, in the semiconductor device 1, by connecting multiple first temperature sensing units 601a in series to increase the electrical resistance, the range of materials that can be used for the first temperature sensing resistor 601 can be expanded compared to a single finger. For example, it becomes possible to use the same material used for the electrodes as the material for the first temperature sensing resistor 601.

[0112] Furthermore, since each of Cu, Al, and Pt in semiconductor device 1 satisfies the requirement of having an electrical resistance of 100 Ω or more and 3000 Ω or less, it is considered that the electrical resistance of an alloy containing at least two of Cu, Al, and Pt also satisfies the requirement of 100 Ω or more and 3000 Ω or less. Therefore, in semiconductor device 1, it is possible to use an alloy containing at least two of Cu, Al, and Pt as the material for the temperature sensing resistor. Note that the alloy may also contain metallic materials other than Cu, Al, and Pt, as long as its electrical resistance satisfies the requirement of 100 Ω or more and 3000 Ω or less.

[0113] Figure 5 shows the electrical resistance when the first temperature sensing resistor 601 is of the above size. Other materials can be used by adjusting the size so that the electrical resistance is between 100 Ω and 3000 Ω. In addition, in the semiconductor device 2, it is possible to use Al by adjusting the size of the first temperature sensing resistor 611 so that, for example, the electrical resistance of Al is 100 Ω or more.

[0114] Next, the range of the width xa1 of the first temperature sensing unit 601a will be explained with reference to Figure 6. Figure 6 is a diagram showing the relationship between the resistor width (width xa1) and the electrical resistance / volume resistivity of the first temperature sensing resistor 601 according to this embodiment. Note that the electrical resistance is the electrical resistance of the first temperature sensing resistor 601 when the gate temperature is 150 degrees. Also, the width yb1 is the same size as the width xa1, and the sizes other than width yb1 and width xa1 are the sizes described above. Since division by volume resistivity is performed, differences in electrical resistance due to material factors can be excluded. Also, if the volume resistivity of Cu is 1.55, the range in which the electrical resistance is between 100Ω and 3000Ω is within the range of the square frame.

[0115] As shown in Figure 6, if the resistor width (width x a1) is 0.5 μm or more and 7 μm or less, it satisfies the range of the square frame and can therefore be used as a resistor for temperature sensing. Note that the resistor width may be within any two values ​​between 0.5 μm and 7 μm. For example, the resistor width may be 1 μm or more and 6 μm or less, 2 μm or more and 5 μm or less, 3 μm or more and 4 μm or less, or any other range.

[0116] Furthermore, width xa2 is the same length as width xa1, and width yb2 is the same length as width yb1. Also, lengths ya1 and ya2 are the same length, and for example, are shorter than length L2.

[0117] (Embodiment 2) The semiconductor device according to this embodiment will be described below with reference to Figures 7 and 8. In the following description, the differences from Embodiment 1 will be the main focus, and the same or similar content as in Embodiment 1 will be omitted or simplified.

[0118] [2-1. Configuration of the Semiconductor Device] First, the configuration of the semiconductor device according to this embodiment will be described with reference to Figure 7. Figure 7 is a plan view showing the configuration of the semiconductor device 3 according to this embodiment. The semiconductor device 3 according to this embodiment differs from the semiconductor device 1 according to Embodiment 1 in that the first temperature sensing resistor 621 and the second temperature sensing resistor 622 are also formed in the inactive region 704.

[0119] As shown in Figure 7, the semiconductor device 3 is equipped with a first temperature sensing resistor 621 and a second temperature sensing resistor 622 in place of the first temperature sensing resistor 601 and the second temperature sensing resistor 602 of the semiconductor device 1 according to Embodiment 1.

[0120] Parts of the first temperature sensing resistor 621 and the second temperature sensing resistor 622 are formed on an inactive region 704 in a plan view (specifically, an inactive region 704 formed on the Y-axis positive side and Y-axis negative side of the active region 701). The first temperature sensing portion 621a of the first temperature sensing resistor 621 has a first portion 621a1 that extends in the Y-axis direction and is arranged from one end to the other in the Y-axis direction within the active region 701, and a second portion 621a2 that is arranged outside the active region 701. Part of the first connecting portion 621b of the first temperature sensing resistor 621 is arranged outside the active region 701.

[0121] In the example shown in Figure 7, the first temperature sensing unit 621a is formed extending from the Y-positive end of the active region 701 to the Y-negative end of the inactive region 704, and its length ya5 ​​is longer than its length L2. The first connection portion 621b on the Y-positive side is formed within the active region 701 along the Y-positive end of the active region 701 (along the X-axis), while the first connection portion 621b on the Y-negative side is formed in the inactive region 704 (i.e., outside the active region 701) along the Y-negative end of the active region 701 (along the X-axis).

[0122] Furthermore, the second temperature sensing portion 622a of the second temperature sensing resistor 622 has a third portion 622a1 that extends in the Y-axis direction and is arranged from one end to the other in the Y-axis direction within the active region 701, and a fourth portion 622a2 that is arranged outside the active region 701. A portion of the second connection portion 622b of the second temperature sensing resistor 622 is located outside the active region 701.

[0123] In the example shown in Figure 7, the second temperature sensing section 622a is formed extending from the negative Y-axis end of the active region 701 to the positive Y-axis end of the inactive region 704, and its length ya6 is longer than its length L2. The second connection section 622b on the negative Y-axis side is formed within the active region 701 along the negative Y-axis end of the active region 701 (along the X-axis), while the second connection section 622b on the positive Y-axis side is formed in the inactive region 704 (i.e., outside the active region 701) along the positive Y-axis end of the active region 701 (along the X-axis).

[0124] Thus, in the semiconductor device 3, the Y-axis length ya5 ​​of the plurality of first temperature detection units 621a and the Y-axis length ya6 of the plurality of second temperature detection units 622a are longer than the Y-axis length L2 of the active region 701, and at least a portion of the plurality of first connection units 621b and the plurality of second connection units 622b are arranged in the inactive region 704 located on the Y-axis side of the active region 701.

[0125] This makes it possible to detect the temperature near the gate electrode 401 and between the gate and drain over the entire area within the active region 701.

[0126] [2-2. Temperature Detection Characteristics] Next, the temperature detection performance of the semiconductor device 3 configured as described above will be explained with reference to Figure 8. Figure 8 is a diagram showing the relationship between the gate temperature and the electrical resistance of the first temperature detection resistor 621 according to this embodiment. The horizontal axis in Figure 8 represents the gate temperature, and the vertical axis represents the electrical resistance of the first temperature detection resistor 621. When the first temperature detection resistor 621 is placed in the inactive region 704, there is concern that the temperature detection sensitivity (an example of detection characteristics) will decrease. Therefore, Figure 8 compares the temperature detection sensitivity of the semiconductor device 1 shown in Figure 1 and the semiconductor device 3 shown in Figure 7. The detection sensitivity is the slope (resistance change rate) connecting each detection point when the horizontal axis is the gate temperature and the vertical axis is the electrical resistance.

[0127] The length ya5 ​​of the first temperature sensing portion 621a of the first temperature sensing resistor 621 of the semiconductor device 3 is 1.65 mm, and the length xb5 of the first connecting portion 621b is 0.65 mm. Of the first temperature sensing portion 621a, the length in the Y-axis direction of the first portion 621a1 is 1.5 mm, and the length in the Y-axis direction of the second portion 621a2 is 0.15 mm.

[0128] As shown in Figure 8, the detection sensitivity of semiconductor device 1 (series (Cu) (601)) is 0.2884% / °C, while the detection sensitivity of semiconductor device 3 (series (Cu) (621)) is 0.2865% / °C. In other words, with the above dimensions, even if a part of the first temperature sensing resistor 621 is placed in the inactive region 704, the influence of temperature on the detection sensitivity is low.

[0129] (Embodiment 3) The semiconductor device according to this embodiment will be described below with reference to Figures 9 to 11. In the following description, the differences from Embodiment 2 will be the main focus, and the same or similar content as in Embodiment 2 will be omitted or simplified.

[0130] [3-1. Configuration of the Semiconductor Device] First, the configuration of the semiconductor device according to this embodiment will be described with reference to Figure 9. Figure 9 is a plan view showing the configuration of the semiconductor device 4 according to this embodiment. The semiconductor device 4 according to this embodiment differs from the semiconductor device 3 according to Embodiment 2 in that the first temperature sensing resistor 631 and the second temperature sensing resistor 632 are also formed in the inactive regions 704 located on the positive and negative sides in the Y-axis direction, and the first connection portion 631b and the second connection portion 632b are wider (longer in the Y-axis direction) than the first connection portion 621b and the second connection portion 622b.

[0131] As shown in Figure 9, the semiconductor device 4 is equipped with a first temperature sensing resistor 631 and a second temperature sensing resistor 632 in place of the first temperature sensing resistor 621 and the second temperature sensing resistor 622 of the semiconductor device 3 according to Embodiment 2.

[0132] Parts of the first temperature sensing resistor 631 and the second temperature sensing resistor 632 are formed on an inactive region 704 in a plan view (specifically, an inactive region 704 formed on the Y-axis positive side and Y-axis negative side of the active region 701). The first temperature sensing portion 631a of the first temperature sensing resistor 631 has a first portion that is arranged from one end to the other in the Y-axis direction within the active region 701, and a second portion that is arranged outside the active region 701. The first connecting portion 631b of the first temperature sensing resistor 631 is located in the inactive region 704.

[0133] In the example shown in Figure 9, the first temperature sensing unit 631a is formed extending from the Y-positive end of the active region 701 to the Y-negative end of the inactive region 704, and is longer than length L2. The first connecting units 631b on the Y-positive and Y-negative sides are formed in the inactive region 704 (i.e., outside the active region 701) along the Y-axis end of the active region 701 (along the X-axis).

[0134] Furthermore, the second temperature sensing portion 632a of the second temperature sensing resistor 632 has a third portion that is positioned from one end to the other in the Y-axis direction within the active region 701, and a fourth portion that is positioned outside the active region 701. The second connection portion 632b of the second temperature sensing resistor 632 is positioned in the inactive region 704.

[0135] Here, the Y-axis width yb7 of the first connection portion 631b is greater than the X-axis width xa7 of the first temperature detection portion 631a, for example, it may be more than twice the width xa7, more than three times the width xa7, or more than four times the width xa7. Also, the Y-axis width yb8 of the second connection portion 632b is greater than the X-axis width xa8 of the second temperature detection portion 632a, for example, it may be more than twice the width xa8, more than three times the width xa8, or more than four times the width xa8.

[0136] For example, in the semiconductor device 3 according to Embodiment 2, the widths of the first connection portion 621b and the second connection portion 622b, which are located in the inactive region 704, may be made larger, as shown in the semiconductor device 4.

[0137] [3-2. Temperature Detection Characteristics] Next, the temperature detection performance of the semiconductor device 4 configured as described above will be explained with reference to Figures 10 and 11. Figure 10 is a diagram showing the relationship between the gate temperature and the electrical resistance of the first temperature detection resistor 631 according to this embodiment. In addition, for comparison, the rate of change of resistance of semiconductor devices 1 and 3 is also shown in Figure 10. The width yb7 is 4.8 μm and the width xa7 is 1.6 μm.

[0138] As shown in Figure 10, by making the width yb7 of the first connection portion 631b three times the width xa7, the detection sensitivity increases from 0.2865% / °C (series (Cu) (621)) to 0.2917% / °C (series (Cu) (631)). In this way, by making the width yb7 of the first connection portion 631b larger than the width xa7, the resistance value of the first connection portion 631b provided outside the active region 701 of the first temperature sensing resistor 631 is reduced, and the detection sensitivity is improved.

[0139] Next, the range of the width yb7 will be explained with reference to Figure 11. Figure 11 is a diagram showing the relationship between the resistor width (width yb7) and the rate of change of resistance according to this embodiment. The horizontal axis in Figure 11 shows the width yb7 in the X-axis direction, and the vertical axis shows the rate of change of resistance (i.e., detection sensitivity). Figure 11 also shows the rate of change of resistance of the first temperature sensing resistor 601 of the semiconductor device 1. The rectangular frame in Figure 11 indicates the range in which the rate of change of resistance is higher than that of the first temperature sensing resistor 601, that is, the detection sensitivity is higher than that of the first temperature sensing resistor 601.

[0140] As shown in Figure 11, the rate of change of resistance of the first temperature sensing resistor 631 tends to increase as the width yb7 of the first connection portion 631b increases. In order to make the rate of change of resistance of the first temperature sensing resistor 631 equal to or greater than that of the first temperature sensing resistor 601, the width yb7 should be 2.5 μm or more. The rate of change of resistance when the width yb7 is 2.5 μm is 0.289% / °C.

[0141] From the above, the width yb7 is preferably 2.5 μm or more, for example, preferably 3 μm or more, more preferably 3.5 μm or more, and even more preferably 4 μm or more.

[0142] (Embodiment 4) The semiconductor device according to this embodiment will be described below with reference to Figure 12. In the following description, the differences from Embodiment 1 will be the main focus, and the same or similar content as in Embodiment 1 will be omitted or simplified.

[0143] [4-1. Configuration of the Semiconductor Device] The configuration of the semiconductor device according to this embodiment will be described with reference to Figure 12. Figure 12 is a cross-sectional view showing the configuration of the semiconductor device 5 according to this embodiment, corresponding to line II-II in Figure 1.

[0144] As shown in Figure 12, in this embodiment, the semiconductor device 5 has a gate electrode 401 provided on the second nitride semiconductor layer 104 in contact with the second nitride semiconductor layer 104. In other words, the semiconductor device 5 does not necessarily have to include a third nitride semiconductor layer 106.

[0145] In a semiconductor device 5 having a configuration in which the gate electrode 401 is directly formed on such a second nitride semiconductor layer 104, the temperature detection accuracy can be improved by arranging a first temperature sensing resistor 601 and a second temperature sensing resistor 602, similar to the embodiments described above.

[0146] (Embodiment 5) The semiconductor module according to this embodiment will be described below with reference to Figures 13 and 14.

[0147] [5-1. Configuration of the Semiconductor Module] First, the configuration of the semiconductor module according to this embodiment will be described with reference to Figure 13. Figure 13 is a diagram showing the configuration of the semiconductor module 1000 according to this embodiment. In Figure 13, an example is shown in which the semiconductor module 1000 is equipped with the semiconductor device 1 according to Embodiment 1, but for example, the semiconductor device 1 may be replaced with any of the semiconductor devices 2 to 5.

[0148] As shown in Figure 13, the semiconductor module 1000 comprises a semiconductor device 1, a control device 1200, and a cooling fan 1300. The semiconductor device 1, the control device 1200, and the cooling fan 1300 may be mounted on a single mounting substrate, or they may be mounted separately on different mounting substrates.

[0149] The semiconductor device 1 comprises an FET (transistor) 1100 and temperature sensing resistors (a first temperature sensing resistor 601 and a second temperature sensing resistor 602).

[0150] The control device 1200 is a processing device that performs control on the semiconductor device 1 based on the resistance value of a temperature-sensing resistor (for example, a change in resistance value). The control device 1200 includes a temperature sensing circuit 1210, a control circuit 1220, a driver circuit 1230, and a fan drive circuit 1240.

[0151] The temperature sensing circuit 1210 is connected to the first connection terminals 805 and 806 and the second connection terminals 807 and 808 by wires or the like, and detects the temperature near the gate electrode 401 and between the gate and drain based on the resistance values ​​of the temperature sensing resistors. Specifically, the temperature sensing circuit 1210 detects a first temperature near the gate electrode 401 based on the resistance value of the first temperature sensing resistor 601, and detects a second temperature between the gate and drain based on the resistance value of the second temperature sensing resistor 602.

[0152] The control circuit 1220 controls the semiconductor device 1 based on the detection result of the temperature detection circuit 1210. Specifically, the control circuit 1220 generates and outputs a control signal to control at least one of the driver circuit 1230 and the fan drive circuit 1240 based on the detection result of the temperature detection circuit 1210.

[0153] The driver circuit 1230 controls the operation (on, off, etc.) of the FET 1100 based on the control signal from the control circuit 1220.

[0154] The fan drive circuit 1240 controls the operation (on, off, airflow, etc.) of the cooling fan 1300 for cooling the FET 1100 based on a control signal from the control circuit 1220.

[0155] The cooling fan 1300 is a fan for cooling the semiconductor device 1.

[0156] [5-2. Operation of the Semiconductor Module] Next, the operation of the semiconductor module 1000 configured as described above will be explained with reference to Figure 14. Figure 14 is a flowchart showing the operation (control method) of the semiconductor module 1000 according to this embodiment. Figure 14 shows the operation of the control device 1200.

[0157] As shown in Figure 14, the temperature detection circuit 1210 of the control device 1200 acquires the resistance values ​​of the temperature detection resistors (S10). The temperature detection circuit 1210 acquires the resistance values ​​of the first temperature detection resistor 601 and the second temperature detection resistor 602 by individually supplying current to each of them. The timing at which the temperature detection circuit 1210 acquires the resistance values ​​is not particularly limited and may, for example, be acquired periodically.

[0158] Next, the temperature detection circuit 1210 detects a temperature rise based on the first resistance value of the first temperature detection resistor 601 and the second resistance value of the second temperature detection resistor 602 acquired in step S10 (S20). The temperature detection circuit 1210 converts the first resistance value to a first temperature and the second resistance value to a second temperature, and detects a temperature rise based on the converted first and second temperatures. The temperature detection circuit 1210 outputs the detected temperature to the control circuit 1220. A conversion table for converting between resistance values ​​and temperatures is pre-set.

[0159] The control circuit 1220 determines whether the temperature is below the upper limit of the control (S30). The upper limit of the control is a temperature that guarantees the quality of the FET 1100, and may be a temperature that does not immediately cause the FET 1100 to fail even if it exceeds the upper limit of the control. The upper limit of the control is set in advance. The upper limit of the control is an example of a first threshold.

[0160] The control circuit 1220 performs the determination in step S30 based on the first temperature and the second temperature. The control circuit 1220 may perform the determination in step S30 for each of the first temperature and the second temperature, or it may perform the determination in step S30 for a representative temperature based on the first temperature and the second temperature. The representative temperature may be, for example, the higher of the first temperature and the second temperature, one temperature selected from the first temperature and the second temperature (for example, the temperature set to be used preferentially), or a temperature obtained by calculating the first temperature and the second temperature (for example, the average temperature). Note that the representative temperature is not limited to one temperature but may include two temperatures.

[0161] Next, if the temperature is below the upper limit of the control (Yes in S30), the control circuit 1220 controls the driver circuit 1230 to increase the gate voltage (S40). Si devices may experience thermal runaway and therefore their output needs to be reduced, but GaN devices are less prone to thermal runaway than Si devices. Therefore, in step S40, the control circuit 1220 controls the current to flow in a direction that does not reduce power, that is, to maintain the output of the FET 1100.

[0162] Furthermore, if the temperature is higher than the upper limit of control (No in S30), the control circuit 1220 further determines whether the temperature is below a limit value (S50). The limit value is a temperature higher than the upper limit of control, and may be, for example, a temperature that, if exceeded, could cause the FET 1100 to fail. The limit value is an example of a second threshold value.

[0163] Next, if the temperature is below a limit value (Yes in S50), the control circuit 1220 increases the gate voltage and the current (drive current) of the cooling fan 1300 (S60). In step S60, the control circuit 1220 controls the FET 1100 to maintain its output, as well as to lower the temperature of the FET 1100, that is, to increase the output of the cooling fan 1300. In step S60, the control circuit 1220 only needs to control the cooling fan 1300 to increase the current (drive current).

[0164] Furthermore, if the temperature exceeds the limit value (No in S50), the control circuit 1220 controls the driver circuit 1230 to turn off the gate voltage (S70). In other words, the control circuit 1220 stops the output of the FET 1100.

[0165] The control circuit 1220 may, for example, determine Yes in step S30 if both the first temperature and the second temperature are below the management upper limit, determine Yes in step S50 if both the first temperature and the second temperature are below the limit value and at least one of the first temperature and the second temperature is above the management upper limit, and determine No in step S50 if at least one of the first temperature and the second temperature is above the limit value. Furthermore, the control circuit 1220 may execute different countermeasures depending on whether the first temperature or the second temperature exceeds the management upper limit or the limit value.

[0166] (Other Embodiments) Although semiconductor devices, etc., according to one or more embodiments have been described above based on Embodiments 1 to 5 (each embodiment), this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications that a person skilled in the art could conceive of may be applied to these embodiments, and forms constructed by combining components from different embodiments may also be included in this disclosure.

[0167] For example, the first temperature sensing resistor and the second temperature sensing resistor in each of the above embodiments are not limited to being provided on the second insulating layer; for example, the first temperature sensing resistor may be provided on the first insulating layer. For example, the first temperature sensing resistor may be provided on the second insulating layer, and the second temperature sensing resistor may be provided below the second insulating layer.

[0168] Furthermore, the lengths in the Y-axis direction of the first temperature detection unit and the second temperature detection unit according to each of the above embodiments are not limited to the lengths shown in each figure. For example, the lengths in the Y-axis direction of the first temperature detection unit and the second temperature detection unit may be 2 / 3 or less, half or less, or 1 / 3 or less of the length in the Y-axis direction of the active region.

[0169] Furthermore, in each of the above embodiments, each component may be implemented by being composed of dedicated hardware or by executing a software program suitable for each component. Each component may also be implemented by a program execution unit such as a CPU or processor reading and executing a software program recorded on a recording medium such as a hard disk or semiconductor memory.

[0170] Furthermore, the order in which each step in the flowchart is performed is illustrative for the purpose of specifically illustrating this disclosure, and may be in a different order. Also, some of the above steps may be performed simultaneously (in parallel) with other steps, and some of the above steps may not be performed.

[0171] Furthermore, the division of functional blocks in the block diagram is just one example; multiple functional blocks can be implemented as a single functional block, a single functional block can be divided into multiple parts, or some functions can be moved to other functional blocks. In addition, the functions of multiple functional blocks with similar functions can be processed in parallel or time-sharing by a single piece of hardware or software.

[0172] Furthermore, each component described in the above embodiments may be implemented as software, or typically as an integrated circuit (LSI). These may be individually integrated onto a single chip, or some or all of them may be integrated onto a single chip. Here, we refer to it as an LSI, but depending on the degree of integration, it may also be called an IC, system LSI, super LSI, or ultra LSI. Moreover, the method of integrated circuit implementation is not limited to LSIs; it may also be implemented using a dedicated circuit (a general-purpose circuit that executes a dedicated program) or a general-purpose processor. After LSI manufacturing, a programmable FPGA (Field Programmable Gate Array) or a reconfigurable processor that can reconfigure the connections or settings of circuit cells inside the LSI may be used. Furthermore, if an integrated circuit implementation technology that replaces LSIs emerges due to advances in semiconductor technology or other derived technologies, it is natural that the components may be integrated using that technology.

[0173] Furthermore, one aspect of this disclosure may be a computer program that causes a computer to execute each characteristic step included in the control method shown in Figure 14.

[0174] Furthermore, for example, the program may be a program to be executed by a computer. Also, in one aspect of this disclosure, such a program may be recorded on a computer-readable non-temporary recording medium. For example, such a program may be recorded on a recording medium and distributed or made available. For example, by installing the distributed program on a device having another processor and having that processor execute the program, it becomes possible to have that device perform the above-mentioned processes.

[0175] (Note) The following technologies are disclosed based on the descriptions of each embodiment above.

[0176] (Technical 1) A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a two-dimensional electron gas layer provided near the boundary between the first nitride semiconductor layer and the second nitride semiconductor layer; a source electrode and a drain electrode provided on the second nitride semiconductor layer at intervals and each electrically connected to the first nitride semiconductor layer; and a gate electrode provided on the second nitride semiconductor layer at intervals from the source electrode and the drain electrode, wherein the substrate has an active region and an inactive region, and further comprises: a first temperature sensing resistor for sensing a first temperature near the gate electrode in the active region; and a second temperature sensing resistor for sensing a second temperature between the gate electrode and the drain electrode in the active region.

[0177] This allows for the detection of a second temperature between the gate and drain, in addition to the first temperature near the gate electrode. Compared to detecting the second temperature using a resistor for first temperature detection, the temperature between the gate and drain can be detected with greater accuracy. Therefore, the temperature detection accuracy can be improved.

[0178] (Technical 2) In a plan view, if the direction in which the gate electrode extends is defined as the first direction, and the direction perpendicular to the first direction in the plan view is defined as the second direction, the semiconductor device comprises a plurality of gate electrodes and a plurality of drain electrodes arranged in the second direction, the first temperature sensing resistor has a plurality of first temperature sensing units extending over the plurality of gate electrodes in the active region and a first connection unit connecting the plurality of first temperature sensing units in series, and the second temperature sensing resistor has a plurality of second temperature sensing units extending between the plurality of gate electrodes and the plurality of drain electrodes in the active region and a second connection unit connecting the plurality of second temperature sensing units in series, the semiconductor device according to Technical 1.

[0179] As a result, a first temperature detection unit is provided on multiple gate electrodes, and a second temperature detection unit is provided between multiple gate electrodes and drain electrodes, thereby suppressing the oversight of temperature-related abnormalities.

[0180] (Technical 3) The semiconductor device described in Technical 2, wherein the first temperature sensing resistor and the second temperature sensing resistor are arranged so as not to overlap in the plan view.

[0181] This allows the first temperature sensing resistor and the second temperature sensing resistor to be formed in a single wiring formation process, thereby reducing manufacturing costs.

[0182] (Technical 4) The semiconductor device according to Technical 2 or 3, wherein the plurality of first temperature sensing units have a first portion extending to both ends in the first direction within the active region and a second portion provided outside the active region, the plurality of second temperature sensing units have a third portion extending to both ends in the first direction within the active region and a fourth portion provided outside the active region, and the first connection portion and the second connection portion are provided outside the active region.

[0183] This makes it possible to detect abnormalities across both ends of the first direction within the active region.

[0184] (Technical 5) The semiconductor device according to Technical 4, satisfying at least one of the following: the width in the second direction of the first connection portion is greater than the width in the first direction of the first temperature sensing portion, and the width in the second direction of the second connection portion is greater than the width in the first direction of the second temperature sensing portion.

[0185] This reduces the resistance of the connection points located outside the active regions of the first and second temperature sensing resistors, thereby improving the accuracy of temperature detection.

[0186] (Technical 6) The semiconductor device according to Technical 5, wherein the line width in the second direction of at least one of the first connection portion and the second connection portion is 2.5 μm or more.

[0187] This allows the resistance value of the connection portion located outside the active region of the first and second temperature sensing resistors to be reduced compared to the case where the line width is less than 2.5 μm, thereby improving the temperature detection accuracy.

[0188] (Technical 7) The semiconductor device according to any one of Technical 1 to 6, wherein the first temperature sensing resistor and the second temperature sensing resistor are made of an alloy containing Al, Au, Cu, or at least one of them.

[0189] This allows the first temperature sensing resistor and the second temperature sensing resistor to be manufactured using materials that can normally be used as electrode materials.

[0190] (Technical 8) The first temperature sensing resistor and the second temperature sensing resistor are semiconductor devices according to any one of Technical 1 to 7, wherein the resistor width within the active region is in the range of 0.5 μm to 7 μm.

[0191] This allows the resistance values ​​of the first and second temperature sensing resistors to be set within a range suitable for temperature detection, thereby improving the accuracy of temperature detection.

[0192] (Technical 9) A semiconductor device according to any one of Technical 1 to 8, further comprising a P-type doped third nitride semiconductor layer near the gate electrode.

[0193] This makes it possible to improve the temperature detection accuracy in semiconductor devices that have a third nitride semiconductor layer near the gate electrode.

[0194] (Technical 10) A semiconductor device according to any one of Technical 1 to 9, further comprising a source field plate electrode electrically connected to the source electrode.

[0195] This makes it possible to improve the temperature detection accuracy in semiconductor devices equipped with source field plate electrodes.

[0196] (Technical 11) A control method comprising: converting the resistance value of the first temperature sensing resistor provided in the semiconductor device described in any one of Technical 1 to 10 to a first temperature; converting the resistance value of the second temperature sensing resistor provided in the semiconductor device to a second temperature; increasing the gate voltage when the representative temperature based on the first and second temperatures is less than or equal to a first threshold; increasing the gate voltage and increasing the drive current of the cooling fan when the representative temperature is greater than or equal to the first threshold and less than or equal to a second threshold higher than the first threshold; and turning off the gate voltage when the representative temperature is higher than the second threshold.

[0197] This allows for the detection of abnormalities based on the first and second temperatures, and enables the system to perform actions in response to these abnormalities.

[0198] These general or specific embodiments may be implemented using a system, method, integrated circuit, computer program, or a non-temporary recording medium such as a computer-readable CD-ROM, or any combination of a system, method, integrated circuit, computer program, or recording medium. The program may be pre-stored on the recording medium or supplied to the recording medium via a wide-area communication network, including the Internet.

[0199] This disclosure is useful for semiconductor devices that include field-effect transistors and the like.

[0200] 1, 2, 3, 4, 5 Semiconductor device 101 Substrate 102 Buffer layer 103 First nitride semiconductor layer 104 Second nitride semiconductor layer 105 Two-dimensional electron gas layer 106 Third nitride semiconductor layer 201 First insulating layer 202 Second insulating layer 203 Third insulating layer 204 Fourth insulating layer 301 Source electrode 302 Drain electrode 401 Gate electrode 501 Source field plate electrode (field plate) 601, 611, 621, 631 First temperature sensing resistor 601a, 611a, 621a, 631a First temperature sensing unit 601b, 611b, 621b, 631b First connection unit 602, 612, 622, 632 Second temperature sensing resistor 602a, 612a, 622a, 632a Second temperature sensing section 602b, 612b, 622b, 632b Second connection section 621a1 First part 621a2 Second part 622a1 Third part 622a2 Fourth part 701 Active region 704 Inactive region 801 First wiring layer 801a Opening for source / drain electrode connection 801b Opening for source field plate electrode connection 801c Opening for gate electrode connection 801d Opening for first temperature sensing resistor connection 801e Opening for second temperature sensing resistor connection 802 Source via hole 803 Drain terminal 804 Gate terminal 805, 806 First connection terminals 807, 808 Second connection terminals 1000 Semiconductor module 1100 FET 1200 Control device 1210 Temperature sensing circuit 1220 Control circuit 1230 Driver circuit 1240 Fan drive circuit 1300 Cooling fan L1, L2, xb1, xb5, ya1, ya2, ya3, ya4, ya5, ya6 Length xa1, xa2, xa3, xa4, xa7, xa8, yb1, yb2, yb7, yb8 Width

Claims

1. A semiconductor device comprising: a substrate; a first nitride semiconductor layer provided on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a larger band gap than the first nitride semiconductor layer; a two-dimensional electron gas layer provided near the boundary between the first nitride semiconductor layer and the second nitride semiconductor layer; a source electrode and a drain electrode provided on the second nitride semiconductor layer at intervals and each electrically connected to the first nitride semiconductor layer; a gate electrode provided on the second nitride semiconductor layer at intervals from the source electrode and the drain electrode; wherein the substrate has an active region and an inactive region; and further comprising: a first temperature sensing resistor for sensing a first temperature near the gate electrode in the active region; and a second temperature sensing resistor for sensing a second temperature between the gate electrode and the drain electrode in the active region.

2. In a plan view, the direction in which the gate electrode extends is defined as the first direction, and the direction perpendicular to the first direction in the plan view is defined as the second direction. The semiconductor device comprises a plurality of gate electrodes and a plurality of drain electrodes arranged in the second direction. The first temperature sensing resistor has a plurality of first temperature sensing units extending over the plurality of gate electrodes in the active region and a first connection unit connecting the plurality of first temperature sensing units in series. The second temperature sensing resistor has a plurality of second temperature sensing units extending between the plurality of gate electrodes and the plurality of drain electrodes in the active region and a second connection unit connecting the plurality of second temperature sensing units in series. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 2, wherein the first temperature sensing resistor and the second temperature sensing resistor are arranged so as not to overlap in the plan view.

4. The semiconductor device according to claim 2, wherein each of the plurality of first temperature sensing units has a first portion extending to both ends in the first direction within the active region and a second portion provided outside the active region, and each of the plurality of second temperature sensing units has a third portion extending to both ends in the first direction within the active region and a fourth portion provided outside the active region, and the first connection portion and the second connection portion are provided outside the active region.

5. The semiconductor device according to claim 4, satisfying at least one of the following: the width in the second direction of the first connection portion is greater than the width in the first direction of the first temperature sensing portion, and the width in the second direction of the second connection portion is greater than the width in the first direction of the second temperature sensing portion.

6. The semiconductor device according to claim 5, wherein the line width in the second direction of at least one of the first connection portion and the second connection portion is 2.5 μm or more.

7. The semiconductor device according to any one of claims 1 to 6, wherein the first temperature sensing resistor and the second temperature sensing resistor are made of an alloy containing Al, Au, Cu, or at least one of them.

8. The semiconductor device according to any one of claims 2 to 6, wherein the first temperature sensing resistor and the second temperature sensing resistor have a resistor width within the active region that is in the range of 0.5 μm to 7 μm.

9. The semiconductor device according to any one of claims 1 to 6, further comprising a P-type doped third nitride semiconductor layer near the gate electrode.

10. The semiconductor device according to any one of claims 1 to 6, further comprising a source field plate electrode electrically connected to the source electrode.

11. A control method comprising: converting the resistance value of a first temperature sensing resistor provided in the semiconductor device according to any one of claims 1 to 6 to a first temperature; converting the resistance value of a second temperature sensing resistor provided in the semiconductor device to a second temperature; increasing the gate voltage when the representative temperature based on the first and second temperatures is less than or equal to a first threshold; increasing the gate voltage and increasing the drive current of the cooling fan when the representative temperature is greater than or equal to the first threshold and less than or equal to a second threshold higher than the first threshold; and turning off the gate voltage when the representative temperature is higher than the second threshold.

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