Dicing method for semiconductor devices including low-k dielectric materials

Abstract

One aspect of the present disclosure pertains to dicing methods for semiconductor devices including low-K dielectric materials. The dicing method includes providing a substrate having a stack of dielectric layers disposed over the substrate. In some embodiments, the method further includes removing the stack of dielectric layers from a dicing street region to form a trench that exposes a surface of the substrate. In some embodiments, the method further includes filling the trench with a silicon layer. In some embodiments, the method further includes after performing a bumping process, removing the silicon layer and a portion of the substrate disposed in the dicing street region to singulate a die from the substrate.

Description

Attorney Docket No. 62306.155WO01 (P241553-WO-UTL)DICING METHOD FOR SEMICONDUCTOR DEVICES INCLUDING LOW-K DIELECTRIC MATERIALSRELATED PATENT APPLICATIONS

[0001] The present application claims the benefit of U.S. Provisional Application No. 63 / 698,183, filed September 24, 2024, which is incorporated herein by reference in its entiretyFIELD OF THE DISCLOSURE

[0002] The technology disclosed herein relates generally to dicing methods, and more particularly to dicing methods for semiconductor devices including low-K dielectric materials.BACKGROUND

[0003] In a complementary metal-oxide-semiconductor (CMOS) technology process flow, a wafer is processed to include a plurality of identical die (or chips). Each of the die includes a multilayer interconnect structure formed to provide an electrical connection to devices (e.g., transistors, etc.) formed in an underlying substrate portion of the die. The multilayer interconnect structure is formed using a combination of conductive metal features (e.g., such as vias and conductive lines) and dielectric layers that serve to isolate the conductive metal feature from each other. The dielectric layers may include low-K dielectric materials to reduce parasitic capacitance and improve overall device performance. During wafer processing, the dielectric layers may be deposited as a stack of blanket layers across the wafer, covering both the plurality of identical die and dicing street regions disposed between adjacent die.

[0004] However, there are significant challenges associated with dicing, or singulating, individual die from a wafer that has a thick stack of dielectric layers, including low-K dielectric materials, formed in dicing street regions. In particular, as a result of a dicing process and because low-K dielectric materials are brittle and porous, the low-K dielectric materials may peel and crack to form defects along a dicing line (e.g., along dicing street regions). Such defects may form along the dicing line whether using mechanical dicing (e.g., using a saw or a blade) or laser dicing. This creates substantial challenges for subsequent die processing. Thus, existing dicing methods have not proved entirely satisfactory in all respects.1© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)SUMMARY

[0005] Embodiments of the present disclosure include dicing methods, and more particularly dicing methods for semiconductor devices including low-K dielectric materials.

[0006] In an exemplary aspect, a dicing method includes providing a substrate comprising a stack of dielectric layers disposed over the substrate. In some embodiments, the method further includes removing the stack of dielectric layers from a dicing street region to form a trench that exposes a surface of the substrate. In some embodiments, the method further includes filling the trench with a silicon layer. In some embodiments, the method further includes after performing a bumping process, removing the silicon layer and a portion of the substrate disposed in the dicing street region to singulate a die from the substrate.

[0007] In some embodiments, the stack of dielectric layers comprises a low-K dielectric material, an ultra-low-K dielectric material, or a combination thereof.

[0008] In some embodiments, the silicon layer comprises a polysilicon layer.

[0009] In some embodiments, the removing the stack of dielectric layers includes forming a patterned hard mask layer comprising a first opening that exposes the stack of dielectric layers in the dicing street region and performing a dry etching process through the patterned hard mask layer to remove the stack of dielectric layers to form the trench.

[0010] In some embodiments, the dry etching process comprises a plasma etching process.

[0011] In some embodiments, the method further includes after forming the trench, removing the patterned hard mask layer.

[0012] In some embodiments, the filling the trench with the silicon layer includes conformally depositing the silicon layer within the trench and over a top surface of the stack of dielectric layers outside the trench and performing a chemical mechanical polishing (CMP) process to remove excess portions of the silicon layer.

[0013] In some embodiments, and after the CMP process, a top surface of the stack of dielectric layers and a top surface of the silicon layer are substantially level with each other.

[0014] In some embodiments, the silicon layer comprises a seam.

[0015] In some embodiments, the method further includes after filling the trench with the silicon layer and prior to performing the bumping process, forming one or2© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) more passivation layers over the stack of dielectric layers and the silicon layer, and after performing the bumping process, performing a laser grooving process to form a second opening in the one or more passivation layers within the dicing street region. In some embodiments, a thickness of the one or more passivation layers is between about 5 pm and about 7 pm. In some embodiments, another dielectric layer is formed over the one or more passivation layers. The thickness of the dielectric layer at which the polysilicon layer is formed may vary depending on the application.

[0016] In some embodiments, the method further includes after performing the laser grooving process, performing a plasma dicing process to remove the silicon layer and the portion of the substrate to singulate the die from the substrate.

[0017] In another exemplary aspect, a method of dicing a 3D stacked wafer includes providing a first substrate comprising a first stack of dielectric layers disposed over a first front side of the first substrate and a second substrate comprising a second stack of dielectric layers disposed over a second front side of the second substrate. In some embodiments, the method further includes bonding the first front side of the first substrate to the second front side of the second substrate to form the 3D stacked wafer. In some embodiments, the method further includes etching, from a dicing street, a portion of the first substrate, the first stack of dielectric layers, and the second stack of dielectric layers, to form a trench that exposes a surface of the second substrate. In some embodiments, the method further includes filling the trench with a polysilicon layer. In some embodiments, the method further includes after forming a passivation layer over back side of the first substrate, removing the polysilicon layer and a portion of the second substrate disposed in the dicing street to singulate a die from the 3D stacked wafer.

[0018] In some embodiments, the method further includes after the bonding, and before the etching performing a backside grinding process to a back side of the first substrate to provide a thinned first substrate.

[0019] In some embodiments, the first stack of dielectric layers and the second stack of dielectric layers comprise a low-K dielectric material, an ultra-low-K dielectric material, or a combination thereof.

[0020] In some embodiments, the etching comprises a dry plasma etching process.

[0021] In some embodiments, and after filling the trench with the polysilicon layer, a surface of the thinned first substrate and a top surface of the polysilicon layer are substantially level with each other.3© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)

[0022] In some embodiments, the method further includes performing a laser grooving process to form an opening in the passivation layer within the dicing street to expose the polysilicon layer, and after performing the laser grooving process, performing a plasma dicing process to remove the polysilicon layer and the portion of the second substrate disposed in the dicing street to singulate the die from the 3D stacked wafer.

[0023] In another exemplary aspect, a method includes providing a first substrate comprising a first stack of dielectric layers disposed over a first front side of the first substrate and a second substrate comprising a second stack of dielectric layers disposed over a second front side of the second substrate. In some embodiments, the method further includes removing, from the first substrate, the first stack of dielectric layers from a first dicing street region to form a first trench that exposes a first surface of the first substrate. In some embodiments, the method further includes filling the first trench with a first polysilicon layer. In some embodiments, the method further includes removing, from the second substrate, the second stack of dielectric layers from a second dicing street region to form a second trench that exposes a second surface of the second substrate. In some embodiments, the method further includes filling the second trench with a second polysilicon layer. In some embodiments, the method further includes after filling the first trench with the first polysilicon layer and the second trench with the second polysilicon layer, bonding the first front side of the first substrate to the second front side of the second substrate to form a 3D stacked wafer.

[0024] In some embodiments, the method further includes after performing a bumping process, removing the first polysilicon layer, the second polysilicon layer and a portion of the second substrate to singulate a die from the 3D stacked wafer.

[0025] In some embodiments, the first stack of dielectric layers and the second stack of dielectric layers comprise a low-K dielectric material, an ultra-low-K dielectric material, or a combination thereof.

[0026] Additional aspects, features, and advantages of the present disclosure will become apparent from the following detailed description.© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description, serve to explain the principles of the disclosure.

[0028] FIG. 1 illustrates a flow chart of a method of dicing a wafer, according to some embodiments.

[0029] FIGS. 2, 3, 4, 5, 6, 7, 8, 9, 10, 1 1 , 12, 13, and 14 illustrate cross-section views of a device at various stages of processing according to the method of FIG. 1 , according to some embodiments.

[0030] FIG. 15 illustrates a flow chart of a method of dicing 3D stacked wafers, according to some embodiments.

[0031] FIGS. 16, 17, 18, 19, 20, 21, 22, 23, 24, and 25 illustrate cross-section views of a device at various stages of processing according to the method of FIG. 15, according to some embodiments.

[0032] FIG. 26 illustrates a flow chart of an alternative method of dicing 3D stacked wafers, according to some embodiments.

[0033] FIGS. 27 and 28 illustrate cross-section views of a device at various stages of processing according to the method of FIG. 26, according to some embodiments.DETAILED DESCRIPTION

[0034] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.5© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)

[0035] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0036] Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within + / - 10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be + / — 15% by one of ordinary skill in the art. Further, disclosed dimensions of the different features can implicitly disclose dimension ratios between the different features. Still further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0037] A semiconductor wafer may be processed to include a plurality of identical die (or chips) that are subsequently singulated using a dicing process. Each of the plurality of die includes a multilayer interconnect structure formed to provide an electrical connection to devices (e.g., transistors, etc.) formed in an underlying substrate portion of the die. The multilayer interconnect structure is formed using a combination of conductive metal features (e.g., such as vias and conductive lines) and dielectric layers that serve to isolate the conductive metal feature from each other. The dielectric layers may include low-K dielectric materials and / or ultra-low-K dielectric materials to reduce parasitic capacitance and improve overall device performance. Low-K dielectrics, as used and described herein, include dielectric6© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) materials having a low dielectric constant, for example, less than that of thermal silicon oxide (~3.9). Ultra-low-K dielectrics, in some examples, may have a dielectric constant less than or equal to about two (2).

[0038] During wafer processing, the dielectric layers may be deposited as a stack of blanket layers across the wafer, covering both the plurality of identical die and dicing street regions disposed between adjacent die. In particular, the stack of blanket layers may include low-K and / or ultra-low-K dielectric materials, which are brittle and porous, formed in the dicing street regions. As a result of a dicing process, the brittle and porous low-K dielectric materials and / or ultra-low-K dielectric materials may commonly peel and crack to form defects along a dicing line (e.g., along dicing street regions). The defects formed along the dicing line may form whether using mechanical dicing (e.g., using a saw or a blade) or laser dicing. This creates substantial challenges for subsequent die processing. These challenges are even more significant in three-dimensional integrated circuit (3D-IC) technology, where the dicing process is performed through an even thicker stack of blanket layers including low-K and / or ultra-low-K dielectric materials. Thus, existing dicing methods have not proved entirely satisfactory in all respects.

[0039] Embodiments of the present disclosure offer advantages over the existing art, though it is understood that other embodiments may offer different advantages, not all advantages are necessarily discussed herein, and no particular advantage is required for all embodiments. For example, embodiments discussed herein include dicing methods, and more particularly dicing methods for semiconductor devices including low-K dielectric materials. In particular, embodiments of the present disclosure effectively overcome the challenges of dicing through dielectric stacks including low-K and / or ultra-low-K materials, as described above. Embodiments of the disclosed dicing methods provide a high throughput, defect-free manufacturable process. Aspects of the disclosed embodiments may be particularly useful for 3D stacked wafers, which have a thicker stack of dielectric layers for dicing.

[0040] In accordance with some embodiments, a wafer is provided that has a dielectric stack (including low-K and / or ultra-low-K materials) formed in dicing street regions of the wafer, where the dielectric stack may be formed as part of a multilayer interconnect structure. Initially, in some examples, the dielectric stack (including low-K and / or ultra-low-K materials) is plasma etched from the dicing street region to form a trench or groove, which is subsequently refilled with a silicon7© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)(Si)-based material such as poly-Si. In some examples, after refilling the trench or groove, further processing may be performed such as passivation layer formation, pad formation, solder bumping, etc. In some embodiments, a laser grooving process may be performed to form an opening which exposes the Si-based material (e.g., poly-Si) previously used to refill the trench or groove. Thereafter, in some embodiments, a plasma dicing process, which is highly effective in removing silicon, is used to remove the Si-based material (e.g., poly-Si) entirely from the trench or groove in the dicing street region and the die is successfully separated from the wafer without any cracking and / or peeling. Thus, the challenges of dicing through dielectric stacks including low-K and / or ultra-low-K materials is effectively addressed. In addition, and in some embodiments, a much narrower street width (~ 10 um) may be used as compared to at least some existing dicing techniques (e.g., such as saw dicing or laser dicing) which use a wider street width (~ 80 um). As a result, embodiments of the present disclosure allow for a greater area of active devices across the wafer. Further, embodiments of the present disclosure provide for increased yield (e.g., due to no die damage), increased throughput (e.g., due to removal of all dicing lines at once), and stronger or more robust die (e.g., due to not damaging the wafer surface during dicing). Additional details of embodiments of the present disclosure are provided below, and additional benefits and / or other advantages will become apparent to those skilled in the art having benefit of the present disclosure.

[0041] Referring to FIG. 1 , illustrated is a method 100 of dicing a wafer, in accordance with some embodiments. The method 100 is described below in more detail with reference to FIGS. 2-14, which illustrate cross-section views of a device 200 at various stages of processing according to the method 100. It will be understood that additional process steps may be implemented before, during, and after the method 100, and some process steps described may be replaced or eliminated in accordance with various embodiments of the method 100. It will be further understood that parts of the method 100 may be fabricated by a well-known complementary metal-oxide-semiconductor (CMOS) technology process flow, and thus some processes are only briefly described herein.

[0042] The method 100 begins at block 102 where a substrate including one or more semiconductor devices and a multilayer interconnect (MLI) structure is provided. With reference to FIG. 2, and in an embodiment of block 102, the device8© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)200 including a substrate 202 is provided. In some embodiments, the substrate 202 may be a semiconductor substrate such as a silicon substrate. The substrate 202 may include various layers, including conductive or insulating layers formed on the substrate 202. The substrate 202 may include various doping configurations depending on design requirements as is known in the art. The substrate 202 may also include other semiconductors such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Further, in some embodiments, the substrate 202 may include an epitaxial layer (epi-layer), the substrate 202 may be strained for performance enhancement, the substrate 202 may include a silicon-on-insulator (SOI) structure, and / or the substrate 202 may have other suitable enhancement features. In some cases, the substrate 202 may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum nitride (AIN), or other materials used in the fabrication of GaN-based devices and circuits.

[0043] In some embodiments, the substrate 202 includes one or more semiconductor devices such as planar bulk metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary MOS (CMOS) devices, multi-gate transistors (planar or vertical) such as FinFET devices or gate-all-around (GAA) devices, strained-semiconductor devices, SOI devices, partially-depleted SOI devices, fully-depleted SOI devices, bipolar junction transistors (BJTs), high-voltage transistors, gallium nitride (GaN)-based devices, radio-frequency (RF) switches, low noise amplifiers (LNAs), antenna tuners, power amplifiers (PAs), memory devices such as flash memory (e.g., NAND or NOR flash memory), logic circuits, or other structures, circuits, or devices. By way of example, the semiconductor devices formed within the substrate 202 may be formed as part of a front-end-of-line (FEOL) process.

[0044] As shown, the device 200 further includes a multilayer interconnect (MLI) 204 coupled to the one or more semiconductor devices in the substrate 202, where the MLI 204 is formed as part of a middle-end-of-line (MEOL) and / or back-end-of- line (BEOL) process. The MLI 204 includes various conductive features, which may be vertical interconnects, such as contacts and / or vias 206, and / or horizontal interconnects, such as conductive lines 208. The various conductive features include conductive materials, such as metal. In some cases, the metal of the MLI 204 may include copper (Cu), aluminum (Al), an aluminum copper (AICu) alloy, ruthenium9© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL)(Ru), cobalt (Co), or other appropriate metal layer. In some examples, the metal of the MLI 204 may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical plating (ECP), electroless deposition (ELD), ALD, or a combination thereof. The MLI 204 is not limited by the number, material, size, and / or dimension of the conductive features depicted, and thus, the MLI 204 may include any number, material, size, and / or dimension of conductive features depending on design requirements of the device 200. In the illustrated embodiment, the MLI 204 further includes metallic pads 210 formed in the uppermost portion of the MLI 204.

[0045] The various conductive features of the MLI 204 are disposed within a stack of dielectric layers 212, which may include interlayer (or inter-level) dielectric (ILD) layers, liner layers, barrier layers, etch stop layers, or combinations thereof. The stack of dielectric layers 212 serves to isolate the conductive features of the MLI 204. In various embodiments, the stack of dielectric layers 212 may include low-K dielectric materials and / or ultra-low-K dielectric materials to reduce parasitic capacitance of the device 200 and improve overall device performance. In some cases, the stack of dielectric layers 212 may include a combination of low-K, ultra- low-K, and conventional oxide layers (e.g., such as silicon dioxide, silicon nitride, or silicon oxynitride). In some embodiments, the low-K and / or ultra-low-K dielectric materials of the stack of dielectric layers 212 may include TEOS oxide, undoped silicate glass, or doped silicate glass such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), porous silicon dioxide, carbon-doped oxide, spin-on organic polymeric dielectrics, spin-on silicon based polymeric dielectrics, and / or other suitable low-K dielectric material, or combinations thereof. In some cases, the stack of dielectric layers 212 may be deposited by ALD, CVD, PVD, SACVD, flowable CVD, spin-on coating, or other suitable deposition technique. In an example, the MLI 204 and the stack of dielectric layers 212 may be formed in an integrated process including a damascene process, such as a dual damascene process or single damascene process.

[0046] As also shown in FIG. 2, and because the stack of dielectric layers 212 may be deposited as blanket layers across the substrate 202, the stack of dielectric layers 212 is formed over a dicing street region 214 that interposes adjacent die 205, 207 which will be singulated at a later stage of processing. The dicing street region 214 includes a region that will be removed (or cut away) during a dicing process. In some10© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) existing implementations, and due to the brittle and / or porous nature of the low-K and / or ultra-low-K dielectric materials in the stack of dielectric layers 212, the stack of dielectric layers 212 may peel or crack during a conventional dicing process (e.g., such as saw dicing or laser dicing) to form defects along the dicing street region 214. As described in more detail below, embodiments of the present disclosure avoid such concerns while providing greater yield, increased throughput, and more robust die.

[0047] After forming the MLI 204 including the various conductive features and the stack of dielectric layers 212, the method 100 proceeds to block 104 where a patterned hard mask layer is formed. Referring to FIG. 2 and FIG. 3, in an embodiment of block 104, a patterned hard mask (HM) layer 302 may be formed over the device 200. As shown, the patterned HM layer 302 includes an opening 304 that exposes the stack of dielectric layers 212 in the dicing street region 214. In some examples, the opening 304 has a width W of about 10 microns. More generally, in various embodiments, the width W may be in a range of between less than 10 microns and more than 100 microns, depending on the particular application. It is also noted that the width W effectively defines a street width of the dicing street region 214. In some embodiments, hard mask material used to form the patterned HM layer 302 may be initially deposited using a CVD, ALD, PVD, or other suitable process. Thereafter, the hard mask material may be patterned using a suitable photolithography process (e.g., photoresist deposition, exposure, baking, and developing) and etching process (e.g., a wet etch, dry etch, or combination thereof) to form the patterned HM layer 302 having the opening 304. Alternatively, in some examples, a lift-off process may be used to form the patterned HM layer 302. In a lift-off process, a patterned photoresist layer is first formed over the device 200. Thereafter, the hard mask material used to form the patterned HM layer 302 is deposited over the patterned photoresist layer, and a solvent or other chemical etchant is used to remove the patterned photoresist layer (along with any hard mask material formed thereupon), thereby leaving the patterned HM layer 302. In some embodiments, the patterned HM layer 302 may include an oxide layer (e.g., such as SiOz) and / or a nitride layer (e.g., such as SiaNa). The patterned HM layer 302 may be used to protect regions of the wafer including adjacent die 205, 207, and layers formed thereupon, while an etch process removes exposed portions of the stack of dielectric layers 212 in the dicing street region 214, as discussed below. In various embodiments, patterned HM layer 302 has a high etch selectivity as compared to the stack of dielectric layers 212 (e.g.,11© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) such as a selectivity of about 1 : 10) and sufficient thickness (e.g., such as between about 5- 10 microns) to withstand subsequent processing (e.g., the etch process that removes the exposed portions of the stack of dielectric layers 212). It is also noted that since the patterned HM layer 302 is defined using photolithography, as described above, and because a dry plasma etching process is used to etch the exposed portions of the stack of dielectric layers 212, as described below, the dicing street region 214 can have a much narrower street width as compared to processes that use existing dicing techniques (e.g., such as saw dicing or laser dicing). As a result, embodiments of the present disclosure allow for a greater area of active devices across the wafer.

[0048] The method 100 proceeds to block 106 where dielectric layers are etched through the patterned hard mask layer. Referring to FIG. 3 and FIG. 4, in an embodiment of block 106, an etch process is performed to remove portions of the stack of dielectric layers 212, exposed by the opening 304 in the patterned HM layer 302, from the dicing street region 214. As a result of the etch process, a groove or trench 402 is formed in the dicing street region 214. In some cases, the groove or trench 402 exposes lateral surfaces of each layer of the stack of dielectric layers 212, as well as a surface of the underlying substrate 202, as shown. In various embodiments, the etch process of block 106 includes a dry plasma etching process (also referred to as a plasma dicing process). The dry plasma etching process is an anisotropic etching process that ensures that sidewalls of the groove or trench 402 are substantially vertical after the etch process. The dry plasma etching process also provides for simultaneous removal of portions of the stack of dielectric layers (such as the stack of dielectric layers 212) in each of the dicing street regions across the wafer (or across the substrate 202), thereby increasing throughput of the dicing process. In some examples, the dry plasma etching process is performed using perfluorocarbons, hydrofluorocarbons, oxygen, inert gases (e.g., such as He, Ar, Xe, N, or H), or combinations thereof.

[0049] The method 100 proceeds to block 108 where the patterned hard mask layer is removed. Referring to FIG. 4 and FIG. 5, in an embodiment of block 108, the patterned HM layer 302 is removed from the surface of the device 200, thereby exposing a top surface of the stack of dielectric layers 212 and the metallic pads 210 formed in the uppermost portion of the MLI 204. In some embodiments, the patterned HM layer 302 is removed using a selective etching process. The selective etching process may include a wet etching process, a dry etching process, or a combination12© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) thereof. After removing the patterned HM layer 302, and in a further embodiment of block 108, a cleaning process may be performed to the device 200 to remove any residue that may be present in the groove or trench 402 (formed in the dicing street region 214) and / or which may be present along a top surface of the device 200.

[0050] The method 100 proceeds to block 110 where a silicon layer is deposited and a chemical mechanical polishing (CMP) process is performed. Referring to FIG. 5 and FIG. 6, in an embodiment of block 110, a silicon layer 602 is conformally deposited within the groove or trench 402, including over the exposed lateral surfaces of the stack of dielectric layers 212 and the underlying substrate 202, as well as over the top surface of the device 200. In some embodiments, the silicon layer 602 includes a polysilicon layer. In various examples, the silicon layer 602 may be deposited by CVD, PVD, SACVD, flowable CVD, LPCVD, PECVD, or other suitable deposition technique. In some cases, and due to some non-conformality in the deposition process, a seam 604 may form within the silicon layer 602 deposited in the groove or trench 402. If formed, however, the seam 604 will be below the top surface of the device 200 and will not impose limitations on the disclosed process, as described below. After formation of the silicon layer 602, referring to FIG. 6 and FIG. 7 and in a further embodiment of block 110, a CMP process is performed to remove excess material and to planarize a top surface of the device 200. After the CMP process, and in some embodiments, the top surface of the stack of dielectric layers 212 and the metallic pads 210 (formed in the uppermost portion of the MLI 204) are exposed. Moreover, after the CMP process and because the groove or trench 402 has been filled by the silicon layer 602, the top surface of the stack of dielectric layers 212 and the top surface of the silicon layer 602 are substantially level with each other, and the overall top surface of the device 200 is substantially flat (planar), making the device 200 suitable for subsequent processing. The presence or absence of the seam 604, below the top surface of the device 200, remains inconsequential to the disclosed process as the topmost portion of the groove or trench 402 is filled with the silicon layer 602 and the overall top surface of the device 200 is planarized by the CMP process.

[0051] The method 100 proceeds to block 112 where further back-end processing is performed. Referring to FIGS. 7-9, in an embodiment of block 112, further back- end processing is performed to the device 200. In some embodiments, the further back-end processing of block 112 may include formation of one or more passivation13© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) layers 802, 804 over the device 200. In some cases, the one or more passivation layers 802, 804 may include dielectric layers such as silicon oxide or a silicon oxide containing material, undoped silicate glass (USG), a nitrogen-containing material or a carbon-containing material (e.g., such as SiCN, SiOC, SiC, SiOCN, SiN), or combinations thereof. In some embodiments, the one or more passivation layers 802, 804 may be deposited by PECVD, HDP-CVD, SACVD, CVD, ALD, PVD, or a combination thereof. In some embodiments, the further back-end processing of block 112 may further include formation of openings in the one or more passivation layers 802, 804 (e.g., using photolithography and etching processes) to expose the top surface of the metallic pads 210 formed in the uppermost portion of the MLI 204. In a further embodiment of block 112, a polyimide (PI) layer 806 may be conformally deposited over the device 200, including within the openings formed in the one or more passivation layers 802, 804. The PI layer 806 may then be patterned (e.g., using photolithography and etching processes) to once again expose the top surface of the metallic pads 210.

[0052] After formation of the patterned PI layer 806, and in a further embodiment of block 112, a bumping process may be performed. The bumping process may include formation of bump metallization 808, which may include formation of underbump metallization (UBM) and formation of copper (Cu) pillars over the UBM, as well as formation of a solder bump 810 over the Cu pillars of the bump metallization 808. In some embodiments, the bump metallization 808 provides a low resistance electrical connection to the metallic pads 210. In some embodiments, the UBM of the bump metallization 808 also hermetically seals and prevents diffusion of other bump metals into the device 200. In various examples, the UBM includes multiple layers of different metals such as an adhesion layer (e.g., Ti, Cr, Al or a combination thereof), a diffusion barrier layer (e.g., CrCu alloy), a solderable layer, and an oxidation barrier layer (e.g., Au). The various layers of the UBM may be deposited by electroplating, sputtering, evaporation, or other suitable method. In some embodiments, a Cu seed layer may be deposited prior to formation of the Cu pillar, which may be formed by an electroplating process. In addition, and in some cases, a diffusion barrier (e.g., such as Ni) may be formed between the Cu pillar and the solder bump 810, to prevent formation of an intermetallic layer and / or to prevent the formation of microvoids. After formation of the Cu pillar, a plating process may be used to form the solder bump 810 over the Cu pillar. One or more patterning14© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) processes (e.g., lithography and / or etching processes) may be performed to pattern one or more of the layers deposited during the bumping process. In some embodiments, a reflow process may also be performed after solder deposition to form the solder bump 810. By way of example, formation of the bump metallization 808 and the solder bump 810 provide contact structures for connection to external circuitry. In various embodiments, the further back-end processing of block 112 also includes formation of a redistribution layer (RDL) to which the MLI 204 is coupled. In some cases, the metallic pads 210 form part of, or are coupled to, the RDL.

[0053] The method 100 proceeds to block 114 where backside grinding and frame mounting is performed. Referring to FIG. 9 and FIG. 10, in an embodiment of block 114, a backside grinding process is performed to a backside surface 902 of the substrate 202 to provide a thinned substrate 202A. The backside grinding process may include multiple grinding processes such as a course grinding process and a fine grinding process. In some examples, a thickness of the substrate 202 is in a range of between about 720-780 microns, and a thickness of the thinned substrate 202A is in a range of between about 150-300 microns. After the backside grinding process, in some examples, the device 200 including the thinned substrate 202A is transferred (or mounted) onto a dicing tape frame for further processing. As shown in the example of FIG. 10, the backside surface 902 of the thinned substrate 202A is attached to dicing tape 904, which is in turn attached to the dicing tape frame (not shown) that circumscribes the wafer (or the thinned substrate 202A) from a top-down view.

[0054] After mounting the substrate 202A onto the dicing tape frame, the method 100 may proceed according to either block 116 or block 118. In some embodiments, the method 100 proceeds to block 116 where a photoresist coating process is performed followed by a laser grooving process. Referring to FIG. 10 and FIG. 11, in an embodiment of block 116, a thick photoresist layer 1102 (e.g., having a thickness between about 5-10 microns) is initially formed over the device 200. After forming the photoresist layer 1102, a laser 1104 is used to perform a laser grooving process that forms an opening in the photoresist layer 1102, thereby providing a patterned photoresist layer. The laser grooving process may further be used to ablate (remove) portions of the PI layer 806, and the one or more passivation layers 802, 804, to expose the silicon layer 602 previously formed within the groove or trench 402. Remaining portions of the patterned photoresist layer 1102, that are not removed15© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) by the laser grooving process, may be used to protect regions of the wafer including adjacent die 205, 207, and layers formed thereupon, while an etch process removes the exposed silicon layer 602 from the dicing street region 214, as discussed below with reference to block 120 of the method 100.

[0055] In some alternative embodiments, the method 100 instead proceeds to block 118 where a laser grooving process is performed followed by forming a patterned photoresist layer. Referring to FIG. 12 and FIG. 11, in an embodiment of block 118, the laser 1 104 may be used to initially perform a laser grooving process that ablates (removes) portions of the PI layer 806, and the one or more passivation layers 802, 804, to expose the silicon layer 602 previously formed within the groove or trench 402 (FIG. 12). After exposing the silicon layer 602, a thick photoresist layer 1102 (e.g., having a thickness between about 5- 10 microns) may then be formed over the device 200, including over the exposed silicon layer 602. Thereafter, the laser 1104 may once again be used to perform another laser grooving process that forms an opening in the photoresist layer 1102 to form a patterned photoresist layer that once again exposes the silicon layer 602 (FIG. 11). Similar to block 116, the remaining portions of the patterned photoresist layer 1102, that are not removed by the laser grooving process, may be used to protect regions of the wafer including adjacent die 205, 207, and layers formed thereupon, while an etch process removes the exposed silicon layer 602 from the dicing street region 214, as discussed below with reference to block 120 of the method 100.

[0056] Regardless of whether the method 100 proceeds according to block 116 or block 118, in some embodiments and after block 116 or block 118, the structure of the device 200 may be as shown in FIG. 11 , where an opening that extends through the patterned photoresist layer 1102, the PI layer 806, and the one or more passivation layers 802, 804 exposes the silicon layer 602 previously formed within the groove or trench 402. After block 116 or block 118, the method 100 then proceeds to block 120 where a silicon etch process is performed to singulate die from the wafer. Referring to FIG. 11 and FIG. 13, in an embodiment of block 120, an etch process is performed to remove an entirety of the silicon layer 602 (e.g., such as polysilicon), as well as the portion of the thinned substrate 202A disposed beneath the silicon layer 602, from the dicing street region 214 to form a trench 1302 that exposes the underlying dicing tape 904 and thereby singulates individual die (e.g., such as the die 205, 207) from the wafer. The portion of the thinned substrate 202A may also include a silicon layer,16© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) albeit crystalline as compared to polysilicon used for the silicon layer 602. Stated another way, the etch process of block 120 serves to remove an entirety of silicon material from the dicing street region 214 to form the trench 1302 that exposes the underlying dicing tape 904 and singulates individual die from the wafer. As shown, the trench 1302 may expose lateral surfaces of each layer of the stack of dielectric layers 212, lateral surfaces of the underlying thinned substrate 202A, and lateral surfaces of the PI layer 806 and the one or more passivation layers 802, 804. In various embodiments, the etch process of block 120 includes a dry plasma etching process (also referred to as a plasma dicing process). The dry plasma etching process is an anisotropic etching process that ensures that sidewalls of the trench 1302 are substantially vertical after the etch process. In various embodiments, the dry plasma etching process includes a deep reactive ion etching process (e.g., such as a Bosch etching process) in cyclic mode (e.g., alternating etch and deposition cycles). For instance, the dry plasma etching process may cycle between an SFe plasma cycle that etches silicon and a C4F8 plasma cycle that forms a protection layer. The dry plasma etching process also provides for simultaneous removal of an entirety of silicon material from the dicing street regions across the wafer (or across the thinned substrate 202A) to simultaneously singulate a plurality of die, thereby increasing throughput of the dicing process. After the die singulation, the patterned photoresist layer 1102 may be removed (e.g., such as by ashing, by using an appropriate solvent or chemical stripper, or a combination thereof).

[0057] The method 100 proceeds to block 122 where a die pick-and-place process is performed. Referring to FIG. 13 and FIG. 14, in an embodiment of block 122, a die pick-and-place process is performed to remove known good die (e.g., determined based on a wafer sort process) from the dicing tape 904 and transfer them to respective package substrates. In the example shown, a pick-and-place tool 1402 selectively picks up (or removes) die 203 (a known good die) from the dicing tape 904 and moves the die 203, as indicated by arrow 1404, to another location for transfer to a package substrate. In some examples, the pick-and-place tool 1402 includes a vacuum plunger for efficient die transfer. After each known good die has been removed from the dicing tape 904, unremoved faulty die may remain on the dicing tape 904 and may be discarded.

[0058] In the exemplary method 100, the device 200 provided at block 102 was described as including a full MLI structure (e.g., the MLI 204 with metallic pads 21017© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) formed in the uppermost portion of the MLI 204) with various conductive features disposed within a stack of dielectric layers (e.g., the stack of dielectric layers 212). As described at blocks 104-110 of the method 100, the stack of dielectric layers 212 (that correspond to the full MLI 204) are etched from the dicing street region 214 to form a trench that exposes the underlying substrate and which is then refilled with a silicon layer (or polysilicon layer) prior to further back-end processing (block 112). The etch and refill processes of blocks 104- 110 may be referred to as an etch-refill loop.

[0059] In some alternative embodiments, the etch-refill loop may be performed at different stages of processing of the MLI structure and may be repeated at various stages of processing of the MLI structure. For instance, consider a case where a full MLI structure includes six (6) metal layers surrounded by a stack of dielectric layers. In some embodiments, the etch-refill loop may be performed on the full stack of dielectric layers corresponding to all six (6) metal layers (e.g., similar to the example of the method 100). In other embodiments, a first part of an MLI structure including three (3) metal layers and a first stack of dielectric layers is formed. A first etchrefill loop may then be performed on the first stack of dielectric layers. Thereafter, a second part of the MLI structure including an additional three (3) metal layers and a second stack of dielectric layers is formed, and a second etch-refill loop is performed on the second stack of dielectric layers. After the second etch-refill loop, the full MLI structure (e.g., for all six metal layers, in this example) has a dicing street region with a trench that has been refilled with a silicon layer (or polysilicon layer). However, as a result of using multiple etch-refill loops at different stages of processing, the dielectric stack height for each of the etch-refill loops is significantly reduced, thereby increasing efficiency of the plasma etch process of the stack of dielectric layers and simplifying the silicon (or polysilicon) refill process. Stated another way, by using multiple etch-refill loops, it becomes much easier to dice thick dielectric stacks. In some examples, the full MLI structure may include up to ten (10) or fifteen (15) metal layers, and the etch-refill loop may be performed one, two, three, or more times during formation of the full MLI structure. As one example, consider a case where the full MLI structure includes nine (9) metal layers. In some embodiments, an etch-refill loop may be performed after formation of the first three metal layers, after formation of the next three metal layers, and after formation of the last three metal layers. Generally, it will be understood that the multi-step etch-refill18© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) loop approach, as described above, may be implemented by repeating the etch-refill loop any of a plurality of times at different stages of formation of a full MLI structure having any number of metallization layers and associated dielectric layers.

[0060] In still other embodiments, the etch-refill loop may be performed selectively to a subset of layers of the stack of dielectric layers that compose the full MLI structure. For example, consider once again a case where a full MLI structure includes six (6) metal layers surrounded by a stack of dielectric layers. In some embodiments, a first part of an MLI structure including less than the full six (6) metallization layers is formed. As one illustrative example, four (4) metal layers and a first stack of dielectric layers surrounding the four (4) metal layers may be formed. A first etch-refill loop may then be performed to a subset of the first stack of dielectric layers, for example, to a portion of the first stack of dielectric layers corresponding to the topmost one (1), two (2), or three (3) metallization layers, while at least a portion of the originally formed first stack of dielectric layers remains beneath the silicon layer (or polysilicon layer) formed by the etch-refill loop. Thereafter, a second part of the MLI structure including an additional two (2) metal layers and a second stack of dielectric layers is formed. As a result, after formation of the second part of the MLI structure, the dicing street region may include: (1) a first portion composed of low-K, ultra-low-K, conventional oxide layers (e.g., such as silicon dioxide, silicon nitride, or silicon oxynitride), or a combination thereof, (2) a second portion over the first portion, the second portion composed a silicon layer (or polysilicon layer) formed by the etch-refill loop, and (3) a third portion over the second portion, the third portion composed of low-K, ultra-low-K, conventional oxide layers, or a combination thereof. It will be further understood that the etchrefill loop may be implemented at any selected stage of formation of a full MLI structure to replace a subset of layers of the stack of dielectric layers that compose the full MLI structure.

[0061] As previously noted, aspects of the disclosed embodiments may be particularly useful for 3D stacked wafers (or 3D IC devices), which have a thicker stack of blanket layers including low-K and / or ultra-low-K dielectric materials. In particular, the method 100 (discussed above) may be similarly applied to applications including 3D stacked wafers, with some modifications. For example, referring to FIG. 15, illustrated is a method 1500 of dicing 3D stacked wafers, in accordance with some embodiments. The method 1500 is described below in more detail with19© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) reference to FIGS. 16-25, which illustrate cross-section views of a 3DIC device 1600 at various stages of processing according to the method 1500. It will be understood that additional process steps may be implemented before, during, and after the method 1500, and some process steps described may be replaced or eliminated in accordance with various embodiments of the method 1500. It will also be understood that the method of forming a stacked 3D structure as discussed with reference to the method 1500 is merely exemplary, and other methods may alternatively be used without departing from the scope of this disclosure. It will he further understood that parts of the method 1500 may be fabricated by a well-known CMOS technology process flow, and thus some processes are only briefly described herein. Moreover, various aspects of the method 1500 may be similar to the method 100, discussed above, and will be noted where applicable.

[0062] The method 1500 begins at block 1502 where two substrates (or wafers) including one or more semiconductor devices and MLI structures are provided. With reference to FIG. 16, in an embodiment of block 1502, substrates 203 A, 203B are provided. The substrates 203A, 203B may be substantially the same as the substrate 202, described above. In addition, the substrates 203A, 203B are complementary to each other and may thus have a same wafer diameter. Like the substrate 202, the substrates 203A, 203B may each include one or more semiconductor devices and an MLI structure. For example, the substrate 203A includes an MLI 204A and the substrate 203B includes an MLI 204B. The MLI 204A includes various conductive features, such as contacts and / or vias 206A and conductive lines 208A, and the MLI 204B includes various conductive features, such as contacts and / or vias 206B and conductive lines 208B. The MLI 204A further includes metallic pads 210A and the MLI 204B includes metallic pads 210B. In various embodiments, the MLI 204A, 204B may be substantially the same as the MLI 204, the contacts and / or vias 206A, 206B may be substantially the same as the contacts and / or vias 206, the conductive lines 208A, 208B may be substantially the same as the conductive lines 208, and the metallic pads 210A, 210B may be substantially the same as the metallic pads 210, each of which has been discussed above with reference to the device 200.

[0063] The various conductive features of the MLI 204A are disposed within a stack of dielectric layers 212A, and the various conductive features of the MLI 204B are disposed within a stack of dielectric layers 212B. The stack of dielectric layers 212A, 212B may be substantially the same as the stack of dielectric layers 212,20© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) described above. As such, the stack of dielectric layers 212A, 212B may each include low-K dielectric materials and / or ultra-low-K dielectric materials. In some cases, the stack of dielectric layers 212A, 212B may each include a combination of low-K, ultra- low-K, and conventional oxide layers (e.g., such as silicon dioxide, silicon nitride, or silicon oxynitride). In some embodiments, the stack of dielectric layers 212A, 212B are formed over dicing street regions 214A, 214B, similar to the dicing street region 214, discussed above.

[0064] The method 1500 proceeds to block 1503 where a bonding process is performed and the stacked substrate is thinned. With reference to FIG. 16 and FIG. 17, in an embodiment of block 1503, the bonding process may be a hybrid bonding process which includes bonding of metal pads (e.g., such as the metallic pads 210A, 210B) and the surrounding dielectric material (e.g., such as a topmost layer of the stack of dielectric layers 212A, 212B) of the two separate substrates 203A, 203B (or two separate wafers) to create a low profile, low parasitic, high-performance interconnect therebetween. In the example of FIG. 16 and FIG. 17, the substrate 203 A may be flipped (as indicated by arrow 1602) so that a front side 1604 of the substrate 203A faces, and is in contact with, a front side 1606 of the substrate 203B. It is noted that prior to contacting the substrates 203A, 203B, a surface activation process may be performed to each of the front side 1604 of the substrate 203 A and the front side 1606 of the substrate 203B. Using a high precision alignment process, the front side 1604 of the substrate 203 A may be brought into contact with the front side 1606 of the substrate 203B such that the metallic pad 210A is substantially aligned with the metallic pad 210B. In some embodiments, the surfaces of the topmost layer of the stack of dielectric layers 212A, 212B, which are also brought into contact, may form covalent bonds and / or may be attracted to each other by van der Waals forces. Once the front side 1604 of the substrate 203 A is brought into contact with the front side 1606 of the substrate 203B, an annealing process may be performed to form an electrical connection between the metallic pad 210A and the metallic pad 210B. It is noted that once bonded, the dicing street regions 214A, 214B of the two wafers may be substantially aligned to provide a combined dicing street region 214C, as illustrated.

[0065] After the bonding process, and in a further embodiment of block 1503, a backside grinding process is performed to a backside surface 1608 of the stacked substrate 203 A to provide a thinned substrate 203A-1. In some embodiments, the21© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) backside grinding process of the backside surface 1608 of the substrate 203 A may be similar to the backside grinding process performed to the backside surface 902 of the substrate 202 to provide the thinned substrate 202A, discussed above.

[0066] Once the bonding process and the backside grinding process of the substrate 203 A is completed (block 1503), blocks 1504- 1522 of the method 1500 closely mirror blocks 104- 122, respectively, of the method 100. As such, the remaining portion of the method 1500 will be somewhat briefly discussed, with focus given to the differences between the method 1500 and the method 100. Following block 1503, the method 1500 proceeds to block 1504 where a patterned hard mask layer is formed. With reference to FIG. 17, in an embodiment of block 1504, a patterned HM layer 302A is formed over the device 1600. The patterned HM layer 302A may be substantially the same as the patterned HM layer 302, discussed above. The patterned HM layer 302A may include an opening that exposes the thinned substrate 203A-1 in the dicing street region 214C. Portions of the stack of dielectric layers 212A, 212B are disposed directly beneath the portion of the thinned substrate 203 A- 1 exposed by the opening in the patterned HM layer 302A.

[0067] The method 1500 then proceeds to block 1506 where an etch process is performed to remove a portion of the thinned substrate 203 A- 1 , portions of the stack of dielectric layers 212A, and portions of the stack of dielectric layers 212B, exposed by the opening in the patterned HM layer 302A, from the dicing street region 214C. As a result of the etch process, a groove or trench 402A is formed in the dicing street region 214C. In some cases, the groove or trench 402A exposes lateral surfaces of each layer of the thinned substrate 203A-1, lateral surfaces of the stack of dielectric layers 212A, lateral surfaces of the stack of dielectric layers 212B, and a surface of the underlying substrate 203B, as shown. The etch process of block 1506 includes a dry plasma etching process (or a plasma dicing process), similar to the etch process of block 106, discussed above.

[0068] The method 1500 proceeds to block 1508 where the patterned hard mask layer is removed. In an embodiment of block 1508, the patterned HM layer 302A may be removed from the surface of the device 1600, thereby exposing the backside surface 1608 of the thinned substrate 203A-1. Similar to the removal of the HM layer 302 from the device 200, and in some embodiments, the patterned HM layer 302A is removed using a selective etching process followed by a cleaning process to remove22© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) any residue present in the groove or trench 402A (formed in the dicing street region 214C) and / or which may be present along a top surface of the device 1600.

[0069] The method 1500 then proceeds to block 1510 where a silicon layer is deposited and a CMP process is performed. Referring to FIG. 17 and FIG. 18, in an embodiment of block 1510, a silicon layer 602A is conformally deposited within the groove or trench 402A, including over the exposed lateral surfaces of the thinned substrate 203 A- 1 , the stack of dielectric layers 212A, the stack of dielectric layers 212B, and the surface of the underlying substrate 203B, as well as over the top surface of the device 1600. In some embodiments, the silicon layer 602A includes a polysilicon layer. More generally, the silicon layer 602A may be substantially the same as the silicon layer 602, discussed above. In some cases, a seam 604A may form below the top surface of the device 1600 and within the silicon layer 602A deposited in the groove or trench 402A, similar to the seam 604 discussed above. After formation of the silicon layer 602 A, referring to FIG. 18 and FIG. 19 and in a further embodiment of block 1510, a CMP process is performed to remove excess material and to planarize a top surface of the device 1600. After the CMP process, and in some embodiments, the backside surface 1608 of the thinned substrate 203 A- 1 is exposed. Moreover, after the CMP process and because the groove or trench 402 A has been filled by the silicon layer 602A, the backside surface 1608 of the thinned substrate 203 A- 1 and the top surface of the silicon layer 602A are substantially level with each other, and the overall top surface of the device 1600 is substantially flat (planar), making the device 1600 suitable for subsequent processing.

[0070] The method 1500 proceeds to block 1512 where further back-end processing is performed. Referring to FIG. 19 and FIG. 20, in an embodiment of block 1512, further back-end processing is performed to the device 1600. In some embodiments, the further back-end processing of block 1512 may include formation of a passivation layer 803 over the top surface of the device 1600, including over the backside surface 1608 of the thinned substrate 203 A- 1 and the top surface of the silicon layer 602A. In some cases, the passivation layer 803 may be similar to the one or more passivation layers 802, 804, discussed above. In at least some examples, the passivation layer 803 includes a nitride-containing layer, such as a silicon nitride (SiN) layer. The passivation layer 803 may have a thickness of between about 3-4 microns, in some embodiments. After forming the passivation layer 803, the further23© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) back-end processing of block 1512 may further include photolithography and etching processes to form an opening through a portion of the passivation layer 803, a portion of the thinned substrate 203A- 1, and a portion of the stack of dielectric layers 212A to expose a conductive line 208C embedded within the stack of dielectric layers 212A. The conductive line 208C is electrically coupled to other conductive lines and / contacts / vias within the stack of dielectric layers 212A, such as the conductive lines 208A and the contacts / vias 206A. After exposing the conductive line 208C, a metal layer is deposited within the opening and in contact with the conductive line 208C to form a backside via 206C that passes through the portion of the passivation layer 803, the portion of the thinned substrate 203A-1, and the portion of the stack of dielectric layers 212A. Thereafter, a backside metal pad 807 is formed over, and in contact with, the backside via 206C. In some examples, the backside metal pad 807 is coupled to, or forms part of, an RDL layer. In a further embodiment of block 1512, a passivation layer 805 may be conformally deposited over the device 1600, including over the backside metal pad 807. In some embodiments, the passivation layer 805 includes a polyimide (Pl) layer, similar to the PI layer 806 discussed above. The passivation layer 805 may then be patterned (e.g., using photolithography and etching processes) to expose the top surface of the backside metal pad 807.

[0071] After exposing the backside metal pad 807, and in a further embodiment of block 1512, a bumping process may be performed in a similar manner as discussed above. The bumping process may include formation of bump metallization (not shown), which may include formation of under-bump metallization (UBM) and formation of copper (Cu) pillars over the UBM, as well as formation of a solder bump 810A over the Cu pillars of the bump metallization. The bumping process provides a low resistance electrical connection to the backside metal pad 807. More generally, the bumping process provides contact structures for connection to external circuitry.

[0072] The method 1500 proceeds to block 1514 where backside grinding and frame mounting is performed. Referring to FIG. 20 and FIG. 21, in an embodiment of block 1514, a backside grinding process is performed to a backside surface 1610 of the substrate 203B to provide a thinned substrate 203B-1. In some embodiments, the backside grinding process of the backside surface 1610 of the substrate 203B may be similar to the backside grinding process performed to the backside surface 902 of the substrate 202 to provide the thinned substrate 202A, discussed above. After the backside grinding process, in some examples, the device 1600 is transferred (or24© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) mounted) onto a dicing tape frame for further processing. As shown in the example of FIG. 21, the backside surface 1610 of the thinned substrate 203B-1 is attached to dicing tape 904A, which is in turn attached to the dicing tape frame (not shown) that circumscribes the wafer from a top-down view.

[0073] After mounting the device 1600 onto the dicing tape frame, the method 1500 may proceed according to either block 1516 or block 1518, similar to blocks 116 and 118 described above. In some embodiments, the method 1500 proceeds to block 1516 where a photoresist coating process is performed followed by a laser grooving process. Referring to FIG. 21 and FIG. 22, in an embodiment of block 1516, a photoresist layer 1102A is initially formed over the device 1600. After forming the photoresist layer 1102A, a laser 1104 is used to perform a laser grooving process that forms an opening in the photoresist layer 1102A, thereby providing a patterned photoresist layer. The laser grooving process may further be used to ablate (remove) portions of the passivation layers 803, 805, to expose the silicon layer 602A previously formed within the groove or trench 402A.

[0074] In some alternative embodiments, the method 1500 instead proceeds to block 1518 where a laser grooving process is performed followed by forming a patterned photoresist layer. Referring to FIG. 23 and FIG. 22, in an embodiment of block 1518, the laser 1104 may be used to initially perform a laser grooving process that ablates (removes) portions of the passivation layers 803, 805, to expose the silicon layer 602A previously formed within the groove or trench 402A (FIG. 23). After exposing the silicon layer 602A, a photoresist layer 1102A may then be formed over the device 1600, including over the exposed silicon layer 602A. Thereafter, the laser 1104 may once again be used to perform another laser grooving process that forms an opening in the photoresist layer 1102 A to form a patterned photoresist layer that once again exposes the silicon layer 602A (FIG. 22).

[0075] Regardless of whether the method 1500 proceeds according to block 1516 or block 1518, in some embodiments and after block 1516 or block 1518, the structure of the device 1600 may be as shown in FIG. 22, where an opening that extends through the patterned photoresist layer 1102A and the passivation layers 803, 805 exposes the silicon layer 602A previously formed within the groove or trench 402A. After block 1516 or block 1518, the method 1500 then proceeds to block 1520 where a silicon etch process is performed to singulate 3DIC die from the wafer. Referring to FIG. 22 and FIG. 24, in an embodiment of block 1520, an etch process is performed25© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) to remove an entirety of the silicon layer 602A (e.g., such as polysilicon), as well as the portion of the thinned substrate 203B- 1 disposed beneath the silicon layer 602A, from the dicing street region 214C to form a trench 1302 A that exposes the underlying dicing tape 904A and thereby singulates individual 3DIC (or stacked) die from the wafer. The portion of the thinned substrate 203B-1 may also include a silicon layer, albeit crystalline as compared to polysilicon used for the silicon layer 602A. Stated another way, the etch process of block 1520 serves to remove an entirety of silicon material from the dicing street region 214C to form the trench 1302 A that exposes the underlying dicing tape 904A and singulates individual 3DIC die from the wafer. As shown, the trench 1302A may expose lateral surfaces of each layer of the stack of dielectric layers 212A, 212B, lateral surfaces of the thinned substrate 203 A- 1 and the thinned substrate 203B-1, and lateral surfaces of the passivation layers 803, 805. In various embodiments, the etch process of block 1520 includes a dry plasma etching process. More generally, the etch process of block 1520 may be substantially the same as the etch process of block 120, discussed above. After the 3DIC die singulation, the patterned photoresist layer 1102A may be removed (e.g., such as by ashing, by using an appropriate solvent or chemical stripper, or a combination thereof) .

[0076] The method 1500 proceeds to block 1522 where a die pick-and-place process is performed. Referring to FIG. 24 and FIG. 25, in an embodiment of block 1522, a die pick-and-place process is performed to remove known good 3DIC die (e.g., determined based on a wafer sort process) from the dicing tape 904A and transfer them to respective package substrates. In the example shown, a pick-and- place tool 1402 selectively picks up (or removes) a 3DIC die (a known good die) from the dicing tape 904A and moves the 3DIC die, as indicated by arrow 1404, to another location for transfer to a package substrate. After each known good 3DIC die has been removed from the dicing tape 904A, unremoved faulty 3DIC die may remain on the dicing tape 904A and may be discarded.

[0077] With reference to FIG. 26, illustrated therein is a method 2600 that provides an alternative method of dicing 3D stacked wafers, in accordance with some embodiments. The method 2600 is described below in more detail with reference to FIGS. 27-28, which illustrate cross-section views of a device 2700 at various stages of processing according to the method 2600. The method 2600 also combines various aspects of the methods 100, 1500, discussed above, and as such, the method 2600 will26© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) also be discussed with reference to the methods 100, 1500. It will be understood that additional process steps may be implemented before, during, and after the method 2600, and some process steps described may be replaced or eliminated in accordance with various embodiments of the method 2600. It will be further understood that parts of the method 2600 may be fabricated by a well-known CMOS technology process flow, and thus some processes are only briefly described herein.

[0078] The method 2600 begins by performing a sequence of steps 2602 to two different substrates (or wafers) including one or more semiconductor devices and MLI structures. With reference to FIG. 27, substrates 203A, 203B are provided, which may be as described above. In accordance with some embodiments, each of the substrates 203A, 203B may be processed according to the sequence of steps 2602, where the sequence of steps 2602 includes blocks 102-1 10 of the method 100, discussed above. As a result of the processing according to the sequence of steps 2602, each of the substrates 203A, 203B will have a structure substantially similar to that shown and described above with reference to FIG. 7. That is, each of the substrates 203A, 203B will include top surfaces of the respective stack of dielectric layers 212A, 212B that are substantially level with the top surface of the silicon layer 602A (e.g., polysilicon), and the overall top surface of each of the device substrates 203A, 203B is substantially flat (planar), making the substrates 203A, 203B suitable for subsequent processing. Each of the device substrates 203A, 203B may also include a seam 604A formed within the silicon layer 602A, as described above.

[0079] The method 2600 proceeds to block 2603 where a bonding process is performed. With reference to FIG. 27 and FIG. 28, in an embodiment of block 2603, the bonding process may be a hybrid bonding process which includes bonding of metal pads (e.g., such as the metallic pads 210A, 210B) and the surrounding dielectric material of the two separate substrates 203A, 203B (or two separate wafers) to create a low profile, low parasitic, high-performance interconnect therebetween. In some embodiments, the bonding process of block 2603 may be substantially the same as described above with reference to block 1503 of the method 1500. It is noted that in some cases, backsides of each of the substrates 203A, 203B may be thinned prior to the bonding process. In other cases, the backside of the substrate 203B may be thinned prior to the bonding process, while the backside of the substrate 203A is thinned after the bonding process. In yet other cases, backsides of each of the substrates 203A, 203B may be thinned after the bonding process. It is further noted27© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) that after the bonding process, the device 2700 will have a structure similar to that shown and described above with reference to FIG. 19, except that the device 2700 may have multiple seams 604A and the stacked substrate 203A is still continuous (has not been etched through) immediately after the bonding process.

[0080] After the bonding process, the method 2600 proceeds to performing a sequence of steps 2604. With reference to FIG. 28, and in accordance with some embodiments, the device 2700 may be processed according to the sequence of steps 2604, where the sequence of steps 2604 includes blocks 1512-1522 of the method 1500, discussed above. Initially, as a result of performing block 1512 of the sequence of steps 2604, the device 2700 will have a structure substantially similar to that shown and described above with reference to FIG. 20. That is, the device 2700 will include passivation layers 803, 805, a backside via 206C coupled to a conductive line 208C, a backside metal pad 807, a solder bump 810A, as well as other features previously described. At this stage, the stacked substrate 203A remains continuous (has not been etched through) at least in the dicing street region 214C. Thereafter, the remaining steps of the sequence of steps 2604 may be performed to the device 2700, resulting in a 3DIC structure that is fully diced from the wafer and that is substantially similar to the example shown and described above with reference to FIG. 25.

[0081] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.28© 2025 Qorvo US, Inc. - All Rights Reserved

Claims

Attorney Docket No. 62306.155WO01 (P241553-WO-UTL)WHAT IS CLAIMED IS:

1. A dicing method, comprising: providing a substrate comprising a stack of dielectric layers disposed over the substrate; removing the stack of dielectric layers from a dicing street region to form a trench that exposes a surface of the substrate; filling the trench with a silicon layer; and after performing a bumping process, removing the silicon layer and a portion of the substrate disposed in the dicing street region to singulate a die from the substrate.

2. The method of claim 1, wherein the stack of dielectric layers comprises a low- K dielectric material, an ultra-low-K dielectric material, or a combination thereof.

3. The method of claim 1, wherein the silicon layer comprises a polysilicon layer.

4. The method of claim 1, wherein the removing the stack of dielectric layers comprises: forming a patterned hard mask layer comprising a first opening that exposes the stack of dielectric layers in the dicing street region; and performing a dry etching process through the patterned hard mask layer to remove the stack of dielectric layers to form the trench.

5. The method of claim 4, wherein the dry etching process comprises a plasma etching process.

6. The method of claim 4, further comprising: after forming the trench, removing the patterned hard mask layer.

7. The method of claim 1, wherein the filling the trench with the silicon layer comprises: conformally depositing the silicon layer within the trench and over a top surface of the stack of dielectric layers outside the trench; and29© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) performing a chemical mechanical polishing (CMP) process to remove excess portions of the silicon layer.

8. The method of claim 7, wherein after the CMP process, a top surface of the stack of dielectric layers and a top surface of the silicon layer are substantially level with each other.

9. The method of claim 1 , wherein the silicon layer comprises a seam.

10. The method of claim 1, further comprising: after filling the trench with the silicon layer and prior to performing the bumping process, forming one or more passivation layers over the stack of dielectric layers and the silicon layer; and after performing the bumping process, performing a laser grooving process to form a second opening in the one or more passivation layers within the dicing street region.

11. The method of claim 10, further comprising: after performing the laser grooving process, performing a plasma dicing process to remove the silicon layer and the portion of the substrate to singulate the die from the substrate.

12. A method of dicing a 3D stacked wafer, comprising: providing a first substrate comprising a first stack of dielectric layers disposed over a first front side of the first substrate and a second substrate comprising a second stack of dielectric layers disposed over a second front side of the second substrate; bonding the first front side of the first substrate to the second front side of the second substrate to form the 3D stacked wafer; etching, from a dicing street, a portion of the first substrate, the first stack of dielectric layers, and the second stack of dielectric layers, to form a trench that exposes a surface of the second substrate; filling the trench with a polysilicon layer; and30© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) after forming a passivation layer over back side of the first substrate, removing the polysilicon layer and a portion of the second substrate disposed in the dicing street to singulate a die from the 3D stacked wafer.

13. The method of claim 12, further comprising: after the bonding, and before the etching performing a backside grinding process to a back side of the first substrate to provide a thinned first substrate.

14. The method of claim 12, wherein the first stack of dielectric layers and the second stack of dielectric layers comprise a low-K dielectric material, an ultra- low-K dielectric material, or a combination thereof.

15. The method of claim 12, wherein the etching comprises a dry plasma etching process.

16. The method of claim 13, wherein after filling the trench with the polysilicon layer, a surface of the thinned first substrate and a top surface of the polysilicon layer are substantially level with each other.

17. The method of claim 12, further comprising: performing a laser grooving process to form an opening in the passivation layer within the dicing street to expose the polysilicon layer; and after performing the laser grooving process, performing a plasma dicing process to remove the polysilicon layer and the portion of the second substrate disposed in the dicing street to singulate the die from the 3D stacked wafer.

18. A method, comprising: providing a first substrate comprising a first stack of dielectric layers disposed over a first front side of the first substrate and a second substrate comprising a second stack of dielectric layers disposed over a second front side of the second substrate; removing, from the first substrate, the first stack of dielectric layers from a first dicing street region to form a first trench that exposes a first surface of the first substrate; filling the first trench with a first polysilicon layer;31© 2025 Qorvo US, Inc. - All Rights ReservedAttorney Docket No. 62306.155WO01 (P241553-WO-UTL) removing, from the second substrate, the second stack of dielectric layers from a second dicing street region to form a second trench that exposes a second surface of the second substrate; filling the second trench with a second polysilicon layer; and after filling the first trench with the first polysilicon layer and the second trench with the second polysilicon layer, bonding the first front side of the first substrate to the second front side of the second substrate to form a 3D stacked wafer.

19. The method of claim 18, further comprising: after performing a bumping process, removing the first polysilicon layer, the second polysilicon layer and a portion of the second substrate to singulate a die from the 3D stacked wafer.

20. The method of claim 18, wherein the first stack of dielectric layers and the second stack of dielectric layers comprise a low-K dielectric material, an ultra- low-K dielectric material, or a combination thereof.32© 2025 Qorvo US, Inc. - All Rights Reserved

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