PPG frontend circuitry

Abstract

An apparatus comprises frontend circuitry for sampling analog PPG signals. The frontend circuitry supports configurable timeslots for inclusion within a sample frame of a succession of sample frames. The frontend circuitry comprises a light source interface, a photodetector interface, an interface for outputting a digital PPG signal to a host system, a configuration memory for storing configuration information received from the host system, an activation memory for storing activation information received from the host system, and PPG sampling circuitry. The configuration information comprises respective timeslot-specific configuration information for each timeslot of the configurable timeslots, and the activation information indicates a selection of the configurable timeslots to be active within a sample frame.

Description

[0001] 7.172.174274 - SS-582

[0002] PPG Frontend Circuitry

[0003] TECHNICAL FIELD

[0004] This application relates to frontend circuitry for sampling photoplethysmography signals, and methods for operating the same.

[0005] BACKGROUND

[0006] Many electronic devices, such as wristwatches, fitness trackers and other health devices, now support photoplethysmography (PPG).

[0007] LEDs in the device illuminate a portion of a user’s skin and photodetectors generate analog signals arising from the light that are indicative of blood volume under the skin. These analog signals may be sampled by analog frontend circuitry in the device, which converts the signals to a digital PPG signal that is passed to a host system for processing to determine heart rate, blood oxygen level, etc.

[0008] However, it can be burdensome for the host system to configure the frontend circuitry for different modes of operation.

[0009] The present invention seeks to provide an improved approach.

[0010] SUMMARY OF THE INVENTION

[0011] From a first aspect, the invention provides an apparatus comprising frontend circuitry for sampling analog photoplethysmography signals, wherein the frontend circuitry is configured to support a set of one or more configurable timeslots for inclusion within a sample frame of a succession of sample frames, and wherein the frontend circuitry comprises: a light-source interface for electrical connection to one or more light sources arranged for performing photoplethysmography; a photodetector interface for electrical connection to one or more photodetectors arranged for performing photoplethysmography; an interface for outputting a digital photoplethysmography signal to a host system; a configuration memory for storing configuration information received from the host system, wherein the configuration information comprises respective timeslotspecific configuration information for each timeslot of the set of one or more configurable timeslots; an activation memory for storing activation information received from the host system, wherein the activation information indicates a selection of the one or more configurable timeslots to be active within a sample frame; and photoplethysmography sampling circuitry providing one or more photoplethysmography signal paths for generating digital samples from analog signals received at the photodetector interface, wherein each photoplethysmography signal path is configured to receive analog signals from a different respective photodetector of the one or more photodetectors; wherein the frontend circuitry is configured to use the configuration information and the activation information to implement, within each of the succession of sample frames and for each timeslot configured for photoplethysmography and indicated as selected by the activation information, a timeslot-specific configuration of the one or more photoplethysmography signal paths of the photoplethysmography sampling circuitry, so as to generate one or more digital photoplethysmography signals for output to the host system using the interface.

[0012] According to a second aspect, the disclosure provides a method of operating an apparatus comprising frontend circuitry as disclosed herein, the method comprising: receiving, from the host system, configuration information for each timeslot in the set of one or more timeslots; storing the configuration information in the configuration memory; receiving, from the host system, activation information indicating a selection of the timeslots to be active; storing the activation information in the activation memory; using the configuration information and activation information to implement, within each of the succession of sample frames and for each timeslot configured for photoplethysmography and indicated as selected by the activation information, a timeslot-specific configuration of the one or more photoplethysmography signal paths of the photoplethysmography sampling circuitry, so as to generate one or more digital photoplethysmography signals; and outputting the one or more digital photoplethysmography signals to the host system.

[0013] Thus it will be seen that, in accordance with embodiments of the disclosure, by supporting timeslot-specific configurations, across a succession of sample frames, that can be selectively enabling by activation information, the frontend circuitry can be preconfigured (e.g. by the host system) for different usage scenarios such that the host system can then subsequently activate the relevant timeslot or timeslots simply by sending appropriate activation information. This can avoid placing a high communication and processing burden on the host system whenever a change of configuration is required by the frontend.

[0014] Each sample frame of the succession of sample frames corresponds to a respective period of time (i.e. a sampling period in a succession of sampling periods). The succession of sample frames may be contiguous in time, although one or more sample frames may include an idle portion in which no sampling occurs. Every sample frame of the succession may be of equal duration (although this may be configurable, e.g. by the host system). Each active timeslot corresponds to a respective period of time within each sample frame. The set of one or more configurable timeslots may comprise a plurality of configurable timeslots. The timeslots may have the same or different durations from each other, e.g. determined by the timeslot-specific configuration information. In some embodiments, each digital PPG sample that is output to the host system corresponds to a different respective timeslot.

[0015] In some embodiment, all of the configurable timeslots are configured for photoplethysmography (e.g. only for photoplethysmography). However, in other embodiments, a first subset of the configurable timeslots is configured for photoplethysmography, while a further subset of the configurable timeslots is configured for one or more other purposes, such as for electrocardiography. In some embodiments, one or more timeslots may be configured to sample a status of the frontend circuitry - e.g. to sample temperature or battery voltage. Which of the timeslots are configured for photoplethysmography or other purposes may be fixed (e.g. being hard-wired), or may be configurable by the host system (e.g. in accordance with data in the configuration information). The frontend circuitry may be provided by an integrated circuit, e.g. by a semiconductor chip. Thus, in some embodiments, the apparatus may be or comprise an integrated circuit chip.

[0016] In a first set of embodiments, the host system is not integrated with the frontend circuitry — e.g. comprising one or more integrated circuits (e.g. semiconductor chips or packages) that are distinct from an integrated circuit (e.g. a semiconductor chip or package) that comprises the fronted circuitry. The frontend circuitry may be configured for off-chip connection to the host system. The interface to the host system may comprise one or more pads or pins. The interface may be a serial interface. It may be configured according to a Serial Peripheral Interface (SPI) specification.

[0017] In a second set of embodiments, the frontend circuitry is integrated with the host system — e.g. on the same system-on-chip. Thus, in some embodiments, the apparatus may additionally comprise the host system. The interface may comprise a connection to a bus between the frontend circuitry and the host system, which may be an Advanced Microcontroller Bus Architecture (AMBA) bus.

[0018] The interface to the host system may be configured for receiving information by the frontend circuitry. The configuration information and / or the activation information may be received by the frontend circuitry via this interface.

[0019] The host system may be arranged to preconfigure an operation of active timeslots within each sample frame and direct the frontend circuitry to carry out the operation independently of further instructions from the host system. The frontend circuitry may be configured to implement the timeslot-specific configuration of each photoplethysmography signal path in a succession of sample frames that continues at least until the frontend circuitry receives further (e.g. different) configuration information or activation information from the host system.

[0020] The configuration memory may comprise a set of hardware registers (which may be addressable over a bus system of the apparatus). It may comprise a respective set of one or more registers for each of a predetermined maximum number of timeslots. For example, it may comprise twenty-four sets of configuration registers for storing up to twenty-four timeslot configurations. However, the configuration information received from the host system may, in some situations, include data only for a subset of these timeslots.

[0021] The activation memory may comprise one or more hardware registers (which may be addressable) for storing a set of flags, each flag corresponding to a different respective timeslot. In some embodiments, the set of flags are a set of binary flags (e.g. a bitfield, stored in a single hardware register), each binary flag corresponding to a different respective timeslot. The frontend circuitry may be configured to use the flags to determine which timeslot or timeslots to include in each sample frame of the succession of sample frames.

[0022] The PPG sampling circuitry may be connected to digital conversion circuitry comprising a set of one or more analog-to-digital converters (ADCs) for converting analog PPG signals received along each PPG signal path into digital PPG samples. Each signal path may have a different respective analog-to-digital converter. The frontend circuitry may be configured to output digital PPG samples over a communication channel (which may be integrated or off-chip) that connects the frontend circuitry to the host system. The frontend circuitry may further comprise a multiplexer which performs a time-multiplexing operation on the digital PPG samples (e.g. to write samples from different signals path sequentially into a same buffer), before the digital PPG samples are output from the frontend circuitry.

[0023] In some embodiments, the frontend circuitry comprises illumination control circuitry electrically connected to the light-source interface for turning each light source on and off.

[0024] The frontend circuitry may comprise analog-signal-adjustment circuitry for adjusting an analog signal received at the photodetector interface to attenuate or remove a DC component (e.g. due to unwanted backscatter) and / or an ambient-light component of the signal (e.g. an ambient-light component below a threshold frequency). It may be configured to pass an AC component representative of blood volume changes and any ambient-light interference components above the threshold frequency. The analog- signal-adjustment circuitry may be configured to perform DC filtering and / or ambientlight filtering. In some embodiments, the analog-signal-adjustment circuitry may comprise one or more analog filters (e.g. an analog high-pass filter in the receive path of the received analog signal).

[0025] However, in a set of preferred embodiments, the analog-signal-adjustment circuitry comprises one or more digital filters, e.g. infinite-impulse response (HR) filters, which may be programmable. The analog-signal-adjustment circuitry may be arranged to use an output of a digital filter to apply an analog adjustment to the received analog signal within a feedback loop. The analog-signal-circuitry may therefore, in some embodiments, provide a DC cancellation feedback loop. The analog-signal-adjustment circuitry may comprise a digital portion, configured to process samples output by the analog-to-digital conversion circuitry to determine a digital adjustment signal (e.g. representative of a DC component and / or an ambient-light component), and an analog portion, configured to adjust the analog signal received at the photodetector interface in accordance with the determined digital adjustment signal. The analog portion may convert the digital adjustment signal to an analog adjustment signal, and may subtract the analog adjustment signal from the received analog signal, e.g. using an analog amplifier. The analog-signal-adjustment circuitry may be configured to generate the adjustment signal by low-pass filtering the received signal. The digital portion may comprise one or more low-pass filters (e.g. low-pass HR filters).

[0026] In some embodiments, the frontend circuitry further comprises a sample control module which is configured to control the frontend circuitry according to the received configuration and activation information from the host system. The sample control module may implement a finite state machine.

[0027] The frontend circuit may also comprise an interrupt system, which is configured to send an interrupt signal in the event that one or more criteria are met by the frontend circuitry. The interrupt signal may be sent to the host system. The interrupt signal may be used to indicate that a buffer of the frontend circuitry has reached a capacity limit. The frontend circuitry may be configured for arbitrating the output of PPG samples from the frontend circuitry. The frontend circuitry may comprise a first in, first out, FIFO, memory buffer and may be configured to store digital samples in the FIFO buffer. The frontend circuitry may further comprise a system memory (e.g. RAM) and be configured to output the digital samples from the FIFO to the system memory (e.g. at intervals). The FIFO buffer may be used to temporarily hold the PPG samples while all of the active timeslots of one or more sample frames are executed. The FIFO buffer may allow the frontend circuitry to save power by reducing the frequency of write operations to a system memory or to the interface to the host system. In some embodiments, the FIFO buffer may store samples from a plurality of consecutive sample frames. In embodiments where the frontend circuitry also comprises an interrupt system, said interrupt system may be triggered when the FIFO buffer is above a threshold capacity.

[0028] The frontend circuitry may comprise a data interconnect to enable communication between components of the frontend circuitry and an interface module of the frontend circuitry (e.g. an SPI module).

[0029] The timeslot-specific configuration information for one or more timeslots may comprise a slot period multiplier value. The frontend circuitry may be configured, responsive to a slot period multiplier value (e.g. an integer p) in the timeslot-specific configuration information for an active timeslot, to suppress sampling within the timeslot for a proportion of occurrences of the timeslot over the succession of sample frames (e.g. for p occurrences out of every p+1 occurrences). The sampling circuitry may be inactive during a suppressed timeslot.

[0030] In some embodiments, the timeslot-specific configuration information for each timeslot configured for PPG may comprise information (i.e. data) for configuring the one or more light sources and / or for configuring the one or more photodetectors. It may comprise information for configuring a duration of the timeslot.

[0031] In some embodiments, the timeslot-specific configuration information for each of the timeslots configured for PPG comprises:

[0032] - a light source electrical current value; or

[0033] - a light source selection value (e.g. identifying which light sources to illuminate); or

[0034] - a photodetector selection value (e.g. identifying which photodetectors to sample); or

[0035] - a PPG gain value for each photodetector; or

[0036] - a PPG signal path settle time value; or - a PPG signal path integration time value when generating a PPG sample; or

[0037] - a PPG signal path integration time value when generating an ambient (i.e. light sources off) sample; or

[0038] - values for coefficients of for the filtering circuitry for each PPG signal path; or

[0039] - a slot period multiplier value; or

[0040] - a PPG mode selection value (e.g. for indicating whether to generate a PPG sample or an ambient sample); or

[0041] - any combination of the above.

[0042] In some embodiments, the activation information is a bit field which, when read in sequence, indicates which timeslots are active and which are inactive within the succession of sample frames.

[0043] In some embodiments, each timeslot configured for PPG may be configurable to have a duration within a predetermined interval. The interval may have a minimum duration of 8 microseconds and may have a maximum duration of 1.3 milliseconds. In an exemplary embodiment, the interval is 20 to 300 microseconds. The length of a timeslot may be configured in software by the host system, and communicated to the frontend circuitry over a bus. The length of each PPG timeslot may depend on a signal-to-noise (SNR) value at the photodetector interface - e.g. higher SNR may result in a shorter timeslot, and vice versa.

[0044] In some embodiments, the frontend circuitry is also configured to receive analog electrocardiography, ECG, signals, and comprises ECG sampling circuitry providing an ECG signal path configured for receiving analog signals from a set of one or more ECG electrodes. The output of the ECG sampling circuitry may be multiplexed into one of the PPG signal paths (e.g. such that an ECG signal path and the PPG signal path share an ADC). The frontend circuitry may be configured for outputting a digital ECG signal to the host system (optionally after storage in a FIFO buffer and / or system memory). The frontend circuitry may be configured such that one or more timeslots (e.g. corresponding to a first collection of configuration registers) are always configured for ECG (i.e. they are ECG timeslots for generating ECG samples), and one or more or all of the remaining timeslots (e.g. corresponding to a second collection of configuration registers) are always configured for PPG (i.e. they are PPG timeslots for generating PPG samples). The frontend circuitry may be configured to use the configuration information and the activation information to implement, within each of the succession of sample frames and for each timeslot configured for ECG and indicated as selected by the activation information, a timeslot-specific configuration of the ECG signal path of the ECG sampling circuitry, so as to generate a digital ECG signal for output to the host system.

[0045] In some embodiments, the timeslot-specific configuration information for each timeslot configured for ECG may comprise information (i.e. data) for configuring a duration of the timeslot.

[0046] In embodiments of the frontend circuitry which comprise ECG sampling circuitry, the timeslot-specific configuration for each ECG timeslot may comprise:

[0047] - a value for the gain of elements of the ECG sampling circuitry; or

[0048] - an ECG signal path settle time; or

[0049] - an ECG signal path integration time; or

[0050] - ECG decimation filter coefficients and / or decimation factor; or

[0051] - a slot period multiplier value; or

[0052] - any combination of the above.

[0053] In some embodiments, the frontend circuitry is further configured to pack the active timeslots in time within each sample frame — i.e., such that within the sample frame, each active timeslot is carried out consecutively. The active timeslots may be packed towards a start of each sample frame. The frontend circuitry may be configured to include an idle period after a last active timeslot in each sample frame. It may be configured to enter a power-saving state during the idle period. The inactive timeslots are unused and skipped during execution of the sample frame.

[0054] The frontend circuitry may be configured to replace the configuration information and / or activation information currently stored in the configuration memory and / or the activation memory when new configuration information and / or activation information is received from the host system. Once received, the frontend circuitry is configured to implement the new configuration and / or activation information on the timeslots of the next sample frame. The apparatus may comprise the one or more light sources and / or the one or more photodetectors. Each light source may comprise a light-emitting diode (LED). Each photodetector may comprise a photodiode. Each light source may be arranged to illuminate a portion of a human or animal body. Each photodetector may be arranged to receive light from an illuminated portion of the human or animal body. The one or more light sources and one or more photodetectors may be arranged for performing transmission PPG or for performing reflectance PPG.

[0055] In some embodiments, the apparatus may be a component for incorporation into a device, such as a wristwatch or a fingertip oximetry sensor. In some embodiments, the apparatus may be such a device. It may comprise a power supply, such as a battery.

[0056] BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0058] FIG. 1 is a schematic diagram of a wearable health device comprising frontend circuitry embodying the present invention;

[0059] FIG. 2 is a schematic block diagram of an example frontend circuitry embodying the present invention;

[0060] FIG. 3 is a schematic block diagram of another example frontend circuitry embodying the present invention;

[0061] FIG. 4 is a diagram showing an example configuration of timeslots within a sample frame as processed by frontend circuitry embodying the present invention;

[0062] FIG. 5 is a diagram showing an example of how the configuration of timeslots can vary between successive sample frames according to embodiments of the present invention;

[0063] FIG. 6 is a diagram showing exemplary successive sample frames operating using a slot period multiplier;

[0064] FIG. 7 is a flowchart showing the steps taken by frontend circuitry to implement timeslot-specific configurations within a sample frame according to embodiments of the present invention;

[0065] FIG. 8 is a diagram showing an example sample frame which is configured to operate with different PPG modes, including one configured to correct for the effect of ambient-light; and FIG. 9 is a flowchart showing the ambient-light correcting steps taken by the frontend circuitry to correct PPG samples received within a timeslot.

[0066] DETAILED DESCRIPTION

[0067] Electronic devices such as wristwatches and fitness trackers can be equipped to monitor a variety of biological parameters of a user, for example heart rate and blood oxygen saturation. This can be useful for monitoring activity levels, fitness, athletic performance, health, etc. The values of these biological parameters are determined on a wearable device using techniques that utilise analog signals, such as those generated by light incident on a photodetector, or electrical signals from an electrode pad. The analog signals are passed through frontend circuitry, which converts the analog signals into digital signals for processing by a host system of the device comprising a host processor and memory.

[0068] Figure 1 shows an example device 100 embodying the present invention. This example is wearable (e.g. a wristwatch) although this is not essential in all embodiments.

[0069] The wearable device 100 comprises an optical assembly 110 containing one or more light sources (e.g. light emitting diodes - LEDs), and one or more photodetectors (PDs - e.g. photodiodes) arranged for reflectance photoplethysmography (PPG). Other embodiments may be arranged for transmissive PPG. The device 100 also comprises an ECG port 150 for coupling the device 100 to a set of external ECG electrodes 152, for receiving electrical impulse data from the user of the device 100.

[0070] The optical assembly 110 and ECG port 150 are electrically connected to frontend circuitry 200, which converts the received analog signals from the optical assembly 110 and ECG electrodes 152 into digital signals to be processed by a host system 120. The host system 120 comprises a host processor and host memory. The host memory may store software for execution by the host processor.

[0071] The frontend circuitry 200 also controls operation of the optical assembly 110 in accordance with instructions from the host system 120. The digital signals are communicated to the host system 120 over a communication channel 140. This channel 140 may be a serial connection which follows the Standard Peripheral Interface (SPI) standard (e.g. when the frontend circuitry 200 is provided by a first IC device and the host system 120 is provided by a second IC device), or it may be an integrated bus of a system-on-chip (e.g. when the frontend circuitry 200 and the host system 120 are integrated on a common IC device).

[0072] The host system 120 comprises a processor (e.g. a CPU) and memory, and processes the digital signals received from the frontend circuitry 200 to determine values of biological parameters. It may store these values and / or process them further. It may output information derived from the digital signals to the user, e.g. via a display of the device 100, or over a wired or wireless network connection.

[0073] The wearable device 100 in this example is powered by an internal battery 130. In some embodiments, the battery 130 is rechargeable. The device 100 may have other components, not shown here, such as a display, buttons, loudspeaker, additional sensors, etc. It may be in a housing which may include a strap or other fastening mechanism for fastening to a user.

[0074] The device 100 can perform photoplethysmography (PPG). PPG is a non-invasive optical technique used to detect blood volume changes in the microvascular bed of tissue of a user. The LEDs of the optical assembly 110 emit light (usually in the infrared or green spectrum) through the user’s skin, and the photodetector(s) capture light reflected or transmitted through the body. Variations in light intensity over time correspond to changes in blood volume.

[0075] Sampling PPG signals accurately is challenging due to motion artefacts, ambient light interference, and low signal-to-noise ratio (SNR). Variability in skin properties and temperature sensitivity further complicate signal accuracy. These challenges require advanced signal processing and adaptive techniques to ensure reliable PPG signal acquisition while consuming as little power as possible.

[0076] Adaptive PPG signal processing techniques and algorithms can require large amounts of data to converge on a result quickly and reliably. The situations in which the device 100 is used change over time - such as when a user of the wearable device 100 is sleeping, or is moving around a home environment, or is running outdoors. These different activities and environments may benefit from different amounts and types of data to be collected with different receiver path configurations. For example, a high frequency of pulse rate measurement may be desired while exercising, but a lower frequency is acceptable while sleep in order to preserve the life of the battery 130. Also, the ambient light conditions can differ significantly (e.g. from a dark room while sleeping, to bright daylight while out running), which may affect the output of the photodetectors. To provide this flexibility, data can be sampled by the frontend circuitry 200 using any of various analog receiver path configurations, as instructed by the host system 120. As explained in more detail below, these configurations include, for example, LED on / off selection for signal and ambient light measurement, LED driving current, LED selection (i.e. choosing a wavelength range), photodetector input selection, receiver gain settings, signal integration time, digital filter settings, and more.

[0077] If the host system 120 has to reconfigure the signal receiver path settings frequently during sampling, this could require numerous runtime register writes by the host software of the device 100, thereby keeping the processor of the host system 120 running continuously and leading to high power consumption. However, embodiments disclosed herein can avoid this by supporting pre-configured settings as described below.

[0078] The device 100 also supports electrocardiography (ECG). ECG measures the electrical activity of the heart using electrodes placed on the skin. Similarly to the challenges faced by standard PPG systems, ECG receiver signal sampling is challenging due to low amplitude signals, motion artefacts, baseline wander, and power line interference. Variability in electrode-skin impedance further complicates signal quality. These issues require advanced filtering and adaptive techniques to ensure accurate ECG data acquisition. The host system 120 of the device 100 therefore needs to contend with a large volume of data, which, if not efficiently implemented, could lead to high processor load and short battery life.

[0079] However, the frontend circuitry 200 disclosed herein can help mitigate some of these challenges.

[0080] Figure 2 shows a detailed block diagram of the frontend circuitry 200 according to some embodiments. In this example, the frontend circuitry 200 is implemented as a semiconductor chip, with a number of connection pads to which the various external components can be connected. It may be mounted on a common printed circuit board (PCB) with a host system 120 chip within a housing of the device 100.

[0081] A first set of connection points (e.g. pads) LEDO to LED5 are for six LEDs. Each LED is controlled by and connected to an LED driver module 216 of the frontend circuitry 200. Whilst six LED connection points are shown in this embodiment, the frontend circuitry 200 may be configured to support fewer connection than this (i.e. five or less) or it may be configured to support more (i.e. seven or more). The frontend circuitry 200 may comprise enough connection points to support any number of LEDs. In use (i.e. when the frontend circuitry 200 is incorporated within the wearable device 100), it is not necessary for all of the connection points to connect to an LED.

[0082] Connection points (e.g. pads) PD0, PD1, PD2, PD3 for respective photodetectors (e.g. photodiodes, metal-semiconductor-metal (MSM) photodiodes, or any other suitable photosensor) are also arranged on the frontend circuitry 200. As with the LEDs, the frontend circuitry 200 may, in some embodiments, support more than four photodetector connections (i.e. five or more), or fewer (i.e. three or less).

[0083] Corresponding photodetectors of the optical assembly 110 may therefore connect to the photodetector connection points when the frontend circuitry 200 is incorporated in the wearable device 100.

[0084] The photodetectors which connect to the frontend circuitry 200 via their respective connection points enable the frontend circuitry 200 to receive analog signals that can be used in PPG measurements. More detail on how the frontend circuitry 200 handles PPG measurements will be provided below.

[0085] In addition to the LED and photodetector connection points, the frontend circuitry 200 comprises connection points for connection to the port 150 and from there to a removable set of ECG electrodes 152 (which may be provided separately from the device 100). These connection points are: a positive terminal (ECGP), a negative terminal (ECGN), and a right-leg drive terminal (RLD). The RLD electrode which connects to the RLD terminal helps to reduce the effect of common mode interference when collecting ECG measurements. In some situations, the RLD terminal may not be used (i.e. an RLD electrode is not connected) depending on the use case of the frontend circuitry 200. The frontend circuitry 200 also has a set of external SPI connection points and an IRQ (interrupt request) connection point for communicating with the host system 120. It may have additional connection points (e.g. pads or pins) that aren’t shown here, e.g. a power input, clock input, connections to other off-chip components, etc. While the frontend circuitry 200 is described below with an SPI interface, in some embodiments any other appropriate communication interface may be used.

[0086] The frontend circuitry 200 receives the analog signals from the ECG and PD connection points and passes them through hardware circuitry that generates digital samples for output to the host system 120.

[0087] Each photodetector connection point (PD0 to PD3) is connected to a dedicated signal path that first passes the current signal received from each photodetector through a respective transimpedance amplifier (TIA) 201. Each TIA converts the received current signal to a voltage signal, which is then digitised using a respective analog-to-digital converter (ADC) 202. Each ADC 202 output is provided to a respective decimation filter module 203.

[0088] The signals produced by the photodetectors can contain DC components and / or ambient light interference and / or motion artefacts, and may exhibit low signal-to-noise ratios. However the frontend circuitry 200 comprises filters 213 to apply coarse filtering by analysing the signals output from the decimation filter modules 203 and adjusting the received analog signal to at least partly address these issues. Additional digital ambient-light compensation may also be applied by the frontend circuit 200, when appropriate, as explained in more detail below, e.g. to provide more rapid adaptation in case of fast-changing lighting situations.

[0089] The signals produced by the photodetectors may, in some circumstances, only originate from ambient light (i.e. when the LEDs are all off), e.g. when the frontend circuitry 200 is configured to operate in a purely ambient mode for all or a portion of a timeslot.

[0090] The filters 213 are used to adjust the analog signals received at the photodetector interface so as to attenuate DC and slow-changing ambient-light interference. They are part of a feedback loop that takes the digital signals output from each of the decimation modules 203 and passes them through the bank of DC and ambient-light filters 213 to determine an analog adjustment signal to apply to the incoming analog signals. These filters 213 are, in some examples, infinite impulse response (HR) filters, though any appropriate type of filter or combination of filters may be used. The DC and ambient-light filters may be separate banks of filters which operate in parallel. They act to isolate a component of each signal that corresponds to ambient light (i.e. light incident on each photodetector that did not originate from an LED driven by the LED driver 216) and / or a DC offset caused by the LEDs (e.g. produced by backscattering of light that originated from material that is not blood, such as glass, plastics, other tissue, etc.). These filters 213 may isolate these components using low-pass filters. The filters may be programmable to support a custom filtering level. In some embodiments, a DC adjustment signal may be determined when one or more LEDs are on, and an ambient adjustment signal may be determined when all of the LEDs are off.

[0091] The DC and ambient-light filters 213 generate a digital adjustment signal for each photodetector that represents the slow-changing ambient-light and DC components of that photodetector’s signal. The output adjustment signals are then converted into analog adjustment signals using respective digital-to-analog converters (DACs) from a set of DACs 204 and subtracted from the incoming analog signals using subtraction modules 205 (e.g. analog amplifiers). Each subtraction module 205 is arranged on a signal path immediately after the respective photodetector connection point of the signal path, so that the subtraction of the DC and ambient-light baseline can be applied to each analog signal following the signal path before any further processing occurs.

[0092] While this analog filtering accounts for longer term changes in ambient light conditions, it cannot always correct adequately for faster changing ambient light conditions, such as a sudden change in the lighting of the environment of the user. A way of providing more fine control of the effects of ambient light in the received signals will be discussed in more detail below in relation to a “tri-mode” PPG operating mode of the frontend circuitry 200.

[0093] The signals which are input to the frontend circuitry via the ECG connection points, ECGP, ECGN, and RLD, are passed through ECG circuitry 206. The ECG circuitry 206 may comprise various filters and amplifiers for providing appropriate analog ECG signals to be sampled. For example, in some embodiments, the ECG circuitry 206 comprises an instrumentation amplifier to boost the differential signal between electrodes, common-mode rejection circuitry to eliminate noise, and high-pass and / or low-pass filters to isolate the frequency band of interest (typically 0.5 to 150 Hz). The ECG circuitry 206 may also comprise one or more antialiasing filters (AAFs).

[0094] Once the ECG signals have been processed by the ECG circuitry 206, a single analog ECG signal can be introduced to the analog signal processing pipeline via a multiplexer which takes as inputs the output of the ECG circuitry module 206 and the output from the TIA connected to the photodetector connection point PD3. While this is not depicted in Figure 2, the decimation modules 203 in some embodiments may comprise a further decimation module dedicated to ECG signals, or the decimation module connected to the connection point PD3 may contain additional circuitry for handling the ECG signal.

[0095] The samples from the decimation modules 203 pass into a multiplexer 207. This allows the digital signals to be interleaved using time-multiplexing with the output of the multiplexer 207 being provided to a master interface module 208 arranged as part of the frontend circuitry 200. The master interface module 208 comprises a set of first in first out (FIFO) buffers, a direct memory access (DMA) module, and an Advanced High-performance Bus (AHB) master interface module. The digital signals output from the multiplexer 207 are held in the FIFO buffers. The AHB master interface module and the DMA module work together to communicate the digital data via the AHB protocol across a bus interconnect 209 compliant with the Advanced Microcontroller Bus Architecture (AMBA) standard. The master interface module 208 acts as a bus master and can read & write data to & from a memory (e.g. RAM or Flash) 214, an SPI module 212 and a slave interface module 210.

[0096] The bus interconnect 209 is connected to other modules of the frontend circuitry 200, for example a memory 214 over an Advanced extensible Interface (AXI) connection.

[0097] The frontend circuitry 200 comprises a slave interface module 210, which comprises a set of addressable hardware registers and interrupt request (IRQ) logic. The IRQ logic is connected to an IRQ connection point on the frontend circuitry 200, so that interrupt signals can be output from the frontend circuitry 200 to the host system 120, which will be discussed in more detail later. The slave interface module 210 is connected to the bus interconnect 209 over an Advanced Peripheral Bus (APB) connection.

[0098] In some embodiments, the AHB, AXI, and APB protocols described above may be replaced with any other suitable bus protocol(s).

[0099] The addressable hardware registers can store configuration information and activation information for controlling the operation of the frontend circuitry 200. The configuration information and activation information are determined by and provided to the frontend circuitry 200 by the host system 120, e.g. over an SPI bus.

[0100] In addition to having connection points for analog signals received from the optical assembly 110, the frontend circuitry 200 can also send and receive digital signals over a Serial Peripheral Interface (SPI) bus. Figure 2 shows the frontend circuitry 200 with an SPI module 212. The SPI module 212 is connected to SPI pinouts for chip select (SPI_SEL), serial clock (SPI_CLK), data input (SPI_DI), and data output (SPI_DO) as required by SPI. The SPI module 212 connects to the bus interconnect 209 via an AXI connection. While an SPI module 212 has been shown in this embodiment of the frontend circuitry 200, the skilled person will understand that, in other embodiments, any other suitable communication interface and / or protocol may be used to interface the frontend circuitry 200 with other modules or circuitry, such as the host system 120 of the device 100.

[0101] The frontend circuitry 200 is controlled by a control module 211 , which comprises hardware logic circuitry implementing a finite state machine. While not depicted in Figure 2 for clarity, the control module 211 is connected to various of the components of the frontend circuitry 200, including the slave interface module 210, the multiplexer 207, the LED driver module 216, the ECG circuitry 206, and the DC and ambient-light filters 213. When the addressable hardware registers are loaded with configuration information and activation information, the control module 211 acts to operate the frontend circuitry according to the loaded information.

[0102] Figure 3 shows a variant embodiment that is similar to that of Figure 2, but in which the frontend circuitry is integrated with the host system 120 on a single system-on-chip (SoC) 220. The host system 120 may be provided by a microcontroller that is integrated with the frontend circuitry. It may execute software from local memory within the microcontroller and / or from the shared memory 214. Instead of using an external SPI link, the host system 120 can communicate directly with the master interface module 208 and slave interface module 210 over an AXI connection 218 to the bus interconnect 209. However, in further variants, SPI communication could still be used even when the host system and frontend circuitry are integrated. In Figure 3, the IRQ line from the slave interface module to the host system 120 is provided on the SoC 220, rather than over an external connection.

[0103] When the frontend circuitry 200 is operational (i.e. receiving and sampling analog signals), it divides time into consecutive sampling periods called sample frames. Figure 4 shows a representative sequence of three sample frames, and provides more detail of the composition of the second sample frame by way of example. The length of the sample frames determines an overall sample rate of the frontend circuitry 200. The frame length can be configured by the host system 120 communicating to the frontend circuitry 200. In some embodiments, each frame may be configured by the host system 120 to be between 61 microseconds and 500 milliseconds in length.

[0104] Each sample frame can contain zero or more active timeslots. Each active timeslot generates zero or one sample from each photodetector or from the ECG circuitry in each sample frame. The frontend circuitry 200 is configured to support a preconfigured maximum number, N+1, of timeslots — e.g. a maximum of ten (N=9) or twenty-four (N=23) or any other appropriate number. The timeslots are numbered sequentially. The slave interface module 210 contains a respective set of hardware configuration registers for each timeslot (for storing configuration information for that timeslot), and the master interface module 208 contains a respective FIFO buffer for each timeslot.

[0105] Whilst timeslots will be described below with particular reference to PPG or ECG signals, one or more timeslots may be used instead to sample other signal types, including monitoring a status of the frontend circuitry. For example, a timeslot may be used to sample a temperature of one or more elements of the frontend circuitry, or a voltage supplied by the battery 130. Each timeslot has its own configuration information, so can potentially be configured differently from any other timeslot (e.g. in terms of gain settings, timeslot duration, analog filter coefficients, etc.). Some of the timeslots may be dedicated PPG timeslots, while another timeslot or timeslots may be dedicated for ECG. This allocation may be hardcoded or may be configurable.

[0106] At any point in time, all or a selected subset of the timeslots may be active for current and future sample frames. This is accomplished by the host system 120 enabling a selection of the timeslots. The selection remains active until the host system 120 enables a different set of timeslots. The host system 120 does this by sending activation information to the slave interface module 210, specifying which of the preconfigured timeslots should be enabled. This activation information can be received into an activation hardware register as a bit field of N+1 bits, denoting in binary which timeslots should currently be enabled and which should be disabled. Thus, a first succession of sample frames could have all of the timeslots active, when the host system 120 desires to have as much data as possible (e.g. when the user of the device is engaging in strenuous exercise), and a subsequent succession of sample frames could have only one timeslot active, to save power (e.g. when the user is asleep).

[0107] Configuration of each timeslot of a sample frame is stored in the hardware registers of the slave interface module 210. The control module 211 uses the configuration stored in the registers to implement the configuration specific to each timeslot when that timeslot is enabled. The configuration information is set by the host system 120, and is communicated to the frontend circuitry 200 over the bus 140 (which may be an SPI bus coupled to the SPI module 212, or which may be the AXI connection 218). The activation information is communicated to the frontend circuitry 200 in the same way.

[0108] This arrangement advantageously enables the host system 120 to pre-configure timeslots before activating them — potentially long in advance of enabling them. For example, the host may configure some or all of the timeslots upon boot-up or reset of the device 100. The host system 120 need then only send relatively-short N+1 bit words of activation information whenever a change of behaviour of the frontend circuitry is desired (e.g. to enter a reduced-power mode). This can be very efficient in terms of communication overhead, since the activation information is expected to be updated more often than the configuration information.

[0109] An example sample frame is decomposed in Figure 4. This particular sample frame has all N+1 timeslots enabled, although other sample frames may have fewer timeslots enabled. The first timeslot in the sample frame shown in Figure 4, Slot N (ECG), is assigned for ECG measurements. This ECG timeslot comprises a reset portion to allow the frontend circuitry 200 to prepare to sample new ECG signals, followed by an ECG settle period, where the ECG circuitry 206 (e.g. the filters and amplifiers thereof) settle, followed by an ECG integration stage, wherein the ECG signals are processed through the signal path and written into the FIFO buffer N in the master interface module 208.

[0110] The ECG timeslot can be configured according to one or more of a number of parameters. The value of the parameters is set in software by the host system 120, and form part of the configuration information that is stored in the slave interface module 210 hardware registers. These parameters may include, but are not limited to: Gain of the ECG circuitry 206 ECG receive path settle time ECG integration time ECG decimation filter coefficients and decimation factor SlotPeriodMultiplier

[0111] The parameter SlotPeriodMultiplier is explained below with reference to Figure 6.

[0112] In general, when the ECG timeslot is enabled, one digital ECG sample is output to a corresponding FIFO buffer N at each sample frame (unless the SlotPeriodMultiplier is active).

[0113] There is only a single ECG timeslot in the sample frame of Figure 4. However, other embodiments may support multiple ECG timeslots. The ECG slot is depicted in Figure 4 as being at the start of the sample frame, thus in general following an idle period at the end of a preceding sample frame. This need not be the case in all embodiments, but appropriate steps may be required to ensure that circuitry (e.g. amplifiers) have settled if it occurs between PPG timeslots. The remaining timeslots of the sample frame in Figure 4 are configured for PPG measurements. Before the PPG timeslots of the sample frame can be enacted, the transimpedance amplifiers (TIAs) of the frontend circuitry 200 are first allowed to settle, following the ECG timeslot, to avoid erroneous signals.

[0114] Slots 0 to N-1 are designated in the sample frame of Figure 4 as PPG timeslots. Each PPG timeslot can have a timeslot-specific configuration according to one or more of a number of parameters set within the configuration information received from the host system 120 and stored in the hardware registers. These may include, but are not limited to:

[0115] LED electrical current

[0116] LED selection (i.e. which of the six LEDs are active) Photodetector selection (i.e. which of the four photodetectors are active) PPG gain for each photodetector (e.g. determined by the respective TIA 201) PPG receive path settle time (when generating a PPG sample) PPG signal path settle time (when generating an ambient-light (AMB) sample) PPG integration time (when generating a PPG sample) PPG integration time (when generating an AMB sample) DC and ambient filter coefficients per PPG signal path (i.e. per photodetector) SlotPeriodMultiplier

[0117] PPG mode selection: single-PPG mode I single-AMB mode I tri-mode

[0118] Taking Slot 1 (PPG) from Figure 4 as an example, each signal path of the frontend circuitry 200 (i.e. all four photodetectors) is active, although this is not necessarily the case for other PPG timeslots of the sample frame. Regardless of the number of active signal paths, each has reset, PPG settle, and PPG integration portions, similarly to the ECG timeslot described above. The reset portion prepares the frontend circuitry for obtaining a sample. The PPG settle portion allows the DACs 204, TIAs 201, and ADCs 202 , to settle. The sample is obtained over the integration period. The time taken for the reset, settle, and integration portions of the PPG timeslot determines the length of the PPG timeslot. The duration of each PPG timeslot can vary according to the configuration settings, and may range from 8 microseconds to 1.3 milliseconds. In some preferred embodiments, this range may be 20 to 300 microseconds, although this can vary between implementations. All active PPG signal paths (i.e. photodetectors) of a given PPG timeslot are sampled simultaneously (i.e. in parallel), but are buffered before the multiplexer 207 so that they can be written to the FIFO buffer corresponding to the current timeslot in a sequential, time-multiplexed manner. In some embodiments, the FIFO buffer may accept multiple simultaneous writes, i.e. one from each signal path.

[0119] When the master interface module 208 detects that a FIFO buffer is full or nearly full, the master interface module 208 will write the buffer contents out to the memory 214 (e.g. using DMA transfer). It may also send an IRQ signal to the host system 120 to alert the host to read the data from the memory 214, for example via the SPI module.

[0120] As with the ECG timeslot, each PPG timeslot corresponds with a specific FIFO buffer, such that the sampled PPG signals do not become disordered from sample frame to sample frame. Figure 4 shows the contents of four exemplary FIFO buffers for four timeslots at the bottom of the diagram. Each contains data collected over multiple sample frames. Looking at the FIFO buffers for Slot 0 and Slot N-1 , it can be seen that only one PPG signal path was active, connected to photodetector PD0, and the buffers for Slots 0 and N-1 only contain samples from that one signal path (denoted PD0 in Figure 4). By contrast, all four signal paths of the frontend circuitry 200 are active in Slot 1, and the corresponding buffer contains a sample from each signal path in turn (denoted PD0, PD1 , PD2, and PD3 in Figure 4). This FIFO buffer will fill four times as rapidly.

[0121] After all the active timeslots in a sample frame have been implemented, any remaining time in the sample frame, before the next sample frame begins, will be idle, as shown by the IDLE time in Figure 4. This may, in practice, fill a large majority of each sample frame. When this occurs, the frontend circuitry 200 is configured to enter a low power state in order to conserve power from the battery 130. This may also involve stopping a clock signal to parts of the frontend circuitry 200. Even when the frontend circuitry 200 is active, any signal paths that are not required in a current timeslot may be put into a low power state, e.g. with their TIAs 201, ADCs 202, decimation filter modules 203 and filters 213 turned off. To maximise the idle time at the end of each sample frame, the frontend circuitry 200 packs the active timeslots in time at the start of each sample frame such that active timeslots execute consecutively. In some embodiments, the time packing is performed by the control module 211.

[0122] Figure 5 shows in more detail how the configuration information and the activation information can be used in combination to efficiently configure timeslots within different sample frames. In this example, the frontend circuitry supports ten timeslots, slot 0 - slot 9, where slot 9 is always an ECG timeslot and slots 0-8 are PPG timeslots. The host system has, at first time, configured each timeslot according to configuration information 501, which sets the values of the parameters each timeslot implements when it is active. A first example sample frame X, shown in Figure 5, is then set to only have a subset of these slots enabled (slots 2, 3, 6, 7, and 9), according to activation data 502.

[0123] The configuration information 501 is shown in Figure 5 as a list of timeslots, with timeslot-specific configurations A, B, C etc. for each timeslot. Some timeslot-specific configurations may be the same, or they may all be different. Each timeslot-specific configuration may comprise any of the parameters set out above. The activation information 502 is shown in Figure 5 as a bit field, with a value of 1 indicating that the corresponding slot is active (enabled), and a value of 0 indicating that the corresponding slot is inactive (disabled).

[0124] Thus, once the configuration information 501 and activation information 502 have been received by the frontend circuitry 200 at the hardware registers of the slave interface module 210, the frontend circuitry 200 will implement the configuration parameters for each of the enabled timeslots from that sample frame onwards, until new configuration information or activation information is received.

[0125] Without time packing in sample frame X, inactive slots 4 and 5, for example, would add dead time in between execution of active slots 3 and 6. However, with time packing, the frontend circuitry 200 can ensure that all of the active slots within a sample frame execute immediately one after the other, to maximise power efficiency. Figure 5 also shows a later sample frame Y. No new configuration information has been received by the frontend circuitry 200, and so the currently stored configuration information 501 is maintained. However, new activation information 503 has been received, and so a different selection of timeslots, configured according to the configuration information 501, is active (slot 0 as PPG and slot 9 as ECG with all other slots inactive) during sample frame Y and many successive sample frames.

[0126] Some time later, new configuration information 504 and new activation information 505 are received. Each timeslot has a new configuration of parameters, and a new selection of those timeslots are set as active during the sample frame Z. As with the previous sample frames, the timeslots of sample frame Z are time packed.

[0127] One of the parameters listed above for both ECG and PPG slots is a SlotPeriodMultiplier. This parameter takes a positive integer value (e.g. p = 0, 1, 2, etc.), and sets how often the specific slot is sampled across multiple sample frames. Specifically, the slot is sampled every (p+1)thsample frame. Thus, when SlotPeriodMultiplier is zero, then the slot is sampled in every sample frame. When SlotPeriodMultiplier is one, the slot is sampled every alternate sample frame. In sample frames where the timeslot is suppressed, it still occupies the same amount of time, but no sample is generated.

[0128] Figure 6 shows the effect of the SlotPeriodMultiplier parameter on the slots of successive sample frames. Figure 6 shows three consecutive sample frames, operating with the same configuration and activation information, and with a time axis moving from left to right. The configuration of the sample frames match those of sample frame i+1 from Figure 5 - i.e. there are only two active slots, slot N for ECG, and slot 0 for PPG. Slot N is also set with a SlotPeriodMultiplier value of one, so that slot N is not sampled every other sampling frame.

[0129] Thus, in the second sample frame, the ECG slot N is not sampled, as represented by the dashed mark 600, whereas the slot is sampled in the first and third sample frames. The PPG slot, slot 0, is configured with a SlotPeriodMultiplier value of zero, such that the PPG slot is sampled in every sample frame in the series until new configuration and / or activation information is received to override the previous activation and / or configuration. Figure 7 shows a flowchart 700 of a method for operating the frontend circuitry 200 according to an embodiment of the present invention. Firstly, at step 701 , the frontend circuitry 200 reads configuration information received over a configuration interface, for example the SPI module 212 in the case of the frontend circuitry 200, or the data bus 218 in the case of the SoC 220. The configuration information is stored in addressable hardware registers of the slave interface module 210.

[0130] In step 702, the frontend circuitry reads activation information to set which timeslots will be active in the current sample frame.

[0131] In step 703, the frontend circuitry 200, via the control module 211 , time packs the selected timeslots for the next sample frame. Thus, all of the active timeslots within the sample frame execute consecutively without any idling time, with the remainder of the sample frame being filled with idle time if needed.

[0132] In step 704, the frontend circuitry 200 samples signals during the sample frame according to the implemented timeslot configuration and activation.

[0133] At the same time, the frontend circuitry 200 checks, at step 705, to see if any new configuration information and / or activation information have been received from the host system 120. If not, the frontend circuitry 200 implements the next sample frame with the same configuration and activation information (albeit the behaviour may be different if any SlotPeriodMultiplier setting is active). If there has been an update, the new information is read and implemented for the next sample frame.

[0134] As noted above, the analog filtering provided by the DC and ambient filters 212 is designed to account for longer-term changes in environmental conditions of the wearable device 100. However, the frontend circuitry 200 also supports applying digital ambient-light compensation method to individual PPG samples, which can provide much faster compensation. This short-term ambient-light correction method is named “tri-mode” in the following discussion. By performing this on the hardware circuitry of the frontend circuitry 200, the host system 120 can receive already-compensated PPG samples, rather than having to receive separate ambient-light and PPG samples in order to perform compensation itself. This can reduce the processing load on the host system 120, and can reduce storage and communication requirements, thus saving power and memory requirements.

[0135] Tri-mode is a mode that the host system 120 can selectively implement for any PPG timeslot. Figure 8 shows an example sample frame that contains a PPG timeslot configured to operate in a single-PPG mode, in which a single PPG sample is generated with one or more LEDs active, and another PPG timeslot that is configured to operate in tri-mode. A tri-mode PPG slot involves first sampling ambient-light signals with all six LEDs inactive, then obtain by a single-PPG sample with one or more LEDs active, followed by obtaining a second ambient-light sample. The first and second ambient sample sub-slots are labelled as AMB1 and AMB2 respectively in Figure 8. Each AMB sub-slot comprises reset, PPG settle, and integration portions, as described above. The settle and integration times are implemented according to the respective AMG and PPG values specified in the configuration information for the timeslot. As a result, three samples are obtained during the timeslot (AMB1 , PPG, AMB2), instead of the usual single sample.

[0136] Once the three samples have been collected by the frontend circuitry 200, the control circuitry 211 calculates the tri-mode PPG sample value according to the following equation: where PPG represents the single PPG sample which has been sampled by the frontend circuitry 200.

[0137] Thus, the frontend circuitry 200 collects samples of the ambient light conditions immediately before and after a PPG measurement, calculates the mean average of these ambient samples, and adjusts the PPG sample by subtracting the mean average from the PPG sample, to produce a compensated PPG sample.

[0138] The adjusted PPG sample is stored to the FIFO buffer for the timeslot, while the two ambient samples are discarded. In this way, the FIFO buffer does not fill any faster than when using single-PPG mode, and the communication overhead to the host system is not increased. Since the frontend circuitry 200 has performed the digital compensation, this saves the host system 120 from having to process three separate samples, which would have been required if the host system 120 had been programmed to perform the same compensation, and avoids the need to transfer additional ambient-light samples to the host system 120.

[0139] It will be appreciated that, while the digital ambient light compensation method described here utilises two ambient light samples, it is possible for only a single ambient light sample to be used. Thus, the ambient light correction method could involve sampling ambient light signals either immediately before or immediately after a PPG sample, and subtracting the result from the PPG sample to produce the final corrected value. This may not be as effective at correcting for ambient-light effects as the full tri-mode method, but will still be better at compensating for fast changing lighting conditions than the DC and ambient filter feedback loop of the frontend circuitry. The reduced ambient-light correction method may also be advantageously used if memory and / or power constraints are imposed, such as for low power modes of a wearable device.

[0140] Figure 9 shows a flowchart for a method 900 of compensating digitally for ambient-light using a tri-mode PPG slot described above. Firstly, at step 901, the LED driver module controls all of the LEDs to be off. The signals received along the photodetector signal paths will thus represent the ambient light conditions of the wearable device 100.

[0141] At step 902, the frontend circuitry 200 creates a first ambient light sample by receiving the ambient light signals from the photodetector and converting it to a digital sample, and stores it in a register. At step 903, the LED driver module directs one or more LEDs to be active (based on the configuration information). At step 904, the frontend circuitry 200 captures a PPG sample and stores it in a register. At step 905, the LED driver module controls all of the LEDs to be off once again. At step 906 a second ambient light sample is obtained and stored in a further register.

[0142] Finally, the ambient light is compensated for in step 907 by calculating, using hardware circuitry of the frontend circuitry 200, an average of the two digital ambient light signal samples, and subtracting the result from the digital PPG sample. Although this has been described for one signal path (i.e. one photodetector), tri-mode may be implemented for any number of photodetectors within a timeslot, with the adjusted PPG sample for each photodetector being written in turn to the FIFO buffer for the timeslot.

[0143] Thus, it can be seen that the frontend circuitry 200 can offload processing burden from the host system 120, and avoid additional traffic along communication buses. Since the frontend circuitry 200 has pre-processed the PPG data to compensate for ambient light, the data received at the host system 120 is in a form more convenient for the host system 120, and so clock cycles are freed up for the host processor to perform other tasks. Power consumption of the device 100 as a whole can be reduced as a result.

[0144] It will be appreciated by those skilled in the art that the invention has been illustrated by describing one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible, within the scope of the accompanying claims.

Claims

CLAIMS1. An apparatus comprising frontend circuitry for sampling analog photoplethysmography signals, wherein the frontend circuitry is configured to support a set of one or more configurable timeslots for inclusion within a sample frame of a succession of sample frames, and wherein the frontend circuitry comprises: a light-source interface for electrical connection to one or more light sources arranged for performing photoplethysmography; a photodetector interface for electrical connection to one or more photodetectors arranged for performing photoplethysmography; an interface for outputting a digital photoplethysmography signal to a host system; a configuration memory for storing configuration information received from the host system, wherein the configuration information comprises respective timeslotspecific configuration information for each timeslot of the set of one or more configurable timeslots; an activation memory for storing activation information received from the host system, wherein the activation information indicates a selection of the one or more configurable timeslots to be active within a sample frame; and photoplethysmography sampling circuitry providing one or more photoplethysmography signal paths for generating digital samples from analog signals received at the photodetector interface, wherein each photoplethysmography signal path is configured to receive analog signals from a different respective photodetector of the one or more photodetectors; wherein the frontend circuitry is configured to use the configuration information and the activation information to implement, within each of the succession of sample frames and for each timeslot configured for photoplethysmography and indicated as selected by the activation information, a timeslot-specific configuration of the one or more photoplethysmography signal paths of the photoplethysmography sampling circuitry, so as to generate one or more digital photoplethysmography signals for output to the host system using the interface.

2. The apparatus of claim 1 , wherein the frontend circuitry is an integrated circuit.

3. The apparatus of claim 2, wherein the host system is not integrated with the frontend circuitry.

4. The apparatus of any preceding claim, wherein the succession of sample frames is contiguous in time.

5. The apparatus of any preceding claim, wherein the frontend circuitry is configured to implement the timeslot-specific configuration of each photoplethysmography signal path in a succession of sample frames that continues at least until the frontend circuitry receives further configuration information or activation information from the host system.

6. The apparatus of any preceding claim, wherein the configuration memory comprises a respective set of one or more hardware registers for each of a predetermined maximum number of timeslots.

7. The apparatus of any preceding claim, wherein the activation memory comprises one or more hardware registers for storing a set of flags, each flag corresponding to a different respective timeslot, and wherein the frontend circuitry is configured to use the flags to determine which timeslot or timeslots to include in each sample frame of the succession of sample frames.

8. The apparatus of any preceding claim, wherein the frontend circuitry comprises illumination control circuitry electrically connected to the light-source interface for turning each light source on and off.

9. The apparatus of any preceding claim, wherein the frontend circuitry comprises analog-signal-adjustment circuitry for adjusting an analog signal received at the photodetector interface to attenuate or remove a DC component of the signal.

10. The apparatus of any preceding claim, wherein the photoplethysmography sampling circuitry provides a plurality of photoplethysmography signal paths for generating digital samples from analog signals received at the photodetector interface, wherein each photoplethysmography signal path comprises a respective analog-to-digital converter and is configured to receive analog signals from a different respective photodetector of the one or more photodetectors.

11. The apparatus of any preceding claim, wherein the timeslot-specific configuration information for one or more timeslots comprises a slot period multiplier value, and wherein the frontend circuitry is configured, responsive to the slot period multiplier value in the timeslot-specific configuration information for an active timeslot, to suppress sampling within the active timeslot for a proportion of occurrences of the active timeslot over the succession of sample frames.

12. The apparatus of any preceding claim, wherein the timeslot-specific configuration information for each timeslot configured for photoplethysmography comprises information for configuring the one or more light sources, and for configuring the one or more photodetectors, and for configuring the one or more PPG signal paths.

13. The apparatus of any preceding claim, wherein a first subset of the configurable timeslots is configured for photoplethysmography, and a further subset of the configurable timeslots is configured for one or more other purposes.

14. The apparatus of any preceding claim, wherein the frontend circuitry further comprises electrocardiography sampling circuitry providing an electrocardiography signal path for receiving analog signals from a set of one or more electrocardiography electrodes, and is configured to use the configuration information and the activation information to implement, within each of the succession of sample frames and for each timeslot configured for electrocardiography and indicated as selected by the activation information, a timeslot-specific configuration of the electrocardiography signal path of the electrocardiography sampling circuitry, so as to generate a digital electrocardiography signal for output to the host system.

15. The apparatus of claim 14, wherein the timeslot-specific configuration information for each timeslot configured for electrocardiography comprises information for configuring the electrocardiography signal path.

16. The apparatus of any preceding claim, wherein the frontend circuitry is configured to pack the active timeslots in time within each sample frame.

17. The apparatus of any preceding claim, wherein the frontend circuitry is configured to include an idle period after a last active timeslot in each sample frame, and to enter a power-saving state in each idle period.

18. The apparatus of any preceding claim, wherein the frontend circuitry is configured to replace the configuration information or activation information stored in the configuration memory or the activation memory when new configuration information or activation information is received from the host system, and, in response to receiving new configuration or activation information, to implement the new configuration or activation information on a next sample frame.

19. A method of operating an apparatus according to any preceding claim, the method comprising: receiving, from the host system, configuration information for each timeslot in the set of one or more timeslots; storing the configuration information in the configuration memory; receiving, from the host system, activation information indicating a selection of the timeslots to be active; storing the activation information in the activation memory; using the configuration information and activation information to implement, within each of the succession of sample frames and for each timeslot configured for photoplethysmography and indicated as selected by the activation information, a timeslot-specific configuration of the one or more photoplethysmography signal paths of the photoplethysmography sampling circuitry, so as to generate one or more digital photoplethysmography signals; and outputting the one or more digital photoplethysmography signals to the host system.

20. The method of claim 19, wherein the frontend circuitry further comprises electrocardiography sampling circuitry providing an electrocardiography signal path for receiving analog signals from a set of one or more electrocardiography electrodes, the method further comprising:using the configuration information and activation information to implement, within each of the succession of sample frames and for each timeslots configured for electrocardiography and indicated as selected by the activation information, a timeslotspecific configuration of the electrocardiography signal path of the electrocardiography sampling circuitry, so as to generate a digital electrocardiography signal; and outputting the digital electrocardiography signal to the host system.

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