High-frequency module and communication device

Abstract

Provided is a high-frequency module with which it is possible to reduce the deterioration of the characteristics of an inductor provided inside a mounting substrate. A high-frequency module (1) comprises a mounting substrate (2), an electronic component (3), a resin layer (5), external connection terminals (6), an inductor (L1), and a partial shield electrode (7). The mounting substrate (2) includes a first main surface (2a) and a second main surface (2b) that oppose each other. The electronic component (3) is disposed on the first main surface (2a) of the mounting substrate (2). The resin layer (5) is provided on the first main surface (2a) of the mounting substrate (2) so as to cover at least a part of the electronic component (3). The plurality of external connection terminals (6) are provided to a main surface (5a) of the resin layer (5) on the side thereof that is opposite the mounting substrate (2) side. The inductor (L1) is provided inside the mounting substrate (2). The partial shield electrode (7) is provided inside or on the second main surface (2b) of the mounting substrate (2). In plan view from the thickness direction (D1) of the mounting substrate (2), the partial shield electrode (7) does not overlap the inductor (L1).

Description

High-frequency Module and Communication Device

[0001] The present invention generally relates to a high-frequency module and a communication device, and more particularly to a high-frequency module provided with an inductor inside a mounting substrate and a communication device provided with the above high-frequency module.

[0002] The high-frequency module described in Patent Document 1 includes a mounting substrate, an inductor, an electronic component, a resin layer, and a shield electrode. The inductor is provided inside the mounting substrate. The electronic component is disposed on one main surface of the mounting substrate. The resin layer is provided on one main surface of the mounting substrate so as to cover the electronic component. The shield electrode covers the top surface and side surfaces of the resin layer.

[0003] International Publication No. 2021 / 215108

[0004] In the high-frequency module described in Patent Document 1, there is a problem that the characteristics of the inductor deteriorate because the magnetic field generated by the inductor provided inside the mounting substrate is affected by the shield electrode.

[0005] In view of the above problems, an object of the present invention is to provide a high-frequency module and a communication device capable of reducing deterioration of the characteristics of an inductor provided inside a mounting substrate.

[0006] The high-frequency module according to one aspect of the present invention includes a mounting substrate, an electronic component, a resin layer, an external connection terminal, an inductor, and a partial shield electrode. The mounting substrate has a first main surface and a second main surface facing each other. The electronic component is disposed on the first main surface of the mounting substrate. The resin layer is provided on the first main surface of the mounting substrate so as to cover at least a part of the electronic component. The plurality of external connection terminals are provided on the main surface of the resin layer on the side opposite to the side of the mounting substrate. The inductor is provided inside the mounting substrate. The partial shield electrode is provided inside the mounting substrate or on the second main surface. In a plan view from the thickness direction of the mounting substrate, the partial shield electrode does not overlap the inductor.

[0007] A communication device according to one aspect of the present invention comprises the high-frequency module and a signal processing circuit. The signal processing circuit is connected to the high-frequency module and processes high-frequency signals.

[0008] The high-frequency module and communication device according to the present invention have the advantage of being able to suppress the degradation of the characteristics of an inductor provided inside the mounting board.

[0009] Figure 1 is a plan view of a high-frequency module according to Embodiment 1. Figure 2 is a cross-sectional view taken along A1-A1 in Figure 1. Figure 3 is a configuration diagram of a filter including a first inductor. Figure 4 is a configuration diagram of a filter including a second inductor. Figure 5 is a configuration diagram of a modified filter including a second inductor. Figure 6 is a plan view of a high-frequency module according to Embodiment 2. Figure 7 is a plan view of a high-frequency module according to Modification 1 of Embodiment 2. Figure 8 is a plan view of a high-frequency module according to Modification 2 of Embodiment 2. Figure 9 is a plan view of a high-frequency module according to Embodiment 3, viewed from the back side (electronic component side). Figure 10 is a plan view of a high-frequency module according to Embodiment 4. Figure 11 is a cross-sectional view taken along A2-A2 in Figure 10. Figure 12 is a plan view of a high-frequency module according to Embodiment 5. Figure 13 is a cross-sectional view taken along A3-A3 in Figure 12. Figure 14 is a plan view of a high-frequency module according to Modification 3 of Embodiment 5. Figure 15 is a cross-sectional view of a high-frequency module according to Modification 4 of Embodiment 5. Figure 16 is a cross-sectional view of a high-frequency module according to Modification 5 of Embodiment 5. Figure 17 is a cross-sectional view taken along line A4-A4 of Figure 16. Figure 18 is a plan view of the high-frequency module according to Embodiment 6. Figure 19 is a cross-sectional view taken along line A5-A5 of Figure 18. Figure 20 is a configuration diagram of the high-frequency module and communication device according to Embodiment 7.

[0010] (1) Embodiment 1 The high-frequency module 1 according to Embodiment 1 will be described in detail with reference to the drawings.

[0011] (1-1) As shown in the schematic diagrams 1 and 2, the high-frequency module 1 according to Embodiment 1 comprises a mounting substrate 2, an electronic component 3, a resin layer 5, a plurality of external connection terminals 6, a first inductor L1 (inductor), and a partial shield electrode 7. The mounting substrate 2 has a first main surface 2a and a second main surface 2b that face each other. The electronic component 3 is arranged on the first main surface 2a of the mounting substrate 2. The resin layer 5 is provided on the first main surface 2a of the mounting substrate 2 so as to cover at least a part of the electronic component 3. The plurality of external connection terminals 6 are provided on the main surface 5a of the resin layer 5 opposite to the side of the mounting substrate 2. The first inductor L1 is provided inside the mounting substrate 2. The partial shield electrode 7 is provided inside the mounting substrate 2 or on the second main surface 2b. In a plan view from the thickness direction D1 of the mounting substrate 2, the partial shield electrode 7 does not overlap with the first inductor L1.

[0012] With this configuration, in a plan view from the thickness direction D1 of the mounting substrate 2, the partial shield electrode 7 does not overlap with the first inductor L1. Therefore, the degradation of the characteristics of the first inductor L1 due to the magnetic field H1 of the first inductor L1 being affected by the partial shield electrode 7 can be reduced.

[0013] (1-2) Detailed explanation (1-2-1) The high-frequency module 1 according to the configuration embodiment 1 can be applied to a high-frequency module provided in a communication device such as a mobile terminal.

[0014] As shown in Figures 1 and 2, the high-frequency module 1 according to Embodiment 1 comprises a mounting substrate 2, one or more (one in the example of Figure 1) electronic components 3, a plurality of (18 in the example of Figure 1) terminal electrodes 4, a resin layer 5, a plurality of (18 in the example of Figure 1) external connection terminals 6, a plurality of circuit elements (first inductor L1 and second inductor L2 in the example of Figure 1), and a partial shield electrode 7.

[0015] The mounting substrate 2 is a substrate on which one or more electronic components 3 are arranged (mounted). The mounting substrate 2 is, for example, a flat plate. The mounting substrate 2 is, for example, a resin multilayer substrate. However, the mounting substrate 2 is not limited to a resin multilayer substrate, and may be, for example, a printed circuit board, an LTCC (Low Temperature Co-fired Ceramics) substrate, or an HTCC (High Temperature Co-fired Ceramics) substrate.

[0016] The mounting substrate 2 is, for example, a multilayer substrate including a plurality of dielectric layers (insulating layers) and a plurality of conductive layers 11. Each of the plurality of conductive layers 11 is provided between the plurality of dielectric layers. That is, the plurality of dielectric layers and the plurality of conductive layers 11 are stacked alternately in the thickness direction D1 of the mounting substrate 2. The plurality of conductive layers 11 are formed in a predetermined pattern defined for each layer. The mounting substrate 2 has a plurality of via electrodes 12. The plurality of via electrodes 12 are provided inside the mounting substrate 2 and connect two conductive layers 11 which are different layers, or connect a conductive layer 11 to a pad 13 described later. The material of the conductive layers 11 and the via electrodes 12 is, for example, copper.

[0017] The mounting substrate 2 has a first main surface 2a and a second main surface 2b. The first main surface 2a and the second main surface 2b are main surfaces that face each other in the thickness direction D1 of the mounting substrate 2. The first main surface 2a is provided with a plurality of pads 13 to which electronic components 3, a first inductor L1 or a second inductor L2 are connected.

[0018] The first main surface 2a of the mounting substrate 2 is provided with a plurality of pads 13, an electronic component 3, a plurality of terminal electrodes 4, and a resin layer 5.

[0019] The multiple pads 13 are areas to which electronic components and the like are electrically connected. The multiple pads 13 are, for example, flat plates. The multiple pads 13 are arranged on the first main surface 2a of the mounting substrate 2. The multiple pads 13 are connected to one of the multiple conductive layers 11 via via electrodes 12.

[0020] The electronic component 3 is, for example, an IC (Integrated Circuit) chip. The electronic component 3 has a component body 3a and a plurality of external electrodes 3b. The component body 3a is the part of the electronic component 3 other than the plurality of external electrodes 3b. The component body 3a is, for example, a flat plate with a rectangular shape in plan view. The plurality of external electrodes 3b are the parts that connect to the corresponding pads 13 of the plurality of pads 13 on the mounting substrate 2. Each of the plurality of external electrodes 3b is, for example, a flat plate. The plurality of external electrodes 3b are arranged on the back surface of the component body 3a (i.e., the main surface facing the mounting substrate 2). The electronic component 3 is arranged on the first main surface 2a of the mounting substrate 2 with the plurality of external electrodes 3b connected to the corresponding pads 13 of the plurality of pads 13 on the mounting substrate 2 via bumps 14. The bumps 14 are members that electrically connect the external electrodes 3b and the pads 13, and are, for example, solder.

[0021] Multiple terminal electrodes 4 are provided on the first main surface 2a of the mounting substrate 2. The multiple terminal electrodes 4 electrically connect via electrodes 12 inside the mounting substrate 2 to external connection terminals 6. The multiple terminal electrodes 4 are, for example, columnar (for example, cylindrical). The multiple terminal electrodes 4 are arranged on the outer circumference of the electronic component 3 on the first main surface 2a of the mounting substrate 2. In other words, the multiple terminal electrodes 4 are arranged between the edge 2c of the mounting substrate 2 and the electronic component 3 adjacent to the edge 2c, in a plan view from the thickness direction D1 of the mounting substrate 2. Here, "A (for example, the edge of the mounting substrate) and B (for example, an electronic component) are adjacent" means that no other electronic components are arranged between A and B.

[0022] The resin layer 5 is a component for solidifying the electronic component 3 and the plurality of terminal electrodes 4 with resin. The resin layer 5 is provided on the first main surface 2a of the mounting substrate 2 so as to cover at least a portion of each of the electronic component 3 and the plurality of terminal electrodes 4. More specifically, the resin layer 5 exposes the main surface 3c of the electronic component 3 (the main surface opposite to the mounting substrate 2 side) and covers the outer peripheral surface 3d and the main surface 3e (the main surface on the mounting substrate 2 side) of the electronic component 3. In addition, the resin layer 5 exposes one end surface 4a of the plurality of terminal electrodes 4 opposite to the mounting substrate 2 side and covers the outer peripheral surface 4b. The thickness d1 of the mounting substrate 2 is greater than the thickness d2 of the resin layer 5. This allows for a wider space to arrange circuit elements (e.g., inductors, capacitors) inside the mounting substrate 2. The main surface 5a of the resin layer 5 opposite to the mounting substrate 2 side is flush with the main surface 3c of the electronic component 3. Furthermore, the main surface 5a of the resin layer 5 is flush with one end surface 4a of the terminal electrode 4.

[0023] The multiple external connection terminals 6 are parts that are electrically connected to an external substrate (e.g., a motherboard). Each of the multiple external connection terminals 6 is, for example, flat. The multiple external connection terminals 6 are arranged on the main surface 5a of the resin layer 5. The main surface 5a is the main surface of the resin layer 5 opposite to the mounting substrate 2 side. The multiple external connection terminals 6 correspond one-to-one with the multiple terminal electrodes 4 and are connected to one end face 4a of the corresponding terminal electrode 4. The multiple external connection terminals 6 include a ground external connection terminal 6a that is connected to ground.

[0024] Since multiple external connection terminals 6 are arranged on the main surface 5a of the resin layer 5, when the high-frequency module 1 is placed on an external substrate, the resin layer 5 is positioned between the mounting substrate 2 and the external substrate, and is not positioned on the outside of the mounting substrate 2 (i.e., on the side opposite to the external substrate). Therefore, even if a shield electrode is provided on the resin layer 5, the influence of the magnetic field H1 of the first inductor L1 on the shield electrode can be reduced. This reduces the degradation of the characteristics of the first inductor L1 due to the influence between the magnetic field H1 and the shield electrode.

[0025] The above-mentioned plurality of circuit elements include, for example, an inductor including a first inductor L1 and a second inductor L2, and a capacitor. In the examples of Figures 1 and 2, only the first inductor L1 and the second inductor L2 are shown as the plurality of circuit elements. The plurality of circuit elements are used, for example, as circuit elements included in a filter or matching circuit.

[0026] The first inductor L1 is, for example, an inductor included in a filter (e.g., a low-pass filter). The first inductor L1 is composed of a conductive layer 11a and via electrodes 12a provided inside the mounting substrate 2. More specifically, the first inductor L1 is composed of a single coil (inductor) formed by multiple coil pattern sections (three in the example of Figure 2) made of multiple conductive layers 11a, which are connected by via electrodes 12a. One end of the first inductor L1 is connected to a predetermined pad 13 on the mounting substrate 2. In the example of Figure 2, one end of the first inductor L1 is connected to a predetermined external electrode 3b of the electronic component 3 via a predetermined pad 13 and bump 14 on the mounting substrate 2. That is, the electronic component 3 is electrically connected to the first inductor L1 via the bump 14. The magnetic field H1 of the first inductor L1 extends in the thickness direction D1 of the mounting substrate 2. In Embodiment 1, the first inductor L1 is connected in series to a signal path provided on the mounting substrate 2. The signal path is the path through which a transmitted signal or a received signal passes. The above signal path connects the antenna terminal of the high-frequency module 1 to either the input terminal or the output terminal.

[0027] The second inductor L2 is, for example, an inductor included in a filter (e.g., a high-pass filter). The second inductor L2 is composed of a conductive layer 11b and via electrodes 12b provided inside the mounting substrate 2. More specifically, the second inductor L2 is composed of a single coil (inductor) formed by multiple coil pattern sections made of multiple (three in the example of Figure 2) conductive layers 11b, which are connected by via electrodes 12b. One end of the second inductor L2 is connected to a predetermined pad 13 on the mounting substrate 2. In the example of Figure 2, one end of the second inductor L2 is connected to a predetermined external electrode 3b of the electronic component 3 via a predetermined pad 13 and bump 14 on the mounting substrate 2. That is, the electronic component 3 is electrically connected to the second inductor L2 via the bump 14. The magnetic field H2 of the second inductor L2 extends in the thickness direction D1 of the mounting substrate 2. In Embodiment 1, the second inductor L2 is connected between a signal path provided on the mounting substrate 2 and ground. The signal path is the path through which a transmitted signal or a received signal passes. The above signal path connects the antenna terminal of the high-frequency module 1 to either the input terminal or the output terminal.

[0028] The partial shielding electrode 7 reduces the incidence of external electromagnetic waves (unwanted signals) on the inductors (first inductor L1 and second inductor L2) and the electronic components 3 located on the first main surface 2a of the mounting substrate 2, as well as the leakage of electromagnetic waves generated from these inductors and electronic components 3 to the outside. The partial shielding electrode 7 is provided on at least one of the inside of the mounting substrate 2 and the second main surface 2b. The partial shielding electrode 7 is patterned by the conductive layer 11 of the mounting substrate 2. In the example of Figure 2, the partial shielding electrode 7 includes a partial shielding electrode 7a provided on the second main surface 2b of the mounting substrate 2 and a partial shielding electrode 7b provided inside the mounting substrate 2. The partial shielding electrode 7 is connected to the ground external connection terminal 6a via predetermined via electrodes 12 and predetermined terminal electrodes 4 of the mounting substrate 2. That is, the partial shielding electrode 7 is connected to ground.

[0029] The partial shield electrode 7 is positioned so as not to overlap with the first inductor L1 (i.e., the inductor connected in series with the signal path) when viewed from the thickness direction D1 of the mounting substrate 2. This reduces the influence of the partial shield electrode 7 on the magnetic field H1 of the first inductor L1, and as a result, it reduces the degradation of the characteristics of the first inductor L1 (i.e., the decrease in the Q value) due to the influence between the magnetic field H1 and the partial shield electrode 7. The first inductor L1 connected in series with the signal path requires a high Q value. Therefore, by ensuring that the first inductor L1 does not overlap with the partial shield electrode 7 in the above-mentioned plan view, the decrease in the Q value is reduced.

[0030] Furthermore, the partial shield electrode 7b is positioned so as to overlap with the second inductor L2 (i.e., the inductor connected between the signal path and ground) in the plan view described above. This allows the magnetic field H2 of the second inductor L2 to be shielded by the partial shield electrode 7b, thereby reducing leakage of the magnetic field H2 to the outer periphery of the high-frequency module 1. The second inductor L2, connected between the signal path and ground, does not require a high Q value. Therefore, by overlapping the partial shield electrode 7 in the plan view described above, the leakage of the magnetic field H2 to the outside of the mounting substrate 2 is reduced rather than reducing the decrease in the Q value of the second inductor L2.

[0031] Of the multiple external connection terminals 6, the ground external connection terminal 6a that overlaps with the partial shield electrode 7 in the plan view is connected to the partial shield electrode 7 via the via electrode 12 of the mounting substrate 2 (see Figure 1). In the example of Figure 1, of the multiple external connection terminals 6, external connection terminals 61 to 64 are ground external connection terminals 6a that overlap with the partial shield electrode 7a in the plan view. Therefore, the ground external connection terminals 61 to 64 are connected to the partial shield electrode 7a via the via electrode 12 of the mounting substrate 2. The multiple via electrodes 12 connecting the ground external connection terminals 61 to 64 and the partial shield electrode 7 are arranged between the edge 2c of the mounting substrate 2 and the electronic component 3 adjacent to the edge 2c. As a result, the multiple via electrodes 12 connecting the external connection terminals 61 to 64 and the partial shield electrode 7 can reduce the amount of electromagnetic waves from the outside passing through the side of the mounting substrate 2 and entering the interior of the mounting substrate 2. As a result, the degradation of the characteristics of the first inductor L1 due to the electromagnetic waves can be reduced.

[0032] (1-2-2) Example of a filter including a first inductor As shown in Figure 3, the first inductor L1 is included in, for example, a low-pass filter 15. The low-pass filter 15 comprises the first inductor L1, a capacitor C11, an input section P11, and an output section P12. The input section P11 and the output section P12 are connected by a signal path M11. The first inductor L1 is connected in series with the signal path M11. The capacitor C11 is connected between the branch point N11 of the signal path M11 and ground. The branch point N11 is located in the signal path M11 between the output section P12 and the first inductor L1. In this way, the first inductor L1 is connected in series with the signal path M11. The capacitor C11 is included in, for example, the plurality of circuit elements described above.

[0033] (1-2-3) Example of a filter including a second inductor As shown in Figure 4, the second inductor L2 is included in, for example, a high-pass filter 16. The high-pass filter 16 comprises the second inductor L2, a capacitor C21, an input section P21, and an output section P22. The input section P21 and the output section P22 are connected by a signal path M21. The capacitor C21 is connected in series with the signal path M21. The second inductor L2 is connected between the branch point N21 of the signal path M21 and ground. The branch point N21 is located in the signal path M21 between the output section P22 and the capacitor C21. Thus, the second inductor L2 is connected between the signal path M21 and ground. The capacitor C21 is included in, for example, the above-mentioned plurality of circuit elements.

[0034] (1-3) The high-frequency module 1 according to the first embodiment of the effect comprises a mounting substrate 2, an electronic component 3, a resin layer 5, an external connection terminal 6, an inductor L1, and a partial shield electrode 7. The mounting substrate 2 has a first main surface 2a and a second main surface 2b that face each other. The electronic component 3 is arranged on the first main surface 2a of the mounting substrate 2. The resin layer 5 is provided on the first main surface 2a of the mounting substrate 2 so as to cover at least a part of the electronic component 3. The plurality of external connection terminals 6 are provided on the main surface 5a of the resin layer 5 that is opposite to the side of the mounting substrate 2. The inductor L1 is provided inside the mounting substrate 2. The partial shield electrode 7 is provided inside the mounting substrate 2 or on the second main surface 2b. In a plan view from the thickness direction D1 of the mounting substrate 2, the partial shield electrode 7 does not overlap with the inductor L1.

[0035] In this configuration, the partial shield electrode 7 does not overlap with the inductor L1 in a plan view. Therefore, the degradation of the inductor L1's characteristics due to the magnetic field H1 of the inductor L1, which is located inside the mounting substrate 2, being affected by the partial shield electrode 7 located inside the mounting substrate 2 or on the second main surface 2b can be reduced.

[0036] Furthermore, the high-frequency module 1 according to Embodiment 1 further comprises a via electrode 12. The via electrode 12 is provided inside the mounting substrate 2. The via electrode 12 electrically connects the partial shield electrode 7 to the ground external connection terminal 6a among the plurality of external connection terminals 6. In a plan view from the thickness direction D1 of the mounting substrate 2, the via electrode 12 is positioned between the edge 2c of the mounting substrate 2 and the electronic component 3 adjacent to the edge 2c. With this configuration, the via electrode 12 can shield unwanted signals (electromagnetic waves) that enter the inside of the mounting substrate 2 from the outside. As a result, the degradation of the characteristics of the inductor L1 due to the unwanted signals can be reduced.

[0037] Furthermore, in the high-frequency module 1 according to Embodiment 1, the inductor L1 is connected in series with the signal path M11 through which the transmitted signal or received signal passes. With this configuration, the inductor L1 connected in series with the signal line is required to have a high Q value. This configuration can reduce the degradation of the characteristics of the inductor L1, which is required to have a high Q value.

[0038] Furthermore, the high-frequency module 1 according to Embodiment 1 further comprises a second inductor L2. The second inductor L2 is a different inductor from the first inductor L1. The second inductor L2 is connected between the signal path M21 through which the transmitted or received signal passes and ground. In a plan view from the thickness direction D1 of the mounting substrate 2, the second inductor L2 overlaps with the partial shielding electrode 7. With this configuration, the partial shielding electrode 7 can reduce the incidence of unwanted signals (electromagnetic waves) from the outside onto the second inductor L2. As a result, it is possible to reduce the coupling of unwanted signals from the outside with the second inductor L2 and the degradation of the characteristics of the second inductor L2.

[0039] Furthermore, in the high-frequency module 1 according to Embodiment 1, the electronic component 3 is electrically connected to at least one (both in the example in Figure 2) of the first inductor L1 and the second inductor L2 via a bump 14. With this configuration, the characteristics of the high-frequency module 1 including the electronic component 3 can be improved by electrically connecting at least one of the first inductor L1 and the second inductor L2 to the electronic component 3.

[0040] In the high-frequency module 1 according to Embodiment 1, the main surface 3c of the electronic component 3 on the side opposite to the mounting substrate 2 is flush with the main surface 5a of the resin layer 5 on the side opposite to the mounting substrate 2. According to this configuration, the height of the high-frequency module 1 can be reduced.

[0041] (1-4) Modified Example Hereinafter, a modified example of Embodiment 1 will be described. The following modified examples can be implemented in combination.

[0042] (1-4-1) Modified Example 1 In Embodiment 1, the case where the first inductor L1 is included in the filter is exemplified. However, the first inductor L1 is not limited to the case where it is included in the filter. The first inductor L1 may be included in any electronic component as long as it is connected in series to the signal path. For example, the first inductor L1 may be included in the matching circuit.

[0043] Also, in Embodiment 1, the case where the second inductor L2 is included in the filter is exemplified. However, the second inductor L2 is not limited to the case where it is included in the filter. The second inductor L2 may be included in any electronic component as long as it is connected between the signal path and the ground. For example, the second inductor L2 may be included in the matching circuit.

[0044] (1-4-2) Modified Example 2 As shown in FIG. 5, the second inductor L2 of Modified Example 2 is included in the band-pass filter 17. The band-pass filter 17 includes the second inductor L2, a capacitor C31, an input portion P31, and an output portion P32. The input portion P31 and the output portion P32 are connected by a signal path M31. The capacitor C31 is connected between the branch point N31 of the signal path M31 and the ground. The second inductor L2 is connected between the branch point N32 of the signal path M31 and the ground. The branch point N32 is disposed between the output portion P32 and the branch point N31 in the signal path M31. Thus, the second inductor L2 is connected between the signal path M31 and the ground. The capacitor C31 is included in, for example, the plurality of circuit elements.

[0045] (1-4-3) Variant Example 3 In Embodiment 1, an example is illustrated in which the electronic component 3 is electrically connected to both the first inductor L1 and the second inductor L2 via the bump 14. However, the electronic component 3 may be electrically connected to at least one of the first inductor L1 and the second inductor L2 via the bump 14.

[0046] (2) Embodiment 2 Referring to FIG. 6, the high-frequency module 1 according to Embodiment 2 will be described. The dot patching applied to the figures indicated by the reference numerals 7a, 31b, and 31a in FIG. 6 is for facilitating the identification of the plan view and does not mean a cross section.

[0047] (2-1) Configuration The high-frequency module 1 according to Embodiment 2 is configured in the same manner as the high-frequency module 1 according to Embodiment 1, except that the partial shield electrode 7a provided on the second main surface 2b of the mounting substrate 2 is also used as the direction identification mark 30 of the high-frequency module 1. Hereinafter, in Embodiment 2, the same components as those in Embodiment 1 will be denoted by the same reference numerals as in Embodiment 1, and detailed description thereof will be omitted. In some cases, the description will focus on the components different from those in Embodiment 1.

[0048] As shown in FIG. 6, in Embodiment 2, the partial shield electrode 7a provided on the second main surface 2b of the mounting substrate 2 is disposed near a predetermined corner 21 among the four corners 21 to 24 of the second main surface 2b. Thus, the partial shield electrode 7a is also used as the direction identification mark 30 by being disposed near the predetermined corner 21 of the second main surface 2b. The direction identification mark 30 is a mark that defines the direction of the high-frequency module 1 with respect to the external substrate when the high-frequency module 1 is disposed on the external substrate.

[0049] On the second main surface 2b of the mounting board 2, in addition to the direction identification mark 30 (partial shield electrode 7a), product information 31 is indicated. The product information 31 is information about the high-frequency module 1, which is the product. The product information 31 includes, for example, part number 31a, model number 31b, and manufacturing date information. In the example in Figure 6, part number 31a and model number 31b are indicated as product information 31. Part number 31a is indicated, for example, as a sequence of numbers (for example, "1234"). Model number 31b is indicated, for example, as an English letter (for example, "K").

[0050] (2-2) In the high-frequency module 1 according to the second embodiment, the partial shield electrode 7 is also used as a direction identification mark 30 for the high-frequency module 1. With this configuration, a formation area for forming the direction identification mark 30 is not required, and the limitation of the information display area for displaying product information 31 (part number 31a, etc.) by the formation area can be reduced.

[0051] (2-3) Modifications Below, modifications of Embodiment 2 will be described. The following modifications can be implemented in combination.

[0052] (2-3-1) Modification 1 As shown in Figure 7, in Modification 1, the product information 31 is written so as to overlap with the partial shield electrode 7a, which is also used as the direction identification mark 30. That is, the partial shield electrode 7a is also used as an information display area for displaying the product information 31. In the example in Figure 7, the part number 31a is written as the product information 31 on the partial shield electrode 7a (direction identification mark 30).

[0053] In the first modified example, the product information 31 may be formed by laser printing directly onto the partial shield electrode 7a, or it may be laser printed onto the second main surface 2b of the mounting substrate 2 directly beneath the partial shield electrode 7a, and the partial shield electrode 7a may be formed on top of it. "Laser printing" refers to a method of printing the product information 31 by irradiating the surface (second main surface 2b) of the mounting substrate 2 with laser light to burn, scrape, or discolor it.

[0054] According to Modification 1, the partial shield electrode 7a is also used as an information display space for displaying product information 31, making it easier to secure space for displaying information.

[0055] (2-3-2) Modification 2 As shown in Figure 8, in Modification 2, a partial shield electrode 7a is provided over the entire second main surface 2b of the mounting substrate 2, and an opening 32 provided in the partial shield electrode 7a is also used as a direction identification mark 30. The opening 32 is provided in the region of the partial shield electrode 7a that overlaps with the first inductor L1 when viewed from the thickness direction of the mounting substrate 2. That is, the opening 32 is formed so that the partial shield electrode 7a does not overlap with the first inductor L1 when viewed from the thickness direction. The opening 32 (i.e., the direction identification mark 30) is located near a predetermined corner 21 of the four corners 21 to 24 of the second main surface 2b. In Modification 2, product information is not shown, but is indicated on the partial shield electrode 7a or on the second main surface 2b exposed from the opening 32.

[0056] According to Modification 2, the opening 32 provided in the partial shield electrode 7a is also used as the direction identification mark 30, thus eliminating the need for a formation area to create the direction identification mark 30. As a result, the limitation on the placement of the notation area for displaying product information due to the formation area can be reduced.

[0057] (3) Embodiment 3 A high-frequency module 1 according to Embodiment 3 will be described with reference to Figure 9.

[0058] (3-1) Configuration Embodiment 3 is configured similarly to Embodiment 1, except that product information 31 is written on the main surface 3c (i.e., the main surface opposite to the mounting board 2 side) of the electronic component 3 placed on the first main surface 2a of the mounting board 2.

[0059] More specifically, in Embodiment 3, similar to Embodiment 1, the main surface 3c of the electronic component 3 placed on the first main surface 2a of the mounting substrate 2 is exposed from the resin layer 5 provided on the first main surface 2a of the mounting substrate 2. Product information 31 is written on this exposed main surface 3c. The product information 31 is written, for example, by laser printing.

[0060] (3-2) Effects: According to Embodiment 3, since product information 31 is written on the main surface 3c of the electronic component 3, the amount of product information 31 written on the second main surface 2b of the mounting substrate 2 can be reduced. Therefore, by reducing the amount of product information 31 written on the second main surface 2b of the mounting substrate 2, the second main surface 2b can be made flatter. As a result, when the second main surface 2b of the mounting substrate 2 of the high-frequency module 1 is attracted and the high-frequency module 1 is picked up, the amount of the high-frequency module 1 falling due to poor attraction can be reduced.

[0061] Furthermore, the information display area for the product information 31 on the second main surface 2b of the mounting board 2 can be reduced by the amount of product information 31 written on the main surface 3c of the electronic component 3. As a result, the influence on the magnetic fields of the first inductor L1 and the second inductor L2 from the printing irregularities formed when printing the product information 31 on the second main surface 2b of the mounting board 2 can be reduced. Consequently, the degradation of the characteristics of the first inductor L1 and the second inductor L2 can be reduced.

[0062] (4) Embodiment 4 The high-frequency module 1 according to Embodiment 4 will be described with reference to Figures 10 and 11.

[0063] (4-1) As shown in the configuration diagrams 10 and 11, Embodiment 4 is configured similarly to Embodiment 1, except that a plurality of via electrodes 12t connected to the partial shield electrode 7b shield the space between the first region 41 and the second region 42 on the mounting substrate 2.

[0064] As shown in Figure 10, in Embodiment 4, the mounting substrate 2 has a first region 41 and a second region 42. In the example in Figure 10, the first region 41 is one half of the second main surface 2b of the mounting substrate 2 in the first direction (for example, the short side direction of the second main surface 2b), and the second region 42 is the other half of the second main surface 2b of the mounting substrate 2 in the same short side direction.

[0065] Furthermore, if one of the first region 41 and the second region 42 is an LB (low band) region, the other is an HB (high band) region. The "LB region" is the region where the electronic component 3 that processes low band signals (transmitted or received signals) is located. The "HB region" is the region where the electronic component 3 that processes high band signals (transmitted or received signals) is located. Also, if one of the first region 41 and the second region 42 is a transmission region, the other is a reception region. The "transmission region" is the region where the electronic component 3 that processes transmitted signals is located. The "reception region" is the region where the electronic component 3 that processes received signals is located.

[0066] In the mounting substrate 2 of Embodiment 4, the partial shield electrode 7b is provided along the gap 45 between the first region 41 and the second region 42 in a plan view from the thickness direction D1 of the mounting substrate 2. That is, the partial shield electrode 7b is formed in the strip-shaped flat plate form in the plan view and is provided along the longitudinal direction of the gap 45 (the left-right direction on the plane of the paper in the example of Figure 10) in the plan view. The partial shield electrode 7b is connected to the external ground connection terminal 6a via the via electrode 12s and the terminal electrode 4s, as in Embodiment 1 (see Figure 11). That is, the partial shield electrode 7b is connected to ground.

[0067] Furthermore, multiple via electrodes 12t are arranged between the partial shield electrode 7b and the second main surface 2b of the mounting substrate 2 (see Figure 11). The multiple via electrodes 12t are electrically connected to the partial shield electrode 7b. The multiple via electrodes 12t constitute multiple connected via electrodes 12r. Each connected via electrode 12r is composed of one or more via electrodes 12 connected in the thickness direction D1 of the mounting substrate 2. The multiple connected via electrodes 12r are arranged in close proximity to each other along the longitudinal direction of the partial shield electrode 7b (the left-right direction in the example of Figure 11). The lower end 12d of each connected via electrode 12r is connected to the partial shield electrode 7b. That is, each connected via electrode 12r is connected to ground via the partial shield electrode 7b. The upper end 12u of each connected via electrode 12r is close to or exposed to the second main surface 2b of the mounting substrate 2. In the example shown in Figure 11, the upper end 12u of each connecting via electrode 12r is close to the second main surface 2b of the mounting substrate 2 and is not exposed from the second main surface 2b.

[0068] In the example shown in Figure 11, the first longitudinal end 7e of the partial shield electrode 7b is close to the first end 2e of the mounting substrate 2, but the second longitudinal end 7f of the partial shield electrode 7b is positioned with a gap 46 between it and the second end 2f of the mounting substrate 2. Since it is not possible to place a connecting via electrode 12r connected to the partial shield electrode 7b in the gap 46, a connecting via electrode 12r not connected to the partial shield electrode 7b (hereinafter referred to as "floating via electrode 12v") is placed there. That is, one or more floating via electrodes 12v are placed along the gap 46 (i.e., along the extension of the partial shield electrode 7b), so that the gap 46 is filled with one or more floating via electrodes 12v. Note that the floating via electrodes 12v are optional.

[0069] In Embodiment 4, as in Embodiment 1, the first inductor L1 does not overlap with the partial shield electrode 7b in the plan view, while the second inductor L2 overlaps with the partial shield electrode 7b. In the example shown in Figure 11, the first inductor L1 is located within the first region 41, and the second inductor L2 is located in the gap 45 between the first region 41 and the second region 42.

[0070] In Embodiment 4, the electromagnetic waves propagating between the first region 41 and the second region 42 can be reduced by the multiple via electrodes 12t. In Embodiment 4, the inside of the mounting substrate 2 is separated by a partial shielding electrode 7b into an upper layer 43 above the partial shielding electrode 7b and a lower layer 44 below the partial shielding electrode 7b (see Figure 11). The upper layer 43 is then separated by the multiple via electrodes 12t into a first upper layer 43a on the first region 41 side and a second upper layer 43b on the second region side (see Figure 10). Electronic components whose electromagnetic wave influence is to be reduced are then distributed and provided in the first upper layer 43a and the second upper layer 43b within the inside of the mounting substrate 2. As a result, the electromagnetic influence from electronic components provided in one of the first upper layer 43a and the second upper layer 43b is reduced by electromagnetic isolation provided by the multiple via electrodes 12t.

[0071] (4-2) The high-frequency module 1 according to the effect embodiment 4 further comprises a plurality of via electrodes 12t. The plurality of via electrodes 12t are provided between a partial shield electrode 7 provided inside the mounting substrate 2 and the second main surface 2b of the mounting substrate 2, and are connected to the partial shield electrode 7. In a plan view from the thickness direction D1 of the mounting substrate 2, the plurality of via electrodes 12t are arranged inside the mounting substrate 2 between a first region 41 and a second region 42 that are adjacent to each other. With this configuration, the electromagnetic isolation between the first region 41 and the second region 42 can be improved by the plurality of via electrodes 12t.

[0072] (4-3) Modifications Below, modifications of Embodiment 4 will be described. In Embodiment 4, the connecting via electrodes 12r are provided in only one row in the width direction of the partial shield electrode 7b (up and down direction in the plane of the paper of Figure 10) (see Figure 10). However, the connecting via electrodes 12r may be provided in two or more rows in the width direction of the partial shield electrode 7b.

[0073] (5) Embodiment 5 The high-frequency module 1 according to Embodiment 5 will be described with reference to Figures 12 and 13.

[0074] (5-1) As shown in the configuration diagrams 12 and 13, Embodiment 5 is configured similarly to Embodiment 4, except that it uses a plurality of (10 in the example of Figures 12 and 13) connected via electrodes 12r and one or more (2 in the example of Figures 12 and 13) floating via electrodes 12v to display product information.

[0075] In Embodiment 5, the multiple connected via electrodes 12r are composed of two types of connected via electrodes (first connected via electrode 51 and second connected via electrode 52) (see Figure 13). The first connected via electrode 51 is a connected via electrode 12r whose upper end 12u is exposed to the second main surface 2b of the mounting substrate 2. The second connected via electrode 52 is a connected via electrode 12r whose upper end 12u is not exposed to the second main surface 2b of the mounting substrate 2. Similarly, one or more floating via electrodes 12v are composed of two types of floating via electrodes (first floating via electrode 53 and second floating via electrode 54). The first floating via electrode 53 is a floating via electrode 12v whose upper end 12u is exposed to the second main surface 2b of the mounting substrate 2. The second floating via electrode 53 is a floating via electrode 12v whose upper end 12u is not exposed to the second main surface of the mounting substrate 2.

[0076] Multiple connected via electrodes 12r are arranged in a line along the partial shield electrode 7b. One or more floating via electrodes 12v are arranged in a line along the extension of the partial shield electrode 7b. Therefore, multiple connected via electrodes 12r and one or more floating via electrodes 12v are arranged in a line.

[0077] Each of the multiple connected via electrodes 12r can be set to either the first connected via electrode 51 or the second connected via electrode 52. Similarly, each of the one or more floating via electrodes 12v can be set to either the first floating via electrode 53 or the second floating via electrode 54. The first connected via electrode 51 and the first floating via electrode 53 are each associated with the numerical value "1". The second connected via electrode 52 and the second floating via electrode 54 are each associated with the numerical value "0". In this way, by associating the first connected via electrode 51 and the first floating via electrode 53 with the numerical value "1", and the second connected via electrode 52 and the second floating via electrode 54 with the numerical value "0", the arrangement of the multiple connected via electrodes 12r and one or more floating via electrodes 12v arranged in a line (hereinafter referred to as the "via electrode arrangement 57") can be considered as an arrangement of the numbers "1" and "0".

[0078] In Embodiment 5, as described above, the via electrode array 57 constitutes a sequence of "1"s and "0"s. This sequence of numbers defines the product information. For example, by applying the rules of binary, it is possible to represent any number using the sequence of "1"s and "0"s. This arbitrary number is then used to define the product information.

[0079] Product information includes, for example, arrangement information showing the placement of the mounting board 2 on a composite board. A composite board is a board in which multiple mounting boards 2 are connected vertically and horizontally. The mounting board 2 used in the high-frequency module 1 is one of the multiple mounting boards 2 cut from the composite board. The above arrangement information makes it possible to know the placement of the mounting board 2 used in the high-frequency module 1 on the composite board.

[0080] The above arrangement information includes first coordinate information X1 and second coordinate information Y1. The first coordinate information X1 indicates the position of the assembled substrate in the first direction (horizontal direction). The second coordinate information Y1 indicates the position of the assembled substrate in the second direction (vertical direction). The first and second directions are orthogonal to each other.

[0081] In Embodiment 5, the first coordinate information X1 of the mounting substrate 2 used in the high-frequency module 1 is defined by the sequence of "1"s and "0"s defined by one half of the via electrode array 57. The second coordinate information Y1 of the mounting substrate 2 used in the high-frequency module 1 is defined by the sequence of "1"s and "0"s defined by the other half of the via electrode array 57. In this way, the via electrode array 57 defines the arrangement information of the mounting substrate 2 used in the high-frequency module 1.

[0082] (5-2) In the high-frequency module 1 according to the effect embodiment 5, the plurality of connected via electrodes 12r provided between the partial shield electrode 7b and the second main surface 2b of the mounting substrate 2 include a first connected via electrode 51 whose upper end 12u is exposed to the second main surface 2b of the mounting substrate 2, and a second connected via electrode 52 whose upper end 12u is not exposed to the second main surface 2b of the mounting substrate 2. In the plurality of connected via electrodes 12r, by combining the arrangement of the first connected via electrode 51 and the second connected via electrode 52, product information (for example, the arrangement information described above) can be defined using the arrangement of the plurality of connected via electrodes 12r (via electrode arrangement 57). This eliminates the need for an information display area to indicate product information.

[0083] (5-3) Modified Examples Below, modified examples of Embodiment 5 will be described.

[0084] (5-3-1) Modification 1 In Embodiment 5, the connected via electrode 12r and the floating via electrode 12v are each provided in only one row in the width direction of the partial shield electrode 7b (up and down direction in the example of Figure 12). However, the connected via electrode 12r and the floating via electrode 12v may each be provided in two or more rows in the width direction of the partial shield electrode 7b. In this case, the first coordinate information X1 and the second coordinate information Y1 are each defined by the arrangement of the numbers "1" and "0" in two rows.

[0085] (5-3-2) Modification 2 In Embodiment 5, the via electrode array 57 is exemplified as being composed of a plurality of connected via electrodes 12r and one or more floating via electrodes 12v. However, the via electrode array 57 may be composed of only a plurality of connected via electrodes 12r.

[0086] (5-3-3) Modification 3 In Embodiment 5, the partial shield electrode 7b is exemplified as being in the shape of a strip along the longitudinal direction (left-right direction on the page in the example of Figure 12) of the gap 45 between the first region 41 and the second region 42. However, as shown in Figure 14, the partial shield electrode 7b is not limited to being within the gap 45, but may be formed beyond the gap 45. In the example of Figure 14, the partial shield electrode 7b is shown to be provided over the entire area of ​​the mounting substrate 2, except for the area overlapping with the first inductor L1, when viewed from the thickness direction of the mounting substrate 2 in plan view. In Modification 3, the partial shield electrode 7b is formed beyond the gap 45, but the multiple connected via electrodes 12r and one or more floating via electrodes 12v are limited to being within the gap 45.

[0087] According to Modification 3, since the partial shielding electrode 7b is provided over the entire area of ​​the mounting substrate 2 in the plan view, the partial shielding electrode 7b improves electromagnetic isolation between the upper layer above the partial shielding electrode 7b and the lower layer below the partial shielding electrode 7b within the mounting substrate 2. As a result, by distributing the electronic components whose influence from external electromagnetic waves is to be reduced between the upper and lower layers of the first region 41 within the mounting substrate 2, the electromagnetic influence from electronic components in the other layer is reduced for the electronic components in one layer of the first region 41 due to the electromagnetic isolation provided by the partial shielding electrode 7b.

[0088] (5-3-4) Modification 4 As shown in Figure 15, Modification 4 is configured similarly to Embodiment 5, except that a circuit element 50 (for example, a capacitor C5) is further provided in the lower layer 44 of the mounting substrate 2.

[0089] The circuit element 50 is constructed using a portion of the partial shield electrode 7b. In the example shown in Figure 15, a capacitor C5, which is an example of the circuit element 50, comprises a first electrode plate 50a and a second electrode plate 50b. The first electrode plate 50a is constructed using the partial shield electrode 7b. The second electrode plate 50b is spaced apart from the first electrode plate 50a and faces the first electrode plate 50a. The second electrode plate 50b is constructed by forming a pattern on the conductive layer 11 within the mounting substrate 2. The first electrode plate 50a is connected to the external electrode 3b of the electronic component 3 via, for example, via electrodes 12, pads 13 and bumps 14 within the mounting substrate 2.

[0090] According to Modification 4, a circuit element 50 (capacitor C5) can be provided inside the mounting substrate 2 using the partial shielding electrode 7b (7). This reduces the space required for the circuit element 50 and also reduces the manufacturing process.

[0091] (5-3-5) Modification 5 As shown in Figures 16 and 17, Modification 5 is configured similarly to Embodiment 5, except that the partial shield electrode 7b is positioned near the first main surface 2a of the mounting substrate 2.

[0092] In modified example 5, the partial shield electrode 7b is formed in a strip shape along the longitudinal direction of the gap 45 between the first region 41 and the second region 42, similar to embodiment 5. The partial shield electrode 7b is positioned near the first main surface 2a of the mounting substrate 2. Note that "the partial shield electrode 7b is positioned near the first main surface 2a of the mounting substrate 2" means that the partial shield electrode 7b is positioned on the side of the first main surface 2a that is more than halfway along the thickness direction D1 of the mounting substrate 2.

[0093] Each of the lower ends 12d of the multiple connected via electrodes 12r is connected to a partial shielding electrode 7b. Therefore, since the partial shielding electrode 7b is positioned near the first main surface 2a of the mounting substrate 2, each of the lower ends 12d of the multiple connected via electrodes 12r is also positioned near the first main surface 2a of the mounting substrate 2. Each of the upper ends 12u of the multiple connected via electrodes 12r is positioned near the second main surface 2b of the mounting substrate 2, similar to the case of Embodiment 5. Thus, in Modification 5, the multiple connected via electrodes 12r electromagnetically shield the space between the first region 41 and the second region 42 over almost the entire thickness direction D1 of the mounting substrate 2, and especially near the first main surface 2a of the mounting substrate 2. This further improves the electromagnetic isolation between the first region 41 and the second region 42. The first region 41 and the second region 42 are, as in the case of Embodiment 5 (i.e., Embodiment 4), the regions on both sides of the partial shield electrode 7b, as demarcated by the partial shield electrode 7b in a plan view from the thickness direction D1 of the mounting substrate 2.

[0094] In modified example 5, a partial shield electrode 7g (7) is provided inside the mounting board 2 so as to overlap with the second inductor L2 in the plan view described above. The partial shield electrode 7g is connected to the external ground connection terminal 6a via a via electrode 12 and terminal electrode 4 (not shown).

[0095] In modified example 5, the first inductor L1 is located in a first region 41 inside the mounting substrate 2. The second inductor L2 is located in a second region 42 inside the mounting substrate 2. Therefore, the first inductor L1 and the second inductor L2 are electromagnetically shielded from each other by a plurality of connecting via electrodes 12r over almost the entire thickness direction D1 of the mounting substrate 2, and especially near the first main surface 2a of the mounting substrate 2.

[0096] (6) Embodiment 6 The high-frequency module 1 according to Embodiment 6 will be described with reference to Figures 18 and 19.

[0097] (6-1) As shown in the configuration diagrams 18 and 19, Embodiment 6 is configured similarly to Embodiment 1, except that it is provided with shield electrodes 80 on the second main surface 2b and side surface 2d of the mounting substrate 2. In the following description, components that are the same as those in Embodiment 1 are given the same reference numerals as in Embodiment 1 and their descriptions are omitted, and the description will focus on the parts that differ from Embodiment 1.

[0098] In Embodiment 6, a shield electrode 80 is provided instead of the partial shield electrode 7a provided on the second main surface 2b of the mounting substrate 2 in Embodiment 1.

[0099] The shield electrode 80 is provided on the second main surface 2b and side surface 2d of the mounting substrate 2 so as not to overlap with the first inductor L1 when viewed from the thickness direction D1 of the mounting substrate 2. More specifically, the shield electrode 80 has a first shield electrode portion 80a and a second shield electrode portion 80b. The first shield electrode portion 80a is the portion of the shield electrode 80 provided on the second main surface 2b of the mounting substrate 2. The second shield electrode portion 80b is the portion of the shield electrode 80 provided on the side surface 2d (i.e., the outer peripheral surface) of the mounting substrate 2. The shield electrode 80 has an opening 80c. The opening 80c is provided in the first shield electrode portion 80a in the portion that overlaps with the first inductor L1 in the above-mentioned plan view.

[0100] The shield electrode 80 is connected to the terminal electrode 4 via at least one of the via electrode 12 and the conductive layer 11 in the mounting substrate 2, and is connected to the external ground connection terminal 6a via the connected terminal electrode 4. In other words, the shield electrode 80 is connected to ground.

[0101] In Embodiment 6, the partial shield electrode 7 consists only of a partial shield electrode 7b provided inside the mounting substrate 2. The partial shield electrode 7b is provided inside the mounting substrate 2 such that, in the plan view described above, it does not overlap with the first inductor L1 but overlaps with the second inductor L2.

[0102] In Embodiment 6, since shield electrodes 80 are provided on the second main surface 2b and side surface 2d of the mounting substrate 2, the overall shielding performance of the high-frequency module 1 can be improved. Furthermore, the first inductor L1 does not overlap with the shield electrodes 80 and the partial shield electrodes 7b. Therefore, the influence of the magnetic field H1 of the first inductor L1 on the shield electrodes 80 and the partial shield electrodes 7b can be reduced. As a result, the degradation of the characteristics of the first inductor L1 due to the influence between the magnetic field H1 and the shield electrodes 80 and the partial shield electrodes 7b (i.e., a decrease in the Q value) can be reduced. Furthermore, in the above plan view, the second inductor L2 overlaps with the shield electrodes 80 and the partial shield electrodes 7b. Therefore, the magnetic field H2 of the second inductor L2 can be shielded by the shield electrodes 80 and the partial shield electrodes 7b. As a result, leakage of the magnetic field H2 to the outer periphery of the high-frequency module 1 can be reduced.

[0103] (6-2) The high-frequency module 1 according to the effect embodiment 6 further comprises a shield electrode 80. The partial shield electrode 7b (7) is provided inside the mounting substrate 2. The shield electrode 80 is provided on the second main surface 2b and the side surface 2d of the mounting substrate 2. The shield electrode 80 is not provided in the area that overlaps with the inductor L1 when viewed from the thickness direction D1 of the mounting substrate 2 in a plan view. With this configuration, the shield performance of the high-frequency module 1 can be improved while reducing the degradation of the characteristics of the inductor L1.

[0104] (7) Embodiment 7 (7-1) A communication device 100 according to Embodiment 7 will be described with reference to the configuration diagram 20. The communication device 100 is a communication device to which any one of the high-frequency modules 1 of Embodiments 1 to 6 is applied.

[0105] As shown in Figure 20, the communication device 100 is, for example, a mobile terminal (e.g., a smartphone), but is not limited to a mobile terminal; it may also be, for example, a wearable device (e.g., a smartwatch). The high-frequency module 1 is, for example, a module compatible with 4G (fourth-generation mobile communication) standards and 5G (fifth-generation mobile communication) standards. The 4G standard is, for example, 3GPP (registered trademark, Third Generation Partnership Project) or the LTE standard (registered trademark, Long Term Evolution). The 5G standard is, for example, 5G NR (New Radio).

[0106] In addition to the high-frequency module 101, the communication device 100 further includes a signal processing circuit 102 and an antenna 103.

[0107] The high-frequency module 101 is configured to amplify the received signal (high-frequency signal) received by the antenna 103 and output it to the signal processing circuit 102. The high-frequency module 101 is also configured to amplify the transmitted signal (high-frequency signal) output from the signal processing circuit 102 and transmit it from the antenna 103. The high-frequency module 101 is controlled, for example, by the signal processing circuit 102.

[0108] The signal processing circuit 102 is connected to the high-frequency module 101 and is configured to process the received signal output from the high-frequency module 101. The signal processing circuit 102 is also configured to process the transmitted signal output to the high-frequency module 101. The signal processing circuit 102 includes an RF (Radio Frequency) signal processing circuit 1021 and a baseband signal processing circuit 122.

[0109] The RF signal processing circuit 121 is, for example, an RFIC (Radio Frequency Integrated Circuit) and performs signal processing on high-frequency signals (transmitted and received signals). The RF signal processing circuit 121 performs signal processing such as down-conversion on the received signal output from the high-frequency module 101 and outputs it to the baseband signal processing circuit 122. The RF signal processing circuit 121 also performs signal processing such as up-conversion on the transmitted signal output from the baseband signal processing circuit 122 and outputs it to the high-frequency module 101.

[0110] The baseband signal processing circuit 122 is, for example, a BBIC (Baseband Integrated Circuit). The baseband signal processing circuit 122 outputs the received signal output from the RF signal processing circuit 121 to the outside. This output signal (received signal) can be used, for example, as an image signal for image display, or as an audio signal for communication. The baseband signal processing circuit 122 also generates a transmission signal from the baseband signal input from the outside (for example, an audio signal and an image signal), and outputs the generated transmission signal to the RF signal processing circuit 121.

[0111] The high-frequency module 101 comprises a plurality of external terminals 110a to 110c and a plurality of electronic components. In the example shown in Figure 20, the plurality of electronic components include a switch 120, matching circuits 131, 132, 151, 152, a transmit filter 141, a receive filter 142, a power amplifier 161, and a low-noise amplifier 162.

[0112] External terminal 110a is an antenna terminal to which the antenna 103 is connected. External terminal 110b is connected to the output section (not shown) of the signal processing circuit 102 and is an input terminal that inputs the transmission signal processed by the signal processing circuit 102 to the high-frequency module 101. External terminal 110c is connected to the input section (not shown) of the signal processing circuit 102 and is an output terminal that outputs the received signal processed by the high-frequency module 101 to the input section of the signal processing circuit 102.

[0113] Switch 120 is, for example, an antenna switch. Switch 120 selects the destination of the external terminal 110a from among a plurality of filters (transmit filter 141 and receive filter 142 in the example of Figure 20). Switch 120 is, for example, a switch IC (Integrated Circuit). Switch 120 is controlled by, for example, a signal processing circuit 102. Switch 120 has a common terminal 120a and a plurality of (two in the example of Figure 20) selection terminals 120b and 120c. The common terminal 120a can be selectively connected to at least one of the plurality of selection terminals 120b and 120c. The common terminal 120a is connected to the external terminal 110a. The selection terminal 120b is connected to the external terminal 110b via the transmit path TL1. The selection terminal 120c is connected to the external terminal 110c via the receive path RL1.

[0114] The transmission path TL1 is equipped with a power amplifier 161, a matching circuit 151, a transmission filter 141, and a matching circuit 131. The reception path RL1 is equipped with a matching circuit 132, a reception filter 142, a matching circuit 152, and a low-noise amplifier 162.

[0115] The power amplifier 161 amplifies the signal (transmit signal) input to the high-frequency module 101 from the signal processing circuit 102 via the external terminal 110b, and outputs the amplified signal to the transmit filter 141 via the matching circuit 151.

[0116] The matching circuit 151 is provided between the transmitting filter 141 and the power amplifier 161 to achieve impedance matching between the transmitting filter 141 and the power amplifier 161.

[0117] The transmit filter 141 has a passband that includes the transmit bandwidth of the first communication band. The transmit filter 141 receives a signal (transmit signal) from the matching circuit 151, restricts the input signal to a signal within the transmit bandwidth of the first communication band and passes it through, and outputs the passed signal to the selection terminal 120b of the switch 120 via the matching circuit 131.

[0118] The matching circuit 131 is provided between the transmitting filter 141 and the select terminal 120b of the switch 120 to achieve impedance matching between the transmitting filter 141 and the select terminal 120b of the switch 120.

[0119] The receiving filter 142 has a passband that includes the receiving band of the second communication band. The receiving filter 142 receives a signal (received signal) from the selection terminal 120c of the switch 120 via the matching circuit 132, restricts the input signal to signals within the receiving band of the second communication band and passes it through, and outputs the passed signal to the low-noise amplifier 162 via the matching circuit 152.

[0120] The matching circuit 132 is provided between the select terminal 120c of the switch 120 and the receiving filter 142 to achieve impedance matching between the select terminal 120c of the switch 120 and the receiving filter 142.

[0121] The low-noise amplifier 162 amplifies the signal (received signal) input from the matching circuit 152 and outputs the amplified signal to the external terminal 110c.

[0122] The matching circuit 152 is provided between the receiving filter 142 and the low-noise amplifier 162 to achieve impedance matching between the receiving filter 142 and the low-noise amplifier 162.

[0123] In Embodiment 7, the first inductor L1 and the second inductor L2 used in any one of Embodiments 1 to 6 are used as the multiple inductors used in the transmitting filter 141, receiving filter 142, and matching circuits 131, 132, 151, and 152.

[0124] (7-2) The communication device 200 according to the effect embodiment 7 comprises a high-frequency module 101 to which any one of the high-frequency modules 1 of embodiments 1 to 6 is applied, and a signal processing circuit 102. The signal processing circuit 102 is connected to the high-frequency module 1 and processes the high-frequency signal. With this configuration, a communication device 100 having the effect of the high-frequency module 1 can be provided.

[0125] 1. High-frequency module 2. Mounting board 2a. First main surface 2b. Second main surface 2c. Edge 2d. Side surface 2e. First end 2f. Second end 3. Electronic component 3a. Component body 3b. External electrode 3c, 3e. Main surface 3d. Outer surface 4, 4s. Terminal electrode 4a. One end surface 4b. Outer surface 5. Resin layer 5a. Main surface 6. External connection terminal 6a. External connection terminal for ground 7, 7a, 7b, 7. Partial shield electrode 7e. First end 7f. Second end 11, 11a, 11b. Conductive layer 12, 12a, 12b, 12s, 12t, 53, 54. Via electrode 12d. Lower end 12r. Connecting via electrode 12u. Upper end 13. Pad 14. Bump 15. Low-pass filter 16. High-pass filter 17. Band-pass filter 21-24 Corners 30 Direction Identification Mark 31 Product Information 31a Part Number 31b Model Number 32 Opening 41 First Area 42 Second Area 43 Upper Layer 43a First Upper Layer 43b Second Upper Layer 44 Lower Layer 45 Gap 46 Spacing 50 Circuit Elements 50a First Electrode Plate 50b Second Electrode Plate 51 First Connecting Via Electrode 52 Second Connecting Via Electrode 57 Via Electrode Arrangement 61-64 External Connection Terminals for Ground 80 Shield Electrode 80a First Shield Electrode Section 80b Second Shield Electrode Section 80c Opening 100 Communication Device 101 High-Frequency Module 102 Signal Processing Circuit 103 Antenna 110a-110c External Terminals 120 Switch 120a Common Terminals 120b, 120c Select terminal 121 RF signal processing circuit 122 Baseband signal processing circuit 131, 132, 151, 152 Matching circuit 141 Transmit filter 142 Receive filter 161 Power amplifier 162 Low noise amplifier 200 Communication device C5, C11, C21, C31 Capacitor D1 Direction H1, H2 Magnetic field L1 First inductor (inductor) L2 Second inductor M11, M21, M31 Signal path N11, N21, N31, N32 Branch point P11, P21, P31 Input section P12, P22, P32 Output section RL1 Receive path TL1 Transmit path X1 First coordinate information Y1 Second coordinate information

Claims

1. A high-frequency module comprising: a mounting substrate having a first main surface and a second main surface facing each other; an electronic component disposed on the first main surface of the mounting substrate; a resin layer provided on the first main surface of the mounting substrate so as to cover at least a portion of the electronic component; a plurality of external connection terminals provided on the main surface of the resin layer opposite to the mounting substrate side; an inductor provided inside the mounting substrate; and a partial shielding electrode provided inside or on the second main surface of the mounting substrate, wherein, in a plan view from the thickness direction of the mounting substrate, the partial shielding electrode does not overlap with the inductor.

2. The high-frequency module according to claim 1, further comprising via electrodes provided inside the mounting substrate, wherein the via electrodes electrically connect the partial shield electrode and a ground external connection terminal among the plurality of external connection terminals, and are positioned between the edge of the mounting substrate and the electronic component adjacent to the edge in a plan view of the mounting substrate from the thickness direction.

3. The high-frequency module according to claim 1, wherein the inductor is connected in series with a signal path through which a transmitted signal or a received signal passes.

4. The high-frequency module according to claim 1, further comprising a second inductor separate from the first inductor, wherein the second inductor is connected between a signal path through which a transmit signal or receive signal passes and ground, and overlaps with the partial shield electrode in a plan view of the mounting substrate from the thickness direction.

5. The high-frequency module according to any one of claims 1 to 4, wherein the partial shielding electrode is also used as a direction identification mark for the high-frequency module.

6. The high-frequency module according to any one of claims 1 to 5, further comprising a plurality of via electrodes provided between the partial shield electrode provided inside the mounting substrate and the second main surface of the mounting substrate and connected to the partial shield electrode, wherein the plurality of via electrodes are arranged between adjacent first and second regions inside the mounting substrate in a plan view from the thickness direction of the mounting substrate.

7. A high-frequency module according to any one of claims 1 to 6, further comprising a shield electrode, wherein the partial shield electrode is provided inside the mounting substrate, the shield electrode is provided on the second main surface and side surface of the mounting substrate, and is not provided in a region that overlaps with the inductor in a plan view of the mounting substrate from the thickness direction.

8. The high-frequency module according to any one of claims 1 to 7, wherein the electronic component is electrically connected to the inductor via a bump.

9. The high-frequency module according to any one of claims 1 to 8, wherein the main surface of the electronic component opposite to the mounting substrate side is flush with the main surface of the resin layer opposite to the mounting substrate side.

10. A communication device comprising: a high-frequency module according to any one of claims 1 to 9; and a signal processing circuit connected to the high-frequency module for processing high-frequency signals.

Images