Substrate with built-in electronic component

Abstract

In the present invention, a component region R is defined as a region where electronic components 20, which are built into a cavity 35 of a substrate 1 with a built-in electronic component, are enveloped by a line segment parallel to the X axis of a core material 30 and a line segment parallel to the Y axis of the core material 30. Where the length from one end of the main surface of the core material 30 to the component region R is X1, the length within the component region R is X2, and the length from the other end of the main surface of the core material 30 to the component region R is X3 in a straight line A-A' parallel to the X axis, in which the overlap with the component region R is longest and the sum of overlaps with the electronic components 20 is largest, and where the length from one end of the main surface of the core material 30 to the component region R is Y1, the length within the component region R is Y2, and the length from the other end of the main surface of the core material 30 to the component region R is Y3 in a straight line B-B' parallel to the Y axis, in which the overlap with the component region R is longest and the sum of overlaps with the electronic components 20 is largest, X2 < Y2 and X1 + X3 > Y1 + Y3 are satisfied or X2 > Y2 and X1 + X3 < Y1 + Y3 are satisfied.

Description

Substrate with Built-in Electronic Components

[0001] The present invention relates to a substrate with built-in electronic components.

[0002] Patent Document 1 discloses a wiring board including a core substrate having a front surface and a back surface, through holes penetrating the front surface and the back surface of the core substrate and having a substantially rectangular shape in plan view, and electronic components built in the through holes via resin, wherein rounded surfaces or chamfers are formed at inner corners of the through holes.

[0003] In FIG. 1 of Patent Document 1, a plurality of chip capacitors (electronic components) are built in through holes of a core substrate via resin. Each chip capacitor has a plurality of electrodes protruding from its upper end and lower end.

[0004] Japanese Patent Application Laid-Open No. 2002-124749

[0005] In the wiring board described in Patent Document 1, if there is a difference in the linear expansion coefficient between the material constituting the core substrate and the electronic components built in the core substrate, for example, thermal strain occurs due to the thermal load during component mounting or the change in the ambient temperature.

[0006] In particular, as shown in FIG. 1 of Patent Document 1, when a plurality of electronic components are arranged side by side in the X direction and the Y direction on the main surface of the core substrate, the ratio of the occupied area of the electronic components to the main surface of the core substrate is different in each direction, so the thermal strain in the X direction and the Y direction is different. As a result, uneven deformation of the wiring board occurs, which may reduce the connection reliability between the electronic components to be mounted on the wiring board and the wiring board, and the connection reliability between the electronic components built in the wiring board and the wiring board.

[0007] The present invention has been made to solve the above problems, and an object thereof is to provide a substrate with built-in electronic components having excellent connection reliability with electronic components.

[0008] The electronic component embedded substrate of the present invention comprises a core layer including at least one core material having a cavity in the thickness direction, and at least one electronic component embedded in the cavity of the core material. On the main surface of the core material, the region enclosing the electronic component embedded in the cavity with a line segment parallel to the X-axis of the core material and a line segment parallel to the Y-axis of the core material is defined as the component region. In the straight line A-A' parallel to the X-axis, where the overlap with the component region is longest and the sum of the overlaps with the electronic components is maximized, let X1 be the length of the line segment from one end of the main surface of the core material to the component region, X2 be the length of the line segment within the component region, and X3 be the length of the line segment from the other end of the main surface of the core material to the component region. In the straight line B-B' parallel to the Y-axis, where the overlap with the component region is longest and the sum of the overlaps with the electronic components is maximized, let Y1 be the length of the line segment from one end of the main surface of the core material to the component region, Y2 be the length of the line segment within the component region, and Y3 be the length of the line segment from the other end of the main surface of the core material to the component region. Then, X2 < Y2 and X1 + X3 > Y1 + Y3, or X2 > Y2 and X1 + X3 < Y1 + Y3.

[0009] According to the present invention, it is possible to provide an electronic component embedded substrate with excellent connection reliability with electronic components.

[0010] Figure 1 is a schematic cross-sectional view showing an example of an electronic component embedded substrate according to the present invention. Figure 2 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component embedded substrate according to the first embodiment of the present invention. Figure 3A is a cross-sectional view along the line A-A' shown in Figure 2. Figure 3B is a cross-sectional view along the line B-B' shown in Figure 2. Figure 4 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component embedded substrate according to the second embodiment of the present invention. Figure 5A is a cross-sectional view along the line A-A' shown in Figure 4. Figure 5B is a cross-sectional view along the line B-B' shown in Figure 4. Figure 6 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component embedded substrate according to the third embodiment of the present invention. Figure 7A is a cross-sectional view along the line A-A' shown in Figure 6. Figure 7B is a cross-sectional view along the line B-B' shown in Figure 6. Figure 8 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component embedded substrate according to the fourth embodiment of the present invention. Figure 9A is a cross-sectional view along the line A-A' shown in Figure 8. Figure 9B is a cross-sectional view along the line B-B' shown in Figure 8. Figure 10 is a schematic cross-sectional view illustrating an example of the process of preparing a core material having a first wiring layer, a second wiring layer, and a through conductor. Figure 11 is a schematic cross-sectional view illustrating an example of the process of forming a cavity in the core material. Figure 12 is a schematic cross-sectional view illustrating an example of the process of mounting electronic components in the cavity. Figure 13 is a schematic cross-sectional view illustrating an example of the process of laminating a first insulating layer and a first metal layer. Figure 14 is a schematic cross-sectional view illustrating an example of the process of laminating a second insulating layer and a second metal layer. Figure 15 is a schematic cross-sectional view illustrating an example of the process of forming a third wiring layer and a fourth wiring layer. Figure 16 is a schematic cross-sectional view illustrating an example of the process of repeating the formation of insulating layers and wiring layers. Figures 17A to 17D are schematic plan views illustrating examples of arrangements when multiple electronic components are embedded in the electronic component embedded substrate of the present invention. Figures 18A to 18D are schematic plan views showing embodiments of the present invention when the electronic component embedded substrate is applied to a power module substrate. Figure 19 is a schematic diagram showing an example of a voltage regulator module using the electronic component embedded substrate of the present invention. Figure 20 is an example of an equivalent circuit diagram of the voltage regulator module shown in Figure 19.

[0011] The electronic component-embedded substrate of the present invention will be described below. However, the present invention is not limited to the following embodiments and may be modified as appropriate without altering the essence of the invention. Furthermore, a combination of several preferred configurations described in the following embodiments also constitutes the present invention.

[0012] In this specification, terms describing relationships between elements (e.g., "perpendicular," "parallel," "orthogonal," etc.) and terms describing the shapes of elements do not necessarily represent only strict meanings, but also include a range of substantially equivalent values, such as differences of a few percent. Furthermore, in this specification, "equivalent" does not necessarily mean exactly equivalent, but rather substantially equivalent, including differences of a few percent.

[0013] The following diagrams are schematic representations, and their dimensions, aspect ratios, and scales may differ from those of the actual product. The same reference numerals are used for identical or equivalent parts in the diagrams. Furthermore, identical elements are denoted by the same reference numerals in each diagram, and redundant explanations are omitted.

[0014] Figure 1 is a schematic cross-sectional view showing an example of an electronic component embedded substrate according to the present invention.

[0015] The electronic component embedded substrate 1 shown in Figure 1 comprises a core layer 10 and an electronic component 20.

[0016] The core layer 10 includes at least one core material 30 in the thickness direction (Z direction in Figure 1). The core material 30 has a cavity 35 that penetrates in the thickness direction (see Figure 11, described later).

[0017] In the example shown in Figure 1, one main surface of the core material 30 (the top surface in Figure 1) is provided with a first wiring layer 41, a third wiring layer 43, a fifth wiring layer 45, and a seventh wiring layer 47 as circuit wiring, and a first insulating layer 51, a third insulating layer 53, and a fifth insulating layer 55 as insulating layers. On the other hand, the other main surface of the core material 30 (the bottom surface in Figure 1) is provided with a second wiring layer 42, a fourth wiring layer 44, a sixth wiring layer 46, and an eighth wiring layer 48 as circuit wiring, and a second insulating layer 52, a fourth insulating layer 54, and a sixth insulating layer 56 as insulating layers.

[0018] The electronic component 20 is embedded in the cavity 35 of the core material 30. The number of electronic components 20 embedded in the cavity 35 may be one or multiple.

[0019] In the example shown in Figure 1, the electronic component 20 is sealed by resin materials that constitute the first insulating layer 51 and the second insulating layer 52.

[0020] The circuit wiring and electronic components 20 on the substrate are electrically connected to the first surface P1 side via via conductors provided in insulating layers such as the first insulating layer 51, and electrically connected to the second surface P2 side via via conductors provided in insulating layers such as the second insulating layer 52.

[0021] As shown in Figure 1, it is preferable that the core material 30 is provided with a through conductor 60 that penetrates the core material 30 in the thickness direction outside the cavity 35. There may be one through conductor 60, but it is preferable that there be two or more.

[0022] The through-conductor 60 may be provided at least on the inner wall surface of the through-hole that penetrates the core material 30 in the thickness direction. The through-conductor 60 may be provided only on the inner wall surface of the through-hole, or it may be provided throughout the entire interior of the through-hole.

[0023] If the through conductor 60 is provided only on the inner wall surface of the through hole, the inside of the through conductor 60 may be filled with a resin material, as shown in Figure 1. In that case, the portion filled with the resin material may be a conductor or an insulator.

[0024] Figure 2 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component embedded substrate according to the first embodiment of the present invention. Figure 3A is a cross-sectional view along the line A-A' shown in Figure 2. Figure 3B is a cross-sectional view along the line B-B' shown in Figure 2.

[0025] Figure 2 shows an example of the arrangement of electronic components 20 on a surface parallel to the main surface of the core material 30 and overlapping with the electronic components 20. The same applies to the plan views from Figure 2 onward.

[0026] First, as shown in Figure 2, on the main surface of the core material 30, the region enclosing the electronic component 20 embedded in the cavity 35 by a line segment parallel to the X-axis of the core material 30 and a line segment parallel to the Y-axis of the core material 30 is defined as the component region R. Preferably, the X-axis and Y-axis are orthogonal.

[0027] As an example, in the following embodiment, the direction of one side along the general shape of the core material 30 as viewed from the thickness direction is described as the X-axis, and the direction perpendicular to the X-axis is described as the Y-axis.

[0028] Next, as shown in Figures 2 and 3A, in a straight line A-A' parallel to the X-axis such that the overlap with the component region R is longest and the sum of the overlaps with the electronic component 20 is maximized, we define the length of the line segment from one end of the main surface of the core material 30 to the component region R as X1, the length of the line segment within the component region R as X2, and the length of the line segment from the other end of the main surface of the core material 30 to the component region R as X3.

[0029] For example, in Figure 2, the straight line extending the double arrow AR1 along the X-axis has the longest overlap with the component region R, but it is not the straight line that maximizes the sum of overlaps with the electronic component 20, and therefore does not correspond to the straight line A-A'. Similarly, the straight line extending the double arrow AR2 parallel to the X-axis along the X-axis is neither the straight line that has the longest overlap with the component region R nor the straight line that maximizes the sum of overlaps with the electronic component 20, and therefore does not correspond to the straight line A-A'.

[0030] Furthermore, as shown in Figures 2 and 3B, in a straight line B-B' parallel to the Y-axis such that the overlap with the component region R is longest and the sum of the overlaps with the electronic component 20 is maximized, the length of the line segment from one end of the main surface of the core material 30 to the component region R is defined as Y1, the length of the line segment within the component region R is defined as Y2, and the length of the line segment from the other end of the main surface of the core material 30 to the component region R is defined as Y3.

[0031] In the examples shown in Figures 2, 3A, and 3B, the conditions X2 < Y2 and X1 + X3 > Y1 + Y3 are satisfied. Note that the relationship between the X and Y axes may be reversed; that is, X2 > Y2 and X1 + X3 < Y1 + Y3 may also be satisfied.

[0032] By arranging the electronic components 20 as described above, the outer width of the substrate parallel to the axis where the electronic components 20 occupy a high proportion can be increased, thereby suppressing substrate deformation due to thermal strain. As a result, the reliability of connections with electronic components mounted on the substrate (also called mounted components) and electronic components embedded in the substrate (also called embedded components) can be improved.

[0033] Figure 4 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component embedded substrate according to a second embodiment of the present invention. Figure 5A is a cross-sectional view along the line A-A' shown in Figure 4. Figure 5B is a cross-sectional view along the line B-B' shown in Figure 4.

[0034] In the examples shown in Figures 4, 5A, and 5B, the same conditions as in the examples shown in Figures 2, 3A, and 3B are met: X2 < Y2 and X1 + X3 > Y1 + Y3. Alternatively, the conditions X2 > Y2 and X1 + X3 < Y1 + Y3 may also be met.

[0035] In this case, as shown in Figures 4, 5A, and 5B, it is preferable that the length of X1 is equal to the length of X3, or that the length of Y1 is equal to the length of Y3. In particular, it is preferable that the length of X1 is equal to the length of X3 and the length of Y1 is equal to the length of Y3.

[0036] As described above, by making the outer width of the circuit board the same dimension, thermal distortion can be made uniform and minimized, thereby further improving connection reliability.

[0037] Figure 6 is a schematic plan view showing an example of the arrangement of electronic components embedded in an electronic component-embedded substrate according to the third embodiment of the present invention. Figure 7A is a cross-sectional view along the line A-A' shown in Figure 6. Figure 7B is a cross-sectional view along the line B-B' shown in Figure 6.

[0038] As shown in Figures 6, 7A, and 7B, one electronic component 20 may be built into the cavity 35. For example, the electronic component 20 is a multi-terminal capacitor. In that case, the electronic component 20 is preferably a multi-terminal silicon capacitor or a multi-array capacitor.

[0039] When one electronic component 20 is formed by integrally forming a plurality of capacitors, the influence of thermal distortion is greater than when a plurality of electronic components 20 are incorporated. Therefore, by arranging the electronic component 20 so as to satisfy X2 < Y2 and X1 + X3 > Y1 + Y3, or X2 > Y2 and X1 + X3 < Y1 + Y3, the influence of thermal distortion can be reduced.

[0040] In the first to third embodiments of the present invention, X2 < Y2 and X1 + X3 > Y1 + Y3 and X2 < X1 + X3 are satisfied. Alternatively, X2 > Y2 and X1 + X3 < Y1 + Y3 and Y2 < Y1 + Y3 may be satisfied.

[0041] FIG. 8 is a plan view schematically showing an example of the arrangement of electronic components incorporated in an electronic component incorporated substrate according to a fourth embodiment of the present invention. FIG. 9A is a cross-sectional view taken along line A - A' shown in FIG. 8. FIG. 9B is a cross-sectional view taken along line B - B' shown in FIG. 8.

[0042] As shown in FIGS. 8, 9A, and 9B, X2 < Y2 and X1 + X3 > Y1 + Y3 and X2 > X1 + X3 may be satisfied. Alternatively, X2 > Y2 and X1 + X3 < Y1 + Y3 and Y2 > Y1 + Y + 3 may be satisfied.

[0043] The number of electronic components 20 incorporated in the cavity 35 is not particularly limited. In the example shown in FIGS. 8, 9A, and 9B, one electronic component 20 is incorporated in the cavity 35, but a plurality of electronic components 20 may be incorporated in the cavity 35.

[0044] By arranging the electronic component 20 as described above, more (or a larger area of) electronic components 20 can be mounted while maintaining connection reliability.

[0045] [Shape] In the electronic component incorporated substrate 1, the outer shape of the component region R viewed from the thickness direction is not particularly limited, but for example, it is a square or a rectangle having two sides parallel to the X axis and two sides parallel to the Y axis. The outer shape of the component region R viewed from the thickness direction is preferably a shape along the outer shape of the cavity 35.

[0046] In the substrate 1 with built-in electronic components, the outer shape of the cavity 35 as viewed from the thickness direction is not particularly limited. For example, it is a square or a rectangle having two sides parallel to the X-axis and two sides parallel to the Y-axis. The outer shape of the cavity 35 as viewed from the thickness direction may be a shape along the outer shape of the core material 30. For example, when the outer shape of the cavity 35 is a quadrilateral such as a square or a rectangle, at least one corner may be rounded.

[0047] In the substrate 1 with built-in electronic components, the outer shape of the core material 30 as viewed from the thickness direction is not particularly limited. For example, it is a square or a rectangle having two sides parallel to the X-axis and two sides parallel to the Y-axis. Note that the X-axis and the Y-axis of the core material 30 do not have to be perpendicular. For example, the outer shape of the core material 30 as viewed from the thickness direction may be an arbitrary quadrilateral having two sides parallel to the X-axis and two sides parallel to the Y-axis. In that case, the direction of one side along the general shape of the core material 30 as viewed from the thickness direction is the X-axis, and the direction of the other side adjacent to that side is the Y-axis. For example, when the outer shape of the core material 30 is a quadrilateral such as a square or a rectangle, at least one corner may be rounded.

[0048] [Material] In the substrate 1 with built-in electronic components, the core material 30 is made of an insulating material. Similarly, the insulating layers such as the first insulating layer 51 are made of an insulating material. The insulating materials constituting these substrate bodies are resin materials such as epoxy, phenol, polyimide, or inorganic fillers or inorganic cloths made of materials such as SiO ２ and Al ２ O ３ etc. as the main materials.

[0049] In the substrate 1 with built-in electronic components, the circuit wirings such as the first wiring layer 41 are made of metal. The metal constituting the circuit wiring uses a metal with good electrical conductivity such as Cu or Ag as the main material. Materials such as Ni for diffusion prevention, Ti or NiCr for improving adhesion, and Au for surface rust prevention may be laminated on the wiring layer. Each wiring layer is electrically connected via via conductors with respect to the thickness direction of the substrate. These via conductors are also made of the same material as the wiring.

[0050] In the electronic component-embedded substrate 1, the electronic component 20 may include, for example, chip capacitors such as multilayer ceramic capacitors (MLCCs), two-terminal components such as chip resistors and chip inductors, and multi-terminal components such as semiconductor chips, silicon capacitors, and multi-array capacitors.

[0051] For example, when the electronic component-embedded substrate 1 is used as a substrate for a power module, the electronic component 20 is mainly a capacitor such as a chip capacitor, silicon capacitor, or multi-array capacitor, which is used as an output capacitor in large numbers. For example, if the electronic component 20 is a capacitor, the capacitor may be embedded in the cavity 35 such that the first electrode and the second electrode face each other in the thickness direction of the substrate.

[0052] If the electronic component 20 is a plurality of multilayer ceramic capacitors, for example, as described in Japanese Patent Application Publication No. 2002-124749, the first and second electrodes of each capacitor are housed in the cavity 35 so that they face each other in the thickness direction of the substrate.

[0053] If the electronic component 20 is a multi-array capacitor, for example, as described in International Publication No. 2022 / 050167, the electronic component 20 includes a capacitor portion and a sealing layer provided to cover at least one main surface of the capacitor portion, the capacitor portion includes an anode plate having a porous portion on at least one main surface of the core portion, a dielectric layer provided on the surface of the porous portion, and a cathode layer provided on the surface of the dielectric layer. In this case, the core portion of the anode plate corresponding to the first electrode and the cathode layer corresponding to the second electrode are housed in the cavity 35 so as to face each other in the thickness direction of the substrate. Furthermore, it is preferable that the cathode layer includes a solid electrolyte layer provided on the surface of the dielectric layer.

[0054] [Manufacturing Method] An example of a manufacturing method for the electronic component embedded substrate of the present invention will be described with reference to Figures 10 to 16.

[0055] Figure 10 is a schematic cross-sectional view showing an example of the process for preparing a core material having a first wiring layer, a second wiring layer, and a through conductor.

[0056] For example, through holes are drilled into a copper-clad laminate (CCL) substrate with a thickness of approximately 0.4 mm, and the openings are metallized by electroless Cu plating and electrolytic Cu plating. Then, both sides of the substrate are covered with a photosensitive resist to form a resist mask by photolithography, the Cu is etched, the resist is peeled off, and a substrate with a patterned metal layer is obtained. This yields a core material 30 having a first wiring layer 41, a second wiring layer 42, and a through conductor 60.

[0057] Figure 11 is a schematic cross-sectional view showing an example of the process of forming a cavity in a core material.

[0058] Cavities 35 are formed in predetermined locations on the core material 30 by methods such as drilling, routing, or laser processing. The cavities 35 are usually formed along the outer shape of the component area R (see Figure 12) with a gap of about 0.1 mm to 0.2 mm between them and the area where the electronic components 20 are placed (see the component area R mentioned above). However, it is not necessary for the cavities to be evenly spaced along the component area R, and the spacing can be set appropriately depending on conditions such as the state in which the electronic components 20 are embedded.

[0059] Figure 12 is a schematic cross-sectional view showing an example of the process of mounting electronic components into a cavity.

[0060] After fixing the core material 30, which has a cavity 35 formed in it, onto a support substrate 70, also called a temporary mounting plate, with a tacky material such as double-sided tape, the electronic components 20 are mounted using a mounter.

[0061] Figure 13 is a schematic cross-sectional view showing an example of the process of laminating the first insulating layer and the first metal layer.

[0062] For example, a first insulating layer 51 made of a laminated sheet material such as prepreg or Ajinomoto Build-Up Film (ABF) and a first metal layer 71 such as Cu foil are laminated from one main surface side of the core material 30. At this time, the resin of the film flows into the gap between the cavity 35 and the electronic component 20, fixing the electronic component 20 in place.

[0063] Figure 14 is a schematic cross-sectional view showing an example of the process of laminating the second insulating layer and the second metal layer.

[0064] The support substrate 70 is mechanically peeled off, and the second insulating layer 52 and the second metal layer 72, such as Cu foil, are similarly laminated on the other main surface side of the core material 30.

[0065] Figure 15 is a schematic cross-sectional view showing an example of the process for forming the third and fourth wiring layers.

[0066] Via holes are formed at predetermined positions by methods such as laser processing, and the inside of the via holes is filled with electroless Cu plating and electrolytic Cu plating. Then, the metal layers formed on both sides of the insulating layer are covered with a photosensitive resist, a resist mask is formed by photolithography, the Cu is etched, the resist is peeled off and patterned. This forms the third wiring layer 43 and the fourth wiring layer 44.

[0067] Figure 16 is a schematic cross-sectional view showing an example of a process in which the insulating layer and wiring layer are repeatedly formed.

[0068] For example, after laminating the above-mentioned laminated sheet material and Cu foil on both sides of the core material 30, via holes are formed at predetermined positions by methods such as laser processing, and the inside of the via holes is filled with electroless Cu plating and electrolytic Cu plating. Then, the metal layers formed on both sides are covered with a photosensitive resist, a resist mask is formed by photolithography, the Cu is etched, the resist is peeled off and patterned. By repeating this process of forming insulating layers and wiring layers a predetermined number of times, an electronic component embedded substrate 1 is obtained.

[0069] Figures 17A to 17D are schematic plan views showing examples of arrangements when multiple electronic components are embedded in the electronic component embedded substrate of the present invention.

[0070] Figures 17A to 17D illustrate that, with respect to the arrangement of electronic components 20 such as capacitors, the relative magnitudes of X2 and Y2 mentioned above differ, as does the relative magnitude of the sum of the distances X1 and X3 to the end of the core material 30 and the sum of the distances Y1 and Y3.

[0071] In the example shown in Figure 17A, X2 > Y2 and X1 + X3 < Y1 + Y3 are satisfied. In the examples shown in Figures 17B to 17D, X2 < Y2 and X1 + X3 > Y1 + Y3 are satisfied.

[0072] Figures 18A to 18D are schematic plan views illustrating embodiments of the present invention when the electronic component-embedded substrate is applied to a power supply module substrate.

[0073] The electronic component-embedded substrate of the present invention is applicable to substrates for power supply modules such as buck switching regulators or boost switching regulators. In power supply module substrates such as buck switching regulators or boost switching regulators, the first and second surfaces of the substrate need to be connected to the input voltage (Vin), output voltage (Vout), ground (GND), and control line (CTL) for driving the regulator. For this reason, the through-conductor 60 provided in the core material 30 needs to be connected to these nodes.

[0074] Figures 18A to 18D illustrate the arrangement of through-conductors 60 and electronic components 20 connected to each node, as well as the outer shape of the core material 30. As shown in Figures 18A to 18D, by arranging many through-conductors 60 in the region where X1 + X3 and Y1 + Y3 are large, which is determined by the relative sizes of X2 and Y2 mentioned above, it is possible to reduce the overall size of the substrate while suppressing a decrease in connection reliability.

[0075] Figure 19 is a schematic diagram showing an example of a voltage regulator module using the electronic component embedded substrate of the present invention. Figure 20 is an example of an equivalent circuit diagram of the voltage regulator module shown in Figure 19.

[0076] The voltage regulator module 100 shown in Figure 19 is placed on the main surface of a system board 110, such as a motherboard.

[0077] The voltage regulator module 100 may be placed on the same main surface of the system board 110 as the main surface on which the arithmetic processing unit 120 is placed, but it is preferable to place it on the main surface opposite to the main surface on which the arithmetic processing unit 120 is placed, as shown in Figure 19. In the arrangement shown in Figure 19, by bringing the output terminal of the voltage regulator module 100 and the input terminal of the arithmetic processing unit 120 close together, transient voltage responses associated with current fluctuations (load fluctuations) of the arithmetic processing unit 120 can be suppressed.

[0078] As shown in the example in Figure 19, in order to arrange the voltage regulator module 100 on the main surface of the system board 110 opposite to the main surface on which the arithmetic processing unit 120 is arranged, it is preferable that peripheral components such as the inductor L, output capacitor Cout, and input capacitor Cin that constitute the circuit shown in Figure 20 are built into the voltage regulator module 100. For this reason, it is preferable to apply the electronic component-integrated board of the present invention to a power supply module board such as a step-down switching regulator or a step-up switching regulator.

[0079] The electronic component embedded substrate of the present invention is not limited to the above embodiments, and various applications and modifications can be made within the scope of the present invention with respect to the configuration of the core layer, electronic components, insulating layer, through conductor, conductor wiring layer, etc., and the manufacturing conditions of the electronic component embedded substrate.

[0080] 1 Electronic component embedded substrate 10 Core layer 20 Electronic component 30 Core material 35 Cavity 41 First wiring layer 42 Second wiring layer 43 Third wiring layer 44 Fourth wiring layer 45 Fifth wiring layer 46 Sixth wiring layer 47 Seventh wiring layer 48 Eighth wiring layer 51 First insulating layer 52 Second insulating layer 53 Third insulating layer 54 Fourth insulating layer 55 Fifth insulating layer 56 Sixth insulating layer 60 Through conductor 70 Support substrate 71 First metal layer 72 Second metal layer 100 Voltage regulator module 110 System board 120 Arithmetic processing unit Cin Input capacitor Cout Output capacitor L Inductor P1 First surface P2 Second surface R Component area

Claims

1. A core layer comprising at least one core material having a cavity in the thickness direction, and at least one electronic component embedded in the cavity of the core material, wherein on the main surface of the core material, the region enclosing the electronic component embedded in the cavity by a line segment parallel to the X-axis of the core material and a line segment parallel to the Y-axis of the core material is defined as the component region, and in a straight line A-A' parallel to the X-axis such that the overlap with the component region is longest and the sum of the overlaps with the electronic component is maximum, the length of the line segment from one end of the main surface of the core material to the component region is X1, the length of the line segment within the component region is X2, and the length of the line segment from the other end of the main surface of the core material to the component region is X3. An electronic component-embedded substrate that satisfies either X2 < Y2 and X1 + X3 > Y1 + Y3, or X2 > Y2 and X1 + X3 < Y1 + Y3, in a straight line B - B' parallel to the Y-axis such that the overlap with the component area is longest and the sum of the overlaps with the electronic component is maximum, where Y1 is the length of the line segment from one end of the main surface of the core material to the component area, Y2 is the length of the line segment within the component area, and Y3 is the length of the line segment from the other end of the main surface of the core material to the component area.

2. The electronic component embedded substrate according to claim 1, wherein the length of X1 is equal to the length of X3, or the length of Y1 is equal to the length of Y3.

3. The electronic component embedded substrate according to claim 1, wherein the length of X1 is equal to the length of X3, and the length of Y1 is equal to the length of Y3.

4. An electronic component embedded substrate according to any one of claims 1 to 3, satisfying X2 < Y2 and X1 + X3 > Y1 + Y3 and X2 > X1 + X3, or X2 > Y2 and X1 + X3 < Y1 + Y3 and Y2 > Y1 + Y3.

5. An electronic component embedded substrate according to any one of claims 1 to 3, satisfying X2 < Y2 and X1 + X3 > Y1 + Y3 and X2 < X1 + X3, or X2 > Y2 and X1 + X3 < Y1 + Y3 and Y2 < Y1 + Y3.

6. The electronic component substrate according to any one of claims 1 to 5, wherein the outer shape of the component area as viewed from the thickness direction is a square or rectangle having two sides parallel to the X-axis and two sides parallel to the Y-axis.

7. The electronic component substrate according to any one of claims 1 to 6, wherein the outer shape of the core material as viewed from the thickness direction is a square or rectangle having two sides parallel to the X-axis and two sides parallel to the Y-axis.

8. The electronic component embedded substrate according to any one of claims 1 to 7, further comprising a through conductor provided outside the cavity so as to penetrate the core material in the thickness direction.

9. The electronic component embedded circuit board according to any one of claims 1 to 8, wherein the electronic component is a capacitor.

10. The electronic component substrate according to claim 9, wherein the capacitor is housed in the cavity such that the first electrode and the second electrode face each other in the thickness direction.

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