Display panel and display apparatus

Abstract

The present application relates to the technical field of display. Provided are a display panel and a display apparatus. A first active layer of a first transistor in a first pixel circuit and a second active layer of a second transistor in a second pixel circuit are both metal oxide active layers, the second pixel circuit is close to a hole region, the first pixel circuit is away from the hole region, a first pixel is provided with a first signal trace, the orthographic projection of the first active layer on a substrate overlaps with the orthographic projection of the first signal trace on the substrate in a second direction, a second pixel is provided with a second signal trace, and the orthographic projection of the second active layer on the substrate overlaps with the orthographic projection of the second signal trace on the substrate in the second direction.

Description

A display panel and display device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202411464866.8, filed on October 18, 2024, entitled “A Display Panel and Display Device,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0004] With the continuous development of science and technology, various display devices have been widely used in people's lives and work, bringing great convenience to people's daily lives. As one of the important components of a display device, the design of the display panel directly or indirectly affects the display effect of the device.

[0005] To reduce power consumption during display operation, pixel circuits in current display panels typically employ LTPO (Low Temperature Polycrystalline Oxide) technology. To accommodate components such as cameras, perforations are created in the display panel to form openings.

[0006] Currently, the wiring design around the metal oxide active layer of the transistor in the pixel circuit of pixels near the aperture area is different from that of pixels far away from the aperture area. The pixel circuit near the aperture area is prone to failure, which can cause the pixel to light up and produce bright spots, affecting the display effect of the display panel. Summary of the Invention

[0007] In view of the above problems, this application provides a display panel and display device. By improving the pixel wiring near the aperture area, the wiring design around the metal oxide active layer of the transistors in the pixel circuits of pixels near the aperture area and pixels far from the aperture area are the same. This solves the problem of easy failure of pixel circuits near the aperture area and improves the display effect of the display panel. The specific solution is as follows:

[0008] A first aspect of this application provides a display panel, the display panel comprising: pixels, an opening area, and a display area at least partially surrounding the opening area; the pixels comprising a first pixel disposed away from the opening area and a second pixel disposed close to the opening area;

[0009] The first pixel includes a first pixel circuit, the first pixel circuit includes a first transistor, the first transistor includes a first active layer and a first bottom gate and a first top gate located on both sides of the first active layer in a first direction; the first direction is perpendicular to the plane of the display panel.

[0010] The second pixel includes a second pixel circuit, the second pixel circuit includes a second transistor, the second transistor includes a second active layer and a second bottom gate and a second top gate located on both sides of the second active layer in the first direction; both the first active layer and the second active layer are metal oxide active layers;

[0011] The first pixel further includes a first signal trace, which is disposed on the same layer as the first top gate, and the orthographic projection of the first active layer on the substrate and the orthographic projection of the first signal trace on the substrate overlap in a second direction;

[0012] The second pixel further includes a second signal trace, which is disposed on the same layer as the second top gate. The orthographic projection of the second active layer on the substrate and the orthographic projection of the second signal trace on the substrate overlap in a second direction. The second direction is parallel to the plane where the display panel is located and perpendicular to the length extension direction of the signal trace. The signal trace is either the first signal trace or the second signal trace.

[0013] A second aspect of this application provides a display device, the display device including the display panel described above. Attached Figure Description

[0014] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0015] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0016] Figure 2 is a schematic diagram of a first pixel circuit provided in an embodiment of this application;

[0017] Figure 3 is a schematic diagram of a second pixel circuit provided in an embodiment of this application;

[0018] Figure 4 is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0019] Figure 5 is a partial layout diagram of a display panel provided in an embodiment of this application;

[0020] Figure 6 is a partial layout diagram of another display panel provided in an embodiment of this application;

[0021] Figure 7 is a schematic diagram of a signal trace in an opening area provided in an embodiment of this application;

[0022] Figure 8 is a schematic diagram of signal routing in another opening area provided in an embodiment of this application;

[0023] Figure 9 is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0024] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will understand that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems. It should be noted that directional terms appearing in this application are based on the relative positional relationships shown in the accompanying drawings and should not be considered as absolute limitations on this application.

[0025] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] Referring to Figure 1, Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of this application. The display panel 100 includes: pixels 10, an opening area A1, and a display area A2 that at least partially surrounds the opening area A1. The opening area A1 is used to house other components such as a camera.

[0027] As shown in Figure 1, the display panel 100 includes signal lines extending in the row direction and signal lines extending in the column direction. The signal lines extending in the row direction and the signal lines extending in the column direction intersect, defining a plurality of arrayed pixels. As shown in Figure 1, the signal lines extending in the row direction may include Scan signal lines, Vref signal lines, and DVH signal lines, etc. The signal lines extending in the row direction may also include Data signal lines and PVDD signal lines, etc.

[0028] Pixel 10 includes a first pixel 11 disposed away from the opening area AA and a second pixel 12 disposed close to the opening area AA. The first pixel 11 includes a first pixel circuit 11a and a first light-emitting element 11b, and the second pixel 12 includes a second pixel circuit 12a and a second light-emitting element 12b.

[0029] Referring to Figure 2, which is a schematic diagram of a first pixel circuit according to an embodiment of this application, the first pixel circuit 11a includes a first driving transistor T1 and a first light-emitting element 11b. One end of the first driving transistor T1 is electrically connected to the anode of the first light-emitting element 11b. The first driving transistor T1 is used to provide a first driving current to the first light-emitting element 11b, and the first light-emitting element 11b emits light in response to the first driving current. It should be noted that the first driving transistor T1 can be a PMOS type driving transistor, or an NMOS type driving transistor, or other types of driving transistors. In this embodiment, the first driving transistor T1 is described as a PMOS type driving transistor. The drain of the first driving transistor T1 is coupled to the first light-emitting element 11b, and provides the first driving current to the first light-emitting element 11b after the first driving transistor T1 is turned on.

[0030] Referring to Figure 3, which is a schematic diagram of a second pixel circuit according to an embodiment of this application, the second pixel circuit 12a includes a second driving transistor M1 and a second light-emitting element 12b. One end of the second driving transistor M1 is electrically connected to the anode of the second light-emitting element 12b. The second driving transistor M1 is used to provide a second driving current to the second light-emitting element 12b, and the second light-emitting element 12b emits light in response to the second driving current. It should be noted that the second driving transistor M1 can be a PMOS type driving transistor, or an NMOS type driving transistor, or other types of driving transistors. In this embodiment, the second driving transistor M1 is described as a PMOS type driving transistor. The drain of the second driving transistor M1 is coupled to the second light-emitting element 12b, and provides a second driving current to the second light-emitting element 12b after the second driving transistor M1 is turned on.

[0031] Referring to Figure 4, which is a cross-sectional schematic diagram of a display panel provided in an embodiment of this application, the display panel 100 includes a substrate 13 and an array layer located on the substrate 13. The array layer includes, but is not limited to, a buffer layer 14, a first insulating layer 15, a second insulating layer 16, a third insulating layer 17, a passivation layer 18, a planarization layer 19, and a pixel definition layer 20. The pixel definition layer 20 has multiple opening regions, and an anode layer 21, a light-emitting layer 22, and a cathode layer 23 are disposed within the opening regions to constitute the light-emitting elements required for the pixel 10.

[0032] Optionally, the substrate 13 is a flexible insulating material substrate with properties such as stretchability, bendability, or flexibility. Its material includes, but is not limited to, polyimide (PI), polycarbonate (PC), or polyethylene terephthalate (PET).

[0033] Optionally, the buffer layer 14 includes, but is not limited to, an inorganic material layer or an organic material layer, wherein the inorganic material layer includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or aluminum nitride, and the organic material layer includes, but is not limited to, acrylic or PI.

[0034] As shown in Figure 4, the display panel 100 further includes transistors that form a first pixel circuit 11a and a second pixel circuit 12a. The first transistor 24 corresponding to the first pixel circuit 11a in the first pixel 11 includes a first active layer 25, a first top gate 26, a first bottom gate 27, a first source 28, and a first drain 29. The first bottom gate 27 is located on the side of the buffer layer 14 facing away from the substrate 13. The first active layer 25 is located on the side of the first insulating layer 15 facing away from the substrate 13. The second insulating layer 16 is located between the first active layer 25 and the first top gate 26. The first top gate 26 is located on the side of the second insulating layer 16 facing away from the substrate 13. The third insulating layer 17 is located on the side of the first top gate 26 facing away from the substrate 13. The first source 28 and the first drain 29 are located on the same layer and on the side of the third insulating layer 17 facing away from the substrate 13. The passivation layer 18 is disposed on the side of the first source electrode 28 and the first drain electrode 29 facing away from the substrate 13, the planarization layer 19 is disposed on the side of the passivation layer 18 facing away from the substrate 13, and the pixel definition layer 20 is disposed on the side of the planarization layer 19 facing away from the substrate 13. The first top gate 26 and the first bottom gate 27 are located on opposite sides of the first active layer 25 in the first direction X.

[0035] The second transistor 30 corresponding to the second pixel circuit 12a in the second pixel 12 includes a second active layer 31, a second top gate 32, a second bottom gate 33, a second source 34, and a second drain 35. The second bottom gate 33 is located on the side of the buffer layer 14 facing away from the substrate 13. The second active layer 31 is located on the side of the first insulating layer 15 facing away from the substrate 13. The second insulating layer 16 is located between the second active layer 31 and the second top gate 32. The second top gate 32 is located on the side of the second insulating layer 16 facing away from the substrate 13. The third insulating layer 17 is located on the side of the second top gate 32 facing away from the substrate 13. The second source 34 and the second drain 35 are located on the same layer and on the side of the third insulating layer 17 facing away from the substrate 13. The passivation layer 18 is disposed on the side of the second source 34 and the second drain 35 facing away from the substrate 13. The planarization layer 19 is disposed on the side of the passivation layer 18 facing away from the substrate 13. The pixel definition layer 20 is disposed on the side of the planarization layer 19 facing away from the substrate 13. The second top gate 32 and the second bottom gate 33 are located on both sides of the second active layer 31 in the first direction X.

[0036] In this design, both the first active layer 25 and the second active layer 31 are metal oxide active layers. The first active layer 25 and the second active layer 31 can be formed in the same layer, for example, they can both be located in the same film layer as the metal oxide active layer.

[0037] It should be noted that, in the embodiments of this application, the active metal oxide layer includes, but is not limited to, an IGZO active layer. In the embodiments of this application, only an IGZO active layer is used as an example for illustration.

[0038] In this design, buffer layer 14 can be understood as a film layer used to set the bottom gate of a transistor. Second insulating layer 16 can be understood as a film layer used to set the top gate of a transistor, and other signal traces may also be formed on second insulating layer 16 as needed. Buffer layer 14 and second insulating layer 16 are two different film layers. Buffer layer 14 can be understood as a film layer used to set an electrode plate of a storage capacitor in the pixel circuit, overlapping with the gate of the driving transistor in the pixel circuit to form a storage capacitor. Other signal traces may also be formed on buffer layer 14 as needed.

[0039] Referring to Figure 5, which is a partial layout schematic diagram of a display panel provided in an embodiment of this application, the first pixel 11 further includes a first signal trace 36, which is disposed on the same layer as the first top gate 26. From the top view of the layout, the orthographic projection of the first active layer 25 on the substrate 13 and the orthographic projection of the first signal trace 36 on the substrate 13 overlap in the second direction Y.

[0040] The second pixel 12 also includes a second signal trace 37, which is disposed on the same layer as the second top gate 32. From a top-view perspective of the layout, the orthographic projection of the second active layer 31 onto the substrate 13 overlaps with the orthographic projection of the second signal trace 37 onto the substrate 13 in the second direction Y. The second direction Y is parallel to the plane of the display panel 100 and perpendicular to the length extension direction of the signal trace, which is either the first signal trace 36 or the second signal trace 37.

[0041] It should be noted that the first signal trace 234 and the second signal trace are not shown in Figure 4.

[0042] Specifically, the applicant discovered that the transistors in the active metal oxide layer of the pixel circuit implemented by LTPO technology are typically top-bottom dual-gate transistors. In the current pixel fabrication process, due to the design of the aperture area A1 in the display panel, the number of pixels in the upper and lower rows is unequal in the column direction. To ensure uniform etching, the wiring design around the active metal oxide layer of the transistors in the pixel circuits of pixels closer to aperture area A1 differs from that of pixels farther away from aperture area A1. Pixel circuits closer to aperture area A1 are prone to failure, leading to bright spots and affecting the display panel's display effect.

[0043] Based on this, in this embodiment of the application, the wiring of the second pixel 12 near the aperture region A1 is improved so that the wiring design around the metal oxide active layer of the transistor in the pixel circuit of the second pixel 12 near the aperture region A1 is the same as that of the first pixel 11 far away from the aperture region A1. This solves the problem that the second pixel circuit 12a near the aperture region A1 is prone to failure and improves the display effect of the display panel 100.

[0044] Specifically, as shown in Figure 5, the first active layer 25 of the first transistor 24 in the first pixel circuit 11a and the second active layer 31 of the second transistor 30 in the second pixel circuit 12a are both metal oxide active layers. The second pixel circuit 12a is close to the aperture region A1, while the first pixel circuit 11a is far away from the aperture region A1. The first pixel 11 is provided with a first signal trace 36. The orthographic projection of the first active layer 25 on the substrate 13 and the orthographic projection of the first signal trace 36 on the substrate 13 overlap in the second direction Y. As shown in Figure 5, the first active layer 25 and the first signal trace 36 have opposite regions in the second direction Y (i.e., the region shown by the dashed box 38).

[0045] The second pixel 12 is provided with a second signal trace 37. The orthographic projection of the second active layer 31 on the substrate 13 and the orthographic projection of the second signal trace 37 on the substrate 13 overlap in the second direction Y. As shown in Figure 5, the second active layer 31 and the second signal trace 37 also have opposite regions in the second direction Y (i.e., the region shown by the dashed box 39).

[0046] It is understood that, based on the relative positional relationship between the first signal trace 36 and the first active layer 25 in this embodiment, by adding a second signal trace 37 to the second pixel 12, the trace design around the metal oxide active layer of the transistors in the second pixel 12, which is closer to the aperture region A1, is the same as that of the first pixel 11, which is farther away from the aperture region A1. This improves the characteristics of the second transistor 30 in the second pixel 12, solves the problem that the second transistor 30 in the second pixel 12 is prone to failure, improves the stability of the second pixel circuit 12a, and ultimately improves the display effect of the display panel 100.

[0047] In an optional embodiment of this application, as shown in FIG1, the orthographic projection of the opening region A1 in the first direction X includes at least an arc-shaped line segment.

[0048] Specifically, in this embodiment, the opening region A1 shown in Figure 1 is illustrated as an elliptical shape. It should be noted that the shape of the opening region A1 is not limited in this embodiment and can be determined according to the actual situation, as long as the orthographic projection of the opening region A1 in the first direction X includes at least one arc segment.

[0049] In an optional embodiment of this application, referring to FIG6, FIG6 is a partial layout schematic diagram of another display panel provided in an embodiment of this application. The second signal trace 37 is a signal trace that extends from the first signal trace 36 to the second pixel 12.

[0050] Specifically, in this embodiment, during the fabrication of the second pixel 12, the first signal trace 36 corresponding to the first pixel 11 is directly extended to the area where the second pixel 12 is located. At this time, the orthographic projection of the first active layer 25 on the substrate 13 overlaps with the orthographic projection of the first signal trace 36 on the substrate 13 in the second direction Y, and the orthographic projection of the second active layer 31 on the substrate 13 overlaps with the orthographic projection of the first signal trace 36 on the substrate 13 in the second direction Y. That is, the orthographic projections of the first active layer 25 and the second active layer 31 on the substrate 13 both overlap with the orthographic projection of the same signal trace on the substrate 13 in the second direction Y. While improving the characteristics of the second transistor 30 in the second pixel 12, it is also possible to ensure that the characteristics of the first transistor 24 and the second transistor 30 are the same, thereby ensuring that the light-emitting performance of the first pixel 11 and the second pixel 12 is the same, and maximizing the display effect of the display panel 100.

[0051] In an optional embodiment of this application, referring to FIG7, FIG7 is a schematic diagram of signal routing at an opening area provided by an embodiment of this application. The display panel 100 provided by this embodiment of the application further includes: a third signal routing line 40 disposed around the opening area A1.

[0052] The end of the first signal trace 36 corresponding to each second pixel 12 that is close to the third signal trace 40 is electrically connected to the third signal trace 40.

[0053] Specifically, in this embodiment, all the first signal traces 36 corresponding to the second pixel 12 located near the opening area A1 are electrically connected to the same third signal trace 40, thereby realizing the series connection of multiple first signal traces 36 within the display panel 100, reducing the influence of the impedance of the first signal trace 36 itself on the transmitted signal, thereby improving the uniformity of the signal transmitted on the first signal trace 36, and further improving the display effect of the display panel.

[0054] In an optional embodiment of this application, the first signal trace 36 may also be connected in a grid pattern on the plane where the display panel 100 is located.

[0055] Specifically, in this embodiment, the first signal traces 36 are connected in a grid pattern on the plane of the display panel 100, which can share the voltage and reduce their own load, thereby improving electrical uniformity and further improving the display effect of the display panel 100.

[0056] In an optional embodiment of this application, as shown in FIG5, there is a gap between the first signal trace 36 and the second signal trace 37.

[0057] Specifically, in this embodiment, the second signal trace 37 added to the second pixel 12 and the first signal trace 36 corresponding to the first pixel 11 are two independent signal traces. That is, this embodiment is not limited to extending the first signal trace 36 to the area where the second pixel 12 is located; the second signal trace 37 can also be formed independently during the fabrication of the second pixel 12, such that the relative positional relationship between the second signal trace 37 and the second active layer 31 is the same as the relative positional relationship between the first signal trace 36 and the first active layer 25. This demonstrates the diverse feasibility of the technical solution in this application.

[0058] In an optional embodiment of this application, when there is a gap between the first signal trace 36 and the second signal trace 37, and they are two independent signal traces, the signals transmitted by the first signal trace 36 and the second signal trace 37 may be the same or different.

[0059] Specifically, in this embodiment, when the signals transmitted by the first signal trace 36 and the second signal trace 37 are the same, in addition to improving the characteristics of the second transistor 30 in the second pixel 12, it is also possible to ensure that the characteristics of the first transistor 24 and the second transistor 30 are the same, thereby ensuring that the light-emitting performance of the first pixel 11 and the second pixel 12 is the same, and maximizing the display effect of the display panel 100.

[0060] When the signals transmitted by the first signal trace 36 and the second signal trace 37 are different, it is necessary to ensure that the voltage value represented by the signal transmitted by the first signal trace 36 is as close as possible to the voltage value represented by the signal transmitted by the second signal trace 37, so as to avoid a large difference between the characteristics of the first transistor 24 and the second transistor 30. In this case, the second signal trace 37 can transmit a different signal than the first signal trace 36. Based on different circuit designs, the second pixel 12 can obviously achieve some additional functions, thereby increasing the display diversity of the display panel 100.

[0061] In an optional embodiment of this application, referring to FIG8, FIG8 is a schematic diagram of signal routing at another opening area provided in an embodiment of this application. The display panel provided in this embodiment of the application further includes: a third signal routing line 40 disposed around the opening area A1.

[0062] The second signal trace 37 corresponding to each second pixel 12 is electrically connected to the third signal trace 40.

[0063] Specifically, in this embodiment, all the second signal traces 37 corresponding to the second pixel 12 located near the opening area A1 are electrically connected to the same third signal trace 40, thereby realizing the series connection of multiple second signal traces 37 in the display panel, reducing the influence of the impedance of the second signal traces 37 themselves on the transmitted signal, thereby improving the uniformity of the signal transmitted on the second signal traces 37, and further improving the display effect of the display panel 100.

[0064] It should be noted that the third signal trace 40 shown in Figures 7 and 8 is illustrated as a closed-loop signal trace surrounding the opening region A1. In some optional embodiments, the third signal trace 40 can also be a single signal trace that is not connected end-to-end.

[0065] In one optional embodiment of this application, the first signal trace 36 is connected in a grid pattern on the plane where the display panel 100 is located; and / or, the second signal trace 37 is connected in a grid pattern on the plane where the display panel 100 is located.

[0066] Specifically, in this embodiment, the signal traces are connected in a grid pattern on the plane of the display panel, which can share the voltage and reduce their own load, thereby improving electrical uniformity and further enhancing the display effect of the display panel.

[0067] In an optional embodiment of this application, as shown in FIG2, the first pixel circuit 11a further includes:

[0068] The first data writing transistor T2 has a first terminal for receiving a data signal Vdata, and a second terminal for connecting to the source of the first driving transistor T1. The control signal S1 received by the gate of the first data writing transistor T2 is used to control the turn-on and turn-off of the first data writing transistor T2.

[0069] The first reset transistor T3 has a first terminal that receives a first reset signal Vref1A, and a second terminal that is electrically connected to the gate of the first driving transistor T1. The control signal S2 received at the gate of the first reset transistor T3 is used to control the turn-on and turn-off of the first reset transistor T3.

[0070] The first anode reset transistor T4 has a first terminal that receives a first anode reset signal Vref1B, and a second terminal that is electrically connected to the anode of the first light-emitting element 11b. The control signal S3 received at the gate of the first anode reset transistor T4 is used to control the turn-on and turn-off of the first anode reset transistor T4.

[0071] The first threshold compensation transistor T5 is used to compensate the threshold voltage of the first driving transistor T1. The control signal S4 received at the gate of the first threshold compensation transistor T5 is used to control the on and off states of the first threshold compensation transistor T5. Its connection relationship with other transistors is shown in Figure 2, and will not be described further here.

[0072] The first A-type light-emitting control transistor T6 and the first B-type light-emitting control transistor T7 are connected. One end of the first A-type light-emitting control transistor T6 is electrically connected to the first power supply terminal PVDD, and the other end is connected to the anode of the first light-emitting element 11b in sequence through the first driving transistor T1 and the first B-type light-emitting control transistor T7. The anode of the first light-emitting element 11b is electrically connected to the second power supply terminal PVEE. The control signal EM1 received by the gates of the first A-type light-emitting control transistor T6 and the first B-type light-emitting control transistor T7 is used to control their on and off states.

[0073] The first bias transistor T8 has a first terminal that receives a first bias signal DVH1, and a second terminal that is electrically connected to one end of the first driving transistor T1. The control signal S5 received at the gate of the first bias transistor T8 is used to control its on / off state. The first bias signal DVH1 is used to reset the state of the first driving transistor T1, which effectively improves hysteresis performance such as short frame brightness / first frame brightness issues.

[0074] As shown in Figure 2, the first pixel circuit 11a also includes a first capacitor C11, the specific connection of which is shown in Figure 2 and will not be described again here. It should be noted that the first capacitor C11 serves as the storage capacitor of the first pixel circuit 11a.

[0075] It should be noted that the operation of the first pixel circuit 11a requires the timing of each transistor to work together, which will only be briefly introduced here.

[0076] As shown in Figure 3, the second pixel circuit 12a further includes: a second data writing transistor M2, the first terminal of the second data writing transistor M2 is used to receive a data signal Vdata, the second terminal of the second data writing transistor M2 is connected to the source of the second driving transistor M1, and the control signal K1 received by the gate of the second data writing transistor M2 is used to control the conduction and turn-off of the second data writing transistor M2.

[0077] The second reset transistor M3 has a first terminal that receives the second reset signal Vref2A, and a second terminal that is electrically connected to the gate of the second drive transistor M1. The control signal K2 received at the gate of the second reset transistor M3 is used to control the turn-on and turn-off of the second reset transistor M3.

[0078] The second anode reset transistor M4 has a first terminal that receives the second anode reset signal Vref2B, and a second terminal that is electrically connected to the anode of the second light-emitting element 12b. The control signal K3 received at the gate of the second anode reset transistor M4 is used to control the turn-on and turn-off of the second anode reset transistor M4.

[0079] The second threshold compensation transistor M5 is used to compensate the threshold voltage of the second driving transistor M1. The control signal K4 received at the gate of the second threshold compensation transistor M5 is used to control the on and off states of the second threshold compensation transistor M5. Its connection relationship with other transistors is shown in Figure 3, and will not be described further here.

[0080] The second A-type light-emitting control transistor M6 and the second B-type light-emitting control transistor M7 are connected. One end of the second A-type light-emitting control transistor M6 is electrically connected to the first power supply terminal PVDD, and the other end is connected to the anode of the second light-emitting element 12b via the second driving transistor M1 and the second B-type light-emitting control transistor M7. The anode of the second light-emitting element 12b is electrically connected to the second power supply terminal PVEE. The control signal EM2 received by the gate of the second A-type light-emitting control transistor M6 and the gate of the second B-type light-emitting control transistor M7 is used to control their on and off states.

[0081] The second bias transistor M8 has a first terminal that receives a second bias signal DVH2, and a second terminal that is electrically connected to one end of the second driving transistor M1. The control signal K5 received at the gate of the second bias transistor M8 is used to control its on / off state. The second bias signal DVH2 is used to reset the state of the second driving transistor M1, which effectively improves hysteresis performance such as short frame brightness / first frame brightness issues.

[0082] As shown in Figure 3, the second pixel circuit also includes a second capacitor C21, the specific connection of which is shown in Figure 3 and will not be described again here. It should be noted that the second capacitor C21 serves as the storage capacitor of the second pixel circuit 12a.

[0083] It should be noted that the operation of the second pixel circuit 12a requires the timing of each transistor to work together, which will only be briefly introduced here.

[0084] The first pixel circuit 11a shown in Figure 2 and the second pixel circuit 12a shown in Figure 3 are also referred to as 8T1C circuits in the field, wherein the threshold compensation transistor and the reset transistor are typically metal-oxide active layer transistors with a top-bottom dual-gate structure. In the embodiments of this application, the first transistor 24 can be the first reset transistor T3, and the second transistor 30 can be the second reset transistor M3.

[0085] In the prior art, the first signal trace 36 corresponds to the area below the metal oxide active layer of the first reset transistor T3 in the region where the first pixel 11 is located, while the area below the metal oxide active layer of the second reset transistor M3 in the region where the second pixel 12 is located does not have a corresponding trace. In this case, the characteristics of the second reset transistor M3, such as the threshold voltage Vth, will be affected, causing the second reset transistor M3 to fail to turn on when it needs to be turned off, thereby affecting the gate potential of the second driving transistor M1, and consequently affecting the display effect of the display panel.

[0086] Based on this, in this embodiment, based on the relative positional relationship between the first signal trace 36 and the first active layer 25, a second signal trace 37 is added to the second pixel 12, so that the metal oxide active layer of the second reset transistor M3 in the area where the second pixel 12 is located also has a corresponding signal trace. This makes the trace design around the metal oxide active layer of the reset transistor in the pixel circuits of the second pixel 12, which is close to the aperture area A1, and the first pixel 11, which is far away from the aperture area A1, the same. This improves the characteristics of the second reset transistor M3 in the second pixel 12, solves the problem that the second reset transistor M3 in the second pixel 12 is prone to failure, improves the stability of the second pixel circuit 12a, and ultimately improves the display effect of the display panel.

[0087] In an optional embodiment of this application, the first terminal of the first reset transistor T3 is electrically connected to the first signal line 36, and the first reset signal Vref1A is transmitted on the first signal line 36; the first terminal of the second reset transistor M3 is electrically connected to the second signal line 37, and the second reset signal Vref2A is transmitted on the second signal line 37. Alternatively, the first terminal of the first anode reset transistor T4 is electrically connected to the first signal line 36, and the first anode reset signal Vref1B is transmitted on the first signal line 36; the first terminal of the second anode reset transistor M4 is electrically connected to the second signal line 37, and the second anode reset signal Vref2B is transmitted on the second signal line 37. Alternatively, the first terminal of the first bias transistor T8 is electrically connected to the first signal line 36, and the first bias signal DVH1 is transmitted on the first signal line 36; the first terminal of the second bias transistor M8 is electrically connected to the second signal line 37, and the second bias signal DVH2 is transmitted on the second signal line 37.

[0088] In other words, the first signal trace 36 can be a signal trace for transmitting the first reset signal Vref1A, the first anode reset signal Vref1B, or the first bias signal DVH1. Similarly, the second signal trace 37 can be a signal trace for transmitting the second reset signal Vref2A, the second anode reset signal Vref2B, or the second bias signal DVH2.

[0089] It should be noted that when there is a gap between the first signal trace 36 and the second signal trace 37, and they are independent signal traces, the signals transmitted by the first signal trace 36 and the second signal trace 37 can be the same or different. For example, the first signal trace 36 transmits the first reset signal Vref1A, and the second signal trace 37 transmits the second reset signal Vref2A; or the first signal trace 36 transmits the first bias signal DVH1, and the second signal trace 37 transmits the second bias signal DVH2; or the first signal trace 36 transmits the first reset signal Vref1A, and the second signal trace 37 transmits the second anode reset signal Vref2B. When the second signal trace 37 is a signal trace that extends from the first signal trace 36 to the second pixel 12, it transmits the same signal.

[0090] Furthermore, when the second signal trace 37 is a signal trace extending from the first signal trace 36 to the second pixel 12, the end of the first signal trace 36 corresponding to each second pixel 12 that is closest to the third signal trace 40 is electrically connected to the third signal trace 40. This achieves series connection of multiple first signal traces 36 within the display panel 100, reduces the influence of the impedance of the first signal trace 36 itself on the transmitted signal, and improves the uniformity of the signal transmitted on the first signal trace 36, thereby further improving the display effect of the display panel 100. For example, when a reset signal is transmitted on the first signal trace 36, the uniformity of the reset signal transmitted on the first signal trace 36 can be improved, ensuring that the reset signal received by the pixel circuit in each pixel 10 is as consistent as possible, ultimately improving the display effect of the display panel.

[0091] When there is a gap between the first signal trace 36 and the second signal trace 37, and they are independent signal traces, the second signal trace 37 corresponding to each second pixel 12 is electrically connected to the third signal trace 40. This enables the series connection of multiple second signal traces 37 within the display panel 100, reduces the influence of the impedance of the second signal trace 37 itself on the transmitted signal, and improves the uniformity of the signal transmitted on the second signal trace 37, thereby further improving the display effect of the display panel. For example, when a bias signal is transmitted on the second signal trace 37, the uniformity of the bias signal transmitted on the second signal trace 37 can be improved, ensuring that the bias signal received by the pixel circuit in each pixel 10 is as consistent as possible, ultimately improving the display effect of the display panel.

[0092] Accordingly, this application also provides a display device. Referring to FIG9, FIG9 is a schematic diagram of the structure of a display device provided in this application embodiment. The display device 200 includes the display panel 100 described in the above embodiments of this application. The display device 200 includes an opening area A1, which is designed primarily for integrating and setting functional components. For example, the opening area A1 can be used to set a front-facing camera or other functional components. The display device 200 can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television.

[0093] The above provides a detailed description of a display panel and display device provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

[0094] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0095] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that elements inherent to a process, method, article, or apparatus that comprises a list of elements, or elements inherent to such processes, methods, articles, or apparatus, are also included. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0096] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, wherein, The display panel includes: pixels, an opening area, and a display area that at least partially surrounds the opening area; the pixels include a first pixel disposed away from the opening area and a second pixel disposed close to the opening area; The first pixel includes a first pixel circuit, the first pixel circuit includes a first transistor, the first transistor includes a first active layer and a first bottom gate and a first top gate located on both sides of the first active layer in a first direction; the first direction is perpendicular to the plane of the display panel. The second pixel includes a second pixel circuit, the second pixel circuit includes a second transistor, the second transistor includes a second active layer and a second bottom gate and a second top gate located on both sides of the second active layer in the first direction; both the first active layer and the second active layer are metal oxide active layers; The first pixel further includes a first signal trace, which is disposed on the same layer as the first top gate, and the orthographic projection of the first active layer on the substrate and the orthographic projection of the first signal trace on the substrate overlap in a second direction. The second pixel further includes a second signal trace, which is disposed on the same layer as the second top gate. The orthographic projection of the second active layer on the substrate and the orthographic projection of the second signal trace on the substrate overlap in the second direction. The second direction is parallel to the plane of the display panel and perpendicular to the length extension direction of the signal trace. The signal trace is either the first signal trace or the second signal trace.

2. The display panel of claim 1, wherein, The orthographic projection of the opening area in the first direction includes at least one arc-shaped line segment.

3. The display panel of claim 1, wherein, The second signal trace is the signal trace that extends from the first signal trace to the second pixel.

4. The display panel of claim 1, wherein, There is a gap between the first signal trace and the second signal trace.

5. The display panel of claim 4, wherein, The first signal trace transmits the same signal as the second signal trace.

6. The display panel of claim 3, wherein, The display panel further includes: a third signal trace disposed around the opening area; The end of the first signal trace corresponding to each second pixel that is close to the third signal trace is electrically connected to the third signal trace.

7. The display panel of claim 4 or 5, wherein, The display panel further includes: a third signal trace disposed around the opening area; The second signal trace corresponding to each second pixel is electrically connected to the third signal trace.

8. The display panel of claim 3, wherein, The first signal traces are connected in a grid pattern on the plane where the display panel is located.

9. The display panel of claim 4 or 5, wherein, The first signal traces are connected in a grid pattern on the plane where the display panel is located; And / or, the second signal traces are connected in a grid pattern on the plane where the display panel is located.

10. The display panel of claim 1, wherein, The first pixel circuit includes a first driving transistor, and the second pixel circuit includes a second driving transistor; The first transistor is a first reset transistor, and the second transistor is a second reset transistor; The first terminal of the first reset transistor receives a first reset signal, and the second terminal is electrically connected to the control terminal of the first drive transistor. The first terminal of the second reset transistor receives the second reset signal, and the second terminal is electrically connected to the control terminal of the second drive transistor.

11. The display panel of claim 10, wherein, The first terminal of the first reset transistor is electrically connected to the first signal trace, and the first reset signal is transmitted on the first signal trace; The first terminal of the second reset transistor is electrically connected to the second signal trace, and the second reset signal is transmitted on the second signal trace.

12. The display panel of claim 10, wherein, The first pixel further includes a first light-emitting element, and the second pixel further includes a second light-emitting element; The first pixel circuit further includes a first anode reset transistor, and the second pixel circuit further includes a second anode reset transistor; One end of the first driving transistor is electrically connected to the anode of the first light-emitting element, and one end of the second driving transistor is electrically connected to the anode of the second light-emitting element; The first terminal of the first anode reset transistor receives the first anode reset signal, and the second terminal is electrically connected to the anode of the first light-emitting element; The first terminal of the second anode reset transistor receives the second anode reset signal, and the second terminal is electrically connected to the anode of the second light-emitting element.

13. The display panel of claim 12, wherein, The first terminal of the first anode reset transistor is electrically connected to the first signal trace, and the first anode reset signal is transmitted on the first signal trace; The first terminal of the second anode reset transistor is electrically connected to the second signal trace, and the second anode reset signal is transmitted on the second signal trace.

14. The display panel of claim 10, wherein, The first pixel circuit further includes a first bias transistor, and the second pixel circuit further includes a second bias transistor; The first terminal of the first bias transistor receives a first bias signal, and the second terminal is electrically connected to one terminal of the first driving transistor. The first terminal of the second bias transistor receives the second bias signal, and the second terminal is electrically connected to one terminal of the second driving transistor.

15. The display panel of claim 14, wherein, The first terminal of the first bias transistor is electrically connected to the first signal trace, and the first bias signal is transmitted on the first signal trace; The first terminal of the second bias transistor is electrically connected to the second signal trace, and the second bias signal is transmitted on the second signal trace.

16. The display panel of claim 1, wherein, The active metal oxide layer is an IGZO active layer.

17. A display device, wherein, The display device includes the display panel as described in any one of claims 1-16.

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