Analog integrated circuit for bayesian classification of an electrical signal

Abstract

The invention relates to a Bayesian inference integrated circuit, referred to as a Bayesian circuit, for determining the probability of a signal S to be classified belonging to one of at least two behavior classes Ci, on the basis of at least one characteristic Fj of the signal S to be classified. The Bayesian circuit is based on spiking neurons.

Description

[0001] DESCRIPTION

[0002] Title of the invention: Analog integrated circuit for Bayesian classification of an electrical signal

[0003]

[0001] The present invention relates to the technical field of integrated circuits used for Bayesian classification of data resulting from physical measurements and, in a preferred but not exclusive application, to the field of integrated circuits used for the processing and classification of measurements of physiological quantities such as, for example, in the context of electroencephalograms.

[0004]

[0002] Over the past few decades, the rapid development of electronics, the Internet of Things (IoT), body networks (BAN), cloud computing, biocompatible materials and nanomaterials has led to the development of portable devices for monitoring and / or measuring physiological quantities, the processing and analysis of which is carried out by remote servers, cloud computing.

[0005]

[0003] Conventional health monitoring systems (e.g., a blood pressure monitor) are generally found in hospitals; they are bulky or fixed, so that it is often difficult or even impossible for the patients whose physiological quantities they measure to have a normal activity or an activity other than that related to therapeutic monitoring.

[0006]

[0004] To overcome this drawback, new portable and personal physiological monitoring devices are emerging. These devices generally comprise a wearable device or accessory, such as a watch, glasses, or a bracelet, which communicates wirelessly with a computing and processing unit that analyzes the data, usually using artificial intelligence algorithms. While such devices improve patient comfort, they have the disadvantages of, firstly, relatively high power consumption requiring regular recharging and, secondly, dependence on remote and separate physiological data processing and analysis units.

[0007]

[0005] A need has therefore arisen for new electronic devices or circuits for analyzing physical and, in particular, physiological quantities that overcome the aforementioned drawbacks, exhibit low or even very low power consumption, and are capable of analyzing measured physiological data without the need for external processing units.

[0006] To achieve these objectives, the invention relates to a Bayesian inference integrated circuit, referred to as a Bayesian circuit, for determining the probability of a signal to be classified S belonging to one of at least two behavioral classes Ci based on at least one characteristic Fj of the signal to be classified S, characterized in that the Bayesian circuit comprises:

[0008] - for each characteristic Fj, at least one input Ej receiving an electrical signal characteristic SFj representative of the characteristic Fj for the signal to be classified s,

[0009] - for each behavior class Ci: and for each characteristic Fj, a likelihood circuit receiving as input the characteristic electrical signal SFj and comprising a conversion circuit converting the characteristic signal SFj into another characteristic signal sFj converted on the basis of a distribution law of the characteristic Fj in relation to the behavior class Ci and a physical likelihood impulse neuron receiving the converted characteristic signal sFj and delivering an impulse electrical signal FjCi representative of the likelihood of the characteristic Fj belonging to the behavior class Ci,a physical impulse neuron with learned probability, whose input receives an electrical quantity Pi whose value is the result of prior learning and whose output delivers an impulse signal PCi representing the probability of the signal to be classified S belonging to the behavior class Ci resulting from prior learning; a stochastic computing circuit receiving as input the impulse signal PCi and each impulse signal FjCi and delivering as output an electrical signal SCi representing the probability of the signal S belonging to class Ci.

[0010] - a comparison circuit receiving each electrical signal SCi and delivering at output an electrical classification signal RCi corresponding to that of the classes Ci for which the signal to be classified S has the greatest probability of belonging.

[0011]

[0007] The integrated circuit according to the invention has the advantage of being simple in design while possessing advanced processing capabilities that enable analysis performance comparable to that obtained with purely software solutions running on microprocessor systems, and this with a much smaller number of elementary circuits. Thus, the invention allows for implementation in devices that can be incorporated into clothing or worn like clothing, and that exhibit low power consumption. These advantages stem in particular from the implementation of physical artificial neurons, that is to say, electronic artificial neurons, each consisting of a small number of transistors, as opposed to artificial neurons emulated by programs running on microprocessor units.

[0012]

[0008] In the context of the invention, physical impulse neurons deliver impulses according to a pattern whose frequency increases with the intensity of the input signal. This model is the most common neurocomputational characteristic and can be implemented by many known artificial neuron models. Among these, the Axon-Hillock circuit, originally proposed by C. Mead, can be mentioned and is considered one of the simplest and most optimal.

[0013]

[0009] The invention operates with "simple" electrical signals, current or voltage, without these being digitized, that is to say, converted into binary signals. For the purposes of the invention, an electrical signal is a signal carrying information in the form of voltage and / or current, that is to say, in which at least one of these two physical quantities varies over time. In the context of the invention, the term "voltage" is equivalent to "potential difference," while the term "current" is equivalent to "intensity."

[0014]

[0010] According to one feature of the invention, each likelihood circuit delivers a signal as a function of the probability of the input signal belonging to the corresponding behavior class, the probability being governed by a normal distribution law whose central value is defined by a normal voltage and a maximum voltage, and comprises a circuit, of the BUMP type, adapted to correlate two input voltages on the basis of a bias voltage of which a first input voltage corresponds to the normal voltage, a second input voltage is the corresponding characteristic signal SFj and a bias voltage is the maximum voltage and which delivers at the output a current constituting the converted characteristic signal sFj supplied to the likelihood impulse neuron.

[0015]

[0011] According to a variant of this feature, each BUMP-type voltage correlation circuit comprises: a first voltage input connected to a normal voltage source, a second voltage input connected to the second input terminal, - a first field-effect correlation transistor having first and second main terminals and a control terminal,

[0016] - a second field-effect correlation transistor having a first main terminal connected to the second main terminal of the first correlation transistor, a second main terminal connected to a supply voltage source, and a control terminal,

[0017] - a third field-effect correlation transistor having a first main terminal, a second main terminal connected to the supply voltage source, and a control terminal connected to the control terminal of the first correlation transistor,

[0018] - a fourth field-effect correlation transistor having a first main terminal, a second main terminal connected to the supply voltage source, and a control terminal connected to the control terminal of the second correlation transistor,

[0019] - a first field-effect input transistor having a first main terminal connected to the first main terminal and a control terminal of the third correlation transistor, a second main terminal connected to a common node, and a control terminal connected to the first voltage input node,

[0020] - a second field-effect input transistor having a first main terminal connected to the first main terminal and a control terminal of the fourth correlation transistor, a second main terminal connected to the common node, and a control terminal connected to the second input,

[0021] - a third field-effect input transistor having a first main terminal connected to the common node, a second main terminal connected to a supply voltage source and a control terminal connected to a source of the bias voltage as a function of the normal current.

[0022]

[0012] According to the invention, the signal to be classified is not necessarily an electrical signal, in which case it is implemented upstream of the circuit. According to the invention, means for converting the signal to be classified into an electrical signal are used. Such means may, for example, include sensors such as sensors for physiological quantities: heart rate, cerebral electrical activity, blood pressure, etc. In the context of the invention, the term "sensor" refers at a minimum to a transducer but also includes, where applicable, all the elements necessary for the operation of the transducer and for the delivery of the electrical signal representing the signal to be classified. In the context of the invention, the electrical signal representing the signal to be classified is an electrical signal that can be described as an analog signal, as opposed to a digital signal whose information is coded in binary or other form.At the stage of its supply to the circuit according to the invention, that is to say at its input, the signal is an electrical signal. Thus, in the context of the invention, the expressions "signal to be classified" and "electrical signal to be classified" are equivalent and may be used interchangeably.

[0023]

[0013] As previously stated, an analog electrical signal is defined by its voltage and / or its current, as well as by the possible variation of one or both of these quantities over time. It is therefore possible to analyze or study an analog signal by studying one or both of these quantities or their variation over time. In the context of this invention, this involves choosing a characteristic representative of the signal to be classified, bearing in mind that it is possible to choose or identify several characteristics representative of the same signal to be classified.

[0024]

[0014] Thus, according to a feature of the invention, the signal to be classified is an electrical signal and the integrated circuit according to the invention comprises upstream of an input Ej a feature extraction circuit which is connected to this input and which comprises at least one physical impulse neuron.

[0025]

[0015] According to a variant of this feature, the circuit according to the invention comprises, for at least one feature Fj, a feature extraction circuit which includes at least one physical impulse neuron whose input receives the signal to be classified S and whose output delivers an impulse signal consisting of a succession of impulses whose frequency and / or amplitude is a function of the signal to be classified, said impulse signal being supplied to an analog integrator circuit which delivers, at the output of the feature extraction circuit, the characteristic electrical signal SFj representative of the feature Fj for the signal to be classified S which is a function of either the amplitude of the impulse signal or the frequency of the impulse signal.

[0026]

[0016] It should be noted that a pulsed signal delivered by a physical pulsed neuron is considered within the scope of the invention to be an analog signal in that it is not encoded according to a binary or other conversion basis. Within the scope of the invention, the term "neuron" should be understood as meaning "artificial neuron." Similarly, the expression "physical artificial neuron" is equivalent to "electronic artificial neuron," namely an artificial neuron resulting from the assembly of elementary electronic circuits, as opposed to an artificial neuron emulated or simulated digitally by a computer program.

[0027]

[0017] According to one feature of the invention, each physical impulse neuron comprises:

[0028] - a current input,

[0029] - a voltage output,

[0030] - a first field-effect transistor having first and second main terminals and a control terminal connected to the voltage input, the first main terminal being connected to a supply voltage source,

[0031] - a second field-effect transistor having a first main terminal connected to the second main terminal of the first transistor, a second main terminal and a control terminal connected to the second main terminal of the first transistor,

[0032] - a third field-effect transistor having a first main terminal connected to the supply voltage source, a second main terminal, and a control terminal connected to the second main terminal of the first transistor,

[0033] - a fourth field-effect transistor having a first main terminal connected to the second main terminal of the third transistor, a second main terminal connected to the second main terminal of the second transistor and to a ground terminal, and a control terminal connected to the second terminal of the third transistor,

[0034] - a capacitor connected to the control terminal of the first transistor and to the second main terminal of the third transistor,

[0035] - a field-effect input transistor having a first main terminal connected to the correlation voltage input, a second main terminal connected to ground, and a control terminal connected to the second main terminal of the first transistor

[0036] - a first field-effect output transistor having a control terminal connected to the first main terminal of the fourth transistor, a first main terminal connected to the supply voltage source, and a second main terminal connected to the voltage output,

[0037] - a second field-effect output transistor having a first main terminal connected to the voltage output, a second main terminal connected to a common voltage terminal and a control terminal connected to the voltage output.

[0038]

[0018] According to another feature of the invention, the stochastic calculation circuit comprises at least one analog "AND" gate

[0039]

[0019] According to yet another feature of the invention, the stochastic calculation circuit comprises at least one MULLER C type circuit.

[0040]

[0020] According to one feature of the invention, the circuit according to the invention is clocked by a physical impulse neuron-based clock circuit. The use of one or more impulse neurons makes it possible to simply create a clock with low power consumption and thus avoids the need for a complex external system.

[0041]

[0021] Of course, the different features, variants and embodiments of the invention can be combined with each other in various ways insofar as they are not incompatible or mutually exclusive.

[0042]

[0022] Furthermore, various other features of the invention become apparent from the attached description made with reference to the drawings which illustrate non-limiting forms and examples of embodiments of Bayesian inference integrated circuits according to the invention or of constituent elements thereof and in which:

[0043] - Fig. 1 is a schematic representation of a system integrating a Bayesian circuit according to the invention,

[0044] - Fig. 2 is a schematic representation of an example of an embodiment of a Bayesian circuit according to the invention designed to ensure the determination of the class to which a signal to be classified belongs, which may belong to two classes of behavior, based on a single characteristic electrical signal.

[0045] - Fig. 3 is a schematic representation of the detail of an integrated electronic circuit, called a conversion circuit, according to the invention and configured to determine the position of a characteristic voltage of a signal to be classified within the framework of a normal distribution law governing the distribution of the value of this voltage for this signal, - Fig. 4 is a schematic representation of an integrated circuit constituting a physical impulse neuron according to the invention,

[0046] - Fig. 5 is a schematic representation of an example of the implementation of a stochastic calculation circuit implemented within the framework of a Bayesian circuit according to the invention.

[0047] - Fig. 6 is an electronic diagram of an integrated circuit corresponding to an embodiment of a Bayesian circuit according to the invention,

[0048] - Figures 7 to 11 are larger-scale electronic diagrams of blocks or circuits constituting the Bayesian circuit according to the invention illustrated in Figure 6,

[0049] - Fig. 12 is an electronic diagram of an integrated circuit corresponding to another embodiment of a circuit according to the invention.

[0050]

[0023] It should be noted that in these figures, the structural and / or functional elements common to the different variants or embodiments may have the same reference numerals. Furthermore, the electronic diagrams use the usual schematic representations and notations well known to those skilled in the art for active electronic components such as, in particular, field-effect transistors, current and voltage sources, and passive electronic components such as capacitors and resistors, without these lists being exhaustive or limiting.

[0051]

[0024] Thus, the symbols "MP" and "MN" used in the diagrams designate, respectively, a P-channel and an N-channel field-effect transistor, without any restriction being imposed as to the nature or technology of the electronics implemented. The circuit according to the invention can therefore be implemented using any suitable analog transistor technology, including but not limited to: MOS, PMOS, NMOS, TFT, OFET, OECT, or any equivalent technology providing the same electronic functions. The logic and architecture of the circuit remain identical, regardless of the implementation technology used.

[0052]

[0025] The invention therefore relates to a Bayesian inference integrated circuit, referred to as a Bayesian circuit, for determining the probability of a signal to be classified belonging to one of at least two behavioral classes. Such a circuit is based on Bayesian classification, namely a statistical approach based on Bayesian inference, so named after the work of Thomas Bayes and well known to specialists in statistical and probabilistic calculations and their implementation. Within the framework of Bayesian inference and the present invention, probability expresses a degree of belief in class membership based on prior knowledge resulting from prior knowledge and observed data used to make the classification decision.

[0053]

[0026] In general the invention is based on a simplified version of Bayes' formula.

[0054]

[0027] Bayes' rule is mathematically expressed in the form of the following equation:

[0055]

[0029] Where P(H) represents the prior probability of hypothesis H before considering the observations E. P(E / H) is the probability of observing E, given H, and is known as the likelihood. P(H / E) is the object of Bayes' theorem, called posterior probability, namely the probability of a hypothesis given the observed evidence. The term P(E'), sometimes called "model proof," is the same for all hypotheses and is often omitted to simplify the calculation. In this case, the observed evidence consists of a set of features extracted from the original data and the hypothesis of a potential category. If features are available, we can write: Fc m n

[0056]

[0030] P(c m | , ..., / oc P(c m ) x P( / i, ... , n |c m) (2)

[0057]

[0031] If all features are assumed to be conditionally independent, this method is known as naive Bayesian. The joint likelihood of the features can be simplified to the product of the probabilities of each feature:

[0058]

[0032] P(c m I, ..., n ) oc P(c m ~) X n? =1 ^( / i m (3)

[0059]

[0033] The Bayesian circuit BC according to the invention is generally implemented within a system as illustrated in Figure 1 and designated as a whole by reference numeral 1, in which the operation of a controller A is controlled according to the class C of a signal S determined by said Bayesian circuit BC. The controller A is capable of performing any type of processing such as displaying information, triggering the operation of an external system, or modifying the operation of such a system, without this list being exhaustive or limiting. It should be noted that the controller A is not part of the present invention and is mentioned for informational purposes only.

[0034] The signal to be classified S is generally acquired by one or more sensors, according to the illustrated example, two sensors 2 and 3, each of which delivers an electrical signal constituting the electrical signal to be classified Se.This electrical signal Se is the image of the signal to be classified S. In the present case the electrical signal Se is multichannel and includes two channels, it being understood that the electrical signal to be classified may include only one channel or even more than two channels.

[0060]

[0035] In order to classify the electrical signal Se and thus the signal S, it is necessary to determine at least one characteristic Fj of the electrical signal Sj on the basis of which the classification is performed. To this end, the system includes a preprocessing block PB whose function is to extract at least one characteristic translated into a characteristic electrical signal SFj, which will be supplied as input to the Bayesian circuit BC and processed by the latter. In the remainder of this document, j corresponds to the number of the characteristic of the signal to be classified.

[0061]

[0036] Thus, the preprocessing block PB includes at least one feature extraction circuit Fi, an example of which will be detailed later. Generally speaking, it can already be specified that the preprocessing block may include different types of feature extraction circuits Fj capable of delivering a characteristic electrical signal SFj compatible with a Bayesian circuit BC according to the invention.

[0062]

[0037] For the purposes of this invention, a characteristic of the signal S may be the signal itself when this signal is an electrical signal, the value of one of the physical quantities that characterize it, or the result of analog preprocessing performed on this signal. Thus, among the preprocessing techniques that may be implemented, one can cite filtering using a high-pass or low-pass filter to eliminate noise or artifacts. One can also cite the implementation of a fast Fourier transform or a continuous wavelet transform.

[0063]

[0038] In a preferred embodiment of the invention, preprocessing is performed by means of a circuit comprising a pulsed artificial neuron that converts the signal to be classified S into a pulsed signal whose pulse nature, frequency and / or value, varies according to the signal to be classified supplied as input to the pulsed artificial neuron. An embodiment of a pulsed neuron according to the invention is detailed later in the description.

[0039] The result of the conversion of the signal to be classified into a pulse train by a pulsed artificial neuron is then stored in a capacitor, and the voltage across this capacitor is then used as the characteristic electrical signal SFj supplied to the Bayesian circuit according to the invention.Indeed, the inventors have demonstrated that the nature of the pulse trains and the result of their accumulation in the capacitor are representative of the class to which the signal to be classified belongs, so that the voltage across the capacitor can be used as a characteristic electrical signal SFj, representative of the characteristic Fj of the signal to be classified. Thus, preferably, the characteristic signal SFj is a voltage.

[0064]

[0040] This characteristic signal SFj is therefore supplied to the Bayesian circuit BC according to the invention. According to the invention, the number of characteristic signals to the Bayesian circuit is at least equal to one, while not being limited in number.

[0065]

[0041] In order to simplify the description, the example embodiment of the Bayesian circuit BC according to the invention illustrated in figure 2 is designed to ensure the processing of a single characteristic electrical signal SFj which may belong to two classes of behavior Ci, thus a class Cl and a class C2.

[0066]

[0042] In the remainder of this document, i corresponds to a class number, while, as previously stated, j corresponds to a characteristic, or signal, number to be classified. Thus, for example, in the case of two possible class numbers, i can take the values ​​1 and 2, and in the case of two characteristic signals, j can also take the values ​​1 and 2.

[0067]

[0043] Thus, the Bayesian circuit BC comprises, for each Class Ci and each characteristic signal SFj, an elementary Bayesian block BBij whose function is to output, for a characteristic signal SFj received at the input Ej, an electrical signal SCi representing the probability of belonging of the characteristic electrical signal SFj, and therefore of the signal to be classified, to the corresponding class Ci. Each SCi signal is then fed to a comparison circuit CC which outputs a classification electrical signal RCi corresponding to the class, in this case the one of the two classes Ci for which the signal to be classified has the highest probability of belonging.

[0068]

[0044] According to the invention, each elementary Bayesian block BBi comprises a learned probability circuit PCi and, for each characteristic signal SFj, a likelihood circuit LCij, which feed in parallel into a stochastic computation circuit SCi that calculates and delivers the signal SCi to the comparison circuit CC. In the context of the invention, "learned probability" is synonymous with the English term "prior" in the field of probability.

[0069]

[0045] According to the invention, each likelihood circuit LCij comprises first of all a conversion circuit LCC which converts the characteristic signal SFj into another converted characteristic signal sFj on the basis of a distribution law of the characteristic Fj in relation to the behavior class Ci.

[0070]

[0046] In the present case and according to the example illustrated in figure 3, the LCC conversion circuit is configured to deliver the converted signal sFj with the assumption that the characteristic signal responds to a normal distribution law also called Gaussian type defined by the position of its central value and the amplitude or height of this central value.

[0071]

[0047] Thus, according to the example illustrated in Fig. 3, the LCC circuit includes a BUMP-type circuit adapted to correlate an input voltage Vin with a reference voltage V2 based on a bias voltage Vb. Within the framework of the invention, the reference voltage V2 defines the position of the normal value of the Gaussian distribution, and the bias voltage defines the absolute value of the normal value. Furthermore, the characteristic signal SFj is here a voltage, and the BUMP circuit outputs the converted signal sFj, which in this case is a current.

[0072]

[0048] It must therefore be understood that the voltages Vd and V2 are predefined and provided to the Bayesian circuit as fixed extrinsic data allowing it to be parameterized to the application for which it is designed.

[0073]

[0049] Figure 3 illustrates an example of an integrated circuit with all its components enabling the implementation of the aforementioned BUMP circuit. Figure 3 implements the representation standards well known to those skilled in the art, electronics engineers designing integrated circuits. To avoid any confusion, it should be noted that Vdd or VDD and Vss or VSS are supply voltages of the circuit or supply voltage sources and have substantially constant values. These values ​​are supplied to all the circuits and components constituting the Bayesian circuit according to the invention. For the record, in Figure 3, as well as in other figures corresponding to electronic circuit diagrams, the notations V represent voltages, while the notations / represent currents.

[0050] Figure 3 shows that the LCC conversion circuit comprises:

[0074] - a first voltage input which is connected to a source of normal voltage V2,

[0075] - a second voltage input Vin receiving Ej,

[0076] - a first P3 field-effect correlation transistor having first and second main terminals and a control terminal, the second main terminal delivering the converted characteristic signal sFj

[0077] - a second field-effect correlation transistor P4 having a first main terminal connected to the second main terminal of the first correlation transistor P3, a second main terminal connected to a supply voltage source VDD, and a control terminal,

[0078] - a third PI field-effect correlation transistor having a first main terminal, a second main terminal connected to the supply voltage source VDD, and a control terminal connected to the control terminal of the first correlation transistor P3,

[0079] - a fourth field-effect correlation transistor P2 having a first main terminal, a second main terminal connected to the supply voltage source VDD, and a control terminal connected to the control terminal of the second correlation transistor P4,

[0080] - a first input field-effect transistor M2 having a first main terminal connected to the first main terminal of the third transistor PI and a control terminal of the first correlation transistor P3, a second main terminal connected to a common node, and a control terminal Vin receiving the characteristic signal SFj and connected to the input Ej,

[0081] - a second input field-effect transistor M3 having a first main terminal connected to a main terminal of the first P3 and fourth transistor P2 and a control terminal of the fourth correlation transistor P2, a second main terminal connected to the common node, and a control terminal receiving the reference voltage V2,

[0082] - a third input field-effect transistor Ml having a first main terminal connected to the common node, a second main terminal connected to a supply voltage source VSS, and a control terminal connected to a maximum voltage source Vb.

[0051] The LCC conversion circuit delivers the converted characteristic signal sFj to a physical likelihood impulse neuron LIN, which delivers an impulse signal FjCi representative of the likelihood of the characteristic Fj belonging to the behavior class Ci. Due to its upstream position of the LIN neuron and its linking function between the preprocessing circuit and the physical likelihood impulse neuron, the LCC conversion circuit can be described as an electronic synapse.

[0083]

[0052] Within the scope of the invention, a pulse neuron IN generally comprises, as shown in Figure 4:

[0084] - a 10 current input

[0085] - a voltage output 11,

[0086] - a first MP18 field-effect transistor having first and second main terminals and a control terminal connected to the voltage input, the first main terminal being connected to a supply voltage source,

[0087] - a second MP19 field-effect transistor having a first main terminal connected to the second main terminal of the first transistor, a second main terminal and a control terminal connected to the second main terminal of the first transistor,

[0088] - a third MP20 field-effect transistor having a first main terminal connected to the supply voltage source VDD, a second main terminal, and a control terminal connected to the second main terminal of the first transistor,

[0089] - a fourth field-effect transistor MP21 having a first main terminal connected to the second main terminal of the third transistor, a second main terminal connected to the second main terminal of the second transistor and to a ground terminal 12, and a control terminal connected to the second terminal of the third transistor MP20,

[0090] - a CF3 capacitor connected to the control terminal of the first transistor and to the second main terminal of the third transistor,

[0091] - an input field-effect transistor MP17 having a first main terminal connected to the correlation voltage input, a second main terminal connected to ground, and a control terminal connected to the second main terminal of the first transistor; - a first output field-effect transistor MP22 having a control terminal connected to the first main terminal of the fourth transistor, a first main terminal connected to the supply voltage source VDD, and a second main terminal connected to the voltage output 11.

[0092] - a second MP23 field-effect output transistor having a first main terminal connected to the voltage output 11, a second main terminal connected to another supply voltage source and a control terminal connected to the voltage output 11.

[0093]

[0053] In the context of the implementation of such an impulse neuron IN to constitute the likelihood impulse neuron LIN, the input 10 receives the sFj and the output 11 delivers the impulse signal FjCi.

[0094]

[0054] Each elementary Bayesian block BBi comprises, in parallel with the likelihood circuit LCij, the learned probability circuit PCi, as illustrated in Figure 8, which, according to the invention, consists of a physical impulse neuron, referred to as a learned probability neuron. It should be noted that the learned probability block can, for the same class, be common to several elementary Bayesian blocks. Within the learned probability circuit PCi, the input 10 of the impulse neuron receives, as an electrical quantity Pi, a current whose intensity is the result of learning or a statistical study of the impulse typology for signals belonging to the corresponding behavior class.

[0095]

[0055] Thus, the quantity Pi is predefined and provided to the Bayesian circuit BC as a fixed extrinsic data point, allowing it to be parameterized for the application for which it is designed, in the same way as the voltages Vd and V2. A Bayesian circuit according to the invention will therefore include as many inputs for the quantities Pi, Vd, and V2 as the number resulting from multiplying the number of classes to which the signal to be classified is likely to belong by the number of features implemented to classify the signal S. In the case of the example in Figure 2, whose objective is to classify the signal S, which is likely to belong to two classes, based on a single characteristic signal SFj, the Bayesian circuit therefore includes two inputs or input terminals for two Pi signals, two inputs for the two voltages Vd, and two inputs for the voltages V2.Within the scope of the invention, the term "input" is equivalent to the expression "input terminal" and they are used interchangeably.

[0056] Each elementary Bayesian circuit comprises, downstream of the physical impulse neuron of learned probability PC and the likelihood circuit, the stochastic computation circuit SC which receives the impulse signals PCi and FjCi from the PC circuit and the LC circuit, respectively.

[0096]

[0057] According to the invention, the stochastic calculation circuit can be implemented in any suitable manner, such as, for example, in the form of an analog "AND" type circuit supplying a capacitor. The voltage across this capacitor then corresponds to the electrical signal SCi representing the probability of the signal S belonging to the corresponding class Ci.

[0097]

[0058] According to the example shown in Fig. 5, two transistors in series are implemented as an analog AND gate to multiply two voltage signals PCi and FjCi, converting the result into a current signal (intensity) which is then collected by a capacitor that acts as an analog counter.

[0098]

[0059] When both inputs are in a high state, i.e., 0V (due to their connection to the PMOS transistors), the analog AND gate generates a current that charges the capacitor, causing its voltage to rise. In other cases, the capacitor remains practically uncharged. In contrast, digital binary streams perform AND operations at the bit level, producing only two possible outcomes for each bit: 0 or 1. However, when time-coded asynchronous streams perform AND operations, the results involve a variable analog duration for each high state. This can increase stochasticity and improve performance.

[0099]

[0060] The relationship between the high-state time of the current flow (or the product value) and the capacitor voltage is monotonic: a higher voltage corresponds to a longer high-state duration and a higher product value. This characteristic is sufficient for classification tasks.

[0100]

[0061] The Bayesian circuit according to the invention finally comprises a CC comparison circuit which receives as input all the SCi signals and outputs the one with the highest value. This type of comparison circuit is known in English as a "winner takes all" circuit, a term well understood by those skilled in the art.

[0101]

[0062] System i and its various components can be implemented for various applications such as, for example, a portable device for studying a user's sleep cycle.

[0063] According to the embodiment described above, the likelihood circuit implements a BUMP-type circuit. However, other types of electronic circuits can be used to implement the likelihood circuit and deliver the corresponding electrical signal to the artificial neuron LIN. It is also possible to combine several BUMP-type circuits to implement the likelihood circuit. The advantage of the invention compared to the prior art is the use of an analog integrated circuit to determine the likelihood and then the probability, whereas digital computing circuits are usually implemented.

[0102]

[0064] It should be noted that, according to the invention, the likelihood function implemented by the LCC likelihood circuit does not necessarily reproduce the entirety of the considered probability distribution law, such as, for example, a complete Gaussian distribution. In some cases, the circuit may implement only a portion or segment of this distribution, corresponding to the region of variation of the characteristic signals that allow discrimination between different classes Ci. This partial implementation of the distribution is then sufficient to deliver a distinctive likelihood signal while simplifying the circuit structure and reducing power consumption and / or the integration area.

[0103]

[0065] According to the example illustrated in Figure 5, the stochastic computing circuit uses two transistors to perform the multiplication of two signals representing probabilities. To multiply several probabilities, additional transistors can be connected in series to perform the operation simultaneously. This generally gives smaller results, and as the final result becomes smaller, the time required to obtain a reliable result across the capacitor increases.

[0104]

[0066] In another embodiment, the Bayesian inference integrated circuit BC according to the invention implements the architecture as illustrated in Fig. 6. According to this example, the circuit is designed to classify a physiological state represented by two characteristic signals SF1 and SF2 (j= 1 or 2) corresponding to physiological measurements according to two behavior classes Cl and C2 (i= 1 or 2).

[0105]

[0067] To this end, the BC circuit includes, for class Cl (i= 1), an elementary Bayesian block BB1 which comprises two likelihood circuits LC11 and LC12 processing, respectively, the characteristic signal SF1 (j=1) and the characteristic signal SF2 (j=2). The elementary Bayesian block BB1 also includes, for class Cl (i= 1), a learned probability circuit PCI and a stochastic computation circuit SCI which receives the outputs of the likelihood circuits LC11 and LC12 and of the learned probability circuit PCI.

[0106]

[0068] Similarly, the BC circuit includes, for class C2 (i=1), an elementary Bayesian block BB2 which comprises two likelihood circuits LC21 and LC22 processing, respectively, the characteristic signal SF1 (j=1) and the characteristic signal SF2 (j=2). The elementary Bayesian block BB2 also includes, for class C2 (i=2), a learned probability circuit PC2 and a stochastic calculation circuit SC2 which receives the outputs of the likelihood circuits LC21 and LC2 and of the learned probability circuit PC2.

[0107]

[0069] The stochastic calculation circuits SCI and SC2 are then connected to a comparison circuit CC as mentioned in the previous example.

[0108]

[0070] The circuit further includes a clock circuit HC which synchronizes the operation of the entire Bayesian circuit BC.

[0109]

[0071] According to this embodiment, the likelihood circuits LCij, the learned probability circuits PCi, the stochastic calculation circuits BCi and the clock circuit HC all comprise a pulse neuron whose circuit is shown in Fig. 7. Each neuronal circuit is here realized as an axon-hillock type pulse neuron, constructed with five field-effect transistors and a capacitor which accumulates current until it reaches a threshold, producing time-coded voltage pulses.

[0110]

[0072] As shown in Fig. 8, and according to this embodiment, each learned probability circuit BCi comprises only a physical, pulsed artificial neuron whose control voltage lEXi is determined during the learning phase. The neuron's firing frequency is proportional to the input current lEXi, generating stochastic fluxes whose activity cycle encodes the corresponding learned probability.

[0111]

[0073] According to the embodiment of Fig. 6, each likelihood circuit LCij comprises, as shown in Fig. 9, firstly the LCC conversion circuit whose output is connected to the physical likelihood impulse neuron LIN. The LCC conversion circuit is a Gaussian-type synaptic circuit comprising a differential pair and a current correlator, producing a bell-shaped output current as a function of the input voltage. The height, width, and center of the Gaussian curve are independently adjustable via three biasing parameters (IBij, VCij, VRij), allowing the encoding of arbitrary Gaussian distributions.

[0112]

[0074] According to the embodiment shown in Fig. 6, each stochastic calculation circuit SCi performs a stochastic multiplication between the likelihood probabilities and the learned probabilities. To this end, each circuit SCi comprises, as shown in Fig. 10, an analog AND logic gate composed of PMOS transistors connected in series, which receives as input the outputs of the corresponding circuits LCij and PCi, as well as a first bias current Vbias, and whose output is connected to a decision neuron DNi (DN1 or DN2), which also receives a second bias current Vbias'.The decision neuron: When the AND gate inputs are high, a current proportional to the product of the probabilities flows and charges the capacitor of neuron DNi, producing a voltage representing the probability of belonging to the non-normalized class i. This voltage is integrated by neuron DNi and drives its discharge. The first bias voltage Vbias and the second bias voltage Bbias' allow adjustment of the speed and accuracy of the integration performed by the stochastic computing circuit SCi.

[0113]

[0075] Thus, within the framework of the operation of the BC circuit in Fig. 6, the DNI or DN2 neuron that discharges first indicates the class for which the probability of belonging of the signal to be classified is the highest.

[0114]

[0076] Finally, the clock circuit HC formed by a pulse neuron, as shown in Fig. 11, acts as a time switch to automatically reset the circuit after each inference cycle, thus eliminating the need for an external clock. The discharge time of the clock circuit HC, i.e., the cycle time of the BC circuit, is then controlled by the value of the supply current IC of the pulse neuron constituting the HC circuit.

[0115]

[0077] The complete classifier as formed by the circuit in Fig. 6 uses approximately 100 transistors and operates entirely in the analog domain without digital conversion and achieves reliable Gaussian classification with a total power consumption of less than 1 microW.

[0116]

[0078] Fig. 12 illustrates another example of an embodiment of a circuit according to the invention which, by means of the preprocessing block PB, extracts a characteristic SF1 from a pure SI signal and performs its classification into two classes by means of the circuit BC according to the invention. In this example, i = 1 or 2 and j = 1.

[0117]

[0079] According to this example, a clock circuit HC is also implemented, comprising three cascaded neural circuits generating ordered time signals (CLK1, CLK2, CLK3) that synchronize the extraction phase performed by PB, the classification phase performed by BC, and the reset phase. The intensity of the input current to the first neuron determines the classification frequency.

[0118]

[0080] As mentioned above, the preprocessing circuit PB is a circuit for extracting a characteristic Fl from the signal to be classified SI. According to this embodiment, the PB circuit comprises a physical impulse neuron whose input receives the signal to be classified SI and whose output delivers an impulse signal consisting of a succession of impulses, said impulse signal being supplied to an analog integrator circuit which delivers, at the output of the characteristic extraction circuit, the characteristic electrical signal SF1 representing the characteristic Fl.

[0119]

[0081] In summary and as can be seen from reading Fig. 12, the feature extraction module receives an analog input signal in the form of a current, integrates it on a capacitor in order to encode the discharge frequency information in the form of a characteristic voltage (VF), then transfers this voltage to a capacitor of lower capacitance for the classification phase.

[0120]

[0082] In the present case, the Bayesian circuit BC comprises, for class Cl (i= 1), an elementary Bayesian block BB1 which includes a likelihood circuit LC11 processing the characteristic signal SF1 (j=l). The elementary Bayesian block BB1 also comprises, for class Cl (i= 1), a learned probability circuit PCI and a stochastic computation circuit SCI which receives the output of the likelihood circuit LC11 and the learned probability circuit PCI.

[0121]

[0083] Similarly, the BC circuit includes, for class C2 (i=1), an elementary Bayesian block BB2 which includes a likelihood circuit LC21 processing the characteristic signal SF1 (j=l). The elementary Bayesian block BB2 also includes, for class C2 (i=2), a learned probability circuit PC2 and a stochastic calculation circuit SC2 which receives the output of the likelihood circuit LC21 and the learned probability circuit PC2.

[0122]

[0084] The SCI and SC2 outputs of the SCI and SC2 stochastic computing circuits are processed by the CC comparison circuit, which, according to this embodiment, comprises two decision neurons forming a winner-take-all (WTA) type circuit. When a decision neuron reaches its threshold, it discharges the capacitor of its competitor and deactivates the upstream neurons via a feedback sub-module, in order to reduce energy consumption.

[0123]

[0085] The entire system, as illustrated in Fig. 12, integrates approximately 150 transistors and performs the classification in less than 2 milliseconds with a consumption of less than one microwatt.

[0124]

[0086] Of course, various modifications can be made to the examples described above within the framework of the annexed claims.

Claims

22 DEMANDS 1. Bayesian inference integrated circuit, called a Bayesian circuit, for determining the probability of a signal to be classified S belonging to one of at least two behavior classes Ci based on at least one characteristic Fj of the signal to be classified S, characterized in that the Bayesian circuit comprises: - for each characteristic Fj, at least one input Ej receiving a characteristic electrical signal SFj representative of the characteristic Fj for the signal to be classified s, for each behavior class Ci: - and for each characteristic Fj, a likelihood circuit receiving as input the characteristic electrical signal SFj and comprising a conversion circuit converting the characteristic signal SFj into another characteristic signal sFj converted on the basis of a distribution law of the characteristic Fj in relation to the behavior class Ci and a physical likelihood impulse neuron receiving the converted characteristic signal sFj and delivering an impulse electrical signal FjCi representative of the likelihood of the characteristic Fj belonging to the behavior class Ci, - a physical impulse neuron with learned probability, one input of which receives an electrical quantity Pi whose value is the result of prior learning, and one output of which delivers an impulse signal PCi representing the probability of the signal to be classified S belonging to the behavior class Ci resulting from prior learning, - a stochastic computing circuit receiving as input the impulse signal PCi and each impulse signal FjCi and delivering as output an electrical signal SCi representative of the probability of the signal S belonging to class Ci, - a comparison circuit receiving each electrical signal SCi and delivering at output an electrical classification signal RCi corresponding to that of the classes Ci for which the signal to be classified S has the greatest probability of belonging.

2. An integrated circuit according to claim 1, characterized in that each likelihood circuit delivers a signal that is a function of the probability of the input signal belonging to the corresponding behavior class, the probability being governed by a normal distribution law whose central value is defined by a normal voltage and a maximum voltage, and comprising a BUMP-type circuit adapted to correlate two input voltages based on a bias voltage where a first input voltage corresponds to the normal voltage, a second input voltage is the corresponding characteristic signal SFj and the bias voltage corresponds to the maximum voltage and which delivers at the output a current constituting the converted characteristic signal sFj supplied to the likelihood impulse neuron.

3. Integrated circuit according to claim 2, characterized in that each BUMP-type voltage correlation circuit comprises: - a first voltage input which is connected to a source of normal voltage, - a second voltage input, - a first field-effect correlation transistor having first and second main terminals and a control terminal, - a second field-effect correlation transistor having a first main terminal connected to the second main terminal of the first correlation transistor, a second main terminal connected to a supply voltage source, and a control terminal, - a third field-effect correlation transistor having a first main terminal, a second main terminal connected to the supply voltage source, and a control terminal connected to the control terminal of the first correlation transistor, - a fourth field-effect correlation transistor having a first main terminal, a second main terminal connected to the supply voltage source, and a control terminal connected to the control terminal of the second correlation transistor, - a first field-effect input transistor having a first main terminal connected to the first main terminal and a control terminal of the third correlation transistor, a second main terminal connected to a common node, and a control terminal connected to the first voltage input node, - a second field-effect input transistor having a first main terminal connected to the first main terminal and a control terminal of the fourth correlation transistor, a second main terminal connected to the common node, and a control terminal connected to the second input, - a third field-effect input transistor having a first main terminal connected to the common node, a second main terminal connected to a supply voltage source and a control terminal connected to a source of the bias voltage as a function of the normal current.

4. Integrated circuit according to any one of the preceding claims characterized in that the signal to be classified is an electrical signal and that it further comprises, for at least one characteristic Fj, a characteristic extraction circuit which includes at least one physical impulse neuron whose input receives the signal to be classified S and whose output delivers an impulse signal consisting of a succession of impulses whose frequency and / or amplitude is a function of the signal to be classified, said impulse signal being supplied to an analog integrator circuit which delivers, at the output of the characteristic extraction circuit, the characteristic electrical signal SFj representative of the characteristic Fj for the signal to be classified S which is a function of either the amplitude of the impulse signal or the frequency of the impulse signal.

5. Integrated circuit according to any one of the preceding claims, characterized in that each physical impulse neuron comprises: - a current input, - a voltage output, - a first field-effect transistor (MP18) having first and second main terminals and a control terminal connected to the voltage input, the first main terminal being connected to a supply voltage source, - a second field-effect transistor (MP19) having a first main terminal connected to the second main terminal of the first transistor, a second main terminal and a control terminal connected to the second main terminal of the first transistor, - a third field-effect transistor (MP20) having a first main terminal connected to the supply voltage source, a second main terminal, and a control terminal connected to the second main terminal of the first transistor, - a fourth field-effect transistor (MP21) having a first main terminal connected to the second main terminal of the third transistor, a second main terminal connected to the second main terminal of the second transistor and to a 25 ground terminal, and a control terminal connected to the second terminal of the third transistor, - a capacitor (CF3) connected to the control terminal of the first transistor and to the second main terminal of the third transistor, - a field-effect input transistor (MP17) having a first main terminal connected to the correlation voltage input, a second main terminal connected to ground, and a control terminal connected to the second main terminal of the first transistor - a first field-effect output transistor (MP22) having a control terminal connected to the first main terminal of the fourth transistor, a first main terminal connected to the supply voltage source and a second main terminal connected to the voltage output, - a second field-effect output transistor (MP23) having a first main terminal connected to the voltage output, a second main terminal connected to the common voltage terminal and a control terminal connected to the voltage output.

6. An integrated circuit according to any one of the preceding claims, characterized in that the stochastic calculation circuit comprises at least one analog AND gate 7. Integrated circuit according to any one of claims 1 to 6, characterized in that the stochastic calculation circuit comprises at least one MULLER C-type circuit 8. Integrated circuit according to claims 1 to 7, characterized in that it comprises upstream of an input Ej a characteristic extraction circuit which is connected to this input and which comprises at least one physical impulse neuron.

9. Integrated circuit according to any one of claims 1 to 8, characterized in that it is clocked by a physical impulse neuron-based clock circuit.

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