Imaging device and imaging method

Abstract

[Problem] To enable uniform characteristics of pixels. [Solution] The present disclosure provides an imaging device comprising: a pixel array unit having pixels each including at least a photoelectric conversion element that generates charge by photoelectric conversion and a discharge transistor that generates a potential barrier between a voltage source (and the photoelectric conversion element; and a signal processing unit that, on the basis of a first measurement signal value corresponding to a first accumulated charge that is accumulated when a first potential barrier corresponding to a first potential is generated, estimates a second measurement signal value corresponding to a second accumulated charge that is accumulated when a second potential barrier corresponding to a second potential is generated.

Description

Imaging device and imaging method

[0001] This disclosure relates to an imaging device and an imaging method.

[0002] PWLR (Piecewise Linear Response) imaging devices are generally known, which expand the dynamic range by gradually changing the applied potential to accumulate charge through photoelectric conversion and gradually releasing the saturated charge (see, for example, Patent Document 1).

[0003] Japanese Patent Publication No. 2020-068501

[0004] However, differences in pixel characteristics may cause variations in the amount of charge emitted by applying potentials in stages.

[0005] Therefore, this disclosure provides an imaging device and an imaging method that enable the homogenization of pixel characteristics.

[0006] To solve the above problems, the present disclosure provides an imaging device comprising: a pixel array section having pixels that include at least a photoelectric conversion element that generates an electric charge by photoelectric conversion and an emission transistor that generates a potential barrier between a voltage source and the photoelectric conversion element; and a signal processing section that estimates a second measurement signal value corresponding to a second accumulated charge accumulated when a second potential barrier is generated corresponding to a second potential, based on a first measurement signal value corresponding to a first accumulated charge accumulated when a first potential barrier is generated corresponding to a first potential.

[0007] The system may further include a control unit that generates a third potential barrier, which is higher than the height of the second potential barrier, at a predetermined time after a first point in time when the second potential barrier is generated.

[0008] The signal processing unit may generate the pixel signal of the pixel based on a value obtained by subtracting the estimated second measurement signal value from a third measurement signal value corresponding to the accumulated charge at a predetermined time after the third potential barrier has been generated.

[0009] The signal processing unit may further estimate a fourth measurement signal value corresponding to the fourth potential, which corresponds to the fourth accumulated charge accumulated when a fourth potential barrier is generated that is higher than the second potential barrier and lower than the third potential barrier, based on the first measurement signal value.

[0010] The signal processing unit may generate the pixel signal of the pixel based on the value obtained by subtracting the fourth measurement signal value from the third measurement signal value.

[0011] The signal processing unit may estimate the second measurement signal value based on a first difference between the first measurement signal value and the first reference value.

[0012] The signal processing unit may estimate the second measured signal value based on the first difference value and the first power.

[0013] The signal processing unit may estimate the fourth measured signal value based on the first difference value and the second square.

[0014] The signal processing unit may determine, based on the accumulated charge, whether or not charge has accumulated beyond either the second potential barrier or the fourth potential barrier.

[0015] If the signal processing unit determines that charge has accumulated beyond the second potential barrier, it may generate a pixel signal for the pixel based on a value obtained by subtracting the second measurement signal value estimated from the third measurement signal value.

[0016] The signal processing unit may, when it determines that charge has accumulated beyond the fourth potential barrier, generate a pixel signal for the pixel based on a value obtained by subtracting the fourth measurement signal value estimated from the third measurement signal value.

[0017] The control unit may inject the first stored charge from the voltage source via the discharge transistor.

[0018] The pixel may include: a first transfer transistor connected to the photoelectric conversion element; a first storage unit connected to the photoelectric conversion element via the first transfer transistor; a second transfer transistor connected to the first storage unit; a third transfer transistor connected to the photoelectric conversion element; a second storage unit connected to the photoelectric conversion element via the third transfer transistor; a fourth transfer transistor connected to the second storage unit; and a floating diffusion layer connected to the first storage unit via the second transfer transistor and to the second storage unit via the fourth transfer transistor, which generates a voltage corresponding to the amount of stored charge.

[0019] The system may further include a column signal processing unit that converts the potential of the suspended diffusion layer into a digital measurement value.

[0020] The control unit may sequentially generate the second potential barrier, the fourth potential barrier, and the third potential barrier, and store the accumulated charge, which has been photoelectrically converted by the photoelectric conversion element, in the first storage unit via the second transfer transistor.

[0021] The control unit may store the first stored charge in the second storage unit via the preceding third transfer transistor.

[0022] The control unit may transfer the accumulated charge and the first accumulated charge to the floating diffusion layer in any order, and have the column signal processing unit convert either the first measurement signal value or the third measurement signal value into the sum of the first measurement signal value and the third measurement signal value. The signal processing unit may then generate the first measurement signal value and the third measurement signal value based on the converted either the first measurement signal value or the third measurement signal value and the sum of the first measurement signal value and the third measurement signal value.

[0023] To solve the above problems, the present disclosure provides an imaging method for an imaging apparatus having a pixel array section having at least a photoelectric conversion element that generates an electric charge by photoelectric conversion and an emission transistor that generates a potential barrier between a voltage source and the photoelectric conversion element, the imaging method comprising a signal processing step of estimating a second measurement signal value corresponding to a second accumulated charge accumulated when a second potential barrier is generated corresponding to a second potential, based on a first measurement signal value corresponding to a first accumulated charge accumulated when a first potential barrier is generated corresponding to a first potential.

[0024] A schematic diagram of the external appearance of the imaging device according to this embodiment. A diagram showing an example configuration of the imaging device according to this embodiment. A diagram showing an example circuit configuration of the laminated substrate. A block diagram showing an example configuration of the signal processing unit and the memory unit. A diagram showing the equivalent circuit of a pixel. A diagram showing the potential of the emission signal supplied to the emission transistor in time series. A diagram schematically showing the relationship between the potential barrier for the photodiode and the stored charge. A diagram showing the relationship between the amount of light received and the stored charge due to the operation of the PWLR method. A diagram showing the relationship between the stored charge and the amount of light received in the PWLR method at a pixel. A diagram showing an example where the stored charge saturates in long storage. A diagram showing an example where the stored charge saturates even in medium storage. A diagram conceptually explaining an example of correcting the variation in the maximum stored charge in long storage. A diagram conceptually explaining an example of correcting the variation in the maximum stored charge in medium storage. A diagram showing a state similar to time point 4 explained in Figure 6. A diagram showing the transfer of the measured charge to the first memory unit. A diagram showing the reset of the FD. A diagram showing the injection state of the preliminary measurement charge. A diagram showing the transfer of the measured charge to the second memory unit. A diagram showing the transfer of charge to the FD. A diagram showing the transfer of measured charge Q to the FD. A characteristic diagram showing the relationship between the voltage of the discharge signal and the accumulated charge. A diagram showing an example of correction processing for the maximum accumulated charge per pixel at the long accumulation potential. A diagram showing an example of correction processing for the maximum accumulated charge per pixel at the medium accumulation potential. A diagram schematically showing an example of the processing process. A diagram schematically showing an example of the discrimination result. A diagram schematically showing an example of the processing result. A diagram showing an example of variation in Figure 24 when saturation occurs only in the long accumulation. A diagram showing an example of variation in Figure 24 when saturation occurs in the medium accumulation. A diagram showing an example of the operation of the PWLR method when N=3. A diagram showing an example of the operation of the PWLR method when N=4. A flowchart showing an example of processing by the imaging device.

[0025] The following describes specific embodiments of this technology with reference to the drawings. The drawings are schematic or conceptual, and the proportions of each part may not necessarily be the same as those of actual objects. In the specification and drawings, elements similar to those described above are denoted by the same reference numerals with respect to previously shown drawings, and detailed explanations are omitted as appropriate.

[0026] (First Embodiment) Figure 1 shows a schematic external view of the imaging device according to this embodiment. The imaging device 1 shown in Figure 1 is a semiconductor package in which a laminated substrate 13, for example, composed of a lower substrate 11 and an upper substrate 12 stacked on top of each other, is packaged. The imaging device 1 converts light incident from the direction indicated by the arrow in the figure into an electrical signal and outputs it.

[0027] Multiple solder balls 14, which are backside electrodes for electrically connecting to an external substrate (not shown), are formed on the lower substrate 11.

[0028] A color filter 15 of R (red), G (green), or B (blue) and an on-chip lens 16 are formed on the upper surface of the upper substrate 12. The upper substrate 12 is connected to the on-chip lens 16 via a protective member 18 and a sealing member 17 in a cavity-less structure. The protective member 18 is made of a transparent material such as glass, silicon nitride, sapphire, or resin. The sealing member 17 is made of a transparent adhesive material such as acrylic resin, styrene resin, or epoxy resin.

[0029] Figure 2 shows an example of the configuration of an imaging device according to this embodiment. For example, as shown in Figure 2A, the upper substrate 12 has a pixel array section 21 in which pixels that perform photoelectric conversion are arranged in a two-dimensional array, and a control circuit 22 that controls the pixels, while the lower substrate 11 has logic circuits 23 such as a signal processing circuit that processes the pixel signals output from the pixels.

[0030] Alternatively, as shown in Figure 2B, the upper substrate 12 may have only the pixel array portion 21 of the pixel region formed on it, while the lower substrate 11 may have the control circuit 22 and logic circuit 23 formed on it.

[0031] As described above, the logic circuit 23, or both the control circuit 22 and the logic circuit 23, are formed on a lower substrate 11 separate from the upper substrate 12 of the pixel array section 21 and stacked. This makes it possible to reduce the size of the imaging device 1 compared to the case where the pixel array section 21, control circuit 22, and logic circuit 23 are arranged in a planar direction on a single semiconductor substrate.

[0032] In the following description, the upper substrate 12 on which at least the pixel array 21 is formed will be referred to as the pixel sensor substrate 12, and the lower substrate 11 on which at least the logic circuit 23 is formed will be referred to as the logic substrate 11.

[0033] Figure 3 shows an example of the circuit configuration of the laminated substrate 13. As shown in Figure 3, the laminated substrate 13 includes a pixel array section 21 in which pixels 32 are arranged in a two-dimensional array, a vertical drive circuit 34, a column signal processing circuit 35, a horizontal drive circuit 36, an output circuit 37, a control circuit 22, input / output terminals 39, and the like.

[0034] Pixel 32 consists of a photodiode as a photoelectric conversion element and multiple pixel transistors. An example of the circuit configuration of pixel 32 will be described later with reference to Figure 5.

[0035] The control circuit 22 receives an input clock and data that commands the operating mode, and outputs data such as internal information of the laminated substrate 13. Specifically, the control circuit 22 generates clock signals and control signals that serve as the reference for the operation of the vertical drive circuit 34, column signal processing circuit 35, and horizontal drive circuit 36, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock. The control circuit 22 outputs the generated clock signals and control signals to the vertical drive circuit 34, column signal processing circuit 35, and horizontal drive circuit 36, etc.

[0036] The vertical drive circuit 34 is configured, for example, by a shift register, and selects a predetermined pixel drive wiring 40, supplies pulses to the selected pixel drive wiring 40 to drive the pixels 32, and drives the pixels 32 row by row. That is, the vertical drive circuit 34 sequentially selects and scans each pixel 32 of the pixel array 21 vertically row by row, and supplies a signal voltage based on the accumulated charge generated in the photoelectric conversion unit of each pixel 32 according to the amount of light received to the column signal processing circuit 35 through the vertical signal line 41.

[0037] The column signal processing circuit 35 is located for each column of pixels 32, and generates a measurement signal by performing an Analogue-to-Digital (AD) conversion on the signal voltage output from one row of pixels 32 for each pixel column. The column signal processing circuit 35 can also perform signal processing such as noise reduction. For example, the column signal processing circuit 35 can perform signal processing such as Correlated Double Sampling (CDS) to remove pixel-specific fixed pattern noise.

[0038] The horizontal drive circuit 36 ​​is configured, for example, by a shift register, and sequentially outputs horizontal scanning pulses to select each of the column signal processing circuits 35 in order, causing each of the column signal processing circuits 35 to output a measurement signal to the horizontal signal line 42. In this embodiment, the analog-converted signal output by the column signal processing circuit 35 is referred to as the measurement signal. The value of the measurement signal is referred to as the measurement signal value. The measurement signal is proportional to the signal voltage output by the FD 55 (see Figure 5), which will be described later. Furthermore, the signal voltage output by the FD 55 is proportional to the stored charge of the FD 55.

[0039] The output circuit 37 processes the measurement signals sequentially supplied from each column signal processing circuit 35 through the horizontal signal line 42 and outputs them. The output circuit 37 may, for example, only perform buffering, or it may perform black level adjustment, column variation correction, various digital signal processing, etc. The input / output terminal 39 exchanges signals with the outside.

[0040] The laminated substrate 13 configured as described above is a CMOS (Complementary Metal Oxide Semiconductor) image sensor called a column AD type, in which column signal processing circuits 35 that perform AD conversion processing are arranged for each pixel row.

[0041] Figure 4 is a block diagram showing an example configuration of the signal processing unit 230 and the memory unit 240 included in the logic circuit 23. The signal processing unit 230 is configured to include, for example, a CPU (Central Processing Unit), and generates pixel values ​​that suppress variations in the characteristics of each pixel 32 based on the accumulated charge D1 for each pixel 32 obtained from preliminary measurements. Note that the location of the signal processing unit 230 and the memory unit 240 is not limited, and they can be configured, for example, within the output circuit 37.

[0042] This signal processing unit 230 includes a characteristic calculation unit 232 and a correction calculation unit 234. In this embodiment, a signal that has undergone some signal processing based on the measurement signal is called a pixel signal, and its value is called a pixel value. The details of the signal processing unit 230 will be described later.

[0043] The memory unit 240 stores data, parameters, etc., required by the signal processing unit 230. This memory unit 240 is, for example, OTP (One Time Programmable memory), but is not limited to this. For example, it may be composed of DRAM, RRAM, STT-MRAM, PCM, Flash, FeFET, etc.

[0044] Figure 5 shows the equivalent circuit of pixel 32. The pixel 32 shown in Figure 5 is an example configuration that enables the PWLR (Piecewise Linear Response) imaging method.

[0045] The pixel 32 includes a photodiode 51 (PD) as a photoelectric conversion element, a first transfer transistor 52, a first memory unit (MEM1) 53, a second transfer transistor 54, an FD (floating diffusion region) 55, a reset transistor 56, an amplification transistor 57, a selection transistor 58, an output transistor 59, a third transfer transistor 60, a second memory unit (MEM2) 61, and a fourth transfer transistor 62.

[0046] The photodiode 51 is a photoelectric conversion unit that generates a signal charge corresponding to the amount of light received and stores it as stored charge. The anode terminal of the photodiode 51 is grounded, and the cathode terminal is connected to the first storage unit 53 via the first transfer transistor 52. The cathode terminal of the photodiode 51 is also connected to the second storage unit 61 via the third transfer transistor 60. Furthermore, the cathode terminal of the photodiode 51 is also connected to the discharge transistor 59 for discharging charge.

[0047] When the first transfer transistor 52 is turned on by the transfer signal TRX1, it reads the charge generated by the photodiode 51 and transfers it to the first storage unit 53. The first storage unit 53 is a charge holding unit that temporarily holds the charge until the charge is transferred to the FD 55.

[0048] When the second transfer transistor 54 is turned on by the transfer signal TRG1, it reads the charge held in the first storage unit 53 and transfers it to the FD 55.

[0049] When the third transfer transistor 60 is turned on by the transfer signal TRX2, it receives a preliminary charge Q. Ｄ１ The data is read and transferred to the second storage unit 61. The second storage unit 61 is a charge holding unit that temporarily holds the charge until the charge is transferred to FD55. Charge Q for measurement Ｄ１ This is the charge injected from the voltage source OFD to the cathode terminal of the photodiode 51 via the discharge transistor 59 for preliminary measurement.

[0050] When the fourth transfer transistor 62 is turned on by the transfer signal TRG2, it reads the charge held in the second storage unit 61 and transfers it to FD55.

[0051] FD55 is, for example, a floating diffusion layer and is a charge holding unit that holds the charge read from at least one of the first storage unit 53 and the second storage unit 61 in order to read it as a signal voltage. That is, FD55 is connected to the first storage unit 53 via the second transfer transistor 54 and to the second storage unit 61 via the fourth transfer transistor 62, and is capable of generating a voltage corresponding to the amount of stored charge. When the reset transistor 56 is turned on by the reset signal RST, the charge stored in FD55 is discharged to the constant voltage source VDD, thereby resetting the potential of FD55.

[0052] The amplifying transistor 57 outputs an output voltage proportional to the signal voltage of FD 55. That is, the amplifying transistor 57 forms a source follower circuit with the load MOS as a constant current source. As a result, a signal voltage indicating a level corresponding to the stored charge accumulated in FD 55 is output from the amplifying transistor 57 to the column signal processing circuit 35 (Figure 3) via the selection transistor 58. The load MOS 60 is, for example, located within the column signal processing circuit 35.

[0053] The selection transistor 58 is turned on when pixel 32 is selected by the selection signal SEL, and outputs the pixel signal of pixel 32 to the column signal processing circuit 35 via the vertical signal line 41.

[0054] The discharge transistor 59 discharges the charge stored in the photodiode (PD) 51 to the voltage source OFD in accordance with the voltage of the discharge signal OFG. That is, the discharge transistor 59 generates a potential barrier between the voltage source OFD and the photodiode 51 that corresponds to the voltage of the discharge signal OFG. The voltage source OFD also receives a preliminary charge Q via the discharge transistor 59. Ｄ１ This is supplied to the cathode terminal of the photodiode 51.

[0055] The transfer signals TRX1 and TRG1, transfer signals TRX2 and TRG2, reset signal RST, ejection signal OFG, and selection signal SEL are supplied from the vertical drive circuit 34 via the pixel drive wiring 40.

[0056] Here, while referring to FIG. 5, an operation example of the PWL-R method of pixel 32 will be described using FIGS. 6 to 7. Here, first, an exposure operation example when pre-measurement is not performed will be described.

[0057] FIG. 6 is a diagram showing the potential of the discharge signal OFG supplied to the discharge transistor 59 in time series. The horizontal axis represents time, and the vertical axis represents the potential of the discharge signal OFG. The magnitude of the potential is V ０ > V ｌｏｎｇ > V ｍｉｄ > V ｓｈｏｒｔ It has. As the potential of the discharge signal OFG decreases, the conductivity of the discharge transistor 59 decreases. In other words, as the potential of the discharge signal OFG decreases, the potential barrier between the voltage source OFD of the discharge transistor 59 and the photodiode 51 increases in order.

[0058] FIG. 7 is a diagram schematically showing the relationship between the potential barrier for the photodiode and the accumulated charge. The potentials V ｌｏｎｇ 、V ｍｉｄ 、V ｓｈｏｒｔ of the discharge signal OFG, the maximum accumulated charges Q ｓｌ 、Q ｓｍ 、Q ｓｓ are schematically shown. The maximum accumulated charges Q ｓｌ 、Q ｓｍ 、Q ｓｓ have the relationship of Q ｓｌ <Q ｓｍ <Q ｓｓ 。

[0059] The transfer signals TRX (TRX1 and TRX2) indicate an off state. As the potential V ｌｏｎｇ 、V ｍｉｄ 、V ｓｈｏｒｔ of the discharge signal OFG changes, the potential barrier of the discharge signal OFG increases, and the maximum accumulated charge changes as Q ｓｌ 、Q ｓｍ 、Q ｓｓ 。 Also, when the transfer signals TRX (TRX1 and TRX2) are in an off state, the potential barriers between the first transfer diode 52 and the photodiode 51 and between the third transfer diode 60 and the photodiode 51 are the potential V ｓｈｏｒｔThe potential barrier becomes higher than in the previous case. The operation of the PWLR method utilizes this accumulation characteristic.

[0060] More specifically, as shown again in Figure 6, first, before exposure begins, the potential V at time t0 ０ When the discharge signal OFG is supplied to the discharge transistor 59, the discharge transistor 59 is turned on, the charge accumulated in the photodiode 51 is discharged to the voltage source OFD, and the photodiodes 51 of all pixels are reset.

[0061] Next, after the photodiode 51 is reset, at time t1, a potential V is applied to the output transistor 59. ｌｏｎｇ The emission signal OFG is supplied, the conductivity decreases, and exposure begins at all pixels in the pixel array 21. As a result, the potential V ｌｏｎｇ In the discharge signal OFG, the maximum accumulated charge Q ｓｌ Charge can be accumulated up to this point. On the other hand, the maximum accumulated charge Q ｓｌ Any charge exceeding this limit is discharged to the voltage source OFD.

[0062] Next, at time t2 after a predetermined long storage time has elapsed, the discharge transistor 59 is subjected to a potential V ｍｉｄ The discharge signal is applied. This further reduces the conductivity of the discharge transistor 59, and the maximum stored charge Q ｓｍ Charge can be accumulated up to this point. On the other hand, the maximum accumulated charge Q ｓｍ Any charge exceeding this limit is discharged to the voltage source OFD.

[0063] Next, at time t3, after a predetermined storage time has elapsed, the discharge transistor 59 is subjected to a potential V ｓｈｏｒｔ The discharge signal is applied. This further reduces the conductivity of the discharge transistor 59, and the maximum stored charge Q ｓｓ This allows for the accumulation of electric charge up to a certain point.

[0064] Next, at time t4, after a predetermined short charging time has elapsed, exposure is completed, and the first transfer transistor 52 is turned on by the transfer signal TRX1 in all pixels of the pixel array 21, and the charge accumulated in the photodiode 51 is transferred to the first storage unit 53.

[0065] After the first transfer transistor 52 is turned off, the charge held in the first storage unit 53 of each pixel 32 is read out row by row to the column signal processing circuit 35. The read operation is performed when the second transfer transistor 54 of the pixel 32 of the read row is turned on by the transfer signal TRG1, and the charge held in the first storage unit 53 is transferred to the FD 55. Then, when the selection transistor 58 is turned on by the selection signal SEL, a signal voltage indicating a level corresponding to the stored charge accumulated in the FD 55 is output as an output voltage from the amplification transistor 57 through the selection transistor 58 to the column signal processing circuit 35.

[0066] Referring to Figure 6, Figure 8 will be used to explain the relationship between the amount of light received and the accumulated charge in the operation of the PWLR system. Figure 8 is a diagram showing the relationship between the amount of light received and the accumulated charge in the operation of the PWLR system.

[0067] Figure 8A shows the relationship between exposure time and the amount of light received. The horizontal axis represents the exposure time, and the vertical axis represents the amount of light received (number of photosons). The number of electrons converted by the photodiode 51 is proportional to the amount of light received. In Figure 8A, it is assumed that the illuminance to the pixel 32 is constant during the exposure time. Therefore, the light intensity lines L0, L2, and L4 show that the illuminance to the pixel 32 is increasing in that order.

[0068] As shown in Figure 8A, the light intensity line L0, which indicates high light intensity, corresponds to the maximum accumulated charge Q in the operation of the PWLR system. ｓｓ This shows an example where the maximum accumulated charge Q is reached at the end of the exposure time, t4. In the light intensity line L0, which indicates a high light intensity, the maximum accumulated charge Q is reached at time t11, which is in a long-accumulation state. ｓｌ Beyond a certain point, the charge saturates. In this case, the saturated charge is discharged to the voltage source OFD. After time t2, the charge accumulates in an intermediate state.

[0069] Next, at time t22, while in the intermediate charge state, the maximum accumulated charge Q ｓｍ Beyond this point, the charge saturates again. After time t3, the charge accumulates in a short-storage state, and at t4, the maximum accumulated charge Q ｓｓ It reaches this point. As can be seen from this, when the illuminance is less than the illuminance indicated by the light intensity line L0, the maximum accumulated charge Q ｓｓThe light intensity does not reach the maximum value, and the amount of light received at the end point t4 can be read out as the accumulated charge. In other words, the maximum accumulated charge Q ｓｓ Light received at or below the corresponding amount can be associated with accumulated charge.

[0070] In the light intensity line L2, which indicates the light intensity, for example, saturation does not occur at long, medium, or short storage, and at time t4, the maximum accumulated charge Q is reached. ｓｍ It reaches the maximum accumulated charge Q. As can be seen from this, the accumulated charge is the maximum accumulated charge Q. ｓｓ And, the maximum stored charge Q ｓｍ If the time is between the two, the amount of light received at the end of time t4 will be between the amount of light received indicated by the light intensity line L0 and the amount of light received indicated by the light intensity line L2 at the end of time t4.

[0071] In the light intensity line L4, which indicates low light intensity, for example, saturation does not occur at long, medium, or short storage, and at time t4, the maximum accumulated charge Q ｓｌ It reaches the maximum accumulated charge Q. As can be seen from this, the accumulated charge is the maximum accumulated charge Q. ｓｍ And, the maximum stored charge Q ｓｌ If the value is between the two values, the amount of light received at the end time t4 will be between the amount of light received indicated by the light intensity line L2 and the amount of light received indicated by the light intensity line L4 at the end time t4. Similarly, the maximum accumulated charge Q ｓ If the following conditions are met, the amount of light received will be less than or equal to the amount of light indicated by the light intensity line L4 at the end time t4.

[0072] Figure 8B summarizes this relationship. Figure 8B is a diagram showing the relationship between the amount of light received and the accumulated charge. The horizontal axis represents the amount of light received, and the vertical axis represents the accumulated charge. As can be seen from this, the maximum accumulated charge Q ｓｌ If the following conditions are met, the maximum accumulated charge Q ｓｍ The following conditions apply, and the maximum accumulated charge Q ｓｓ The amount of change in the number of stored charges with respect to the amount of light received differs in each of the following cases. As described above, in this embodiment, the signal voltage due to the stored charge moved to FD55 and the output voltage applied from pixel 32 to signal line 41 are assumed to be proportional.

[0073] Figure 9 shows the relationship between the accumulated charge and the amount of light received in the PWLR method at pixel 32. The horizontal axis represents the amount of light received, and the vertical axis represents the accumulated charge. Line L6 shows the relationship between the amount of light received and the accumulated charge in the PWLR method, and line L8 shows the relationship between the amount of light received and the accumulated charge when the PWLR method is not implemented.

[0074] Furthermore, it is shown that the dynamic range expands as the range of light received increases for the same range of accumulated charge. Thus, when the PWLR method is implemented, the maximum accumulated charge Q of the pixel 32 ｓｓ Even with the same parameters, it becomes possible to widen the dynamic range.

[0075] Furthermore, in this embodiment, the signal processing is performed so that the amount of light received by the pixel 32 and the value of the pixel signal output from the output circuit 37 of the pixel 32 are in a proportional relationship. In such a case, based on the relationship between the accumulated charge Q and the amount of light shown in Figure 9, a lookup table that takes the measurement signal of the column signal processing circuit 35 based on the accumulated charge Q as input and outputs the pixel signal can be converted into a pixel signal that is in a proportional relationship with the amount of light received by the pixel 32.

[0076] Figure 10 shows an example where the accumulated charge saturates during long-term storage. The horizontal axis represents the exposure time, and the vertical axis represents the number of accumulated charges. Line L10 shows the time change of the accumulated charge Q.

[0077] Box B10 shows the accumulated charge Q at the end of exposure time t4. Box B12 shows the accumulated charge Q during the intermediate and short accumulation periods, which are the accumulated charge Q during time points t2 to t4. Ｄ２ This shows that box B14 represents the maximum stored charge Q during long-term storage. ｓｌ This indicates.

[0078] In PWLR imaging, time points t1, t2, t3, and t4 are predetermined, and the accumulated charge Q at time point t4 is measured as a measurement signal. Ｄ２ , maximum accumulated charge Q ｓｌ It is not possible to obtain this value as a constant signal.

[0079] Referring again to Figure 7, the maximum accumulated charge Q ｓｌ The values ​​are the same potential Vｌｏｎｇ Even if this is supplied to the discharge diode 59 (see Figure 5) as the discharge signal OFG, variations will occur due to variations in the potential barrier. For example, the minimum value Q in all pixels 32 ｓｌ＿ｍｉｎ For this, the maximum accumulated charge Q ｓｌ This results in a variation on the larger side of the value. Therefore, the maximum accumulated charge Q ｓｌ The value of also varies from pixel to pixel 32, and even with the same amount of light, variations occur in the accumulated charge Q for each pixel 32.

[0080] In contrast, the accumulated charge Q Ｄ２ Since it is not affected by the characteristics of the emission diode 59 (see Figure 5), the accumulated charge Q accumulated during time t2 to t4 Ｄ２ This is proportional to the amount of light in each of the 32 pixels.

[0081] Figure 11 shows an example where the accumulated charge saturates even during moderate storage. The horizontal axis represents exposure time, and the vertical axis represents the number of accumulated charges. Line L11 shows the time change of the accumulated charge Q when the accumulated charge saturates during long and moderate storage.

[0082] Box B16 shows the accumulated charge Q at the end of exposure time t4. Box B18 shows the accumulated charge Q accumulated during the short accumulation period, from time t3 to t4. Ｄ２ This shows that box B20 represents the maximum stored charge Q in the intermediate storage. ｓｍ This indicates.

[0083] As described above, in the PWLR imaging drive, time points t1, t2, t3, and t4 are predetermined, and the accumulated charge Q at time point t4 is measured as the measurement signal of the column signal processing circuit 35. On the other hand, the accumulated charge Q Ｄ２ , maximum accumulated charge Q ｓｍ This value cannot be obtained as a measurement signal.

[0084] Referring again to Figure 7, the maximum accumulated charge Q ｓｍ The values ​​are the same potential V ｍｉｄ Even if this is supplied to the discharge diode 59 (see Figure 5) as the discharge signal OFG, variations will occur due to variations in the potential barrier. For example, the minimum value Q in all pixels 32 ｓｍ＿ｍｉｎ For this, the maximum accumulated charge Qｓｍ varies on the larger value side. Therefore, the value of the maximum stored charge Q ｓｍ also varies for each pixel 32, and the stored charge Q varies even for the same amount of light.

[0085] In contrast, the stored charge Q accumulated during a short storage period Ｄ２ is not affected by the characteristics of the discharge diode 59 (see Fig. 5), so the stored charge Q accumulated during the time from t3 to t4 Ｄ２ is proportional to the amount of light.

[0086] Here, referring to Fig. 4, using Figs. 12 and 13, the correction examples of the variation of the maximum stored charge Q for long storage ｓｌ , the maximum stored charge Q for medium storage ｓｍ will be conceptually explained. Fig. 12 is a diagram conceptually explaining the correction example of the variation of the maximum stored charge Q for long storage ｓｌ . Fig. 13 is a diagram conceptually explaining the correction example of the variation of the maximum stored charge Q for medium storage ｓｍ .

[0087] As shown in Figs. 12 and 13, the stored charge Q of the preliminary measurement Ｄｌ is the stored charge injected from the voltage source OFD side to the cathode terminal of the photodiode 51 by applying the same potential V Ｄ１ to each pixel 32 as the discharge signal OFG. For example, the potential V Ｄ１ is lower than the potential V ｌｏｎｇ . In this embodiment, in order to suppress the measurement power, the potential V Ｄ１ will be described by taking an example of a potential lower than the potential V ｌｏｎｇ , but it is not limited to this. For example, the potential V Ｄ１ can be the potential, V ｌｏｎｇ the potential V ｍｉｄ as well. Note that the details of the operation example of the preliminary measurement of the stored charge Q Ｄｌ will be described using Figs. 14 to 22 described later.

[0088] The stored charge Q Ｄｌ applies the same potential V Ｄ１ to the discharge diode 59 (see Fig. 5) of each pixel 32, so it reflects the characteristics of the threshold voltage Vth, which is the height of the potential barrier in the discharge diode 59. For example, the stored charge QＤｌ When the measured value is small, it has the characteristic that the threshold voltage Vth with respect to the applied voltage of the potential barrier is low, and the stored charge Q Ｄｌ When the measured value is large, it has the characteristic that the threshold voltage Vth is high. Even when a potential V ｌｏｎｇ , V ｍｉｄ is applied to the discharge diode 59 (see FIG. 5), it shows the same characteristics. That is, when the measured value of the stored charge Q Ｄｌ is large, the maximum stored charge Q ｓｌ、 of long storage and the maximum stored charge Q ｓｍ of medium storage also tend to be large. When the measured value of the stored charge Q Ｄｌ is small, the maximum stored charge Q ｓｌ、 of long storage and the maximum stored charge Q ｓｍ of medium storage also tend to be small. As will be described later, the correlation between these stored charges Q Ｄｌ and the maximum stored charge Q ｓｌ can be approximated by a linear relational expression. Similarly, the correlation between the stored charge Q Ｄｌ and the maximum stored charge Q ｓｍ can be approximated by a linear relational expression.

[0089] As shown in FIG. 12, due to the characteristics of such a correlation, the characteristic calculation unit 232 of the signal processing unit 230 uses the stored charge Q Ｄｌ for each pixel 32 to generate an estimated value of the maximum stored charge Q ｓｌ for each pixel 32. The correction calculation unit 234 of the signal processing unit 230 subtracts this estimated value of the maximum stored charge Q ｓｌ from the measured value Q. Thereby, the stored charge Q Ｄ２ with the influence of the characteristics of the discharge transistor 59 suppressed is generated. That is, the stored charge Q ｓｌ is generated without saturation in medium and short storage by suppressing the fluctuation component of the maximum stored charge Q Ｄ２ .

[0090] Next, the correction calculation unit 234 adds, for example, the estimated minimum value Q Ｄ２ to the calculated stored charge Q ｓｌ＿ｍｉｎ . Thereby, the correction calculation unit 234 can generate a pixel value that varies according to the stored charge from the relationship equivalent to the received light amount shown in FIG. 8B and the stored charge. For example, the minimum value Qｓｌ＿ｍｉｎ It is also possible to add an offset value. This allows the correction calculation unit 234 to uniformly generate pixel values ​​that fluctuate according to the accumulated charge, based on the relationship between the amount of light received and the accumulated charge shown in Figure 8B. As described above, these pixel values ​​can be generated to have a proportional relationship with the amount of light received.

[0091] Similarly, as shown in Figure 13, the characteristic calculation unit 232 of the signal processing unit 230 calculates the accumulated charge Q for each pixel 32. Ｄｌ Using this, the maximum accumulated charge Q in the intermediate charge for each pixel 32 ｓｍ The signal processing unit 230's correction calculation unit 234 generates an estimated value of this maximum accumulated charge Q. ｓｍ The estimated value is subtracted from the measured value Q. This suppresses the fluctuating component and the accumulated charge Q that is not saturated by short-term accumulation. Ｄ２ This is generated.

[0092] Next, the correction calculation unit 234 calculates the accumulated charge Q Ｄ２ For example, the estimated minimum value Q ｓｍ＿ｍｉｎ This is added. As a result, the correction calculation unit 234 can generate a pixel value that fluctuates according to the amount of light received, based on the same relationship between the pixel signal shown in Figure 8B and the accumulated charge. For example, the minimum value Q ｓｍ＿ｍｉｎ It is also possible to add an offset value. This allows the correction calculation unit 234 to uniformly generate pixel values ​​that fluctuate according to the accumulated charge, based on the relationship between the amount of light received and the accumulated charge shown in Figure 8B. As described above, these pixel values ​​can be generated to have a proportional relationship with the amount of light received.

[0093] Here, we will explain an example of operation including preliminary measurements using Figures 14 to 20. Figure 14 shows a state similar to time point 4 described in Figure 6. That is, it shows the measured charge Q after exposure with the PWLR accumulation drive has finished. Reset noise RST KTC1 is accumulated in FD55.

[0094] Figure 15 shows the transfer of the measured charge Q to the first storage unit 53. As shown in Figure 15, when the first transfer transistor 52 is turned on by the transfer signal TRX1, it reads the charge generated by the photodiode 51 and transfers it to the first storage unit 53. The first storage unit 53 temporarily holds the charge until it is transferred to the FD 55.

[0095] Figure 16 shows the reset of FD55. When the reset transistor 56 is turned on by the reset signal RST, the charge stored in FD55 is discharged to the constant voltage source VDD, thereby resetting the charge of FD55.

[0096] Figure 17 shows the charge Q measured in the preliminary measurement. Ｄ１ This diagram shows the injection state. Charge Q is injected from the voltage source OFD side to the cathode terminal of photodiode 51. Ｄ１ Inject the following: At this time, the discharge transistor 59 is at potential V Ｄ１ The discharge signal OFG is applied. Also, the reset transistor 56 is turned off by the reset signal RST, and the reset noise RST KTC2 is accumulated. Note that charge Q Ｄ１ The injection of charge Q is not limited to this, for example, by pre-irradiation. Ｄ１ It is also possible to accumulate data.

[0097] Figure 18 shows the measured charge Q to the second storage unit 61. Ｄ１ This is a diagram showing the transfer. As shown in Figure 18, when the third transfer transistor 60 is turned on by the transfer signal TRX2, the charge Q injected into the photodiode 51 Ｄ１ The data is read and transferred to the second storage unit 61. The second storage unit 61 stores the charge Q in FD55. Ｄ１ Temporarily charge Q until it is transferred. Ｄ１This is maintained. At this time, the selection transistor 58 is turned on by the selection signal SEL, and a voltage signal indicating a level corresponding to the reset noise RST KTC2 stored in FD 55 is output from the amplification transistor 57 through the selection transistor 58 to the column signal processing circuit 35 as a noise pixel signal. This noise pixel signal is converted from analog to digital by the column signal processing circuit 35 and stored in the storage unit 240 for each pixel 32.

[0098] Figure 19 shows the charge Q on FD55. Ｄ１ This is a diagram showing the transfer. As shown in Figure 19, when the fourth transfer transistor 61 is turned on by the transfer signal TRG1, the charge Q held in the second storage unit 61 is transferred. Ｄ１ The data is read and transferred to FD55. At this time, the selection transistor 58 is turned on by the selection signal SEL, and the charge Q stored in FD55 is read. Ｄ A signal indicating the level corresponding to the reset noise RST KTC2 is output from the amplification transistor 57 to the column signal processing circuit 35 via the selection transistor 58 as a preliminary measurement pixel signal and a noise pixel signal. This preliminary measurement pixel signal and noise pixel signal are converted from analog to digital by the column signal processing circuit 35 as the sum of the preliminary measurement pixel signal and the noise pixel signal, and stored in the storage unit 240 for each pixel 32.

[0099] Figure 20 shows the transfer of the measured charge Q to FD55. As shown in Figure 20, when the second transfer transistor 54 is turned on by the transfer signal TRG1, it reads the charge Q held in the first storage unit 53 and transfers it to FD55. At this time, when the selection transistor 58 is turned on by the selection signal SEL, the measured charge Q stored in FD55 and the charge Q Ｄ１A signal indicating the level corresponding to the reset noise RST KTC2 is output from the amplification transistor 57 to the column signal processing circuit 35 via the selection transistor 58 as the measurement pixel signal, the preliminary measurement pixel signal, and the noise pixel signal. This measurement pixel signal, preliminary measurement pixel signal, and noise pixel signal are converted from analog to digital by the column signal processing circuit 35 as the sum of the measurement pixel signal, the preliminary measurement pixel signal, and the noise pixel signal, and stored in the storage unit 240 for each pixel 32.

[0100] Here, with reference to Figure 4, the details of the signal processing unit 230 will be explained using Figures 21 to 26. The characteristic calculation unit 232 of the signal processing unit 230 uses the sum of the measurement pixel signal, the preliminary measurement pixel signal, and the noise pixel signal, the sum of the preliminary measurement pixel signal and the noise pixel signal, and the value of the noise pixel signal for each pixel stored in the storage unit 240 to calculate the measurement pixel signal Q and the preliminary measurement pixel signal Q for each pixel. Ｄ１ The calculation is performed and stored in the memory unit 240 for each pixel 32. Note that the measurement signal of the column signal processing circuit 35 is proportional to the accumulated charge multiplied by a proportionality constant, but in this embodiment, for the sake of simplicity, the proportionality constant may be described as 1. In this case, the sign of the measurement signal is set to charge Q, Q Ｄ１ It is sometimes explained using this method.

[0101] Figure 21 is a characteristic diagram showing the relationship between the voltage of the emission signal OFG and the accumulated charge. The horizontal axis represents the voltage of the emission signal OFG, and the vertical axis represents the accumulated charge. For example, this characteristic line L210 is characteristic data of the voltage of the emission signal OFG and the accumulated charge. This characteristic line L210 is statistical data measured, for example, during the manufacturing of the imaging device 1.

[0102] In Figure 21, the discharge signal OFG has an intermediate potential (V ｍｉｄ ), long storage potential (potential V ｌｏｎｇ ), preliminary measurement potential (V Ｄ１ ) are shown as medium storage, long storage, and D1 storage. Also, the medium storage potential (V ｍｉｄ The average value Q of the intermediate charge accumulated in each pixel 32 when the applied charge is ｓｍ＿ａｖｅ This shows that the same mid-potential (V) is used as the emission signal OFG for each pixel 32. ｍｉｄEven when a certain voltage is applied, the accumulated charge varies along the characteristic curve L210. The characteristic calculation unit 232 calculates the average value Q ｓｍ＿ａｖｅ The calculation is performed and stored in the memory unit 240.

[0103] Similarly, long-term storage potential (V ｌｏｎｇ The average value Q of the long-accumulated charge accumulated in each pixel 32 when the applied charge is Q ｓｌ＿ａｖｅ This shows that the same long storage potential (V) is used as the output signal OFG for each pixel 32. ｌｏｎｇ Even when a certain voltage is applied, the accumulated charge varies along the characteristic curve L210. The characteristic calculation unit 232 calculates the average value Q ｓｌ＿ａｖｅ The calculation is performed and stored in the memory unit 240.

[0104] Similarly, the preliminary measurement potential (V Ｄ１ The average value Q of the preliminary measured charge accumulated in each pixel 32 when the applied charge is Q Ｄ１＿ａｖｅ This shows that the same preliminary measurement potential (V) is used as the output signal OFG for each pixel 32. Ｄ１ Even when a certain voltage is applied, the accumulated charge varies along the characteristic curve L210. The characteristic calculation unit 232 calculates the average value Q Ｄ１＿ａｖｅ The calculation is performed and stored in the memory unit 240.

[0105] These statistical data include preliminary measured potentials (V Ｄ１ When ) is applied, the average value Q Ｄ１＿ａｖｅ In pixel 32, where the accumulated charge increases more than in pixel 32, the long-storage potential (V ｌｏｎｇ When ) is applied, the average value Q ｓｌ＿ａｖｅ The accumulated charge increases compared to [this value]. More specifically, the preliminary measurement potential (V) Ｄ１ ) The average value Q when applied Ｄ１＿ａｖｅ Deviation from ΔQ Ｄ１ Maximum accumulated charge (preliminary measurement potential (V) Ｄ１ )) and minimum accumulated charge (preliminary measurement potential (V Ｄ１ )) and the ratio to the difference is long-term storage potential (V ｌｏｎｇ ) The average value Q when applied ｓｌ＿ａｖｅ Deviation from ΔQ ｓｌ Maximum stored charge (long storage potential (V) ｌｏｎｇ )) and minimum stored charge (long stored potential (potential V ｌｏｎｇ )) shows a tendency to correlate with the ratio of the difference.

[0106] Similarly, these statistical data include the preliminary measured potential (V). Ｄ１ When ) is applied, the average value Q Ｄ１＿ａｖｅ In pixel 32, where the accumulated charge increases more than in pixel 32, the intermediate potential (V) ｍｉｄ When ) is applied, the average value Q ｓｌ＿ａｖｅ The accumulated charge increases compared to [this value]. More specifically, the preliminary measurement potential (V) Ｄ１ ) The average value Q when applied Ｄ１＿ａｖｅ Deviation from ΔQ Ｄ１ Maximum accumulated charge (preliminary measurement potential (V) Ｄ１ )) and minimum accumulated charge (preliminary measurement potential (V Ｄ１ )) and the ratio to the difference is the intermediate potential (V ｍｉｄ ) The average value Q when applied ｓｍ＿ａｖｅ Deviation from ΔQ ｓｍ Maximum stored charge (long storage potential (V) ｌｏｎｇ )) and minimum stored charge (long stored potential (potential V ｌｏｎｇ )) shows a tendency to correlate with the ratio of the difference.

[0107] The average value Q of the accumulated charge ｓｍ＿ａｖｅ Let a be the slope of the central stored charge with respect to the OFG voltage centered at [point]. ｓｍ This is shown, and the average value Q of the long-accumulated charge is shown. ｓｌ＿ａｖｅ Let a be the slope of the long-stored charge centered at a with respect to the OFG voltage. ｓｌ The average value of the preliminary measured charge Q is shown. Ｄ１＿ａｖｅ The slope of the preliminary measured charge with respect to the OFG voltage, centered at [point number], is a. Ｄ１ This is shown. The characteristic calculation unit 232 calculates these a ｓｍ a ｓｌ , and a Ｄ１ Each of these is given a medium potential (V ｍｉｄ ), long storage potential (V ｌｏｎｇ ), and preliminary measurement potential (V Ｄ１ The variation data of ) is generated, for example, by least-squares approximation, and stored in the storage unit 240.

[0108] Furthermore, the characteristic calculation unit 232 a ｌ = a Ｄ１ / a ｓｌ a ｍ = a Ｄ１ / a ｓｍThe calculation is performed and stored in the memory unit 240. Referring again to Figure 8, the characteristic calculation unit 232 performs the calculation of t １ = t² - t¹, t ｍ = t3 - t1, t ｓ The equation = t4 - t1 is calculated and stored in the memory unit 240.

[0109] Here, an example of the processing of the correction calculation unit 234 will be explained using Figures 22 and 23. Figure 22 shows the long-storage potential (V ｌｏｎｇ Maximum accumulated charge Q for each pixel 32 in ) ｓｌ This figure shows an example of the correction process. Figure 23 shows the intermediate potential (V ｍｉｄ Maximum accumulated charge Q for each pixel 32 in ) ｓｍ This figure shows an example of the correction process.

[0110] First, long-term storage potential (V ｌｏｎｇ Maximum accumulated charge Q for each pixel 32 in ) ｓｌ An example of the correction process will be explained. As shown in Figure 22, the correction calculation unit 234 calculates the preliminary measured charge Q Ｄ１ The data is obtained (step S100). Subsequently, the correction calculation unit 234 calculates the preliminary measurement potential (V Ｄ１ ) The average value Q when applied Ｄ１＿ａｖｅ Deviation from ΔQ Ｄ１ ΔQ Ｄ１ = Q Ｄ１ - Q Ｄ１＿ａｖｅ The calculation is performed and stored in the memory unit 240 (step S102).

[0111] Next, the correction calculation unit 234 calculates the maximum accumulated charge Q of the pixel 32 according to equation (1). ｓｌ We estimate the mean Q. Ｄ１＿ａｖｅ Deviation from ΔQ Ｄ１ Based on this, slope a Ｄ１ and a ｓｌ The ratio of this ratio determines the maximum stored charge Q ｓｌ This is linearly estimated and stored in the memory unit 240 (step S104).

[0112] Next, the correction calculation unit 234 calculates the measured charge Q in the case where the pixel 32 does not saturate with long-storage and medium-storage, according to equation (2). ｌｃThe value is estimated and stored in the memory unit 240 (step S106). For example, referring to Figure 8A, in line L2, the maximum accumulated charge at time t2 is Q. ｓｌ Therefore, the estimated measured charge at time t4 is Q ｌｃ This is the result. Steps S100 to S110 will be explained later.

[0113] Next, the intermediate potential (V ｍｉｄ Maximum accumulated charge Q for each pixel 32 in ) ｓｍ An example of the correction process will be explained. The correction calculation unit 234 performs the same processing as described above in steps S100 to S102.

[0114] Next, the correction calculation unit 234 calculates the maximum accumulated charge Q of the pixel 32 according to equation (3). ｓｍ We estimate the mean Q. Ｄ１＿ａｖｅ Deviation from ΔQ Ｄ１ Based on this, slope a Ｄ１ and a ｓｍ The ratio of this ratio determines the maximum stored charge Q ｓｍ This is linearly estimated and stored in the memory unit 240 (step S204).

[0115] Next, the correction calculation unit 234 calculates the estimated measured charge Q in the case where the pixel 32 does not saturate with long-storage and medium-storage, according to equation (4). ｍｃ The value is estimated and stored in the memory unit 240 (step S206).

[0116] Returning to Figure 22, the correction calculation unit 234 acquires the measured charge Q of the pixel 32 (step S108). Subsequently, it determines whether or not the charge is saturated in either long charge or medium charge according to the conditional expression (step S108).

[0117] The correction calculation unit 234 calculates that the measured charge Q is the estimated measured charge Q ｌｃ If the value is smaller than this, it is determined that there is no saturation, and the pixel signal Qr is output as the final output. In practice, the pixel signal Qr is converted into a pixel value based on the measured charge Q.

[0118] The correction calculation unit 234 calculates that the measured charge Q is the estimated measured charge Q ｌｃIf it is smaller than this, it is determined that there is no saturation and the measured charge Q is output as the final output. On the other hand, the correction calculation unit 234 calculates that the measured charge Q is the estimated measured charge Q ｌｃ Larger than, estimated measured charge Q ｍｃ If it is smaller than this, it is determined that the long-term storage is saturated.

[0119] In this case, as shown in equation (5), the correction calculation unit 234 calculates the maximum accumulated charge Q estimated from the measured charge Q. ｓｌ Subtracting this, we obtain the minimum estimated value Q. ｓｌ＿ｍｉｎ The corrected measurement result Qr is generated by adding the representative value.

[0120] The correction calculation unit 234 outputs a pixel signal Qr as the final output. In practice, the pixel signal Qr is converted into a pixel value based on the measured charge Qr.

[0121] Minimum value Q of the estimated value ｓｌ＿ｍｉｎ Instead, Q is shown in Figure 8B. ｓｌ The reference value may be added as a representative value. This makes it possible to obtain a corrected measurement result Qr with suppressed fluctuation components.

[0122] On the other hand, the correction calculation unit 234 calculates that the measured charge Q is the estimated measured charge Q ｍｃ If it is greater than this, it is determined that the intermediate storage is saturated. In this case, as shown in equation (6), the correction calculation unit 234 calculates the maximum accumulated charge Q estimated from the measured charge Q. ｓｍ Subtracting this, we obtain the minimum estimated value Q. ｓｍ＿ｍｉｎ The corrected measurement result Qr is generated by adding the representative value.

[0123] The correction calculation unit 234 outputs the pixel signal Qr as the final output. In practice, the pixel signal Qr is converted into a pixel value based on the measured charge Qr. Minimum estimated value Q ｓｍ＿ｍｉｎ Instead, Q is shown in Figure 8B. ｓｍ The reference value may be added as a representative value. This makes it possible to obtain a corrected measurement result Qr with suppressed fluctuation components.

[0124] Figure 24 is a schematic diagram showing an example of the processing process. The storage area 242 of the storage unit 240 contains, for example, the -(estimated measured charge Q) of equation (5). ｓｌ- Minimum value of the estimated value Q ｓｌ＿ｍｉｎ ) is stored. Similarly, in the storage area 244 of the storage unit 240, for example, the -(estimated measured charge Q) of equation (6) is stored. ｓｍ - Minimum value of the estimated value Q ｓｍ＿ｍｉｎ The data is stored. The correction calculation unit 234 uses this data to calculate the correction measurement result Qr for each pixel 32.

[0125] Figure 25 schematically shows an example of the discrimination result. The memory areas 246, 248, etc., of the memory unit 240 store codes indicating, for example, long storage, medium storage, and no saturation. The correction calculation unit 234 calculates the correction measurement result Qr for each pixel 32 using these condition data. In this embodiment, saturation may be referred to as wear.

[0126] Figure 26 is a schematic diagram showing an example of the processing result. The storage areas 250, 252, etc. of the storage unit 240 store, for example, the calculation results of equations (5) and (6). The signal (sig) in the figure schematically shows, for example, an example in which the correction measurement result Qr is converted to a pixel value.

[0127] Figure 27 shows an example of the variation in Figure 24 when saturation is present only in the long-storage portion. Image G10 is the case without correction processing, and image G12 is the case with correction processing. The variation values ​​of pixels 32 in 2 rows and 4 columns are displayed in an enlarged view. For example, with correction processing, the variation is improved from, for example, 30 LSB to 10 LSB.

[0128] Figure 28 shows an example of the variation in Figure 24 when there is saturation in the intermediate storage. Image G14 is the case without correction processing, and image G16 is the case with correction processing. The variation values ​​of pixels 32 in 2 rows and 4 columns are displayed in an enlarged view. For example, with correction processing, the variation is improved from, for example, 70 LSB to 40 LSB.

[0129] Figures 29 and 30 show examples of operation of the PWLR system according to this embodiment. The PWLR system according to this embodiment changes the potential of the emission signal OFG N or more times. N is a natural number of 2 or more. Figure 29 shows an example of operation of the PWLR system when N=3. Figure 30 shows an example of operation of the PWLR system when N=4. The horizontal axis is exposure time, and the vertical axis is accumulated charge. Thus, in the PWLR system according to this embodiment, it is possible to change the potential of the emission signal OFG N or more times.

[0130] Figure 31 is a flowchart showing an example of processing by the imaging device 1. First, the control circuit 22 of the imaging device 1 controls the potential of the ejection signal OFG of all pixels 32 to V ０ , V ｌｏｎｇ , V ｍｉｄ , V ｓｈｏｒｔ Exposure is performed by changing the sequence in a predetermined time interval (step S300).

[0131] Next, the control circuit 22 reads out the charge Q generated by the photodiode 51 of each pixel 32 in response to the transfer signal TRX1 and transfers it to the first storage unit 53 (step S302). Subsequently, the control circuit 22 discharges the charge stored in FD 55 to the constant voltage source VDD in response to the reset signal RST (step S304).

[0132] Next, the control circuit 22 controls the potential V Ｄ１ The discharge signal OFG is supplied to the discharge transistor 59, and the preliminary measured charge Q is sent from the voltage source OFD side to the cathode terminal of the photodiode 51. Ｄ１ Inject (step S306). Subsequently, the control circuit 22 receives the transfer signal TRX2 and the preliminary measured charge Q Ｄ１ The data is read and transferred to the second storage unit 61 (step S308). At this time, the control circuit 22 uses the selection signal SEL to convert a signal indicating the level corresponding to the reset noise RST KTC2 stored in FD55 into an analog-to-digital noise pixel signal and stores it in the storage unit 240.

[0133] Next, the control circuit 22 receives the transfer signal TRG1 and the charge Q held in the second storage unit 61 Ｄ１The data is read and transferred to FD55. Then, the control circuit 22, using the selection signal SEL, selects the charge Q stored in FD55. Ｄ１ The signal indicating the level corresponding to the reset noise RST KTC2 is converted from analog to digital as the sum of the preliminary measurement pixel signal and the noise pixel signal, and stored in the storage unit 240 (step S310).

[0134] Next, the control circuit 22 reads the charge Q held in the first storage unit 53 by the transfer signal TRG1 and transfers it to FD 55. At this time, the selection transistor 58 is turned on by the selection signal SEL, and the charge Q stored in FD 55 and the charge Q Ｄ１ The signal indicating the level corresponding to the reset noise RST KTC2 is converted from analog to digital as the sum of the measurement pixel signal, the preliminary measurement pixel signal, and the noise pixel signal, and stored in the storage unit 240 (step S312). In addition, the correction calculation unit 234 of the signal processing unit 230 uses the information on the measurement pixel signal, the preliminary measurement pixel signal, and the noise pixel signal stored in the storage unit 240 to separate the signal into the measurement pixel signal, the preliminary measurement pixel signal, and the noise pixel signal, and stores them in the storage unit 240.

[0135] Next, the correction calculation unit 234 calculates the estimated measured charge Q according to equations (2) and (4). ｌｃ Q ｍｃ The saturation level of the charge Q is determined by performing the calculation (step S314). Next, the correction calculation unit 234 generates a pixel signal Qr that may include correction processing based on the determined saturation level, according to equations (5), (6), etc. (step S316).

[0136] Thus, the exposure operation of the PWLR method and the preliminary measurement charge Q for obtaining the characteristics of the pixel 32 are obtained. Ｄ１ By performing the injection operation during the imaging operation, it becomes possible to separate and measure the measured pixel signal, the preliminary measured pixel signal, and the noise pixel signal. This makes it possible to generate a pixel signal Qr that has undergone correction processing for variations due to the characteristics of the pixel 32.

[0137] As described above, according to this embodiment, the discharge transistor 59 is given a preliminary measurement potential (V Ｄ１With the output signal OFG supplied, the preliminary measured charge Q is applied to the cathode terminal of the photodiode 51. Ｄ１ Inject charge Q Ｄ１ A preliminary measurement pixel signal corresponding to this was generated. Since the preliminary measurement pixel signal reflects the characteristics of the emission transistor 59, it becomes possible to estimate the maximum accumulated charge at saturation in the PWLR method, which changes the potential of the emission signal OFG N times or more. This makes it possible to estimate the measurement pixel signal in the non-saturated region of the pixel 32, thereby suppressing variations in charge accumulation at saturation and obtaining a pixel signal that enables uniformity of the characteristics of the pixel 32.

[0138] At least a part of the imaging device and imaging method described in the above-described embodiments may be configured as hardware or as software. In the case of software configuration, a program that realizes at least a part of the functions of the information processing method and information processing device may be stored on a recording medium such as a flexible disk or CD-ROM, and loaded into a computer for execution. The recording medium is not limited to removable ones such as magnetic disks or optical disks, but may also be a fixed recording medium such as a hard disk drive or memory.

[0139] Furthermore, programs that implement at least some of the functions of the imaging device and imaging method may be distributed via communication lines such as the Internet (including wireless communication). In addition, the same programs may be encrypted, modulated, or compressed and distributed via wired or wireless lines such as the Internet, or stored on a recording medium.

[0140] Furthermore, this technology can take the following configuration.

[0141] (1) An imaging device comprising: a pixel array section having pixels that include at least a photoelectric conversion element that generates an electric charge by photoelectric conversion and an emission transistor that generates a potential barrier between a voltage source and the photoelectric conversion element; and a signal processing section that estimates a second measurement signal value corresponding to a second accumulated charge that is accumulated when a second potential barrier is generated, based on a first measurement signal value corresponding to a first accumulated charge that is accumulated when a first potential barrier is generated that is corresponding to a second potential.

[0142] (2) The imaging apparatus according to (1), further comprising a control unit that generates a third potential barrier higher than the height of the second potential barrier at a predetermined time after a first time point in time when the second potential barrier is generated.

[0143] (3) The imaging apparatus according to (2), wherein the signal processing unit generates a pixel signal for the pixel based on a value obtained by subtracting the estimated second measurement signal value from a third measurement signal value corresponding to the accumulated charge at a predetermined time elapsed from the time the third potential barrier was generated.

[0144] (4) The imaging apparatus according to (3), wherein the signal processing unit further estimates a fourth measurement signal value corresponding to a fourth potential and a fourth accumulated charge that is accumulated when a fourth potential barrier is generated which is higher than the second potential barrier and lower than the third potential barrier, based on the first measurement signal value.

[0145] (5) The imaging apparatus according to (4), wherein the signal processing unit generates a pixel signal for the pixel based on the value obtained by subtracting the fourth measurement signal value from the third measurement signal value.

[0146] (6) The imaging apparatus according to (5), wherein the signal processing unit estimates the second measurement signal value based on the first difference between the first measurement signal value and the first reference value.

[0147] (7) The imaging apparatus according to (6), wherein the signal processing unit estimates the second measurement signal value based on the first difference value and the first power.

[0148] (8) The imaging apparatus according to (7), wherein the signal processing unit estimates the fourth measurement signal value based on the first difference value and the second square.

[0149] (9) The imaging apparatus according to (8), wherein the signal processing unit determines, based on the accumulated charge, whether or not the charge has accumulated beyond either the second potential barrier or the fourth potential barrier.

[0150] (10) The imaging apparatus according to (9), wherein the signal processing unit determines that charge has accumulated beyond the second potential barrier, and generates a pixel signal for the pixel based on a value obtained by subtracting the second measurement signal value estimated from the third measurement signal value.

[0151] (11) The imaging apparatus according to (10), wherein the signal processing unit determines that charge has accumulated beyond the fourth potential barrier, and generates a pixel signal for the pixel based on a value obtained by subtracting the fourth measurement signal value estimated from the third measurement signal value.

[0152] (12) The imaging apparatus according to (11), wherein the control unit injects the first stored charge from the voltage source via an exhaust transistor.

[0153] (13) The imaging apparatus according to (12), wherein the pixel comprises: a first transfer transistor connected to the photoelectric conversion element; a first storage unit connected to the photoelectric conversion element via the first transfer transistor; a second transfer transistor connected to the first storage unit; a third transfer transistor connected to the photoelectric conversion element; a second storage unit connected to the photoelectric conversion element via the third transfer transistor; a fourth transfer transistor connected to the second storage unit; and a floating diffusion layer connected to the first storage unit via the second transfer transistor and to the second storage unit via the fourth transfer transistor, which generates a voltage corresponding to the amount of stored charge.

[0154] (14) The imaging apparatus according to (13), further comprising a column signal processing unit that converts the potential of the floating diffusion layer into a digital measurement value.

[0155] (15) The imaging apparatus according to (14), wherein the control unit sequentially generates the second potential barrier, the fourth potential barrier, and the third potential barrier, and stores the accumulated charge photoelectrically converted by the photoelectric conversion element in the first storage unit via the second transfer transistor.

[0156] (16) The imaging apparatus according to (15), wherein the control unit stores the first stored charge in the second storage unit via the previous third transfer transistor.

[0157] (17) The imaging apparatus according to (16), wherein the control unit transfers the accumulated charge and the first accumulated charge to the floating diffusion layer in any order, and the column signal processing unit converts either the first measurement signal value or the third measurement signal value into the sum of the first measurement signal value and the third measurement signal value, and the signal processing unit generates the first measurement signal value and the third measurement signal value based on the converted either the first measurement signal value or the third measurement signal value and the sum of the first measurement signal value and the third measurement signal value.

[0158] (18) An imaging method for an imaging apparatus having a pixel array section having at least a photoelectric conversion element that generates an electric charge by photoelectric conversion and an emission transistor that generates a potential barrier between a voltage source and the photoelectric conversion element, the imaging method comprising a signal processing step of estimating a second measurement signal value corresponding to a second stored charge that is stored when a second potential barrier is generated, based on a first measurement signal value corresponding to a first stored charge that is stored when a first potential barrier is generated that is stored when a second.

[0159] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents.

[0160] 1: Imaging device, 21: Pixel array unit, 22: Control circuit (control unit), 32: Pixel, 35: Column signal processing circuit (column signal processing unit), 51: Photodiode (photoelectric conversion element), 52: First transfer transistor, 53: First memory unit (MEM1), 54: Second transfer transistor, 55: FD (floating diffusion layer), 56: Reset transistor, 59: Ejection transistor, 60: Third transfer transistor, 61: Second memory unit (MEM2), 62: Fourth transfer transistor, 230: Signal processing unit, a1: First power, am: Second power, OFD: Voltage source, Q Ｄ２ : Accumulated charge (first accumulated charge), Q ｓｌ : Maximum accumulated charge (second accumulated charge), Q ｓｍMaximum accumulated charge (4th accumulated charge), V Ｄ１ Potential (first potential), V ｌｏｎｇ Potential (second potential), V ｍｉｄ Potential (4th potential), V ｓｈｏｒｔ Potential (3rd potential)

Claims

1. An imaging device comprising: a pixel array section having pixels that include at least a photoelectric conversion element that generates an electric charge by photoelectric conversion and an emission transistor that generates a potential barrier between a voltage source and the photoelectric conversion element; and a signal processing section that estimates a second measurement signal value corresponding to a second accumulated charge that is accumulated when a second potential barrier is generated, based on a first measurement signal value corresponding to a first accumulated charge that is accumulated when a first potential barrier is generated that is corresponding to a second potential.

2. The imaging apparatus according to claim 1, further comprising a control unit that generates a third potential barrier higher than the height of the second potential barrier at a predetermined time after a first time point in time when the second potential barrier is generated.

3. The imaging apparatus according to claim 2, wherein the signal processing unit generates a pixel signal for the pixel based on a value obtained by subtracting the estimated second measurement signal value from a third measurement signal value corresponding to the accumulated charge at a predetermined time after a predetermined time has elapsed since the time the third potential barrier was generated.

4. The imaging apparatus according to claim 3, wherein the signal processing unit further estimates a fourth measurement signal value corresponding to a fourth potential and a fourth accumulated charge accumulated when a fourth potential barrier is generated that is higher than the second potential barrier and lower than the third potential barrier, based on the first measurement signal value.

5. The imaging apparatus according to claim 4, wherein the signal processing unit generates a pixel signal for the pixel based on the value obtained by subtracting the fourth measurement signal value from the third measurement signal value.

6. The imaging apparatus according to claim 5, wherein the signal processing unit estimates the second measurement signal value based on a first difference value between the first measurement signal value and the first reference value.

7. The imaging apparatus according to claim 6, wherein the signal processing unit estimates the second measurement signal value based on the first difference value and the first power.

8. The imaging apparatus according to claim 7, wherein the signal processing unit estimates the fourth measurement signal value based on the first difference value and the second square.

9. The imaging apparatus according to claim 8, wherein the signal processing unit determines, based on the accumulated charge, whether or not the charge has accumulated beyond either the second potential barrier or the fourth potential barrier.

10. The imaging apparatus according to claim 9, wherein the signal processing unit determines that charge has accumulated beyond the second potential barrier, and generates a pixel signal for the pixel based on a value obtained by subtracting the second measurement signal value estimated from the third measurement signal value.

11. The imaging apparatus according to claim 10, wherein when the signal processing unit determines that charge has accumulated beyond the fourth potential barrier, it generates a pixel signal for the pixel based on a value obtained by subtracting the fourth measurement signal value estimated from the third measurement signal value.

12. The imaging apparatus according to claim 11, wherein the control unit injects the first stored charge from the voltage source via an exhaust transistor.

13. The imaging apparatus according to claim 12, wherein the pixel comprises: a first transfer transistor connected to the photoelectric conversion element; a first storage unit connected to the photoelectric conversion element via the first transfer transistor; a second transfer transistor connected to the first storage unit; a third transfer transistor connected to the photoelectric conversion element; a second storage unit connected to the photoelectric conversion element via the third transfer transistor; a fourth transfer transistor connected to the second storage unit; and a floating diffusion layer connected to the first storage unit via the second transfer transistor and to the second storage unit via the fourth transfer transistor, which generates a voltage corresponding to the amount of accumulated charge.

14. The imaging apparatus according to claim 13, further comprising a column signal processing unit that converts the potential of the floating diffusion layer into a digital measurement value.

15. The imaging apparatus according to claim 14, wherein the control unit sequentially generates the second potential barrier, the fourth potential barrier, and the third potential barrier, and stores the accumulated charge photoelectrically converted by the photoelectric conversion element in the first storage unit via the second transfer transistor.

16. The imaging apparatus according to claim 15, wherein the control unit stores the first accumulated charge in the second storage unit via the preceding third transfer transistor.

17. The imaging apparatus according to claim 16, wherein the control unit transfers the accumulated charge and the first accumulated charge to the floating diffusion layer in any order, and the column signal processing unit converts either the first measurement signal value or the third measurement signal value into the sum of the first measurement signal value and the third measurement signal value, and the signal processing unit generates the first measurement signal value and the third measurement signal value based on the converted either the first measurement signal value or the third measurement signal value and the sum of the first measurement signal value and the third measurement signal value.

18. An imaging method for an imaging apparatus having a pixel array section having at least a photoelectric conversion element that generates an electric charge by photoelectric conversion and an emission transistor that generates a potential barrier between a voltage source and the photoelectric conversion element, the imaging method comprising a signal processing step of estimating a second measurement signal value corresponding to a second accumulated charge accumulated when a second potential barrier is generated corresponding to a second potential, based on a first measurement signal value corresponding to a first accumulated charge accumulated when a first potential barrier is generated corresponding to a first potential.

Images