Radiation-resistant circuit having feedback structure, and semiconductor device comprising same

Abstract

A radiation-resistant circuit is disclosed. The radiation-resistant circuit comprises: a time delay circuit, which inverts an input signal that is input into a first terminal, so as to output the inverted input signal through a second terminal; a first output circuit, which mitigates a temporary voltage increase for a clock signal so as to output a first clock signal; a second output circuit, which mitigates a temporary voltage decrease for the clock signal so as to output a second clock signal; and a switch circuit, which responds to the inverted input signal so as to transmit any one of the first clock signal and the second clock signal to the first terminal.

Description

Radiation-resistant circuit having a feedback structure and a semiconductor device including the same

[0001] The present invention relates to an electronic circuit, and more particularly to a radiation-resistant circuit having a feedback structure capable of generating a stable clock signal by mitigating transient voltage changes induced in a clock signal due to radiation or noise, and a semiconductor device including the same.

[0002] A clock signal serves to provide a time signal in digital circuits. Clock signals are periodic and repetitive, generally having a square waveform and a constant period.

[0003] Clock signals are used for synchronization, timing, and pulse generation. During the synchronization process, the clock signal enables multiple digital circuits to perform tasks at the same time. For example, various operations of a processor are executed in synchronization with the clock signal.

[0004] In the timing process, the clock signal determines when data should be read and written. Data transmission and processing are controlled by the clock signal. In the pulse generation process, the clock signal generates periodic pulses to control the operation of various digital circuits. The clock signal plays an essential role in various electronic devices, such as computer CPUs, memory, or timers, and is a critical factor that determines the overall operating speed and efficiency of digital systems.

[0005] If a problem occurs with the clock signal, various errors may occur. For example, if the clock signal is unstable or its period is irregular, data transmission may not be properly carried out, potentially leading to data loss or errors.

[0006] If the clock signal is mismatched, the timing of the digital circuit becomes chaotic, causing the timing of data reading and writing to be out of sync, which can lead to the processing of incorrect data.

[0007] If the clock cycle becomes too long, the processing speed slows down, which may reduce the throughput of the digital system, and as a result, the performance of the digital system may degrade and the throughput of the digital system may decrease.

[0008] If the time it takes for the clock signal to arrive at each part of a digital circuit is different, clock skew occurs. As a result, some parts of the digital circuit may not receive the signal properly, and data may not be properly synchronized.

[0009] The technical problem that the present invention aims to solve is to provide a radiation-resistant circuit having a feedback structure capable of stabilizing a clock signal by mitigating (or eliminating) transient voltage changes induced in the clock signal due to radiation or noise, and a semiconductor device including the same.

[0010] A radiation-resistant circuit according to embodiments of the present invention comprises a time delay circuit that inverts an input signal input to a first terminal and outputs the inverted input signal through a second terminal, a first output circuit that mitigates a temporary voltage increase for a clock signal and outputs a first clock signal, a second output circuit that mitigates a temporary voltage decrease for the clock signal and outputs a second clock signal, and a switch circuit that transmits either the first clock signal or the second clock signal to the first terminal in response to the inverted input signal.

[0011] A semiconductor device according to embodiments of the present invention comprises a clock signal generator that outputs a clock signal and an internally radiated circuit connected to the clock signal generator, wherein the internally radiated circuit comprises a time delay circuit that inverts a signal input to a first terminal and outputs the inverted signal through a second terminal, a first output circuit that mitigates a temporary voltage increase for the clock signal and outputs a first clock signal, a second output circuit that mitigates a temporary voltage decrease for the clock signal and outputs a second clock signal, and a switch circuit that transmits either the first clock signal or the second clock signal to the first terminal in response to the inverted input signal.

[0012] The semiconductor device includes an input terminal connected to the first terminal, and further includes a digital circuit that uses either the first clock signal and the second clock signal received through the input terminal as an operating clock signal.

[0013] The first output circuit outputs the first clock signal that maintains the low level by mitigating the temporary voltage increase for the low level of the clock signal, and the second output circuit outputs the second clock signal that maintains the high level by mitigating the temporary voltage decrease for the high level of the clock signal.

[0014] The radiation-resistant circuit according to an embodiment of the present invention has the effect of mitigating (or eliminating) transient voltage changes induced in the clock signal due to radiation or noise, thereby generating a stable clock signal.

[0015] The radiation-resistant circuit according to an embodiment of the present invention can provide a strong defense function against radiation or noise that may affect the output clock signal, and thus has the effect of improving the operational stability and reliability of a digital system including the radiation-resistant circuit.

[0016] FIG. 1 is a conceptual block diagram of a radiation-resistant circuit according to an embodiment of the present invention.

[0017] Figure 2 is a timing diagram of signals related to the operation of the radiation resistance circuit shown in Figure 1.

[0018] FIG. 3 is a conceptual diagram showing an example of a clock tree including the radiation-resistant circuit illustrated in FIG. 1.

[0019] FIG. 4 is a conceptual diagram showing another embodiment of a clock tree including the radiation-resistant circuit illustrated in FIG. 1.

[0020] FIG. 5 is a conceptual diagram showing another embodiment of a clock tree including the radiation-resistant circuit shown in FIG. 1.

[0021] FIG. 6 is a conceptual diagram showing another embodiment of a clock tree including the radiation-resistant circuit shown in FIG. 1.

[0022] Figure 7 is a conceptual diagram of a clock mesh including the radiation-resistant circuit shown in Figure 1.

[0023] FIG. 1 is a conceptual block diagram of a radiation-resistant circuit according to an embodiment of the present invention, and FIG. 2 is a timing diagram of signals related to the operation of the radiation-resistant circuit shown in FIG. 1.

[0024] Referring to FIGS. 1 and FIGS. 2, the semiconductor device (100) includes a time delay circuit (110), a first output circuit (130), a second output circuit (150), and a switch circuit (160).

[0025] The semiconductor device (100) is also called an integrated circuit (IC), a semiconductor chip, a radiation-resistant circuit, or a single output single event transient (SET) mitigation (SSM) circuit.

[0026] The radiation-resistant circuit (100) refers to an electronic circuit capable of minimizing adverse effects of radiation. The radiation-resistant circuit (100) can be applied primarily to electronic devices requiring high reliability, such as spacecraft, satellites, nuclear power plants, or radiation environments.

[0027] The time delay circuit (110) inverts the input signal (XOUT) input to the first terminal (also called the 'first node' IT) and outputs the inverted input signal ( / XOUT) through the second terminal (also called the 'second node' OT).

[0028] The first terminal (IT) may be an input terminal of the radiation-resistant circuit (100) and simultaneously an input terminal of another digital circuit connected to the radiation-resistant circuit (100). Accordingly, from the perspective of the radiation-resistant circuit (100), 'XOUT' is an input signal of the radiation-resistant circuit (100) and simultaneously an output signal transmitted to another digital circuit, and from the perspective of the other digital circuit, 'XOUT' is an input signal.

[0029] The time delay circuit (110) delays a signal (XOUT), such as a clock signal (Xpsm or Xnsm), input through the first terminal (IT) by half a cycle of the clock signal (Xpsm or Xnsm) and outputs an inverted clock signal ( / XOUT) through the second terminal (OT).

[0030] The time delay circuit (110) includes a plurality of inverters (111, 113, 117, and 119) connected in series and a transmission gate (115).

[0031] Inverters (111 and 113) function as input buffers for the transmission gate (115), and inverters (117 and 119) function as output buffers for the transmission gate (115).

[0032] An input buffer including inverters (111 and 113) and an output buffer including inverters (117 and 119) perform the function of separating a first terminal (IT) and a second terminal (OT), the input buffer performs the function of mitigating the interaction between a signal (XOUT) and a transmission gate (115), and the output buffer performs the function of mitigating the interaction between a transmission gate (115) and an output signal ( / XOUT).

[0033] As the power supply voltage (VDD) is supplied to the gate of the NMOS transistor at the transmission gate (115) and the ground voltage (GND) is supplied to the gate of the PMOS transistor, the transmission gate (115) that performs the switching function always remains in the ON state.

[0034] The signal (XOUT) passing through the transmission gate (115) is delayed according to the resistance component and parasitic capacitor component of the transmission gate (115). The greater the resistance component and parasitic capacitor component, the greater the delay time.

[0035] In the design phase for the time delay circuit (110), when the resistance component and parasitic capacitor component of the transmission gate (115) are adjusted, the time delay circuit (110) can delay the signal (XOUT) by half a period of the signal (XOUT) and output an inverted signal ( / XOUT) through the second terminal (OT).

[0036] The first output circuit (130) can mitigate (or eliminate) the temporary voltage increase for the clock signal (CLK) and output the stabilized first clock signal (Xpsm) to the first line (FBL1).

[0037] The second output circuit (150) can mitigate (or eliminate) the temporary voltage drop for the clock signal (CLK) and output a stabilized second clock signal (Xnsm) to the second line (FBL2).

[0038] The first output circuit (130) can be implemented as a mitigation circuit to mitigate a positive single event transient (SET).

[0039] Here, the single-event transient state (SET) refers to the phenomenon where the logic level of a signal changes due to the occurrence of a transient pulse.

[0040] A positive SET mitigation circuit (130) refers to a circuit that performs the function of protecting a semiconductor device (100) from a temporary voltage increase (PSET) of a clock signal (CLK) caused by external factors (HI), such as radiation particles or noise. When such a temporary voltage increase (PSET) occurs, the function of the semiconductor device (100) or a digital system including the semiconductor device (100) may be temporarily distorted or an error may occur.

[0041] As illustrated in FIG. 2, when the low level (L) of the clock signal (CLK) is temporarily transitioned to a high level (H) due to radiation or a soft error (HI), etc., the positive SET relaxation circuit (130) can generate a first clock signal (Xpsm) that maintains the low level (L) by relaxing or removing the temporary voltage increase (PSET) included in the clock signal (CLK), but the negative SET relaxation circuit (150) cannot relax or remove the temporary voltage increase (PSET).

[0042] A temporary increase in voltage (PSET) can be restored to a low level (Xpsm=L) by a positive SET relaxation circuit (130), but cannot be restored to a low level (L) by a negative SET relaxation circuit (150).

[0043] The second output circuit (150) can be implemented as a mitigation circuit to mitigate a negative single event transient (SET).

[0044] The negative SET mitigation circuit (150) refers to a circuit that performs the function of protecting the semiconductor device (100) from a temporary voltage drop (NSET) of the clock signal (CLK) caused by external factors (HI), such as radiation particles or noise. When such a temporary voltage drop (NSET) occurs, the function of the semiconductor device (100) or the digital system including the semiconductor device (100) may be temporarily distorted or an error may occur.

[0045] As illustrated in FIG. 2, when the high level (H) of the clock signal (CLK) is temporarily transitioned to a low level (L) due to radiation or soft error (HI), etc., the negative SET relaxation circuit (150) can generate a second clock signal (Xnsm) that maintains the high level (H) by relaxing or removing the temporary voltage drop (NSET) included in the clock signal (CLK), but the positive SET relaxation circuit (130) cannot relax or remove the temporary voltage drop (NSET).

[0046] A temporary voltage drop (NSET) can be restored to a high level (Xnsm=H) by a negative SET relaxation circuit (150), but cannot be restored to a high level (H) by a positive SET relaxation circuit (130).

[0047] At least one of a transient voltage increase (PSET) or a transient voltage decrease (NSET) may be generated by at least one of radiation or noise.

[0048] In response to the inverted input signal ( / XOUT), the switch circuit (160) transmits the first clock signal (Xpsm) to the first terminal (IT) through the first line (FBL1) (this is also called 'feedback') or transmits the second clock signal (Xnsm) to the first terminal (IT) through the second line (FBL2).

[0049] The switch circuit (160) includes a first switch (170) that controls the transmission of a first clock signal (Xpsm) to a first terminal (IT) in response to an inverted input signal ( / XOUT), and a second switch (190) that controls the transmission of a second clock signal (Xnsm) to the first terminal (IT).

[0050] The first switch (170) and the second switch (190) operate complementarily. The fact that the switches operate complementarily means that when one switch (either one of 170 and 190) is turned on, the other switch (the other one of 170 and 190) is turned off, or the two switches (170 and 190) operate alternately.

[0051] For example, one of the first switch (170) and the second switch (190) is a PMOS transistor, and the other of the first switch (170) and the second switch (190) is an NMOS transistor.

[0052] As shown in FIG. 2, the first clock signal (Xpsm), the second clock signal (Xnsm), and the input signal (XOUT) each have the same phase.

[0053] At the first time point (T1), when a signal (XOUT) having a high level (H) is input to the first terminal (IT), the time delay circuit (110) outputs an inverted signal ( / XOUT) having a low level (L) through the second terminal (OT).

[0054] As an inverted signal ( / XOUT) having a low level (L) is output, the NMOS transistor (170) is turned off and the PMOS transistor (190) is turned on, so the second clock signal (Xnsm) of the second output circuit (150) is output (or fed back) to the first terminal (IT) through the second line (FBL2).

[0055] When a signal (XOUT=Xnsm) having a low level (L) is input to the first terminal (IT) at the second time point (T2), the time delay circuit (110) outputs an inverted signal ( / XOUT) having a high level (H) through the second terminal (OT).

[0056] As an inverted signal ( / XOUT) having a high level (H) is output, the NMOS transistor (170) is turned on and the PMOS transistor (190) is turned off, so the first clock signal (Xpsm) of the first output circuit (130) is output (or fed back) to the first terminal (IT) through the first line (FBL1).

[0057] When a signal (XOUT=Xpsm) having a high level (H) at the third time point (T3) is input to the first terminal (IT), the time delay circuit (110) outputs an inverted signal ( / XOUT) having a low level (L) through the second terminal (OT).

[0058] As an inverted signal ( / XOUT) having a low level (L) is output, the NMOS transistor (170) is turned off and the PMOS transistor (190) is turned on, so the second clock signal (Xnsm) of the second output circuit (150) is output to the first terminal (IT) through the second line (FBL2).

[0059] When a signal (XOUT=Xnsm) having a low level (L) is input to the first terminal (IT) at the fourth time point (T4), the time delay circuit (110) outputs an inverted signal ( / XOUT) having a high level (H) through the second terminal (OT).

[0060] As an inverted signal ( / XOUT) having a high level (H) is output, the NMOS transistor (170) is turned on and the PMOS transistor (190) is turned off, so the first clock signal (Xpsm) of the first output circuit (130) is output to the first terminal (IT) through the first line (FBL1).

[0061] When a signal (XOUT=Xpsm) having a high level (H) is input to the first terminal (IT) at the fifth time point (T5), the time delay circuit (110) outputs an inverted signal ( / XOUT) having a low level (L) through the second terminal (OT).

[0062] As an inverted signal ( / XOUT) having a low level (L) is output, the NMOS transistor (170) is turned off and the PMOS transistor (190) is turned on, so the second clock signal (Xnsm) of the second output circuit (130) is output to the first terminal (IT) through the second line (FBL2).

[0063] In this way, the switch circuit (160) alternately transmits the first clock signal (Xpsm) and the second clock signal (Xnsm) to the first terminal (IT) according to the voltage level of the signal ( / XOUT) of the second terminal (OT).

[0064] FIG. 3 is a conceptual diagram illustrating an embodiment of a clock tree including the radiation-resistant circuit illustrated in FIG. 1. Referring to FIG. 3, a clock tree (200_1, or semiconductor device) corresponding to a clock distribution network includes a clock source (210), clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), buffers (230_1 to 230_4), and loads (240_1 to 240_4). Each of the loads (240_1 to 240_4) may be a D-flip-flop (DFF), but is not limited thereto.

[0065] Each configuration (210, 220, 222_1, 222_2, 224_1~224_4, 230_1~230_4, and 240_1~240_4) refers to an electronic circuit or digital circuit that operates in response to a clock signal.

[0066] Referring to FIGS. 1 and FIGS. 3, the clock source (210) can be implemented as a clock signal generator or oscillator that generates a clock signal (CLK).

[0067] Among the clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), the clock tree cell (220) connected to the clock source (210) can be implemented as the radiation-resistant circuit (100) shown in FIG. 1.

[0068] The first terminal (IT) of the radiation circuit (100) is connected to the clock input terminal of each clock tree cell (222_1 and 222_2).

[0069] FIG. 4 is a conceptual diagram showing another embodiment of a clock tree including the radiation-resistant circuit illustrated in FIG. 1. Referring to FIG. 4, a clock tree (200_2, or semiconductor device) corresponding to a clock distribution network includes a clock source (210), clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), buffers (230_1 to 230_4), and loads (240_1 to 240_4).

[0070] Among the clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), each clock tree cell (221_1 and 222_2) can be implemented as the radiation-resistant circuit (100) shown in FIG. 1.

[0071] Each clock tree cell (222_1 and 222_2) receives a clock signal (CLK) output from the clock tree cell (220), and the first terminal (IT) of the clock tree cell (222_1) is connected to the clock input terminal of each clock tree cell (224_1 and 224_2), and the first terminal (IT) of the clock tree cell (222_2) is connected to the clock input terminal of each clock tree cell (224_3 and 224_4).

[0072] FIG. 5 is a conceptual diagram showing another embodiment of a clock tree including the radiation-resistant circuit illustrated in FIG. 1. Referring to FIG. 4, a clock tree (200_3, or semiconductor device) corresponding to a clock distribution network includes a clock source (210), clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), buffers (230_1 to 230_4), and loads (240_1 to 240_4).

[0073] Among the clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), each clock tree cell (224_1 to 224_4) can be implemented as a radiation-resistant circuit (100) as shown in FIG. 1.

[0074] Each clock tree cell (224_1 and 224_2) receives a clock signal (CLK) output from the clock tree cell (222_1), each clock tree cell (224_3 and 224_4) receives a clock signal (CLK) output from the clock tree cell (222_2), and the first terminal (IT) of each clock tree cell (224_1 and 224_2) is connected to the clock input terminal of each buffer (230_1 to 230_4).

[0075] FIG. 6 is a conceptual diagram showing another embodiment of a clock tree including the radiation-resistant circuit illustrated in FIG. 1. Referring to FIG. 6, a clock tree (200_4, or semiconductor device) corresponding to a clock distribution network includes a clock source (210), clock tree cells (220, 222_1, 222_2, and 224_1 to 224_4), buffers (230_1 to 230_4), and loads (240_1 to 240_4).

[0076] Referring to FIGS. 3 and FIGS. 6, each buffer (230_1 to 230_4) can be implemented with the radiation-resistant circuit (100) shown in FIG. 1.

[0077] FIG. 7 is a conceptual diagram of a clock mesh including the radiation-resistant circuit illustrated in FIG. 1. Referring to FIG. 7, a clock mesh (clock mesh, 300, or semiconductor device) corresponding to a clock distribution network includes a clock source (210), pre-mesh drivers (320, 322_1, and 322_2), mesh drivers (324_1 to 324_4), mesh nets (330), buffers (340_1 to 340_4), and loads (350_1 to 350_4).

[0078] As described with reference to FIGS. 3 to 6, which of the configurations (320, 322_1, 322_2, 324_1 to 324_4, and 340_1 to 340_4) is replaced with the radiation-resistant circuit (100) shown in FIG. 1 can be modified in various ways according to design specifications.

[0079] A semiconductor device including a clock distribution network (200_1, 200_2, 200_3, 200_4, or 300) may be implemented as an integrated circuit, a semiconductor chip, a CPU, a GPU, a processor, an ASIC (Application-Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), a SoC (System on Chip), a memory device, a memory system including said memory device, or a communication system (e.g., a communication system such as Ethernet or Wi-Fi).

[0080] As described with reference to FIGS. 3 to 7, in a clock distribution network (200_1, 200_2, 200_3, 200_4, or 300), the configuration that supplies a clock signal to the radiation-resistant circuit (100) from the perspective of the radiation-resistant circuit (100) performs the function of a clock signal generator.

[0081] The present invention has been described with reference to embodiments illustrated in the drawings, but this is merely illustrative, and those skilled in the art will understand that various modifications and equivalent alternative embodiments are possible therefrom. Accordingly, the true technical scope of protection of the present invention should be determined by the technical spirit of the appended claims.

[0082] The present invention can be used in electronic circuits or semiconductor devices.

Claims

1. A time delay circuit that inverts an input signal input through a first terminal and outputs the inverted input signal through a second terminal; A first output circuit that outputs a first clock signal by mitigating a transient voltage increase for a clock signal; A second output circuit that outputs a second clock signal by mitigating a temporary voltage drop for the above clock signal; and A radiation-resistant circuit comprising a switch circuit that transmits either the first clock signal or the second clock signal to the first terminal in response to the inverted input signal.

2. In Paragraph 1, The first output circuit outputs the first clock signal that maintains the low level by mitigating the transient voltage increase for the low level of the clock signal, and The above second output circuit is a radiation-resistant circuit that outputs the second clock signal, which maintains the high level by mitigating the temporary voltage drop for the high level of the clock signal.

3. In Paragraph 2, At least one of the above-mentioned transient voltage increase or the above-mentioned transient voltage decrease is a radiation-resistant circuit generated by at least one of radiation or noise.

4. In paragraph 1, the switch circuit is, A first switch that controls the transmission of the first clock signal to the first terminal in response to the inverted input signal; and A radiation-resistant circuit comprising a second switch that controls the transmission of the second clock signal to the first terminal in response to the inverted second signal.

5. In Paragraph 4, The first switch and the second switch above are a radiation-resistant circuit that operates complementarily.

6. In Paragraph 4, One of the first switch and the second switch is a PMOS transistor, and A radiation-resistant circuit in which the other of the first switch and the second switch is an NMOS transistor.

7. In Paragraph 1, A radiation-resistant circuit in which the first clock signal, the second clock signal, and the input signal each have the same phase.

8. A clock signal generator that outputs a clock signal; and It includes an internally radiated circuit connected to the above clock signal generator, and The above-mentioned internally radiated circuit is, A time delay circuit that inverts a signal input to a first terminal and outputs the inverted signal through a second terminal; A first output circuit that outputs a first clock signal by mitigating a temporary voltage increase for the above clock signal; A second output circuit that outputs a second clock signal by mitigating a temporary voltage drop for the above clock signal; and A semiconductor device comprising a switch circuit that transmits either the first clock signal or the second clock signal to the first terminal in response to the inverted input signal.

9. In Paragraph 8, A semiconductor device further comprising a digital circuit including an input terminal connected to the first terminal, and using either of the first clock signal and the second clock signal received through the input terminal as an operating clock signal.

10. In Paragraph 8, The first output circuit outputs the first clock signal that maintains the low level by mitigating the transient voltage increase for the low level of the clock signal, and The above second output circuit is a semiconductor device that outputs the second clock signal, which maintains the high level by mitigating the temporary voltage drop for the high level of the clock signal.

11. In Paragraph 10, At least one of the above-mentioned temporary voltage increase or the above-mentioned temporary voltage decrease is generated by at least one of radiation or noise, and The above switch circuit is, A first switch that controls the transmission of the first clock signal to the first terminal in response to the inverted input signal; and A semiconductor device comprising a second switch that controls the transmission of the second clock signal to the first terminal in response to the inverted second signal.

12. In Paragraph 11, The first switch and the second switch are semiconductor devices that operate complementarily.

13. In Paragraph 8, The above semiconductor device is a semiconductor device that is a clock distribution network.

14. In Paragraph 8, The above semiconductor device is a semiconductor device that is a CPU, GPU, ASIC (Application-Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), SoC (System on Chip), memory device, or communication device.

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