Circuit board and semiconductor package

Abstract

This circuit board comprises: a core layer; an electrode layer disposed on the core layer; a first build-up layer disposed on one surface of the core layer; and a second build-up layer disposed on the other surface of the core layer, wherein: the core layer includes a first core layer, a second core layer disposed on the first core layer, and a third core layer disposed on the second core layer; the electrode layer includes a first electrode layer disposed on one surface of the core layer, a second electrode layer disposed between the first core layer and the second core layer, a third electrode layer disposed between the second core layer and the third core layer, and a fourth electrode layer disposed on the other surface of the core layer; the second electrode layer includes a plurality of first holes; the third electrode layer includes a plurality of second holes; and the plurality of first holes and the plurality of second holes are arranged misaligned in a vertical direction.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products, such as AI and servers, are progressing toward multifunctionality and high speed, and to respond to this trend, semiconductor chip manufacturing technology is also developing rapidly.

[0004] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on the chips is growing. To meet this trend, not only are the wiring densities, lengths, and widths of circuit boards becoming finer, but there is also a trend toward high-layer, large-area designs.

[0005] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the applied circuit boards is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to each other, which was previously considered only from the perspective of conventional semiconductor packaging.

[0006] A circuit board is a device in which circuit line patterns are arranged using a conductive material, such as copper, on an electrically insulating substrate; it is a general term for the package board immediately before mounting electronic components. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed and fixed onto the surface.

[0007] A circuit board includes a plurality of insulating layers arranged in a vertical direction and a plurality of via electrodes and pads arranged on each of the plurality of insulating layers. Recent circuit boards, which are trending toward high multi-layer and large-area designs, have problems such as low productivity and reduced yield when arranging via electrodes and pads within the core layer as the thickness of the core layer increases to prevent warping.

[0008]

[0009] The present invention provides a circuit board and a semiconductor package that facilitate the implementation of fine pitch in the circuit area while maintaining a thick core layer of the circuit board, and can increase productivity and yield.

[0010]

[0011] A circuit board according to the present embodiment comprises a core layer; an electrode layer disposed on the core layer; a first build-up layer disposed on one side of the core layer; and a second build-up layer disposed on the other side of the core layer, wherein the core layer comprises a first core layer, a second core layer disposed on the first core layer, and a third core layer disposed on the second core layer, and wherein the electrode layer comprises a first electrode layer disposed on one side of the core layer, a second electrode layer disposed between the first core layer and the second core layer, a third electrode layer disposed between the second core layer and the third core layer, and a fourth electrode layer disposed on the other side of the core layer, wherein the second electrode layer comprises a plurality of first holes, and the third electrode layer comprises a plurality of second holes, and the plurality of first holes and the plurality of second holes are arranged to be offset in a vertical direction.

[0012] The plurality of first holes and the plurality of second holes may each be holes for gas discharge within the core layer.

[0013] It includes a first wiring portion disposed on one side of the second core layer and a second wiring portion disposed on the other side of the second core layer, wherein the first wiring portion is disposed on the third electrode layer and the second wiring portion may be disposed on the second electrode layer.

[0014] It includes a sixth wiring section disposed on the upper surface of the third core layer and a fourth wiring section disposed on the lower surface of the first core layer, wherein the fourth wiring section is disposed on the first electrode layer.

[0015] The above-mentioned sixth wiring section may be disposed on the above-mentioned fourth electrode layer.

[0016] It may include a via that electrically connects the first wiring section, the second wiring section, the fourth wiring section, and the sixth wiring section.

[0017] It includes a first via portion penetrating the second core layer, and the first via portion may include a first region and a second region having the same vertical length.

[0018] It includes a second via portion penetrating the first core layer and a fifth via portion penetrating the third core layer, and the second via portion and the fifth via portion may each include a third region and a fourth region with different vertical lengths.

[0019] The thickness of the second core layer may be thicker than the thickness of the first core layer or the third core layer.

[0020] The first electrode layer and the fourth electrode layer each include a first pad portion, and the first pad portion may include a region that is folded at least once.

[0021] A semiconductor package according to the present embodiment comprises: a core layer; an electrode layer disposed on the core layer; a first build-up layer disposed on one side of the core layer; a second build-up layer disposed on the other side of the core layer; and a semiconductor chip disposed on the surface of the first build-up layer or the second build-up layer. The core layer comprises a first core layer, a second core layer disposed on the first core layer, and a third core layer disposed on the second core layer. The electrode layer comprises a first electrode layer disposed on one side of the core layer, a second electrode layer disposed between the first core layer and the second core layer, a third electrode layer disposed between the second core layer and the third core layer, and a fourth electrode layer disposed on the other side of the core layer. The second electrode layer comprises a plurality of first holes, and the third electrode layer comprises a plurality of second holes. The plurality of first holes and the plurality of second holes are arranged to be offset in a vertical direction.

[0022]

[0023] In this embodiment, by forming the core layer into multiple layers, the electrode layer disposed on the core layer is also provided in multiple layers, which has the advantage of minimizing the occurrence of warping of the circuit board due to the high multi-layer structure.

[0024] In addition, compared to a single layer of core and electrode layers, a relatively thin thickness can be formed through multiple layers of core and electrode layers, so holes and pads can be processed using a laser method rather than a drilling method, and thus there is an advantage of improved production efficiency.

[0025] In addition, since the thickness of each electrode layer can be reduced, the electrode layers can be processed by the mSAP (Modified Semi-Additive Process) method; compared to the tenting method, this offers the advantage of easier implementation of fine pitch and the formation of high-density wiring.

[0026] In addition, by reducing the size of the pad portions within the electrode layer, the residual copper content can be lowered, thereby resolving the problem of reduced moisture removal efficiency due to the residual copper content within the circuit board.

[0027]

[0028] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0029] FIG. 2 is a cross-sectional view of a core layer according to an embodiment of the present invention.

[0030] FIG. 3 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0031] FIG. 4 is an enlarged view of A in FIG. 3.

[0032] FIG. 5 is a perspective view of an electrode layer according to an embodiment of the present invention.

[0033] FIG. 6 is an exploded perspective view of an electrode layer according to an embodiment of the present invention.

[0034] FIG. 7 is a plan view of an outer electrode layer according to an embodiment of the present invention.

[0035] FIG. 8 is a plan view of an inner electrode layer according to an embodiment of the present invention.

[0036] FIG. 9 is a cross-sectional view of a circuit board showing an electrode layer according to an embodiment of the present invention.

[0037] FIG. 10 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0038]

[0039] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0040] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0041] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0042] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0043] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0044] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0045] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0046] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0047] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0048] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0049] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0050] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0051] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0052] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0053] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0054] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a core layer according to an embodiment of the present invention, FIG. 3 is a cross-sectional view of a circuit board according to an embodiment of the present invention, and FIG. 4 is an enlarged view of A of FIG. 3.

[0055] Referring to FIGS. 1 to 4, a circuit board (10) according to an embodiment of the present invention may include a core layer (100), a first build-up layer (200) disposed on one side of the core layer (100), a second build-up layer (300) disposed on the other side of the core layer (100), and a plurality of pads and via electrodes.

[0056] The core layer (100) may be positioned in the center with respect to the vertical direction of the circuit board (10). The core layer (100) may have a structure in which a plurality of insulating layers are stacked in the vertical direction. The core layer (100) can prevent deformation such as bending or warping of the circuit board (10) caused by external factors such as heat between the first build-up layer (200) and the second build-up layer (300).

[0057] The core layer (100) may include a first core layer (110), a second core layer (120) disposed on the first core layer (110), and a third core layer (130) disposed on the second core layer (120). Based on the second core layer (120), the first core layer (110) and the third core layer (130) may be disposed on one side and the other side of the second core layer (120), respectively. For example, the first core layer (110) may be disposed on the lower surface of the second core layer (120), and the third core layer (130) may be disposed on the upper surface of the second core layer (120). The first core layer (110) and the third core layer (130) may each be implemented as a single layer, but are not limited thereto. As shown in FIG. 1, they may be implemented as two or more layers and placed on one side and the other side, respectively, with respect to the second core layer (120).

[0058] The first core layer (110) may include a first-1 core layer (112) and a first-2 core layer (114) arranged in a vertical direction. The first-2 core layer (114) may be placed on the first-1 core layer (112). The third core layer (130) may include a third-1 core layer (132) and a third-2 core layer (134) arranged in a vertical direction. The third-2 core layer (134) may be placed on the third-1 core layer (132). When the first core layer (110) and the third core layer (130) are implemented as a single layer, either the first-1 core layer (112) and the first-2 core layer (114), and either the third-1 core layer (132) or the third-2 core layer (134) may be omitted, respectively.

[0059] Based on the vertical direction, the thickness (H1) of the second core layer (120) may be thicker than the thickness (H2) of the first core layer (110) or the third core layer (130). According to an embodiment, the thickness (H1) of the second core layer (120) may be 100 µm or more and 300 µm or less in order to prevent bending of the circuit board and to facilitate processing of the via electrode (150). For example, the via electrode (150) penetrating the first core layer (120) has a structure in which the entire via hole of the second core layer (120) is filled with metal, which is advantageous for improving mechanical properties such as heat dissipation and / or electrical properties such as power and signal transmission. If the thickness of the second core layer (120) exceeds 300 μm, it is difficult to fill the entire via hole with metal and also difficult to process the via hole; therefore, according to the embodiment, it is preferable that the thickness of the second core layer (120) be provided within the range described above. In addition, the thickness (H2) of the first core layer (110) or the third core layer (130) may be 60 μm or more and 80 μm or less in order to prevent bending of the circuit board and to advantageously control the total thickness of the core layer (100). In this case, the ratio of the thickness of the second core layer (120) to the first core layer (110) or the second core layer (120) to the third core layer (130) may be 1:0.2 to 1:0.8.

[0060] If the ratio of the thickness of the first core layer (110) or the third core layer (130) to the second core layer (120) is 0.2 or less, the thickness of the core layer (100) may not be sufficiently secured, and thus durability issues such as bending of the circuit board (10) may occur.

[0061] If the ratio of the thickness of the first core layer (110) or the third core layer (130) to the second core layer (120) exceeds 0.8, the manufacturing cost for forming the core layer (100) increases relatively, or the yield or productivity decreases, which reduces the utility of the core layer formation structure through multiple layers and makes it difficult to form via electrodes within the second core layer (120).

[0062] The thickness of the core layer (100), that is, the sum of the thicknesses in the vertical direction of the first to third core layers (110, 120, 130), may be 200 µm or more and 1500 µm or less.

[0063] The second core layer (120) may be a prepreg (PPG) containing glass fibers within the resin. Accordingly, glass fibers may be disposed within the resin constituting the second core layer (120). As shown in FIG. 3, a plurality of vertically stacked glass fibers may be disposed within the second core layer (120). A first glass fiber (121) and a second glass fiber (122) disposed below the first glass fiber (121) may be disposed within the resin constituting the second core layer (120). The glass fibers disposed within the second core layer (120) have a structure in which a large number of glass fibers disposed in the first core layer (110) and the third core layer (130) are stacked in a vertical direction, thereby preventing warping that occurs during the process of the circuit board.

[0064] The first core layer (110) and the third core layer (130) may each be a prepreg (PPG) containing glass fibers (112, 132) within the resin. Accordingly, glass fibers (112, 132) may be disposed within the resin constituting the first core layer (110) and the third core layer (130). As shown in FIG. 3, a single layer of glass fibers (112, 132) may be disposed within the first core layer (110) and the third core layer (130), respectively. Thus, by stacking the thickness of the first core layer (110) and the third core layer (130) thinner than the thickness of the second core layer (120), it is easier to control the overall thickness of the core layer (100) and improve the freedom of wiring design.

[0065] Meanwhile, the glass fibers disposed within the resin constituting the first core layer (110) and the third core layer (130) are not limited to a single layer, and multiple layers of glass fibers may each be disposed within the resin constituting the first core layer (110) and the third core layer (130).

[0066] According to the embodiment, the first core layer (110) and the third core layer (130) are each formed as two layers, but are not limited thereto. In order to control the overall thickness of the core layer (100), the first core layer (110) and the third core layer (130) can each be stacked in multiple layers. Additionally, by arranging the number of stacked insulating layers constituting the first core layer (110) and the third core layer (130) differently, warping that occurs during the process of the circuit board or warping that occurs after the process can be controlled.

[0067] The core layer (100) provided as a single layer according to the prior art has a thick thickness, so when processing via holes, it must be processed using a mechanical drill. When using a mechanical drill, it is difficult to narrow the spacing between via holes, the processing time for the mechanical drill is long, and expensive processing costs are incurred. In addition, when placing via electrodes through a plating process within the via holes of the core layer (100) provided as a single layer, it is difficult to fill the entire interior of the via holes, so a metal layer having a predetermined thickness is placed only along the horizontal direction on the inner wall of the via holes. Therefore, there are limitations in improving mechanical and / or electrical characteristics such as heat dissipation, power transmission, electrical signal transmission, insertion loss, and resistance. However, according to a structure such as that of the present invention, the core layer (100) is implemented as a structure in which a plurality of insulating layers are stacked, and compared to a structure in which the core layer is implemented as a single layer, via holes of each core layer (100) can be formed using a laser as well as a mechanical drill, thereby lowering the manufacturing cost, and as shown in FIG. 3, the inside of the via holes of the core layer (100) can be easily filled with metal. In addition, according to the structure in which a plurality of insulating layers are stacked vertically, the degree of design freedom regarding the formation of pads and via electrodes is increased, and accordingly, there is an advantage that production efficiency can be improved.

[0068] The first build-up layer (200) and the second build-up layer (300) can be disposed on the upper and lower surfaces, respectively, of the core layer (100). The first build-up layer (200) can be disposed on the third core layer (130). The second build-up layer (300) can be disposed on the lower surface of the first core layer (110).

[0069] The first build-up layer (200) and the second build-up layer (300) may each include a plurality of insulating layers. The plurality of insulating layers of the first build-up layer (200) and the second build-up layer (300) may be arranged along the vertical direction on one side and the bottom side of the core layer (100), respectively. Each of the plurality of insulating layers has a thickness smaller than the thickness of each of the first to third core layers (110, 120, 130), and may be provided with a via electrode having a width smaller in the horizontal direction than the via electrode of the core layer (100). Accordingly, a finer pitch can be realized than that of the via electrode or wiring portion arranged within the core layer (100).

[0070] Based on the vertical direction, the thickness (H7) of each of the plurality of insulating layers constituting the first build-up layer (200) and the second build-up layer (300) may be thinner than the thickness (H2) of each of the insulating layers constituting the first core layer (110) and the third core layer (130). The thickness (H7) of the plurality of insulating layers constituting the first build-up layer (200) and the second build-up layer (300) may be 30 µm or more and 45 µm or less in order to secure insulation in the vertical direction and to arrange fine wiring and via electrodes. Accordingly, the ratio of the thickness (H2) of the insulating layer constituting the first core layer (110) or the third core layer (130) to the thickness (H7) of the insulating layer constituting the first build-up layer (200) and the second build-up layer (300) may be 1:0.3 to 1:0.8.

[0071] If the ratio of the thickness (H7) of the insulating layer constituting the first build-up layer (200) and the second build-up layer (300) to the thickness (H2) of the insulating layer constituting the first core layer (110) or the third core layer (130) is less than 0.3, delamination may occur due to stress applied to the thickness (H7) of the insulating layer constituting the first build-up layer (200) and the second build-up layer (300), and if it exceeds 0.8, a pattern having a spacing and width similar to the spacing and width of the via electrodes and / or wiring placed within the core layer (100) may be placed. That is, there may be difficulties in placing fine patterns, which not only reduces the degree of freedom of wiring design but also becomes a factor requiring a significant increase in the overall size and thickness of the circuit board (10), which may cause delamination and / or warping problems. In addition, when electrically connecting with a semiconductor device, the difference between the impedance matching or the wiring for transmitting signals or power and the terminals of the semiconductor device may be large, making it difficult to make a close connection between the circuit board (10) and the semiconductor device.

[0072] A plurality of insulating layers of the first build-up layer (200) may include a first insulating layer (211) disposed on the third core layer (130), a second insulating layer (212) disposed on the first insulating layer (211), a third insulating layer (213) disposed on the second insulating layer (212), a fourth insulating layer (214) disposed on the third insulating layer (213), a fifth insulating layer (215) disposed on the fourth insulating layer (214), a sixth insulating layer (216) disposed on the fifth insulating layer (215), and a seventh insulating layer (217) disposed on the sixth insulating layer (216).

[0073] A plurality of insulating layers of the second build-up layer (300) may include an eighth insulating layer (311) disposed on the lower surface of the first core layer (110), a ninth insulating layer (312) disposed on the lower surface of the eighth insulating layer (311), a tenth insulating layer (313) disposed on the lower surface of the ninth insulating layer (312), an eleventh insulating layer (314) disposed on the lower surface of the tenth insulating layer (313), a twelfth insulating layer (315) disposed on the lower surface of the eleventh insulating layer (314), a thirteenth insulating layer (316) disposed on the lower surface of the eleventh insulating layer (315), and a fourteenth insulating layer (317) disposed on the lower surface of the eleventh insulating layer (316).

[0074] The first to fourth insulating layers (211, 212, 213, 214, 215, 216, 217, 311, 312, 313, 314, 315, 316, 317) may each be any insulating material, such as photocurable and / or thermosetting insulating materials. As thermosetting insulating materials, insulating materials in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and prepregs (PPG) containing glass fibers within a resin may be used. In addition, the resins described above may be, for example, epoxy resin, bismaleimide triazine resin (BT resin), phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. When an insulating resin is used as a core, it may include reinforcing materials such as glass fibers or aramid fibers. Additionally, if it is a photocurable insulator, it may be a PID (Photo Imageable Dielectric).

[0075] When the insulating layer constituting the first build-up layer (200) and the second build-up layer (300) is prepreg (PPG), a single layer of glass fiber may be disposed within the resin constituting the insulating layer.

[0076] The circuit board (10) may include a protective layer. The protective layer may include a first protective layer (510) disposed on the surface of the first build-up layer (200) and a second protective layer (520) disposed on the surface of the second build-up layer (300). When a semiconductor device is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (510) and the second protective layer (520) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (510) and the second protective layer (520) may each utilize a photocurable insulating material. Accordingly, the first protective layer (510) and the second protective layer (520) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, it is not limited to this, and can be provided with various materials capable of performing low wettability with solder and the resulting short-circuit prevention function between solders as described above.

[0077] The first protective layer (510) and the second protective layer (520) may each include a hole (512, 522) for exposing to the outside a wiring portion disposed on the surface of the first build-up layer (200) or the second build-up layer (300).

[0078] Below, the circuit pattern of the circuit board (10) will be described.

[0079] The circuit board (10) may include a circuit pattern for transmitting electrical signals and / or power to an electronic device such as a semiconductor chip. The circuit pattern may include a plurality of wiring portions and a plurality of via portions.

[0080] A plurality of wiring sections may each be disposed on the surface of a plurality of insulating layers. Here, the meaning of being disposed on the surface may also include the meaning that at least a portion of the plurality of wiring sections is embedded within a plurality of insulating layers or protective layers and exposed to the outside from the surface. A wiring section may also be referred to as a metal layer. Furthermore, the surface of the plurality of insulating layers includes a first surface, a second surface, and a side between the first surface and the second surface. Here, the first surface of the insulating layer may be understood as the upper surface, and the second surface of the insulating layer may be understood as the lower surface. The meaning of a wiring section being disposed on the surface is that it is disposed on at least one of the first surface, the second surface, or the side between the plurality of insulating layers. A structure may be formed in which wiring sections are disposed on the first surface and the second surface of some of the insulating layers, respectively, and wiring sections are disposed on only the first surface or the second surface of other parts of the plurality of insulating layers.

[0081] A plurality of wiring sections may include a wiring section disposed in the core layer (100) and a wiring section disposed in the first build-up layer (200) or the second build-up layer (300).

[0082] A wiring section disposed in the core layer (100) may include a first wiring section (141) disposed on the upper surface of the second core layer (120), a second wiring section (142) disposed on the lower surface of the second core layer (120), a third wiring section (145) disposed on the lower surface of the first-2 core layer (114), a fourth wiring section (146) disposed on the lower surface of the first-1 core layer (112), a fifth wiring section (143) disposed on the upper surface of the third-1 core layer (132), and a sixth wiring section (144) disposed on the upper surface of the third-2 core layer (134).

[0083] A wiring section disposed on the first build-up layer (200) may include a seventh wiring section (222) disposed on the upper surface of the first insulating layer (211), an eighth wiring section (223) disposed on the upper surface of the second insulating layer (212), a ninth wiring section (224) disposed on the upper surface of the third insulating layer (213), a tenth wiring section (225) disposed on the upper surface of the fourth insulating layer (214), an eleventh wiring section (226) disposed on the upper surface of the fifth insulating layer (215), a twelfth wiring section (227) disposed on the upper surface of the sixth insulating layer (216), and a twelfth wiring section (228) disposed on the upper surface of the seventh insulating layer (217).

[0084] A wiring section disposed in the second build-up layer (300) may include a 13th wiring section (322) disposed on the lower surface of the 8th insulating layer (311), a 14th wiring section (323) disposed on the lower surface of the 9th insulating layer (312), a 15th wiring section (324) disposed on the lower surface of the 10th insulating layer (313), a 16th wiring section (325) disposed on the lower surface of the 11th insulating layer (314), a 17th wiring section (326) disposed on the lower surface of the 12th insulating layer (315), an 18th wiring section (327) disposed on the lower surface of the 13th insulating layer (316), and a 19th wiring section (328) disposed on the lower surface of the 14th insulating layer (317).

[0085] The horizontal width of the wiring portion disposed in the core layer (100) may be greater than the horizontal width of the wiring portion disposed in the first build-up layer (200) or the third build-up layer (300). Accordingly, the horizontal width of the via portion connecting a plurality of wiring portions can be formed thickly in the area of ​​the core layer (100) where the vertical thickness is relatively thick.

[0086] The via portion may be a metallic material disposed in a via hole formed in each of a plurality of insulating layers to connect a plurality of wiring portions facing each other in a vertical direction. Here, the via hole penetrates at least a portion of each of the plurality of insulating layers in a vertical direction, and a via portion may be disposed within the via hole.

[0087] The via portion may include a via portion disposed in the core layer (100) and a via portion disposed in the first build-up layer (200) or the second build-up layer (300).

[0088] A via portion disposed in the core layer (100) may include a first via portion (150) penetrating at least a portion of the second core layer (120), a second via portion (155) penetrating at least a portion of the first-2 core layer (114), a third via portion (156) penetrating at least a portion of the first-1 core layer (112), a fourth via portion (153) penetrating at least a portion of the second-1 core layer (132), and a fifth via portion (154) penetrating at least a portion of the second-2 core layer (134).

[0089] The first via section (150) can electrically connect the first wiring section (141) and the second wiring section (142). The second via section (155) can electrically connect the second wiring section (142) and the third wiring section (145). The third via section (156) can electrically connect the third wiring section (145) and the fourth wiring section (146). The fourth via section (153) can electrically connect the first wiring section (141) and the fifth wiring section (143). The fifth via section (154) can electrically connect the fifth wiring section (143) and the sixth wiring section (144).

[0090] The first via section (150) may be positioned to penetrate the second core layer (120). The first via section (150) may include a first region (151) whose width gradually narrows as it approaches the lower surface of the second core layer (120) from the upper surface of the second core layer (120), and a second region (152) which is positioned below the first region (151) and whose width gradually widens. The first region (151) and the second region (152) may be positioned adjacent to each other in a vertical direction. The first region (151) and the second region (152) may be formed integrally. The upper end of the first region (151) may be connected to the first wiring section (141). The lower end of the second region (152) may be connected to the second wiring section (142). The first via portion (150) may have an hourglass shape in cross-section due to the first region (151) and the second region (152). The side of the first region (151) and the side of the second region (152) may each be inclined surfaces.

[0091] When forming via holes in the second core layer (120) for arranging the first via section (150) using a laser, the via holes can be processed by irradiating the upper and lower surfaces of the second core layer (120) with a laser, respectively. At this time, depending on conditions such as positional precision and laser intensity, the vertical length (H3) of the first region (151) of the first via section (150) and the vertical length (H4) of the second region (152) may be equal to each other. That is, the area where the first region (151) and the second region (152) meet may be an area that divides the vertical length (H1) of the first via section (150) into 1 / 2. The ratio of the vertical length (H3) of the first region (151) and the vertical length (H4) of the second region (152) may be 1:1. However, it is not necessarily limited to this, and depending on the conditions of the process described above, the vertical length (H3) of the first region (151) and the vertical length (H4) of the second region (152) may differ from each other.

[0092] The second to fifth via sections (155, 156, 153, 154) may have a structure that is symmetric in the vertical direction with respect to the second core layer (120). With respect to the fifth via section (154), the fifth via section (154) may include a first region (157) in which the width gradually narrows as it approaches the lower surface of the second-2 core layer (134) from the upper surface of the second-2 core layer (134), and a second region (159) in which the width gradually widens. The first region (157) may be positioned above the second region (159). The first region (157) and the second region (159) may be positioned adjacent to each other in the vertical direction. The first region (157) and the second region (159) may be formed integrally.

[0093] The fifth via (154) may have an hourglass shape with an asymmetrical cross-section formed by the first region (157) and the second region (159). The side of the first region (157) and the side of the second region (159) may each be inclined surfaces. As illustrated in FIG. 4, the vertical length (H5) of the first region (157) and the vertical length (H6) of the second region (159) may be different from each other. For example, the vertical length (H5) of the first region (157) may be longer than the vertical length (H6) of the second region (159). The ratio of the vertical length (H5) of the first region (157) and the vertical length (H6) of the second region (159) in the fifth via section (154) may differ from the ratio of the vertical length (H3) of the first region (151) and the vertical length (H4) of the second region (152) in the first via section (150). For example, the ratio of the vertical length (H5) of the first region (157) and the vertical length (H6) of the second region (159) in the fifth via section (154) may be 1.5:1 to 3:1. The fifth via section (154) can be processed by irradiating a laser from the upper surface of the second-2 core layer (134) toward the lower surface of the second-2 core layer (134). Thus, a first region (157) with a gradually narrowing width is formed.

[0094] However, depending on the process conditions, scattering of the laser irradiated on the upper surface of the fifth wiring section (143) may occur, and a second region (159) with a gradually widening width may be formed. Due to the second region (159), the bonding area between the fifth via section (154) and the fifth wiring section (143) is widened, and the bonding strength with the fifth via section (154) can be improved. In addition, if the scattering of the laser occurring on the upper surface of the fifth wiring section (143) is large, it is difficult to form the shape of the via hole of the second-2 core layer (134) for the placement of the fifth via section (154) uniformly across the entire circuit board, and the yield may be low. Accordingly, when the fifth via section (154) is completely filled within the via hole of the second-2 core layer (134), it is preferable to have a ratio of the vertical length (H5) of the first region (157) of the fifth via section (154) and the vertical length (H6) of the second region (159) of the fifth via section (154) of 1.5:1 to 3:1. Additionally, with reference to FIG. 4, the second region (159) may be located below the glass fiber (132). Thus, by preventing excessive exposure of the glass fiber (132), problems such as leakage current or signal loss can be prevented.

[0095] Referring to FIG. 3, the ratio of the vertical lengths of the first region (151) and the second region (152) within the first via section (150) is different from the ratio of the vertical lengths of the first region (157) and the second region (159) within the fifth via section (154). Additionally, the via section disposed in the first build-up layer (200) may include only the first region, which becomes narrower as it moves from the upper surface toward the lower surface, and may not include the second region, but is not limited thereto. Accordingly, the first ratio of the vertical length of the first region (151) of the first via section (150) to the vertical length of the second region (152), the second ratio of the vertical length of the first region (157) of the fifth via section (154) to the vertical length of the second region (159), and the third ratio of the vertical length of the first region of the via section of the first build-up layer (200) to the vertical length of the second region may differ from each other. Here, each ratio is based on the first regions (151, 157) whose width gradually narrows from the top surface toward the bottom surface. Additionally, the first ratio may be greater than the second ratio, and the second ratio may be greater than the third ratio. For example, the above ratios may change as the thickness of the insulating layer within the core layer (100) and the build-up layers decreases. Accordingly, the difference between the first and third ratios described above can relieve stress applied to the upper and / or lower part of the circuit board (10), suppress bending of the circuit board (10), and improve the degree of integration of wiring and the degree of freedom of design for connecting to electronic components such as semiconductor devices.

[0096] In particular, by making the first ratio and the second ratio different, bending occurring during the process of the core layer (100) can be prevented, and wiring can be arranged in the third core layer (130) to have a density between the wiring density of the insulating layer within the build-up layers and the wiring density of the second core layer (110), making it easier to control impedance matching, insertion loss, etc. In addition, there is an effect of lowering the process cost of forming via portions arranged in the core layer (100) and the insulating layer within the build-up layers, and increasing the yield. Here, density or integration refers to the size of the width and spacing of wiring or via electrodes, and high density is equivalent to high integration, which should be understood as the width and / or spacing of wiring and the width and / or spacing of via electrodes being small.

[0097] Meanwhile, the shape and structure of the above-described fifth via section (154) are explained using the via section disposed in the third-2nd core layer (134) of the third core layer (130) as an example, and the fourth via section (153) disposed in the third-1st core layer (132) may also have the same shape. Additionally, the second via section (155) and the third via section (156) disposed within the first core layer (110) may have a shape in which the first region and the second region are inverted in the vertical direction from the structure described above. According to this, the second via section (155) and the third via section (156) within the first core layer (110) may each include a first region (157) in which the width gradually narrows as it approaches the upper surface of the first core layer (110) from the lower surface of the first core layer (110), and a second region (159) in which the width gradually widens, and the second via section (155) and the third via section (156) within the first core layer (110) may also have a vertical length of the first region (157) longer than the vertical length of the second region (159).

[0098] The second to fifth via sections (155, 156, 153, 154) can be arranged to overlap vertically with the first via section (150). Accordingly, the signal transmission length within the core layer (100) can be minimized.

[0099] The width of each of the second to fifth via sections (155, 156, 153, 154) may be smaller than the width of the first via section (150). This is in consideration of the fact that the second core layer (120) has a relatively larger thickness than the first core layer (110) or the third core layer (130), and by forming the width of the first via section (150) within the second core layer (120), which has a relatively larger thickness, resistance to signal transmission can be minimized.

[0100] Meanwhile, at least a portion of the first via section (150) may include an area having a width smaller than that of the fifth via section (154). Specifically, the area where the first region (151) and the second region (152) meet in the first via section (150) may have a minimum width in the horizontal direction. In this case, the maximum width in the horizontal direction of the area placed at the top or bottom of the fifth via section (154) may be greater than the minimum width of the first via section (150). Accordingly, the amount of plating required to form the first via section (150) placed within the second core layer (120) can be reduced.

[0101] However, this is exemplary, and the minimum width in the horizontal direction of the first via part (150) at the area where the first region (151) and the second region (152) meet may be greater than the maximum width in the horizontal direction of the fifth via part (154).

[0102] The via portion disposed in the first build-up layer (200) comprises a sixth via portion (231) that penetrates at least a portion of the first insulating layer (211) and electrically connects the sixth wiring portion (144) and the seventh wiring portion (222), a seventh via portion (232) that penetrates at least a portion of the second insulating layer (212) and electrically connects the seventh wiring portion (222) and the eighth wiring portion (223), an eighth via portion (233) that penetrates at least a portion of the third insulating layer (213) and electrically connects the eighth wiring portion (223) and the ninth wiring portion (224), a ninth via portion (234) that penetrates at least a portion of the fourth insulating layer (214) and electrically connects the ninth wiring portion (224) and the tenth wiring portion (225), and a via portion that penetrates at least a portion of the fifth insulating layer (215). It may include a 10 via section (235) that electrically connects the 10th wiring section (225) and the 11th wiring section (226), a 11 via section (236) that penetrates at least a portion of the 6th insulating layer (216) and electrically connects the 11th wiring section (226) and the 12th wiring section (227), and a 12 via section (237) that penetrates at least a portion of the 7th insulating layer (217) and electrically connects the 12th wiring section (227) and the 13th wiring section (228).

[0103] The via portion disposed in the first build-up layer (200) may have a shape in which the horizontal width gradually decreases as it approaches the core layer (100).

[0104] The via portion disposed in the second build-up layer (300) comprises: a 13th via portion (331) that penetrates at least a portion of the eighth insulating layer (311) and electrically connects the fourth wiring portion (146) and the 13th wiring portion (322); a 14th via portion (332) that penetrates at least a portion of the ninth insulating layer (312) and electrically connects the 13th wiring portion (322) and the 14th wiring portion (323); a 15th via portion (333) that penetrates at least a portion of the tenth insulating layer (313) and electrically connects the 14th wiring portion (323) and the 15th wiring portion (324); and a 16th via portion (334) that penetrates at least a portion of the eleventh insulating layer (314) and electrically connects the 15th wiring portion (324) and the 16th wiring portion (325). It may include a 17 via section (335) that penetrates at least a portion of the 12th insulating layer (315) and electrically connects the 16th wiring section (325) and the 17th wiring section (326), an 18 via section (336) that penetrates at least a portion of the 13th insulating layer (316) and electrically connects the 17th wiring section (326) and the 18th wiring section (327), and a 19 via section (337) that penetrates at least a portion of the 14th insulating layer (317) and electrically connects the 18th wiring section (327) and the 19th wiring section (328).

[0105] The via portion disposed in the second build-up layer (300) may have a shape in which the horizontal width gradually decreases as it approaches the core layer (100).

[0106] Hereinafter, the structure of the electrode layer in the circuit board (10) according to an embodiment of the present invention will be described.

[0107] FIG. 5 is a perspective view of an electrode layer according to an embodiment of the present invention, FIG. 6 is an exploded perspective view of an electrode layer according to an embodiment of the present invention, FIG. 7 is a plan view of an outer electrode layer according to an embodiment of the present invention, FIG. 8 is a plan view of an inner electrode layer according to an embodiment of the present invention, and FIG. 9 is a cross-sectional view of a circuit board showing an electrode layer according to an embodiment of the present invention.

[0108] Referring to FIGS. 5 to 9, a circuit board (10) according to an embodiment of the present invention may include an electrode layer (400). The electrode layer (400) may be disposed on a core layer (100), a first build-up layer (200), and a second build-up layer (300), but below, the structure and function of the electrode layer (400) will be described based on the electrode layer (400) disposed on the core layer (100).

[0109] The electrode layer (400) may include an outer electrode layer (410, 440) disposed on the surface of the core layer (100) and an inner electrode layer (420, 430) disposed within the core layer (100). For example, the outer electrode layer (410, 440) may include a first electrode layer (410) disposed on one side of the core layer (100) and a fourth electrode layer (440) disposed on the other side of the core layer (100). The outer electrode layer (410, 440) may include a first electrode layer (410) disposed on the lower surface of the first core layer (110) and a fourth electrode layer (440) disposed on the upper surface of the third core layer (130).

[0110] The inner electrode layers (420, 430) may include a second electrode layer (420) disposed on the lower surface of the second core layer (120) and a third electrode layer (430) disposed on the upper surface of the second core layer (120). The first to fourth electrode layers (410, 420, 430, 440) may be arranged along a vertical direction. However, the number of inner electrode layers (420, 430) within the aforementioned electrode layer (400) is exemplary, and the number of inner electrode layers (420, 430) may vary depending on the number of insulating layers forming the first core layer (110) and the third core layer (130). For example, as illustrated in FIG. 1, when the insulating layer forming the first core layer (110) and the third core layer (130) is two layers each, the inner electrode layer (420, 430) may include four electrode layers disposed respectively between the first-1 core layer (112) and the first-2 core layer (114), between the first-2 core layer (114) and the second core layer (120), between the second core layer (120) and the third-1 core layer (132), and between the third-1 core layer (132) and the third-2 core layer (134). When the first core layer (110) and the third core layer (130) are three layers or more, the inner electrode layer can be disposed between the first core layer (110) and the second core layer (120), between the third core layer (130) and the second core layer, between each insulating layer within the first core layer (110), and between each insulating layer within the third core layer (130).

[0111] As illustrated in FIG. 7, the outer electrode layer (410, 440) may include a plurality of pad portions (412, 414, 416). The outer electrode layer (410, 440) may include a first pad portion (412), a second pad portion (414), and a third pad portion (416).

[0112] The first pad portion (412) may include a plurality of lines. The plurality of lines may be spaced apart from each other along the horizontal direction. Between the plurality of lines, and between the plurality of lines and the circuit portion (411) of the outer electrode layer (410, 440), a hole area shaped to penetrate the outer electrode layer (410, 440) in the vertical direction may be disposed. Through the hole area, the plurality of lines within the first pad portion (412) and the circuit portion (411) may be mutually partitioned.

[0113] The first pad portion (412) may include a region that is bent at least once. For example, the first pad portion (412) may include a first region (412a), a second region (412b) that is bent from the end of the first region (412a) and extends horizontally, and a third region (412c) that is bent from the end of the second region (412b) and extends horizontally. The first region (412a) and the second region (412b) may form an obtuse angle with respect to each other. The second region (412b) and the third region (412c) may form an obtuse angle with respect to each other.

[0114] The horizontal pitch (c) between multiple lines of the first pad portion (412) may be 30 µm or more. The horizontal distance (d) between the first pad portion (412) and the circuit portion (411) may be 15 µm or more. If the horizontal pitch (c) between multiple lines of the first pad portion (412) is less than 30 µm, or the horizontal distance (d) between the first pad portion (412) and the circuit portion (411) is less than 15 µm, there is a risk of a short circuit occurring between adjacent multiple lines and between the first pad portion (412) and the circuit portion (411).

[0115] The second pad portion (414) may have a circular shape. A hole-shaped space may be disposed between the second pad portion (414) and the circuit portion (411). The space may be disposed along the perimeter of the second pad portion (414). The second pad portion (414) may be provided in multiple numbers and disposed spaced apart from each other along the horizontal direction. The diameter (e) of the second pad portion (414) may be 12.5 μm or more. Based on two adjacent second pad portions (414), the horizontal distance (f) between the spaces disposed on the outer side of each second pad portion (414) may be 15 μm or more. The horizontal width (f) of the circuit portion (411) disposed between the multiple second pad portions (414) may be 15 μm. If the diameter (e) of the second pad portion (414) is less than 12.5 μm, the process of forming via portions for electrical connection with other electrode layers may not be easy. If the horizontal width (f) of the circuit portion (411) placed between the plurality of second pad portions (414) is less than 15 μm, there is a risk of short circuit occurring between adjacent second pad portions (414). In addition, the horizontal spacing between the second pad portion (414) and the circuit portion (411) may be 15 μm or more to prevent short circuits. Accordingly, the diameter (e) of the second pad portion (414) is implemented to be 12.5 μm or more, but can be freely designed by considering the minimum spacing of 15 μm to prevent short circuits between the second pad portion (414) and the circuit portion (411) as described above.

[0116] The third pad portion (416) may include a plurality of lines. The third pad portion (416) may be arranged parallel to at least a portion of the first pad portion (412). For example, the third pad portion (416) may be arranged parallel to the second region (412b) of the first pad portion (412). The horizontal width (a) of each of the plurality of lines of the third pad portion (416) may be 15 µm or more. The horizontal separation distance (b) between the plurality of lines of the third pad portion (416) or between the plurality of lines of the third pad portion (416) and the circuit portion (411) may be 15 µm or more. If the horizontal width (a) of each of the plurality of lines of the third pad portion (416) is less than 15 µm, the process of forming via portions for electrical connection with other electrode layers may not be easy. If the horizontal separation distance (b) between multiple lines of the third pad section (416) or between multiple lines of the third pad section (416) and the circuit section (411) is less than 15 µm, there is a risk of a short circuit occurring between multiple lines within the third pad section (416) or between the circuit section (411).

[0117] The first to third pad portions (412, 414, 416) of the outer electrode layer (410, 440) may each be one of the sixth wiring portion (144) disposed on one side of the core layer (100) within the circuit board (10) and the fourth wiring portion (146) disposed on the other side of the core layer (100).

[0118] The circuit portion (411) of the outer electrode layer (410, 440) can function as a ground power source.

[0119] As illustrated in FIG. 8, the inner electrode layer (420, 430) may include a plurality of pad portions (432, 434, 436). The inner electrode layer (420, 430) may include a fourth pad portion (432), a fifth pad portion (434), and a sixth pad portion (436).

[0120] The fourth pad portion (432) may have a circular cross-sectional shape. The fourth pad portion (432) may be electrically connected to the first pad portion (412) of the outer electrode layer (410, 440). The fourth pad portion (432) may be electrically connected to the first pad portion (412) through the first via portion (470, see FIG. 5). The fourth pad portion (432) is spaced horizontally apart from the circuit portion (431) of the inner electrode layer (420, 430), and a hole penetrating the inner electrode layer (420, 430) in the vertical direction may be disposed in the spaced-away area between the circuit portion (431) and the fourth pad portion (432). The fourth pad portion (432) may be disposed in areas that overlap vertically with both ends of a plurality of lines of the first pad portion (412).

[0121] The fifth pad portion (434) may have a circular cross-sectional shape. The fifth pad portion (434) may be electrically connected to the second pad portion (414) of the outer electrode layer (410, 440). The fifth pad portion (434) may be electrically connected to the second pad portion (414) through the second via portion (480, see FIG. 5). The fifth pad portion (434) is spaced horizontally apart from the circuit portion (431), and a hole penetrating the inner electrode layer (420, 430) in the vertical direction may be disposed in the spaced area between the circuit portion (431) and the fifth pad portion (434). The horizontal separation distance (h) between the circuit portion (431) and the fifth pad portion (434) may be 15 μm or more. The horizontal width (i) of the circuit section (431) positioned between adjacent multiple fifth pad sections (434) may be 15 µm or more. If the horizontal separation distance (h) between the circuit section (431) and the fifth pad section (434) is less than 15 µm, the process of forming the via section (480) may not be easy. If the horizontal width (i) of the circuit section (431) positioned between adjacent multiple fifth pad sections (434) is less than 15 µm, there is a risk of short circuits occurring between multiple via sections or multiple fifth pad sections (434).

[0122] The sixth pad portion (436) may have a circular cross-sectional shape. The sixth pad portion (436) may be electrically connected to the third pad portion (416) of the outer electrode layer (410, 440). The sixth pad portion (436) may be electrically connected to the third pad portion (416) through a third via portion (not shown). The sixth pad portion (436) is spaced horizontally apart from the circuit portion (431), and a hole penetrating the inner electrode layer (420, 430) in the vertical direction may be disposed in the spaced area between the circuit portion (431) and the sixth pad portion (436). The sixth pad portion (436) may be disposed in an area that overlaps vertically with both ends of a plurality of lines of the third pad portion (416).

[0123] The horizontal diameter (g) of the sixth pad portion (436) may be less than or equal to the horizontal width (a) of each of the multiple lines of the third pad portion (416). For example, the horizontal diameter (g) of the circuit portion (431) may be smaller than the horizontal width (a) of each of the multiple lines of the third pad portion (416). Accordingly, since the formation area of ​​the sixth pad portion (436) for electrical connection with the third pad portion (416) in the inner electrode layer (420, 430) may be formed smaller, a larger space can be secured for designing the circuit area within the inner electrode layer (420, 430). The horizontal diameter (g) of the sixth pad portion (436) may be 12.5 µm or more. If the horizontal diameter (g) of the sixth pad portion (436) is less than 12.5 µm, the formation process of the third via portion may not be easy.

[0124] The fourth to sixth pad portions (432, 434, 436) of the inner electrode layer (420, 430) may each be any one of the first wiring portion (141), the second wiring portion (142), the third wiring portion (145), and the fifth wiring portion (143) disposed in the core layer (100) within the circuit board (10).

[0125] Additionally, a via portion electrically connecting a plurality of inner electrode layers (420, 430) arranged in a vertical direction may be the aforementioned first via portion (150), and a via portion connecting the outer electrode layer (410, 440) and the inner electrode layer (420, 430) may be the aforementioned second to fifth via portions (155, 156, 153, 154).

[0126] The circuit portion (431) of the inner electrode layer (420, 430) can function as a ground power source.

[0127] The inner electrode layer (420, 430) may include a hole (439). The hole (439) may have a shape that penetrates from one side of the inner electrode layer (420, 430) to the other side in a vertical direction. The hole (439) may have a shape that penetrates the circuit portion (431) in a vertical direction. The holes (439) may be provided in multiple numbers and arranged spaced apart from each other along the horizontal direction. The holes (439) may be provided in multiple numbers to form a group, and in this case, a group having multiple holes (439) arranged therein may be provided in multiple numbers within the inner electrode layer (420, 430) and arranged spaced apart in the horizontal direction.

[0128] The hole (439) is for discharging gas generated during the curing of the pad portion within the electrode layer (400) or during the curing of the insulating layer placed on the surface of the electrode layer (400), and may have various cross-sectional shapes such as circular or polygonal.

[0129] Meanwhile, as illustrated in FIGS. 5 and 9, holes (439) arranged in a plurality of inner electrode layers (420, 430) adjacent in the vertical direction may be arranged in a staggered manner. Specifically, holes (429) arranged in the second electrode layer (420) and holes (439) arranged in the third electrode layer (430) may be arranged so as not to overlap in the vertical direction. Accordingly, a staggered arrangement structure of different holes (429, 439) in the plurality of electrode layers (420, 430) can secure a wider space for gas discharge within the circuit board (10). In addition, based on a region of the core layer (100) arranged between the plurality of inner electrode layers (420, 430), there is an advantage in that stress can be distributed due to the staggered arrangement structure of the holes (429, 439).

[0130] A plurality of holes (429) disposed in the second electrode layer (420) can be named the first hole, and a plurality of holes (439) disposed in the third electrode layer (430) can be named the second hole.

[0131] Meanwhile, holes for gas discharge may be omitted in the outer electrode layers (410, 440) disposed on the surface of the core layer (100), and holes (429, 439) for gas discharge may be formed only in the inner electrode layers (420, 430) disposed within the core layer (100). In this case, the holes (429, 439) of the inner electrode layers (420, 430) may overlap in a vertical direction with the circuit portion of the outer electrode layers (410, 440). Accordingly, by easily discharging the gas generated during the manufacturing process of the core layer (100) to the outside, warping caused by residual gas in the circuit board (10) is prevented, and delamination between the inner electrode layers (420, 430) and the core layer (100) is prevented when discharging the gas, while simultaneously improving the yield.

[0132] However, the formation of holes for gas discharge within the outer electrode layers (410, 440) is not completely excluded, and holes for gas discharge can also be formed in the outer electrode layers (410, 440), in which case the holes (429, 439) placed in the inner electrode layers (420, 430) may be arranged in a vertically offset manner.

[0133] As illustrated in FIG. 8, the diameter (j) of the hole (439) may be 100 µm or more. The horizontal pitch (k) between the multiple holes (439) may be 200 µm or more. If the diameter (j) of the hole (439) is less than 100 µm, gas discharge may not be smooth. Additionally, if the horizontal pitch (k) between the multiple holes (439) is less than 200 µm, considering that the holes are for gas discharge, a problem may arise where gas discharge occurs only in a localized area.

[0134] According to the present embodiment, by forming the core layer (100) into multiple layers, the electrode layer (400) disposed on the core layer (100) is also provided in multiple layers, thereby having the advantage of minimizing bending of the circuit board (10) due to the high multi-layer structure.

[0135] In addition, compared to a single layer of core layer and electrode layer, the thickness can be formed relatively thinly through multiple layers of core layer (100) and electrode layer (400), so holes and pads can be processed using a laser method rather than a drilling method, and thus there is an advantage of improved production efficiency.

[0136] In addition, the thickness of each electrode layer (400) can be reduced, so the electrode layer (400) can be processed by the mSAP (Modified semi-Additive process) method, and compared to the tenting method, it is easier to implement a fine pitch and has the advantage of being able to form high-density wiring.

[0137] In addition, by reducing the size of the pad portions within the electrode layer (400), the residual rate can be lowered, thereby resolving the problem of reduced moisture removal efficiency due to the residual rate within the circuit board (10).

[0138] FIG. 10 is a drawing illustrating a semiconductor package according to an embodiment of the present invention.

[0139] Referring to FIG. 10, a semiconductor package according to an embodiment of the present invention may include a first semiconductor chip (1000) disposed on the aforementioned circuit board (10) and a second semiconductor chip (2000), wherein the first semiconductor chip (1000) is coupled to the first build-up layer (200) through a first connection part (540) and the second semiconductor chip (2000) is coupled to the second build-up layer (300) through a second connection part (530). Here, the first connection part (540) and the second connection part (530) may each be solder balls.

[0140] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0141] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0142] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0143] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. Core layer; Electrode layer disposed on the above core layer; A first build-up layer disposed on one surface of the above-mentioned core layer; and It includes a second build-up layer disposed on the other side of the core layer, and The core layer comprises a first core layer, a second core layer disposed on the first core layer, and a third core layer disposed on the second core layer. The electrode layer comprises a first electrode layer disposed on one side of the core layer, a second electrode layer disposed between the first core layer and the second core layer, a third electrode layer disposed between the second core layer and the third core layer, and a fourth electrode layer disposed on the other side of the core layer. The above second electrode layer includes a plurality of first holes, and The above third electrode layer includes a plurality of second holes, and A circuit board in which the plurality of first holes and the plurality of second holes are arranged in a vertically offset manner.

2. In Paragraph 1, The plurality of first holes and the plurality of second holes are each holes for gas discharge within the core layer, forming a circuit board.

3. In Paragraph 1, It includes a first wiring section disposed on one side of the second core layer and a second wiring section disposed on the other side of the second core layer, The first wiring portion is disposed on the third electrode layer, and The above second wiring section is a circuit board disposed on the above second electrode layer.

4. In Paragraph 3, It includes a sixth wiring section disposed on the upper surface of the third core layer and a fourth wiring section disposed on the lower surface of the first core layer, The above-mentioned fourth wiring portion is disposed on the above-mentioned first electrode layer, and The above-mentioned sixth wiring section is a circuit board disposed on the above-mentioned fourth electrode layer.

5. In Paragraph 4, A circuit board comprising vias that electrically connect the first wiring section, the second wiring section, the fourth wiring section, and the sixth wiring section.

6. In Paragraph 1, It includes a first via portion penetrating the second core layer, and The above first via portion is a circuit board comprising a first region and a second region having the same vertical length.

7. In Paragraph 6, It includes a second via portion penetrating the first core layer and a fifth via portion penetrating the third core layer, A circuit board comprising a third region and a fourth region, each having different vertical lengths, for the second via and the fifth via.

8. In Paragraph 1, A circuit board in which the thickness of the second core layer is thicker than the thickness of the first core layer or the third core layer.

9. In Paragraph 1, The first electrode layer and the fourth electrode layer each include a first pad portion, and The above-mentioned first pad portion is a circuit board including an area that is folded at least once.

10. Core layer; Electrode layer disposed on the above core layer; A first build-up layer disposed on one side of the above-mentioned core layer; A second build-up layer disposed on the other side of the core layer; and A semiconductor chip disposed on the surface of the first build-up layer or the second build-up layer, and The core layer comprises a first core layer, a second core layer disposed on the first core layer, and a third core layer disposed on the second core layer. The electrode layer comprises a first electrode layer disposed on one side of the core layer, a second electrode layer disposed between the first core layer and the second core layer, a third electrode layer disposed between the second core layer and the third core layer, and a fourth electrode layer disposed on the other side of the core layer. The above second electrode layer includes a plurality of first holes, and The above third electrode layer includes a plurality of second holes, and A semiconductor package in which the plurality of first holes and the plurality of second holes are arranged in a vertically offset manner.

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