Nedmos FET with reduced peak e-field

Abstract

Novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability. Embodiments include a modified NEDMOS IC structure that reduces the maximum E-field between the P-well and the N− drift region, accomplished by creating a region of intrinsic or near-intrinsic semiconductor between the P-well and the N− drift region that locally lowers the maximum E-field and widens the depletion width. The modified NEDMOS IC structure results in a split of the peak of the E-field that would otherwise occur at the junction of the P-well and the N– drift region of a NEDMOS FET. This in turn drops more VDD and therefore lowers the maximum E-field in this region (largely in the OFF state). The threshold voltage VTH is also lowered, which lowers RON in the ON state. The NEDMOS FET simultaneously exhibits improved reliability and an improved transconductance characteristic.

Description

Attorney Docket No. : P3132-PCTNEDMOS FET With Reduced Peak E-FieldCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application claims priority to U.S. Provisional Application No. 63 / 706,982, filed on October 14, 2024, entitled “NEDMOS FET with Reduced Peak E-Field” with docket number PER-537-PROV, the contents of which are incorporated herein by reference in their entirety.TECHNICAL FIELD

[0002] This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits that include metal-oxide-semiconductor field-effect transistors (MOSFETs).BACKGROUND

[0003] Virtually all modern electronic products - including laptop computers, mobile telephones, and electric cars - utilize MOSFET-based integrated circuits (ICs). A number of architectural variations exist for MOSFETs. The most common type of MOSFETs are N-type MOSFETs (NFETs), which have N+ doped source and drain regions abutting opposite sides of a channel region, which, for an enhancement-mode device, may be doped with P-type material. NFETs have been adapted to withstand relatively high drain voltages. For example, N-type Extended Drain MOS (NEDMOS) FETs and Laterally-Diffused MOS (LDMOS) FETs are transistor devices capable of handling relatively high drain voltages. NEDMOS FETs are generally fabricated using silicon-on-insulator (SOI) processes, but may be fabricated using bulk silicon processes. LDMOS FETs are generally fabricated using bulk silicon processes.

[0004] FIG. l is a stylized cross-sectional view of an SOI IC structure for a prior art NEDMOS FET 100. The SOI structure includes a substrate 102, an insulating buried-oxide (BOX) layer 104, and an active layer 106 (note that the dimensions for the elements of the SOI IC structure are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 102 is typically a semiconductor material such as silicon, but may be other materials such as glass or sapphire. The BOX layer 104 is a dielectric and is often SiO? formed as a “top” surface of theAttorney Docket No. : P3132-PCT substrate 102; for some substrates (e.g, glass or sapphire, a BOX layer 104 optionally may be omitted. Some embodiments may include a trap-rich Si layer (not shown) between the BOX layer 104 and the substrate 102. A trap-rich Si layer mitigates parasitic surface conduction and improves device performance at high frequencies.

[0005] The active layer 106 may include some combination of implants and / or layers that include dopants, dielectrics, polysilicon, conductors, passivation, and other materials to form active and / or passive electronic components and / or mechanical structures. For example, the NEDMOS FET 100 of FIG. 1 has an active layer 106 that includes an N+ source 110, a P-type body region or “P-well” 112 in which an electrically conductive channel can be formed, an N- Si drift region 114, and an N+ drain 116, all bounded by an isolation structure 118, such as a shallow trench isolation (STI) structure. The designation “N- means a lesser concentration of N-type dopant (e.g., arsenic or phosphorous) than the designation “N+”.

[0006] Optional features within the active layer 106 include a halo region 122 and a lightly- doped drain (LDD) region 124 (“LDD” being somewhat of a misnomer, since the LDD region 124 is only on the source-side for the illustrated embodiment). A halo implant mitigates punch-through while an LDD region mitigates avalanche breakdown and hot carrier effects. More specifically, the halo region 122 increases a sub-surface electric field to reduce so-called punch -through, or short channel, conduction between the source 1 10 and the drain 116, thus increasing the channel breakdown voltage. The LDD region 124 extends the source 110 underneath a gate structure 130 and modulates the threshold voltage VTH, transconductance (Gm), and leakage current of the device.

[0007] The gate structure 130 is formed in contact with a surface of the active layer 106, positioned with respect to the P-well 112 so as to be able to influence current flow through the P- well 112 between the source 110 and the drain 116. The gate structure 130 includes a conductive layer 132, such as N+ doped polysilicon, in contact with an insulating gate oxide (GOX) layer 134, the thickness of which may be varied for different applications. In the illustrated example, the gate structure 130 is surrounded by insulating spacers 136. Part of the gate structure 130 and the N- drift region 114 may be coated with a dielectric 138, such as SiCL, SiaN4, etc., which in turn may be overlaid with a salicide block (SAB) layer 140, such as silicon nitride (SisN^, to preventAttorney Docket No. : P3132-PCT subsequent formation of self-aligned silicides (also known as “salicides”) on those structures / regi ons .

[0008] A conductive source contact 142, a conductive gate contact 144, and a conductive drain contact 146, which may be salicides, are respectively formed in contact with the source 110, the conductive layer 132 of the gate structure 130, and the drain 116. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 142, gate contact 144, and drain contact 146.

[0009] The gate structure 130, the BOX layer 104, and the active layer 106 (which may include multiple FETs) may be collectively referred to as a “device region” or “substructure” for convenience (noting that other structures or regions may intrude into the substructure in particular IC designs). A superstructure (not shown) of various elements, regions, and structures may be fabricated on or above the substructure in order to implement particular functionality. The superstructure may include, for example, conductive interconnections from the illustrated NEDMOS FET 100 to other components (including other FETs on the same IC die) and / or external contacts, passivation layers, and protective coatings.

[0010] One of the purposes of the N- drift region 114 is to reduce the electrical field (“E- field”) that would otherwise occur at and near the junction of the P-well 1 12 and an abutting drain (near the region 150 marked with a dotted-line oval) when a high drain voltage VDD value (e.g., about 3.3V and above) is applied to the device. A high E-field generates “hot” (i.e., energetic) electrons, which may cause impact ionization which can result in avalanche breakdown and hot carrier injection, which degrades GOX reliability. In addition, hot electrons with sufficient energy to penetrate the GOX layer 134 can be trapped at the junction interface in and around region 150, which causes increased resistance in the channel of the device, thus reducing the device drain-to- source current IDS. These adverse effects are reduced by introduction of the N- drift region 114, which improves reliability of an NEDMOS FET.

[0011] The present invention is directed to novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability.Attorney Docket No. : P3132-PCTSUMMARY

[0012] The present invention encompasses novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability. One aspect of the present invention is a modified NEDMOS IC structure that the maximum E- field between the P-well and the N- drift region. This is accomplished by creating a region of intrinsic or near-intrinsic semiconductor between the P-well and the N- drift region that locally lowers the maximum E-field within that region and widens the depletion width. The modified NEDMOS IC structure results in a split of the peak of the E-field that would otherwise occur at the junction of the P-well and the N- drift region of a NEDMOS FET. This in turn drops more VDD and therefore lowers the maximum E-field in this region (largely in the OFF state). The threshold voltage VTH is also lowered, which lowers RON in the ON state. The modified NEDMOS FET simultaneously exhibits both improved reliability and an improved transconductance Gm characteristic.

[0013] More generally, the invention encompasses an extended drain FET that includes an intrinsic silicon region positioned between a body region of the extended drain FET and a drift region of the extended drain FET. As one example, the invention encompasses an integrated circuit field-effect transistor fabricated on a substrate and including a source region fabricated within an active layer on the substrate and doped to have a first semiconductor characteristic, a body region fabricated within the active layer adjacent to the source region and doped to have a second semiconductor characteristic, a gate structure formed above the body region, an intrinsic silicon region fabricated within the active layer adjacent to the body region, a drift region fabricated within the active layer adjacent the intrinsic silicon region and doped to have a third semiconductor characteristic, and a drain region fabricated within the active layer adjacent the drift region and doped to have a fourth semiconductor characteristic.

[0014] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention should be apparent from the description and drawings, and from the claims.Attorney Docket No. : P3132-PCTDESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is a stylized cross-sectional view of an SOI IC structure for a prior art NEDMOS FET.

[0016] FIG. 2 is a stylized cross-sectional view of an example NEDMOS FET having an applied VDD of about 4.8V.

[0017] FIG. 3 is a graph showing electric field in a NEDMOS FET as a function of the relative distance between the device source (at X=0) and the device drain (where the local source and drain potentials equal the applied voltages) for a modeled conventional NED-MOS device.

[0018] FIG. 4 is a stylized cross-sectional view of a NEDMOS FET in accordance with the present invention.

[0019] FIG. 5 is a graph showing electric field in a NEDMOS FET as a function of the relative distance between the device source (at X=0) and the device drain (where the local source and drain potentials equal the applied voltages) for two example NEDMOS devices in accordance with the present invention.

[0020] FIG. 6 is a graph showing transconductance as a function of gate voltage for two example NEDMOS devices in accordance with the present invention.

[0021] FIGS. 7A-7F show one method of fabricating the NEDMOS FET structure shown in FIG. 4.

[0022] FIG. 8 is a process flowchart showing another representation of an example fabrication process for an improved NEDMOS FET that is suitable for some contemporary IC front-end-of- line (FEOL) foundries.

[0023] FIGS. 9A-9C are top plan views of three example configurations of a BTS structure for a NEDMOS device of the types described in this disclosure.

[0024] FIG. 10 is a top plan view of a substrate that may be, for example, a printed circuit board or chip module substrate (e.g., a thin-film tile).Attorney Docket No. : P3132-PCT

[0025] Like reference numbers and designations in the various drawings indicate like elements unless the context requires otherwise.Attorney Docket No. : P3132-PCTDETAILED DESCRIPTION

[0026] The present invention encompasses novel NEDMOS FETs capable of withstanding higher drain voltages than conventional NEDMOS devices while attaining high device reliability. The modified NEDMOS FET simultaneously exhibits both improved reliability and an improved transconductance Gm characteristic.

[0027] The inventors have discovered that another phenomenon occurs that appears to involve hot carrier impact ionization when even higher drain voltages (e.g., in excess of about 3.3V) are applied to a conventional NDEMOS FET. It is believed that hot electrons can be trapped between the N- drift region 114 and the overlaying portions of the dielectric 138 and SAB layer 140, which repels (depletes) the electrons at or near the surface of the N- drift region 114.

[0028] For example, FIG. 2 is a stylized cross-sectional view of an example NEDMOS FET 200 having an applied VDD of about 4.8V. Similar in most respects to the NEDMOS FET 100 of FIG. 1, but with higher VDD applied, FIG. 2 shows a drain-side region 202 marked with a dotted- line oval that can trap hot electrons. The result is depletion of electrons within the N- drift region 114, which effectively raises the ON resistance RON of the N- drift region 114, thereby reducing the drain-to-source current IDS.

[0029] The junction of the P-well 112 and the N- drift region 114 when VDD is relatively high exhibits a peaked E-field that contributes to the trapped hot electron region 202. For example, FIG. 3 is a graph 300 showing electric field in a NEDMOS FET as a function of the relative distance between the device source 100 (at X=0) and the device drain 116 (where the local source and drain potentials equal the applied voltages) for a modeled conventional NEDMOS device. Graph line 302 shows a peak 304 in the E-field at or near the junction of the P-well 112 and the N- drift region 114.

[0030] One aspect of the present invention is a modified NEDMOS IC structure that reduces the maximum E-field between the P-well 112 and the N- drift region 114. This is accomplished by creating a region of intrinsic or near-intrinsic semiconductor between the P-well 112 and the N- drift region 114 that locally lowers the maximum E-field within that region and widens the depletion width. The modified NEDMOS IC structure results in a split of the peak of the E-fieldAttorney Docket No. : P3132-PCT shown in FIG. 3 (see FIG. 5 for further details). This in turn drops more VDD and therefore lowers the maximum E-field in this region (largely in the OFF state). The threshold voltage VTH is also lowered, which lowers RON in the ON state.

[0031] FIG. 4 is a stylized cross-sectional view of a NEDMOS FET 400 in accordance with the present invention. The SOI structure includes a substrate 402, a buried-oxide (BOX) insulator layer 404, and an active layer 406 (note that the dimensions for the elements of the SOI IC structure are not to scale; some dimensions have been exaggerated for clarity or emphasis). The substrate 402 is typically a semiconductor material such as silicon, but may be other materials such as glass or sapphire. The BOX layer 404 is a dielectric and is often SiO2 formed as a “top” surface of the substrate 402; for some substrates (e.g., glass or sapphire), a BOX layer 404 optionally may be omitted. Some embodiments may include a trap-rich Si layer 405 (shown in dotted outline) between the BOX layer 404 and the substrate 402.

[0032] The NEDMOS FET 400 of FIG. 4 has an active layer 406 that includes an N+ source 410, a P-type body region or “P-well” 412 in which an electrically conductive channel can be formed, an N- Si drift region 414, and an N+ drain 416, all bounded by an isolation structure 418, such as an STI structure. Optional features within the active layer 406 may include a halo region 422 and a lightly-doped drain (LDD) region 424 (again, “LDD” being somewhat of a misnomer, since the LDD region 424 is only on the source-side for the illustrated embodiment). A halo region 422 mitigates punch-through while an LDD region 424 mitigates avalanche breakdown.

[0033] The gate structure 430 is formed in contact with a surface of the active layer 406, positioned with respect to the P-well 112 so as to be able to influence current flow through the P- well 412 between the source 410 and the drain 416. The gate structure 430 includes a conductive layer 432, such as N+ doped polysilicon, in contact with a GOX layer 434, the thickness of which may be varied for different applications. In the illustrated example, the gate structure 430 is surrounded by insulating spacers 436. Part of the gate structure 430 and the N- drift region 414 may be coated with a dielectric 438, such as SiCh, SiaN4, etc., which in turn is overlaid with a salicide block (SAB) layer 440, such as silicon nitride (SiN), to prevent subsequent formation of salicide on those structures / regions.Attorney Docket No. : P3132-PCT

[0034] A conductive source contact 442, a conductive gate contact 444, and a conductive drain contact 446, which may be salicides, are respectively formed in contact with the source 410, the conductive layer 432 of the gate structure 430, and the drain 416. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 442, gate contact 444, and drain contact 446.

[0035] Of note, an intrinsic or near-intrinsic semiconductor region 450 (silicon in this example, thus referenced as / -Si region 450) is formed within the active layer 406 between the P-well 412 and the N- drift region 414. An intrinsic semiconductor (also called a pure semiconductor, undoped semiconductor, or / -type semiconductor) is a semiconductor without a significant concentration of dominant dopant species present, and thus has an essentially equal number of electrons and holes. The number of charge carriers is therefore determined by the properties of the material itself instead of the amount of impurities. While the / -Si region 450 is preferably just intrinsic semiconductor, some light amount of doping may be tolerable (but less than the degree of doping for the P-well 412).

[0036] The / -Si region 450 is located at least in part relative to the conductive layer 432 of the gate structure 430 such that application of a voltage to or presence of a charge within the conductive layer 432 can influence current flow through the P-well 412 and the / -Si region 450 between the source 410 and the drain 416. The X-dimension (length) of the / -Si region 450 may be, for example, between about 10% and about 25% of the gate length LG.

[0037] The P-well 412 is doped to a greater degree than the / -Si region 450 (which is nominally not doped at all). Accordingly, the P-well 412 will exhibit a threshold voltage VTH-Pthat is greater than the threshold voltage Vm-i of the / -Si region 450. Note that the implanted regions within the active layer 406 are not sharply delimited, as suggested by the solid lines, but instead blend somewhat into adjacent zones over a gradient of concentrations. However, even in blended form, by using the threshold voltage zones VTH-Pand Vm-i together, a lower effective ON-state drain-to- source resistance RON is achieved. In particular, the / -Si region 450 has more charge carrier combinations when the FET device is in the ON state, resulting in a lower resistance in the / -Si region 450, thus increasing IDS. The modified NEDMOS FET 400 can still withstand higher drain-Attorney Docket No. : P3132-PCT to-source voltages, thus achieving high device reliability and higher performance in parameters such as gain, power out, and transconductance.

[0038] FIG. 5 is a graph 500 showing electric field in a NEDMOS FET as a function of the relative distance between the device source (at X=0) and the device drain (where the local source and drain potentials equal the applied voltages) for two example NEDMOS devices in accordance with the present invention. Graph line 502 corresponds to a NEDMOS FET in which the P-well 412 is doped to 9.56el7 and the N- drift region 414 is doped to 1.45el7. Graph line 504 corresponds to a NEDMOS FET in which the P-well 412 is doped to 2.56el7 and the N- drift region 414 is doped to 1.47el7. In both modeled embodiments, the z-Si region 450 is not intentionally doped. Dotted graph line 506 represents the peak 304 of the E-field for a conventional NEDMOS device, as shown in FIG. 3.

[0039] Both modeled embodiments represented by graph lines 502, 504 exhibit two E-field peaks 506, 508 - essentially “splitting” the peak 304 of the E-field for a conventional NEDMOS device and exhibiting a lower average E-field value across the P-well 412, z-Si region 450, and N- drift region 414. In essence, the widened depletion region resulting from use of the z-Si region 450 creates a lower maximum e-field that results in higher operating voltages.

[0040] Further, the modified NEDMOS FET 400 simultaneously exhibits both improved reliability and an improved transconductance Gm characteristic. For example, FIG. 6 is a graph 600 showing transconductance as a function of gate voltage for two example NEDMOS devices in accordance with the present invention. Graph line 602 corresponds to a NEDMOS FET in which the P-well 412 is doped to 9.56el7 and the N- drift region 414 is doped to 1.45el7. Graph line 604 corresponds to a NEDMOS FET in which the P-well 412 is doped to 2.56el7 and the N- drift region 414 is doped to 1.47el7. In both modeled embodiments, the z-Si region 450 is not intentionally doped. Graph line 504 from FIG. 5 and graph line 604 from FIG. 6 - which correspond to the same example NEDMOS FET with a low P-well doping - show that use of an z-Si region 450 results in a device with a low total source-to-drain E-field (and thus higher device reliability) but high transconductance Gm characteristic.Attorney Docket No. : P3132-PCT

[0041] A number of different processes may be used to fabricate the improved FET devices described in this disclosure. For example, FIGS. 7A-7F show one method of fabricating the NEDMOS FET structure shown in FIG. 4.

[0042] FIG. 7A shows a portion of a semiconductor active layer 406 formed on a BOX layer 404, which is in turn formed on top of a substrate 402. The active layer 406 may be masked and implanted to form a P-type body region or well 412, leaving a portion of the active layer 406 protected from implantation to form an z-Si region 450. If needed, the active layer 406 may be thinned to a suitable thickness, such as by chemical-mechanical polishing (CMP). For example, commercially available SOI wafers may have an active layer thickness of about 750A. It may be useful for some applications, particularly for RF ICs, to thin the active layer 406, for example, to about 500A. Additionally, isolation structures 418 have been formed.

[0043] FIG. 7B shows a gate structure 430 formed in contact with a surface of the active layer 406. The gate structure 430 includes a conductive layer 432 (e.g., N+ doped polysilicon) in contact with an insulating gate oxide (GOX) layer 434, and surrounding insulating spacers 436. The gate structure 430 may be formed by conventional MOSFET fabrication processes such as thermal oxidation, epitaxial deposition, photolithographic masking and etching, etc.

[0044] In an alternative embodiment, the / -Si region 450 is formed after formation of the gate structure 430 by angled implantation (from the drain-side of gate structure 430) of a counterdopant to transform a portion of the P-well 412 to an / -type semiconductor. The conductive layer 432 and the region that is to become the source 410 may be protected by masking material during such implantation. This approach assures self-alignment of the gate structure 430 with respect to the / -Si region 450.

[0045] FIG. 7C shows that the active layer 406 on the drain-side of the gate structure 430 is doped (e.g., by angled ion implantation after suitable masking) with an N- material (e.g., arsenic or phosphorous) to form an N- Si drift region 414. Again, the conductive layer 432 and the region that is to become the source 410 may be protected by masking material during such implantation.

[0046] FIG. 7D shows that an N+ source 410 and an N+ drain 416 have been formed by suitably masking and then doping with an N+ dopant. Doping may be by ion implantation orAttorney Docket No. : P3132-PCT diffusion. The conductive layer 432 and a portion of the N- drift region 414 may be protected by masking material during such implantation. Subsequently, P+ material may be implanted in selective areas of the N+ source 410 to form body-tied -to-source connections (see FIGS. 9A-9C below for further details).

[0047] FIG. 7E shows that the active layer 406 on the source-side of the gate structure 430 may be doped (e.g., by angled ion implantation after suitable masking) with a suitable dopant to form a halo region 422 and / or an LDD region 424 within the P-well material (including a portion underneath the gate structure 430). Note that formation of the halo region 422 and / or the LDD region 424 may precede formation of the N+ source 410 and an N+ drain 416.

[0048] FIG. 7F shows that part of the gate structure 430 and the exposed portions of the N- drift region 414 have been coated with a dielectric 438 (SiCh, SiaN , etc. . and a SAB layer 440 (e.g., SiN) has been formed over the dielectric 438. A conductive source contact 442, a conductive gate contact 444, and a conductive drain contact 446, which may be salicides, have been respectively formed in contact with the N+ source 410, the gate structure 430, and the N+ drain 418. Stylized electrical terminals S, G, and D are shown coupled to the corresponding source contact 442, gate contact 444, and drain contact 446.

[0049] It should be appreciated that fabrication of an improved NEDMOS FET device in accordance with the present invention may be accomplished using alternative process steps. Note that not all steps that may be performed during the manufacture of a novel FET device as part of an IC are shown in the aforementioned figures. Such steps may vary between IC foundries and may include (but are not limited to) substrate thinning, planarization, special implantations, annealing, formation of ohmic contacts, and formation of additional temporary or permanent structures (e.g., drift regions, substrate contacts, passivation layers, salicide blocks, replacement metal gate (RMG)), etc. After formation of a basic MOSFET structure, back-end-of-line (BEOL) processes may be applied, such as fabrication of electrical contacts (pads), vias, insulating layers (dielectrics), metallization layers, and bonding sites for die-to-package connections.

[0050] FIG. 8 is a process flowchart 800 showing another representation of an example fabrication process for an improved NEDMOS FET that is suitable for some contemporary IC front-end-of-line (FEOL) foundries. Note that some conventional steps, such as planarization,Attorney Docket No. : P3132-PCT passivation, details of masking and etching, and superstructure formation have been omitted as known to those of ordinary skill in the art. The illustrated process includes:• If needed, thinning the semiconductor active layer (e.g., Si, Ge, SiGe, SiC, or the like) formed on a substrate to a suitable thickness (Step 802).• Forming shallow trench isolation (STI) regions (Step 804).• Forming a P-type well (Step 806).• Performing gate oxidation (Step 808).• Depositing gate material (e.g., P+ poly-Si), patterning (e.g., masking and etching) to define a gate structure, and forming gate structure spacers (Step 810).• Forming an i- Si region at least partially under the drain-side of the gate structure (Step 812).• Patterning a drain-side drift region and angle implanting N- dopant (Step 814)• Optionally, patterning source-side halo and / or LDD regions and angle implanting dopant (Step 816).• Implanting an N+ source region, an N+ drain region, and one or more P+ body contact regions (Step 818).• Depositing a salicide block layer and patterning to define contact regions (Step 820).• Depositing salicide (e.g., NiSi) in the defined contact regions and annealing (Step 822).

[0051] As should be appreciated, other “recipes” that include additive and / or subtractive process steps may be used to fabricate essentially the same improved NEDMOS FET device structures of the types described in this disclosure. Further, the fabrications steps may be performed in any feasible order.Attorney Docket No. : P3132-PCT

[0052] It is common to include a Body-Tied-to-Source (BTS) structure for MOSFETs, and a BTS configuration may be used with the inventive devices. For example, FIGS. 9A-9C are top plan views of three example configurations of a BTS structure for a NEDMOS device of the types described in this disclosure.

[0053] FIG. 9A is a top plan view of a first configuration of a BTS structure for a NEDMOS device of the types described in this disclosure. Most of the component elements in the illustrated example have the same reference numbers as shown in FIG. 4. One added element includes a centrally-located P+ body contact region 902 fabricated in a conventional manner to electrically connect to the body (i.e., the P-well 412 in FIG. 4) of the device to provide a fourth terminal for the NEDMOS device. Also added is a contact 904 to the P+ region 902 that may be coupled to the source 410 through a device superstructure (not shown).

[0054] FIG. 9B is a top plan view of a second configuration of BTS structures for a NEDMOS device of the types described in this disclosure. Similar in many aspects to the device structure shown in FIG. 9A, the example configuration shown in FIG. 9B includes two end-positioned BTS structures comprising P+ body contact regions 902 and associated contacts 904. Again, the associated contacts 904 may be coupled to the source 410 through a device superstructure (not shown). Placing the BTS structures parallel to the X-dimension edges of the NEDMOS device reduces current leakage by increasing the VTH at those edges. Having more than one BTS structure provides more efficient electron (e-) collection compared to the single central BTS structure shown in FIG. 9A.

[0055] The number of BTS structures may be increased in some embodiments. For example, FIG. 9C is a top plan view of a third configuration of BTS structures for a NEDMOS device of the types described in this disclosure. Similar in many aspects to the device structure shown in FIG. 9B, the configuration shown in FIG. 9C includes four BTS structures comprising P+ body contact regions 902 and associated contacts 904, with two of the BTS structures being end-positioned as in FIG. 9B and two of the BTS structures being positioned at intermediate locations. As should be clear, embodiments of the inventive NEDMOS device may have any desired number of BTS structures that fit within the confines of the NEDMOS device layout.Attorney Docket No. : P3132-PCT

[0056] It should be appreciated that a number of features described in this disclosure may be “mixed and matched” to create further variations without departing from the scope of the invention. For instance, one or more NEDMOS FETs in an IC structure may include a secondary gate structure. As another example, one or more of the NEDMOS FETs in an IC structure may include a stepped GOX layer. As yet another example, a NEDMOS or N-type LDMOS device in accordance with the present invention may be combined with a P-type MOSFET device (e.g., a PEDMOS device or P-type LDMOS) to provide a high-voltage complementary MOS (CMOS) device pair. Accordingly, the invention is not limited to the specific examples described and illustrated in this disclosure.

[0057] Circuits and devices in accordance with the present invention may be used alone or in combination with other components, circuits, and devices. Embodiments of the present invention may be fabricated as integrated circuits (ICs), which may be encased in IC packages and / or in modules for ease of handling, manufacture, and / or improved performance. In particular, IC embodiments of this invention are often used in modules in which one or more of such ICs are combined with other circuit components or blocks (e.g., filters, amplifiers, passive components, and possibly additional ICs) into one package. The ICs and / or modules are then typically combined with other components, often on a printed circuit board, to form part of an end-product such as a cellular telephone, laptop computer, or electronic tablet, or to form a higher-level module which may be used in a wide variety of products, such as vehicles, test equipment, medical devices, etc. Through various configurations of modules and assemblies, such ICs typically enable a mode of communication, often wireless communication.

[0058] As one example of further integration of embodiments of the present invention with other components, FIG. 10 is a top plan view of a substrate 1000 that may be, for example, a printed circuit board or chip module substrate e.g., a thin-film tile). In the illustrated example, the substrate 1000 includes multiple ICs 1002a-1002d having terminal pads 1004 which would be interconnected by conductive vias and / or traces on and / or within the substrate 1000 or on the opposite (back) surface of the substrate 1000 (to avoid clutter, the surface conductive traces are not shown and not all terminal pads are labelled). The ICs 1002a-1002d may embody, for example, signal switches, active and / or passive fdters, amplifiers (including one or more low-noiseAttorney Docket No. : P3132-PCT amplifiers), and other circuitry. For example, IC 1002b may incorporate one or more instances of a NEDMOS FET like the device shown in FIG. 4

[0059] The substrate 1000 may also include one or more passive devices 1006 embedded in, formed on, and / or affixed to the substrate 1000. While shown as generic rectangles, the passive devices 1006 may be, for example, filters, capacitors, inductors, transmission lines, resistors, antennae elements, transducers (including, for example, MEMS-based transducers, such as accelerometers, gyroscopes, microphones, pressure sensors, etc. , batteries, etc., interconnected by conductive traces on or in the substrate 1000 to other passive devices 1006 and / or the individual ICs 1002a-1002d.

[0060] The front or back surface of the substrate 1000 may be used as a location for the formation of other structures. For example, one or more antennae may be formed on or affixed to the front or back surface of the substrate 1000; one example of a front-surface antenna 1008 is shown, coupled to an IC die 1002b, which may include RF front-end circuitry. Thus, by including one or more antennae on the substrate 1000, a complete radio may be created.

[0061] Embodiments of the present invention are useful in a wide variety of larger radio frequency (RF) circuits and systems for performing a range of functions, including (but not limited to) impedance matching circuits, RF power amplifiers, RF low-noise amplifiers (LNAs), phase shifters, attenuators, antenna beam-steering systems, charge pump devices, RF switches, etc. Such functions are useful in a variety of applications, such as radar systems (including phased array and automotive radar systems), radio systems (including cellular radio systems), and test equipment.

[0062] Radio system usage includes wireless RF systems (including base stations, relay stations, and hand-held transceivers) that use various technologies and protocols, including various types of orthogonal frequency-division multiplexing (“OFDM”), quadrature amplitude modulation (“QAM”), Code-Division Multiple Access (“CDMA”), Time-Division Multiple Access (“TDMA”), Wide Band Code Division Multiple Access (“W-CDMA”), Global System for Mobile Communications (“GSM”), Long Term Evolution (“LTE”), 5G, 6G, and WiFi (e.g., 802.1 la, b, g, ac, ax, be) protocols, as well as other radio communication standards and protocols.Attorney Docket No. : P3132-PCT

[0063] Another aspect of the invention includes methods for fabricating an integrated circuit on a substrate. For example, one such method includes: fabricating a source region within an active layer on the substrate, the source region doped to have a first semiconductor characteristic; fabricating a body region within the active layer adjacent to the source region, the body region doped to have a second semiconductor characteristic; fabricating a gate structure above the body region; fabricating an intrinsic silicon region within the active layer adjacent to the body region; fabricating a drift region within the active layer adjacent the intrinsic silicon region, the drift region doped to have a third semiconductor characteristic; and fabricating a drain region within the active layer adjacent the drift region, the drain region doped to have a fourth semiconductor characteristic.

[0064] Additional aspects of the above method may include one or more of the following: wherein the first semiconductor characteristic is N+, the second semiconductor characteristic is P- type, the third semiconductor characteristic is N-, and the fourth semiconductor characteristic is N+; fabricating a halo region and / or a lightly-doped drain region within the active layer on a source-side of the gate structure; fabricating an insulating layer and a trap rich layer between the substrate and the active layer; and / or wherein the gate structure is located so as to influence current flow through the body region and the intrinsic silicon region.

[0065] The term “MOSFET”, as used in this disclosure, includes any field effect transistor (FET) having an insulated gate whose voltage or charge level determines the conductivity of the transistor, and encompasses insulated gates having a metal or metal-like, insulator, and / or semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.

[0066] As used in this disclosure, the term “radio frequency” (RF) refers to a rate of oscillation in the range of about 3 kHz to about 300 GHz. This term also includes the frequencies used in wireless communication systems. An RF frequency may be the frequency of an electromagnetic wave or of an alternating voltage or current in a circuit.Attorney Docket No. : P3132-PCT

[0067] With respect to the figures referenced in this disclosure, the dimensions for the various elements are not to scale; some dimensions may be greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “vertical”, “horizontal”, etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.

[0068] Various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice. Various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, high-resistivity bulk CMOS, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, embodiments of the invention may be implemented in other transistor technologies, such as BiCMOS, LDMOS, BCD, FinFET, GAAFET, and SiC-based device technologies, using 2-D, 2.5- D, and 3-D structures. However, embodiments of the invention are particularly useful when fabricated using an SOI or SOS based process, or when fabricated with processes having similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation ( / .e., radio frequencies up to and exceeding 300 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.

[0069] A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, and / or parallel fashion.Attorney Docket No. : P3132-PCT

[0070] It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufactures, or compositions of matter set forth in the claims below. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).

Claims

Attorney Docket No. : P3132-PCTCLAIMSWHAT IS CLAIMED IS:

1. An extended drain field-effect transistor (FET) that includes an intrinsic silicon region positioned between a body region of the extended drain FET and a drift region of the extended drain FET.

2. The extended drain FET of claim 1, wherein the extended drain FET is a NEDMOS FET on a silicon-on-insulator substrate.

3. The extended drain FET of claim 1, wherein the extended drain FET is an LDMOS FET fabricated using bulk silicon.

4. An integrated circuit field-effect transistor fabricated on a substrate and including:(a) a source region fabricated within an active layer on the substrate and doped to have a first semiconductor characteristic;(b) a body region fabricated within the active layer adjacent to the source region and doped to have a second semiconductor characteristic;(c) a gate structure formed above the body region;(d) an intrinsic silicon region fabricated within the active layer adjacent to the body region;(e) a drift region fabricated within the active layer adjacent the intrinsic silicon region and doped to have a third semiconductor characteristic; and(f) a drain region fabricated within the active layer adjacent the drift region and doped to have a fourth semiconductor characteristic.

5. The integrated circuit field-effect transistor of claim 4, wherein the first semiconductor characteristic is N+, the second semiconductor characteristic is P-type, the third semiconductor characteristic is N-, and the fourth semiconductor characteristic is N+.

6. The integrated circuit field-effect transistor of claim 4, further including a halo region and / or a lightly-doped drain region fabricated within the active layer on a source-side of the gate structure.Attorney Docket No. : P3132-PCT7. The integrated circuit field-effect transistor of claim 4, further including an insulating layer and a trap rich layer between the substrate and the active layer.

8. The integrated circuit field-effect transistor of claim 4, wherein the gate structure is located so as to influence current flow through the body region and the intrinsic silicon region.

9. The integrated circuit field-effect transistor of claim 4, wherein the intrinsic silicon region is fabricated at least partially under a drain-side of the gate structure.

10. An integrated circuit field-effect transistor fabricated on a substrate and including:(a) a source region fabricated within an active layer on the substrate and doped to have a first semiconductor characteristic;(b) a body region fabricated within the active layer adjacent to the source region and doped to have a second semiconductor characteristic;(c) a gate structure formed above the body region;(d) a drift region fabricated within the active layer and doped to have a third semiconductor characteristic;(e) a drain region fabricated within the active layer adjacent the drift region and doped to have a fourth semiconductor characteristic; and(f) an intermediate region, fabricated within the active layer between the body region and the drift region, with substantially lower doping than the drift region.

11. The integrated circuit field-effect transistor of claim 10, wherein the first semiconductor characteristic is N+, the second semiconductor characteristic is P-type, the third semiconductor characteristic is N-, and the fourth semiconductor characteristic is N+.

12. The integrated circuit field-effect transistor of claim 10, further including a halo region and a lightly-doped drain region fabricated within the active layer on a source-side of the gate structure.

13. The integrated circuit field-effect transistor of claim 10, further including an insulating layer and a trap rich layer between the substrate and the active layer.Attorney Docket No. : P3132-PCT14. The integrated circuit field-effect transistor of claim 10, wherein the gate structure is located so as to influence current flow through the body region and the intermediate region.

15. The integrated circuit field-effect transistor of claim 10, wherein the intermediate silicon region is fabricated at least partially under a drain-side of the gate structure.

16. A method of fabricating a field-effect transistor within an integrated circuit on a substrate and including:(a) fabricating a source region within an active layer on the substrate, the source region doped to have a first semiconductor characteristic;(b) fabricating a body region within the active layer adjacent to the source region, the body region doped to have a second semiconductor characteristic;(c) fabricating a gate structure above the body region;(d) fabricating an intrinsic silicon region within the active layer adjacent to the body region;(e) fabricating a drift region within the active layer adjacent the intrinsic silicon region, the drift region doped to have a third semiconductor characteristic; and(f) fabricating a drain region within the active layer adjacent the drift region, the drain region doped to have a fourth semiconductor characteristic.

17. The method of claim 16, wherein the first semiconductor characteristic is N+, the second semiconductor characteristic is P-type, the third semiconductor characteristic is N-, and the fourth semiconductor characteristic is N+.

18. The method of claim 16, further including fabricating a halo region and / or a lightly-doped drain region within the active layer on a source-side of the gate structure.

19. The method of claim 16, further including fabricating the intrinsic silicon region at least partially under a drain-side of the gate structure.

20. The method of claim 16, wherein the gate structure is located so as to influence current flow through the body region and the intrinsic silicon region.

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