Chip frequency control circuit, buck power supply and chip frequency control method

Abstract

A chip frequency control circuit, a BUCK power supply and a chip frequency control method, which are applied to the technical field of power electronics. An input end of a frequency scaling control unit is connected to an output voltage feedback signal of a BUCK power supply, and an output end of the frequency reduction control unit is connected to a control end of a clock oscillator, which is used for adjusting, on the basis of the output voltage feedback signal, the frequency of a clock signal that is output by the clock oscillator, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The clock oscillator outputs clock signals to a switching tube control unit, and the switching tube control unit controls, on the basis of a clock signal driving voltage, the switching tube to turn on. Since the circuit directly changes the frequency of a clock signal of a chip clock oscillator, FB voltages corresponding to turn-on and turn-off instants of a voltage-controlled switching tube are relatively constant, such that the duty cycle variations among different cycles are small, and the amplitudes of the finally obtained inductor current pulses are uniformly distributed, thereby achieving linear and smooth adjustment of the frequency.

Description

Chip frequency control circuit, BUCK power supply and chip frequency control method

[0001] This application claims priority to Chinese Patent Application No. 2024115052854, filed on October 25, 2024, entitled "Chip Frequency Control Circuit, BUCK Power Supply and Chip Frequency Control Method", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of power electronics technology, and in particular to a chip frequency control circuit, a BUCK power supply, and a chip frequency control method. Background Technology

[0003] Figure 1 is a schematic diagram of a traditional chip frequency control circuit. As shown in Figure 1, the current frequency reduction control mode is a passive frequency reduction method, characterized by the clock signal CLK output by the clock oscillator OSC remaining constant in frequency. When the frequency is the constant highest frequency (i.e., not in frequency reduction mode), the falling edge of the CLK pulse will set the output of the D flip-flop DFF to a high level, providing a turn-on signal to the MOS transistor Q0 via the driver circuit Driver; and as long as the inductor current is within the resistor R... CS When the voltage drop across the transistor reaches the threshold voltage Vlimit, the MOSFET Q0 will turn off. When the load decreases, the feedback signal FB (i.e., the output voltage feedback signal) generated by the output voltage increases, and the voltage of FB becomes equal to the first reference voltage Vlimit. REF1 The output signal, amplified by operational amplifier EA1, is connected to the non-inverting input of feedback voltage comparator COMP1. The output signal of EA1 is compared with the second reference voltage V. REF2 The resulting down-frequency signal is set high, which resets the D flip-flop (DFF) and causes the driver output to go low, thus forcibly turning off the MOSFET Q0. This down-frequency signal typically lasts for several cycles, continuing until the FB voltage drops to equal V. REF1 hour.

[0004] As can be seen, in the traditional solution, the operating frequency decreases in a skip-cycle pattern, and the sudden frequency changes lead to instability in the inductor current. Furthermore, the FB signal exhibits voltage ripple, causing the width of the down-frequency signal output by the feedback voltage comparator COMP1 to be inconsistent across different cycles, potentially resulting in the MOSFET Q0 turning off earlier or later. This manifests as an unpredictable on-time of MOSFET Q0 and an unstable inductor current exhibiting varying levels of high and low values.

[0005] Therefore, how to achieve smooth linear frequency reduction and avoid instability of inductor current caused by frequency abrupt changes is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] The purpose of this application is to provide a chip frequency control circuit, a BUCK power supply, and a chip frequency control method to solve the problem of unstable inductor current caused by frequency sudden changes when entering the frequency reduction mode in traditional solutions.

[0007] To solve the above-mentioned technical problems, this application provides a chip frequency control circuit, including: a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage control switching transistor;

[0008] The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator. It is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0009] The output of the clock oscillator is connected to the switching control unit to output the clock signal to the switching control unit. The switching control unit is connected to the switch to drive the voltage control switch to turn on according to the clock signal.

[0010] Preferably, it further includes: a first operational amplifier;

[0011] The first input terminal of the first operational amplifier is connected to the output voltage feedback signal of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage; the output terminal of the first operational amplifier is connected to the input terminal of the frequency reduction control unit, and is used to output the amplified output voltage feedback signal to the frequency reduction control unit.

[0012] Preferably, the frequency reduction control unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first fixed current source, and a second fixed current source;

[0013] The sources of both the first PMOS transistor and the second PMOS transistor are connected to a voltage source, and the gates and drains of the first PMOS transistor and the second PMOS transistor are connected to each other.

[0014] The common terminal of the gate and drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is connected to the output terminal of the first operational amplifier.

[0015] The common terminal of the gate and drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the second reference voltage.

[0016] The source of the first NMOS transistor, the source of the second NMOS transistor, the positive terminal of the first fixed current source, and the gate of the third PMOS transistor are interconnected; the negative terminal of the first fixed current source and the drain of the third PMOS transistor are grounded.

[0017] The positive terminal of the second fixed current source is connected to a voltage source; the negative terminal of the second fixed current source and the source of the third PMOS transistor are connected to each other, and the common terminal of the connection is connected to the output terminal of the frequency reduction control unit and the control terminal of the clock oscillator.

[0018] Preferably, the clock oscillator includes: a variable current source, a first capacitor, a switch, and an internal comparator;

[0019] The positive terminal of the variable current source is connected to the voltage source; the negative terminal of the variable current source, the first terminal of the first capacitor, the first terminal of the switch, and the non-inverting input terminal of the internal comparator are connected to each other; the second terminal of the first capacitor and the second terminal of the switch are grounded.

[0020] The inverting input of the internal comparator is connected to the output of the frequency reduction control unit; the output of the internal comparator is connected to the control terminal of the switch; wherein, the output of the internal comparator serves as the output of the clock oscillator to output the clock signal.

[0021] Preferably, the variable current source is a voltage-controlled current source;

[0022] The control terminal of the voltage-controlled current source is connected to the output terminal of the frequency reduction control unit.

[0023] Preferably, the switching transistor control unit includes: a D flip-flop and a driving circuit;

[0024] The clock oscillator is connected to the first input terminal of the D flip-flop and is used to output the clock signal to the D flip-flop so as to set the output of the D flip-flop to a high level when the falling edge of the clock signal arrives.

[0025] The output of the D flip-flop is connected to the input of the driving circuit, and the output of the driving circuit is connected to the voltage control switch. When the D flip-flop outputs a high level, the driving circuit drives the voltage control switch to turn on.

[0026] Preferably, it further includes: a current sampling line for acquiring the peak current sampling signal;

[0027] The current sampling line is connected to the second input terminal of the D flip-flop and is used to reset the D flip-flop according to the peak current sampling signal and the amplified output voltage feedback signal, so as to turn off the voltage control switch.

[0028] Preferably, the current sampling line includes: a current sampling resistor, an adder, and an inductor current peak comparator;

[0029] The current sampling resistor is connected in series with the voltage control switch in the output circuit, and the first end of the current sampling resistor is grounded.

[0030] The first input terminal of the adder is connected to the second terminal of the current sampling resistor; the second input terminal of the adder is connected to the output terminal of the first operational amplifier; the output terminal of the adder is connected to the first input terminal of the inductor current peak comparator.

[0031] The second input terminal of the inductor current peak comparator is connected to a threshold voltage, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop. The output signal is used to reset the D flip-flop after the output of the adder is greater than the threshold voltage.

[0032] To address the aforementioned technical problems, this application also provides a BUCK power supply, including the aforementioned chip frequency control circuit.

[0033] To address the aforementioned technical problems, this application also provides a chip frequency control method applied to the aforementioned frequency reduction control unit; the method includes:

[0034] Obtain the output voltage feedback signal of the BUCK power supply;

[0035] The frequency of the clock signal output by the clock oscillator is adjusted according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0036] This application provides a chip frequency control circuit, comprising: a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator. It is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. Therefore, this scheme is an active frequency reduction method, characterized by a variable clock signal frequency of the clock oscillator. The output terminal of the clock oscillator is connected to the switching transistor control unit to output a clock signal to the switching transistor control unit. The switching transistor control unit is connected to a switch to drive the voltage control of the switching transistor to conduct according to the clock signal. Because this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the on and off points of the voltage-controlled switching transistor is relatively fixed, the duty cycle difference between different periods is small, and the final inductor current pulse amplitude is uniformly distributed, thereby achieving linear and smooth frequency adjustment.

[0037] This application also provides a BUCK power supply and a chip frequency control method, which corresponds to the chip frequency control circuit described above, and therefore has the same beneficial effects as the chip frequency control circuit described above. Attached Figure Description

[0038] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 is a schematic diagram of a traditional chip frequency control circuit.

[0040] Figure 2 is a schematic diagram of the inductor current and frequency curves of a common BUCK power supply.

[0041] Figure 3 is a schematic diagram of the operation of a traditional chip frequency control circuit in continuous mode.

[0042] Figure 4 is a schematic diagram of a common high-voltage BUCK power supply application circuit.

[0043] Figure 5 shows a simulation waveform diagram of the traditional Skip pulse frequency reduction method;

[0044] Figure 6 is a schematic diagram of a chip frequency control circuit provided in an embodiment of this application;

[0045] Figure 7 is a schematic diagram of the specific circuit structure of a frequency reduction control unit and a clock oscillator provided in an embodiment of this application;

[0046] Figure 8 is a schematic diagram of the simulation waveform of the novel chip frequency control circuit provided in the embodiment of this application in the frequency reduction region. Detailed Implementation

[0047] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0048] The core of this application is to provide a chip frequency control circuit, a BUCK power supply, and a chip frequency control method to solve the problem of unstable inductor current caused by frequency sudden changes when entering the frequency reduction mode in traditional solutions.

[0049] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0050] A buck converter, also known as a step-down converter, is a DC-DC converter circuit whose output voltage is lower than its input voltage. In this circuit, the input current is pulsating, while the output current is continuous. The core component of a buck converter is the inductor, which is responsible for converting the input voltage to the output voltage. The voltage-controlled switch is the control element, regulating the output voltage by changing its on and off states. Figure 2 shows a schematic diagram of the inductor current and frequency curves of a common buck converter; the output current Iout represents the load change, with a smaller Iout indicating a smaller load. As shown in Figure 2, as the load decreases, the current I... PK It will decrease to I PK_MIN At this point, continue to decrease I PK Switching frequency F SW It will start to decrease from a constant maximum frequency, that is, enter frequency reduction mode. Frequency reduction mode is one of the important means to reduce switching losses and improve power supply efficiency.

[0051] Taking the chip frequency control circuit in Figure 1 as an example, Figure 3 is a schematic diagram of the continuous mode operation of a traditional chip frequency control circuit. As shown in Figure 3, the built-in clock oscillator OSC provides a fixed frequency clock signal CLK. When the falling edge of CLK appears, the output of the D flip-flop sets the level of the driver circuit of the drive voltage control switch (i.e., MOS transistor Q0) to high. At this time, Q0 is turned on, and the inductor current I... IN_DUCTANCE It begins to rise. When the frequency is constant at its highest frequency, as long as the inductor current is within the resistance R... CS The voltage drop across reaches voltage V LIMIT When (i.e., when the inductor current reaches I) PK_LIMITQ0 will then be turned off.

[0052] As the load decreases from full load, the switching frequency needs to decrease from its constant maximum frequency to reduce losses in the switching devices. Its operating mechanism involves using an amplified output voltage feedback signal FB and a fixed second reference voltage V. REF2 As the input to the feedback voltage comparator COMP1, the output level of COMP1 serves as the down-frequency signal. When the down-frequency signal is high, it forcibly clears the D flip-flop DFF. After clearing, the output of the D flip-flop is low, and the drive of MOSFET Q0 remains off until the output voltage begins to decrease. Only after the down-frequency signal turns low will the D flip-flop output a high level generated by the falling edge of CLK, at which point the drive of MOSFET Q0 reverses back to high. As the load continuously decreases, the amplified FB voltage is lower than the second reference voltage V. REF2 In high frequency reduction, the high-level time of the signal will be continuously extended, thereby achieving a continuous decrease in frequency.

[0053] Figure 4 shows a schematic diagram of a common high-voltage BUCK power supply application circuit. As shown in Figure 4, the FB signal and the output capacitor are not grounded. The FB voltage comes from the resistor divider of the sampling capacitor C5. Because the time constant of capacitor C5 and resistor R1+R2 differs from the time constant of output capacitor C3*load resistance, a voltage ripple difference occurs between the two capacitors. Therefore, the FB signal can only approximately represent the output voltage signal. The circuit shown in Figure 1 uses a Skip pulse method. The clock pulse frequency of the OSC is fixed. When the frequency reduction circuit starts working, it reduces the frequency by shielding part of the drive pulse generated by the clock signal, i.e., reducing the number of drive pulses. Furthermore, the more frequently the frequency shielding signal appears and the longer each instance lasts, the greater the frequency reduction.

[0054] During the frequency reduction phase, the turn-off signal of MOSFET Q0 is controlled by R. CS The voltage drop and the down-frequency signal are jointly determined. The FB signal is generated by the voltage obtained by charging the sampling capacitor C5 through inductor L2 and diode D2 during the off-state of MOSFET Q0, and then passing it through voltage divider resistors R1 and R2. Since the FB signal and the output voltage signal do not share a common ground, this signal can only indirectly reflect the output voltage signal. The FB signal has voltage ripple, which causes the width of the down-frequency signal output by the feedback voltage comparator COMP1 to be inconsistent in different cycles, and the off-state time of MOSFET Q0 may be advanced or delayed. This manifests as an unstable conduction time of MOSFET Q0 and an unstable inductor current with varying levels.

[0055] Figure 5 shows a simulation waveform diagram of the traditional Skip pulse frequency reduction method. As shown in Figure 5, it includes the frequency reduction control signal, the MOSFET turn-on signal of the internal MOSFET Q0, the output voltage Vo on the output capacitor, the inductor current in inductor L2, the internal clock frequency CLK, and the voltage FB (i.e., the output voltage feedback signal) after the voltage on the output sampling capacitor is divided by a resistor. Due to the difference in the FB ripple voltage, the width of the frequency reduction signal varies in different cycles, resulting in significant differences in the conduction time of MOSFET Q0 in different cycles. Consequently, the peak value of the corresponding inductor current varies, directly leading to an increase in output voltage ripple.

[0056] The purpose of this application is to solve the problem of duty cycle instability that occurs after the BUCK power supply frequency decreases from a constant maximum frequency. To address this, a chip frequency control circuit is proposed, comprising: a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply. The output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator, used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The output terminal of the clock oscillator is connected to the switching transistor control unit to output a clock signal to the switching transistor control unit. The switching transistor control unit is connected to a switch to control the switching transistor to conduct according to the driving voltage of the clock signal.

[0057] This application does not limit the specific types and structures of the aforementioned components. A specific implementation is provided here. Figure 6 is a schematic diagram of a chip frequency control circuit provided in an embodiment of this application. As shown in Figure 6, the falling edge of the CLK pulse sets the output of the D flip-flop DFF to a high level, providing an on-state signal to the MOS transistor Q0 via the driver circuit. When the load decreases, the output voltage feedback signal FB increases, and the FB voltage is equal to the first reference voltage V. REF1 After passing through the first operational amplifier EA1, a down-frequency control signal is generated (i.e., the signal level increases). The clock frequency of the clock oscillator OSC decreases proportionally with the increase in signal level. In this mode, the output voltage feedback signal FB and the peak current sampling signal are superimposed and input to the non-inverting input of the inductor current peak comparator COMP2, and compared with the threshold voltage V. LIMIT After comparison, the inductor current peak comparator COMP2 generates a high-level reset D flip-flop DFF. At this time, the driver output is set to low, and the MOSFET Q0 is turned off. As the output load decreases from full load, the switching frequency begins to decrease, i.e., it enters the frequency reduction mode. The output feedback voltage FB and the first reference voltage V... REF1The compared voltage, after error amplification, directly controls the frequency of the chip's internal clock oscillator (OSC). This prevents sudden frequency changes and achieves smooth, linear frequency reduction.

[0058] Figure 7 is a schematic diagram of the specific circuit structure of a frequency reduction control unit and a clock oscillator (OSC) provided in an embodiment of this application. As shown in Figure 7, the first PMOS transistor Q1 and the second PMOS transistor Q2 use the "diode connection" method in analog circuits, with their gates and drains shorted. The transistors always operate in the saturation region, and their function is equivalent to a load resistor, used to regulate the current flowing through the series NMOS transistor. The first NMOS transistor Q3 and the second NMOS transistor Q4 realize the output voltage follower, realizing the switching of the input voltage at the inverting terminal of the internal comparator COMP3 at a constant maximum frequency and frequency reduction.

[0059] When the system load decreases, the output voltage feedback signal FB, after being compared with the reference voltage and amplified, triggers the frequency reduction function. The internal CLK clock frequency of the chip can be adjusted by changing the voltage comparison reference of the sawtooth wave of the internal capacitor's charging and discharging, or by changing the charging and discharging current of the capacitor. The left half of the figure shows the frequency reduction control unit, and the right half shows the clock oscillator OSC.

[0060] Clock frequency: C1 is charged by the variable current source I3, and the capacitor C1 is discharged by the switch S1 to generate a sawtooth wave. Then the sawtooth wave is compared with the input voltage IN1 to generate pulse width modulation CLK.

[0061] Constant operating frequency: determined by the second reference voltage V REF2 Control, at this time IN1 voltage = V REF2 -Vth4+Vth5≈V REF2 Vth4 and Vth5 are the threshold voltages corresponding to the second NMOS transistor Q4 and the third PMOS transistor Q5.

[0062] Operating frequency during frequency reduction: determined by the feedback voltage FB and the first reference voltage V. REF1 After comparison, the output Vout1 of the first operational amplifier EA1 controls the input. At this time, the IN1 voltage = Vout1 - Vth3 + Vth5 ≈ Vout1, where Vth3 and Vth5 are the threshold voltages of the first NMOS transistor Q3 and the third PMOS transistor Q5. During frequency reduction, Vout1 > V... REF2 As the voltage of IN1 increases, the sawtooth wave charging cycle on C1 becomes longer, and the operating frequency of the clock oscillator (OSC) decreases. I3 is specifically a voltage-controlled current source, and its current is also controlled by the voltage of IN1. When the voltage of IN1 increases, the current of I3 decreases. This design is intended to broaden the frequency range of the OSC, which helps to further reduce the switching frequency under light loads and improve system efficiency.

[0063] This scheme uses a variable frequency clock signal. When the output load decreases from full load and the frequency enters a frequency reduction mode, the output voltage feedback signal FB and the first reference voltage V... REF1 The compared voltage is amplified and directly reduces the frequency of the internal clock oscillator (OSC) of the chip. Furthermore, the frequency decreases smoothly and linearly as the load decreases. Figure 8 shows a simulation waveform diagram of the novel chip frequency control circuit provided in this application within the frequency reduction region. As shown in Figure 8, the simulation results indicate that the duty cycle of the power supply is relatively fixed for different cycles, the amplitude of the inductor current is relatively stable, and the resulting output ripple is uniform.

[0064] Traditional frequency reduction methods use a fixed clock frequency (CLK) for the OSC (Optical Clock Oscillator) and employ a method of shielding the Q0 drive pulse of a portion of the MOSFET to achieve frequency reduction. However, voltage ripple in the FB signal causes a difference in the FB voltage at the turn-off point, resulting in inconsistent amplitude of the inductor current in the frequency reduction region. In contrast, the novel frequency reduction method in this application avoids clearing the D flip-flop from the frequency reduction signal after the circuit starts operating, and does not forcibly pull down the CLK signal emitted by the OSC. Instead, the FB voltage signal is compared with a reference and directly controls the frequency of the OSC, thus reducing the switching frequency and achieving linear frequency reduction.

[0065] This application provides a chip frequency control circuit, including: a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator. It is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. Therefore, this scheme is an active frequency reduction method, characterized by a variable clock signal frequency of the clock oscillator. The output terminal of the clock oscillator is connected to the switching transistor control unit to output a clock signal to the switching transistor control unit. The switching transistor control unit is connected to a switch to drive the voltage control of the switching transistor to conduct according to the clock signal. Since this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the on and off points of the voltage-controlled switching transistor is relatively fixed, the duty cycle difference between different periods is small, and the final inductor current pulse amplitude is uniformly distributed, thereby achieving linear and smooth frequency adjustment.

[0066] As mentioned in the above embodiments, this application does not limit the specific structure of the chip frequency control circuit. The circuit provided in this embodiment also includes a first operational amplifier EA1; the first input terminal of the first operational amplifier is connected to the output voltage feedback signal FB of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage V. REF1The output of the first operational amplifier is connected to the input of the frequency reduction control unit, and is used to output the amplified output voltage feedback signal to the frequency reduction control unit. Amplifying the output voltage feedback signal through the first operational amplifier makes subsequent control more precise.

[0067] Based on the above implementation, this embodiment provides a specific frequency reduction control unit to control the clock frequency of a clock oscillator. Specifically, the frequency reduction control unit of this embodiment consists of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first fixed current source, and a second fixed current source. The sources of both the first and second PMOS transistors are connected to a voltage source, and their gates and drains are interconnected. The common terminal of the gate and drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is connected to the output terminal of the first operational amplifier. The common terminal of the gate and drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and its gate is connected to a second reference voltage. The sources of the first and second NMOS transistors, the positive terminal of the first fixed current source, and the gate of the third PMOS transistor are interconnected; the negative terminal of the first fixed current source and the drain of the third PMOS transistor are grounded. The positive terminal of the second fixed current source is connected to the voltage source; the negative terminal of the second fixed current source and the source of the third PMOS transistor are interconnected, and their common terminal serves as the output terminal of the frequency reduction control unit, which is connected to the control terminal of the clock oscillator. Correspondingly, the clock oscillator specifically consists of a variable current source, a first capacitor, a switch, and an internal comparator. The positive terminal of the variable current source is connected to the voltage source; the negative terminal of the variable current source, the first terminal of the first capacitor, the first terminal of the switch, and the non-inverting input terminal of the internal comparator are interconnected; the second terminal of the first capacitor and the second terminal of the switch are grounded; the inverting input terminal of the internal comparator is connected to the output terminal of the frequency reduction control unit; the output terminal of the internal comparator is connected to the control terminal of the switch; wherein, the output terminal of the internal comparator serves as the output terminal of the clock oscillator to output the clock signal. Specifically, the variable current source is a voltage-controlled current source; the control terminal of the voltage-controlled current source is connected to the output terminal of the frequency reduction control unit. By controlling the voltage-controlled switch Q0 through the specific structure provided in this embodiment, a smooth linear frequency reduction can be achieved because the frequency of the clock oscillator will not change abruptly.

[0068] In practical applications, the switching control unit can be composed of a D flip-flop and a driving circuit. The clock oscillator is connected to the first input terminal of the D flip-flop and is used to output a clock signal to the D flip-flop so that the output of the D flip-flop is set to a high level when the falling edge of the clock signal arrives. The output terminal of the D flip-flop is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is connected to the voltage control switching transistor. After the D flip-flop outputs a high level, the driving circuit drives the voltage control switching transistor to conduct.

[0069] The above structure can drive the voltage-controlled switch to turn on. After the voltage-controlled switch is turned on, it needs to be turned off to achieve complete control of the voltage-controlled switch. This embodiment provides a specific implementation scheme. The chip frequency control circuit also includes a current sampling circuit for acquiring the peak current sampling signal. The current sampling circuit is connected to the second input terminal of the D flip-flop and is used to reset the D flip-flop based on the peak current sampling signal and the amplified output voltage feedback signal to turn off the voltage-controlled switch. Here is a specific structure of the current sampling circuit, including: a current sampling resistor, an adder, and an inductor current peak comparator; the current sampling resistor is connected in series with the voltage-controlled switch in the output circuit, and the first terminal of the current sampling resistor is grounded; the first input terminal of the adder is connected to the second terminal of the current sampling resistor; the second input terminal of the adder is connected to the output terminal of the first operational amplifier; the output terminal of the adder is connected to the first input terminal (non-inverting input terminal) of the inductor current peak comparator; the second input terminal (inverting input terminal) of the inductor current peak comparator is connected to a threshold voltage, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop, used to output a signal to reset the D flip-flop after the output of the adder is greater than the threshold voltage. The output voltage feedback signal FB and the peak current sampling signal are superimposed and then input to the non-inverting input of the inductor current peak comparator, and compared with the threshold voltage V at the inverting input. LIMIT After comparison, the inductor current peak comparator generates a high-level reset D flip-flop. At this time, the output of the drive circuit is set to low level, and the voltage-controlled switch Q0 is turned off.

[0070] To address the aforementioned technical problems, this application provides a BUCK power supply, including the chip frequency control circuit described in the above embodiments.

[0071] Since the embodiments of the BUCK power supply section correspond to the embodiments of the chip frequency control circuit section, please refer to the description of the embodiments of the chip frequency control circuit section for the embodiments of the BUCK power supply section, which will not be repeated here.

[0072] The BUCK power supply provided in this embodiment corresponds to the frequency control circuit of the chip described above, and therefore has the same beneficial effects as the frequency control circuit of the chip described above.

[0073] To address the aforementioned technical problems, this application also provides a chip frequency control method applied to the frequency reduction control unit in the above embodiments. The method includes the following steps: S1: Obtaining the output voltage feedback signal of the BUCK power supply. S2: Adjusting the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. Wherein, the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0074] Since the embodiments of the method section correspond to the embodiments of the chip frequency control circuit section, please refer to the description of the embodiments of the chip frequency control circuit section for the embodiments of the method section, which will not be repeated here.

[0075] The method provided in this embodiment corresponds to the chip frequency control circuit described above, and therefore has the same beneficial effects as the chip frequency control circuit described above.

[0076] The foregoing has provided a detailed description of a chip frequency control circuit, a BUCK power supply, and a chip frequency control method provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of this application.

[0077] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

Claims

1. A chip frequency control line circuit, characterized by, include: Frequency reduction control unit, clock oscillator, switching transistor control unit, and voltage-controlled switching transistor; The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator. It is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The output of the clock oscillator is connected to the switching control unit to output the clock signal to the switching control unit. The switching control unit is connected to the switch to drive the voltage control switch to turn on according to the clock signal.

2. The chip frequency control line according to claim 1, characterized in that, Also includes: First operational amplifier; The first input terminal of the first operational amplifier is connected to the output voltage feedback signal of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage; the output terminal of the first operational amplifier is connected to the input terminal of the frequency reduction control unit, and is used to output the amplified output voltage feedback signal to the frequency reduction control unit.

3. The chip frequency control line according to claim 2, characterized in that The frequency reduction control unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first fixed current source, and a second fixed current source; The sources of both the first PMOS transistor and the second PMOS transistor are connected to a voltage source, and the gates and drains of the first PMOS transistor and the second PMOS transistor are connected to each other. The common terminal of the gate and drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is connected to the output terminal of the first operational amplifier. The common terminal of the gate and drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to the second reference voltage. The source of the first NMOS transistor, the source of the second NMOS transistor, the positive terminal of the first fixed current source, and the gate of the third PMOS transistor are interconnected; the negative terminal of the first fixed current source and the drain of the third PMOS transistor are grounded. The positive terminal of the second fixed current source is connected to a voltage source; the negative terminal of the second fixed current source and the source of the third PMOS transistor are connected to each other, and the common terminal of the connection is connected to the output terminal of the frequency reduction control unit and the control terminal of the clock oscillator.

4. The chip frequency control line according to claim 3, characterized in that The clock oscillator includes: a variable current source, a first capacitor, a switch, and an internal comparator; The positive terminal of the variable current source is connected to the voltage source; the negative terminal of the variable current source, the first terminal of the first capacitor, the first terminal of the switch, and the non-inverting input terminal of the internal comparator are connected to each other; the second terminal of the first capacitor and the second terminal of the switch are grounded. The inverting input of the internal comparator is connected to the output of the frequency reduction control unit; the output of the internal comparator is connected to the control terminal of the switch; wherein, the output of the internal comparator serves as the output of the clock oscillator to output the clock signal.

5. The chip frequency control line according to claim 4, characterized in that The variable current source is specifically a voltage-controlled current source; The control terminal of the voltage-controlled current source is connected to the output terminal of the frequency reduction control unit.

6. The chip frequency control circuit according to any one of claims 2 to 5, wherein The switching control unit includes: a D flip-flop and a driving circuit; The clock oscillator is connected to the first input terminal of the D flip-flop and is used to output the clock signal to the D flip-flop so as to set the output of the D flip-flop to a high level when the falling edge of the clock signal arrives. The output of the D flip-flop is connected to the input of the driving circuit, and the output of the driving circuit is connected to the voltage control switch. When the D flip-flop outputs a high level, the driving circuit drives the voltage control switch to turn on.

7. The chip frequency control line according to claim 6, characterized in that Also includes: A current sampling circuit used to acquire peak current sampling signals; The current sampling line is connected to the second input terminal of the D flip-flop and is used to reset the D flip-flop according to the peak current sampling signal and the amplified output voltage feedback signal, so as to turn off the voltage control switch.

8. The chip frequency control line according to claim 7, characterized in that The current sampling circuit includes: a current sampling resistor, an adder, and an inductor current peak comparator; The current sampling resistor is connected in series with the voltage control switch in the output circuit, and the first end of the current sampling resistor is grounded. The first input terminal of the adder is connected to the second terminal of the current sampling resistor; the second input terminal of the adder is connected to the output terminal of the first operational amplifier; the output terminal of the adder is connected to the first input terminal of the inductor current peak comparator. The second input terminal of the inductor current peak comparator is connected to a threshold voltage, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop. The output signal is used to reset the D flip-flop after the output of the adder is greater than the threshold voltage.

9. A BUCK power supply, characterized by, Includes the chip frequency control circuit as described in any one of claims 1 to 8.

10. A method of chip frequency control, characterized by, The method is applied to the frequency reduction control unit according to any one of claims 1 to 8; the method includes: Obtain the output voltage feedback signal of the BUCK power supply; The frequency of the clock signal output by the clock oscillator is adjusted according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

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