3D optoelectronic interconnection packaging structure and preparation method therefor

Abstract

The present invention belongs to the technical field of semiconductor manufacturing. Provided are a 3D optoelectronic interconnection packaging structure and a preparation method therefor. A glass waveguide structure can be constructed using a glass composite in combination with a dielectric layer. By means of forming a through trench which exposes a glass waveguide layer and bonding a lateral light-emitting chip in the through trench, a light transmission path can be constructed by a photosensitive region of the lateral light-emitting chip and the glass waveguide layer; and optoelectronic interconnection can be realized by means of the interconnection between metal pillars, redistribution layers and an adapter plate. The present invention can achieve optoelectronic interconnection integration, reduce package size, lower power consumption and improve reliability, and is applicable to high-density integration packaging and can achieve good optoelectronic transmission.

Description

3D optoelectronic interconnect packaging structure and its fabrication method Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology and relates to a 3D optoelectronic interconnect packaging structure and its preparation method. Background Technology

[0002] 3D interconnect packaging is a packaging technology that achieves high-density integration and efficient interconnection by stacking chips in the vertical direction. This technology mainly uses through-silicon via (TSV) adapters, through-glass via (TGV) adapters, and microbump technology to achieve interconnection between chips.

[0003] A microprocessor is an integrated circuit chip used to perform arithmetic and logical operations in a computer and control other devices and functions; it is a core component of computers or other electronic devices. With the continuous increase in microprocessor performance, the maximum available data communication rate of electronic interconnects used for data inflow and outflow has become increasingly dominant, meaning that the maximum available data communication rate of electronic interconnects limits the overall system performance. Optical interconnects, due to their high bandwidth-length product (BLP) and the ability to reduce power and save costs, are used to integrate electronic interconnects for optoelectronic interconnects, effectively solving the bottleneck problem of electronic interconnects.

[0004] Therefore, it is necessary to provide a 3D optoelectronic interconnect packaging structure and its fabrication method. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a 3D optoelectronic interconnect packaging structure and its fabrication method, so as to solve the bottleneck problem of electronic interconnect in the application of the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a method for fabricating a 3D optoelectronic interconnect packaging structure, comprising the following steps:

[0007] A glass composite is provided, the glass composite comprising a stacked glass substrate and a glass waveguide layer, wherein the refractive index of the glass waveguide layer is greater than the refractive index of the glass substrate;

[0008] The glass waveguide layer is patterned to expose a portion of the glass substrate;

[0009] A dielectric layer is formed on the exposed glass substrate, the dielectric layer covering the glass waveguide layer, and the refractive index of the dielectric layer is less than the refractive index of the glass waveguide layer;

[0010] A metal pillar is formed that penetrates the dielectric layer and the glass substrate;

[0011] A first redistribution layer is formed on the dielectric layer and a second redistribution layer is formed on the glass substrate, and both the first redistribution layer and the second redistribution layer are electrically connected to the metal pillar;

[0012] A through-groove is formed that penetrates the first redistribution layer, the dielectric layer, the glass substrate, and the second redistribution layer, and the sidewalls of the through-groove expose the glass waveguide layer;

[0013] A composite adapter board is provided, the composite adapter board including an adapter board and a third rewiring layer and a fourth rewiring layer located on both sides of the adapter board, and the adapter board, the third rewiring layer and the fourth rewiring layer are electrically connected.

[0014] The composite adapter board is bonded to the second redistribution layer and located above the through slot; the third redistribution layer is electrically connected to the second redistribution layer.

[0015] An electrical chip and a side-emitting chip are provided, and the electrical chip is bonded to the fourth redistribution layer and electrically connected to the fourth redistribution layer. The side-emitting chip is bonded to the through-groove and electrically connected to the third redistribution layer. The photosensitive area of ​​the side-emitting chip is correspondingly disposed with the glass waveguide layer.

[0016] Metal bumps are formed on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.

[0017] Optionally, the glass composite is prepared by a fusion drawing and lamination method.

[0018] Optionally, the dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer.

[0019] Optionally, the drilling method for forming the metal column includes laser drilling or mechanical drilling; the method for forming the through groove includes laser drilling or mechanical drilling.

[0020] Optionally, the adapter board includes a TSV adapter board or a TGV adapter board.

[0021] Optionally, the method further includes the step of forming an underfill layer between the electrical chip and the fourth redistribution layer.

[0022] Optionally, the glass composite is wafer-level in size and includes a dicing process after the metal bumps are formed.

[0023] The present invention also provides a 3D optoelectronic interconnect packaging structure, the 3D optoelectronic interconnect packaging structure comprising:

[0024] A glass composite comprising stacked glass substrates and patterned glass waveguide layers, wherein the glass waveguide layers expose a portion of the glass substrates and the refractive index of the glass waveguide layers is greater than the refractive index of the glass substrates.

[0025] A dielectric layer is located on the exposed glass substrate and covers the glass waveguide layer, and the refractive index of the dielectric layer is less than that of the glass waveguide layer.

[0026] A metal pillar that penetrates the dielectric layer and the glass substrate;

[0027] A first redistribution layer is located on the dielectric layer and is electrically connected to the metal pillar.

[0028] A second redistribution layer is located on the glass substrate and is electrically connected to the metal pillar.

[0029] A through-slot, the through-slot passing through the first redistribution layer, the dielectric layer, the glass substrate and the second redistribution layer, and the sidewall of the through-slot exposing the glass waveguide layer;

[0030] A composite adapter board, which is bonded to the second redistribution layer and located above the through slot, includes an adapter board and a third redistribution layer and a fourth redistribution layer located on both sides of the adapter board. The adapter board, the third redistribution layer and the fourth redistribution layer are electrically connected, and the third redistribution layer is electrically connected to the second redistribution layer.

[0031] An electrical chip, which is bonded to the fourth redistribution layer and electrically connected to the fourth redistribution layer;

[0032] A side-emitting chip is bonded to the through groove, the side-emitting chip is electrically connected to the third redistribution layer, and the photosensitive area of ​​the side-emitting chip is correspondingly disposed with the glass waveguide layer.

[0033] A metal bump is located on the first redistribution layer and is electrically connected to the first redistribution layer.

[0034] Optionally, the dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer; the adapter board includes a TSV adapter board or a TGV adapter board.

[0035] Optionally, the electrical chip and the fourth redistribution layer also have an underfill layer.

[0036] As described above, the 3D optoelectronic interconnect packaging structure and its fabrication method of the present invention can construct a glass waveguide structure by combining a glass composite with a dielectric layer. By forming a through-groove that exposes the glass waveguide layer and bonding a side-emitting chip in the through-groove, the photosensitive area of ​​the side-emitting chip and the glass waveguide layer can form a light transmission path. Furthermore, optoelectronic interconnection can be achieved through the interconnection of metal pillars, a redistribution layer, and an adapter board.

[0037] The 3D optoelectronic interconnect packaging structure and its fabrication method of the present invention can realize optoelectronic interconnect integration, reduce packaging size, reduce power consumption, improve reliability, are suitable for high-density integrated packaging, and can achieve good optoelectronic transmission. Attached Figure Description

[0038] Figure 1 shows a schematic diagram of the process flow for fabricating a 3D optoelectronic interconnect packaging structure in an embodiment of the present invention.

[0039] Figure 2 shows a schematic diagram of the structure of the glass composite in an embodiment of the present invention.

[0040] Figure 3 shows a schematic diagram of the structure after the patterned photoresist layer is formed in an embodiment of the present invention.

[0041] Figure 4 shows a schematic diagram of the structure after the patterned glass waveguide layer is formed in an embodiment of the present invention.

[0042] Figure 5 shows a schematic diagram of glass waveguide layers with different structural morphologies in an embodiment of the present invention.

[0043] Figure 6 shows a schematic diagram of the structure after the dielectric layer is formed in an embodiment of the present invention.

[0044] Figure 7 shows a schematic diagram of the structure after the metal column is formed in an embodiment of the present invention.

[0045] Figure 8 shows a schematic diagram of the structure after the formation of the first redistribution layer and the second redistribution layer in an embodiment of the present invention.

[0046] Figure 9 shows a schematic diagram of the structure after the through groove is formed in an embodiment of the present invention.

[0047] Figure 10 shows a schematic diagram of the distribution structure of the through groove in an embodiment of the present invention.

[0048] Figure 11 shows a schematic diagram of the structure after bonding the composite adapter plate in an embodiment of the present invention.

[0049] Figure 12 shows a schematic diagram of the structure of the bonded electrical chip in an embodiment of the present invention.

[0050] Figure 13 shows a schematic diagram of the structure after bonding the lateral light-emitting chip in an embodiment of the present invention.

[0051] Figure 14 shows a schematic diagram of the structure after the bottom filling layer and metal bumps are formed in an embodiment of the present invention.

[0052] Explanation of reference numerals in the attached figures: 100-glass substrate; 200-glass waveguide layer; 300-photoresist layer; 400-dielectric layer; 500-metal pillar; 610-first redistribution layer; 620-second redistribution layer; 630-third redistribution layer; 640-fourth redistribution layer; 700-through groove; 800-interchange plate; 910-electrical chip; 920-side-emitting chip; 921-photosensitive area; 110-bottom filler layer; 120-metal bump. Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0055] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, when a layer is referred to as “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0056] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0057] Referring to Figure 1, this embodiment provides a method for fabricating a 3D optoelectronic interconnect packaging structure, which can realize optoelectronic interconnect integration, reduce packaging size, reduce power consumption, improve reliability, is suitable for high-density integrated packaging, and can achieve good optoelectronic transmission.

[0058] The fabrication of the 3D optoelectronic interconnect packaging structure will be further described below with reference to Figures 2 to 14 of the specification.

[0059] First, referring to Figures 1 and 2, step S1 is performed to provide a glass composite, which includes a stacked glass substrate 100 and a glass waveguide layer 200, and the refractive index of the glass waveguide layer 200 is greater than the refractive index of the glass substrate 100.

[0060] As an example, the preparation method of the glass composite may include a fusion-drawing lamination method, but is not limited to this. In this embodiment, the glass composite adopts a fusion-drawing lamination method, and the refractive index of the upper glass waveguide layer 200 is greater than the refractive index of the lower glass substrate 100, so as to facilitate the subsequent construction of the glass waveguide structure.

[0061] When the glass composite is prepared by fusion drawing and lamination method, it is preferable that the refractive index difference between the glass waveguide layer 200 and the glass substrate 100 is 5% to 10%, such as 5%, 6%, 8%, 10%, etc., so that the glass substrate 100 can serve as the lower cladding layer of the glass waveguide layer 200, so as to facilitate the subsequent preparation of a glass waveguide structure with good transmission performance.

[0062] As an example, the glass composite may be wafer-level in size.

[0063] Specifically, in this embodiment, the glass composite is preferably wafer-level in size, such as 4 inches, 6 inches, 8 inches, 12 inches, etc., to facilitate the fabrication of high-performance wafer-level packaging structures. The specific size of the glass composite is not excessively limited here, and the thickness of the glass substrate 100 and the glass waveguide layer 200 in the glass composite can also be selected as needed.

[0064] Next, referring to Figures 1, 3 and 4, step S2 is performed to pattern the glass waveguide layer 200 and expose a portion of the glass substrate 100.

[0065] Specifically, referring to Figure 3, the patterned photoresist layer 300 can be formed by coating photoresist on the glass waveguide layer 200, selecting a mask with the desired pattern, and then performing exposure and development steps. Then, the glass waveguide layer 200 is etched based on the photoresist layer 300, and the excess photoresist layer 300 is removed, thus the patterned glass waveguide layer 200 can be prepared.

[0066] The morphology of the glass waveguide layer 200 can be referred to Figure 5, which illustrates six structural schematic diagrams of the glass waveguide layer 200 with different morphologies. The morphology of the glass waveguide layer 200 is not limited to these. The required patterned mask can be selected and set as needed to form the photoresist layer 300 with different morphologies, and the glass waveguide layer 200 with different morphologies can be prepared by etching. The specific morphology of the glass waveguide layer 200 is not excessively limited here.

[0067] The material of the photoresist layer 300 can be either positive or negative photoresist, and the specific choice can be made according to the needs, without limitation here.

[0068] Next, referring to Figures 1 and 6, step S3 is performed to form a dielectric layer 400 on the exposed glass substrate 100. The dielectric layer 400 covers the glass waveguide layer 200, and the refractive index of the dielectric layer 400 is less than the refractive index of the glass waveguide layer 200.

[0069] Specifically, the dielectric layer 400 can be made of insulating materials such as polyimide (PI) or silicon oxide to avoid subsequent impact on electrical transmission.

[0070] Furthermore, when selecting the material of the dielectric layer 400, the refractive index of the selected material must also be considered so that the dielectric layer 400 can be used as the upper cladding layer of the glass waveguide layer 200.

[0071] Next, referring to Figures 1 and 7, step S4 is performed to form a metal pillar 500 that penetrates the dielectric layer 400 and the glass substrate 100.

[0072] Specifically, the step of forming the metal pillar 500 may include forming a through hole (not shown) penetrating the dielectric layer 400 and the glass substrate 100, and filling the through hole with metal.

[0073] The drilling methods can include laser drilling or mechanical drilling, which can be selected according to the needs. The filling method can be electroplating, etc.

[0074] The specific steps for preparing the metal pillar 500, the size of the metal pillar 500, and the distribution of the metal pillar 500 are not overly restricted here, and can be selected as needed. The material of the metal pillar 500 can be copper, but is not limited to this; other conductive metal materials can also be used.

[0075] Next, referring to Figures 1 and 8, step S5 is performed to form a first redistribution layer 610 on the dielectric layer 400 and a second redistribution layer 620 on the glass substrate 100, and both the first redistribution layer 610 and the second redistribution layer 620 are electrically connected to the metal pillar 500.

[0076] Specifically, the method for forming the first redistribution layer 610 on the dielectric layer 400 may include a semiconductor process method or a substrate bonding method. Similarly, the method for forming the second redistribution layer 620 on the glass substrate 100 may include a semiconductor process method or a substrate bonding method.

[0077] The semiconductor manufacturing process is a method that uses steps such as coating, exposure, development, deposition, and etching to prepare the first redistribution layer 610 and the second redistribution layer 620. The substrate bonding method is a method that prepares the required first redistribution layer 610 and the second redistribution layer 620 in advance, and then bonds the first redistribution layer 610 and the second redistribution layer 620 to the dielectric layer 400 and the glass substrate 100, respectively.

[0078] Since both the first redistribution layer 610 and the second redistribution layer 620 are electrically connected to the metal pillar 500, the first redistribution layer 610 and the second redistribution layer 620 can be electrically interconnected through the metal pillar 500.

[0079] The specific structure, material, and preparation method of the first redistribution layer 610 and the second redistribution layer 620 are not excessively restricted here. They can be selected as needed. They can use the same structure, material, and preparation method, or they can use different structures, materials, and preparation methods.

[0080] Next, referring to Figures 1, 9 and 10, step S6 is performed to form a through-groove 700 that penetrates the first redistribution layer 610, the dielectric layer 400, the glass substrate 100 and the second redistribution layer 620, and the sidewall of the through-groove 700 exposes the glass waveguide layer 200.

[0081] Specifically, the method for forming the through-slot 700 may include laser drilling or mechanical drilling. The preparation method, size, morphology, and distribution of the through-slot 700 can be selected as needed. Figure 10 illustrates a distribution of multiple through-slots 700 with a rectangular morphology. It should be noted that, in order to construct the subsequent optical transmission path, the sidewalls of the through-slot 700 need to expose the glass waveguide layer 200.

[0082] Next, referring to Figures 1 and 11, step S7 is performed to provide a composite adapter board, which includes an adapter board 800 and a third redistribution layer 630 and a fourth redistribution layer 640 located on both sides of the adapter board 800, and the adapter board 800, the third redistribution layer 630 and the fourth redistribution layer 640 are electrically connected.

[0083] As an example, the adapter board 800 may include a TSV adapter board or a TGV adapter board, and the specific type can be selected as needed.

[0084] The third redistribution layer 630 and the fourth redistribution layer 640, together with the intermediate adapter board 800, can achieve electrical interconnection. The specific structure and fabrication method of the composite adapter board are not limited here.

[0085] Next, referring to Figures 1 and 11, step S8 is performed, whereby the composite adapter board is bonded to the second redistribution layer 620 and located above the through slot 700, and the third redistribution layer 630 is electrically connected to the second redistribution layer 620.

[0086] Specifically, the composite adapter board can be bonded to the second redistribution layer 620 via reflow soldering or similar processes, and the electrical interconnection between the third redistribution layer 630 and the second redistribution layer 620 can be achieved using solder balls. However, the bonding method between the composite adapter board and the second redistribution layer 620 is not limited to this. The portion of the composite adapter board exposed in the through-groove 700 may have pads, which facilitate subsequent electrical interconnection with the optical chip.

[0087] Next, referring to Figures 1, 12, and 13, step S9 is performed, providing an electrical chip 910 and a side-emitting chip 920, and bonding the electrical chip 910 to the fourth redistribution layer 640, and electrically connecting the electrical chip 910 to the fourth redistribution layer 640, and bonding the side-emitting chip 920 to the through-groove 700, and electrically connecting the side-emitting chip 920 to the third redistribution layer 630, and the photosensitive area 921 of the side-emitting chip 920 is correspondingly disposed with the glass waveguide layer 200.

[0088] Specifically, after the side-emitting chip 920 is bonded within the through-groove 700, it can be electrically interconnected with the third redistribution layer 630. The photosensitive area 921 of the side-emitting chip 920 is correspondingly disposed with the glass waveguide layer 200, thereby forming an optical transmission path. The electrical chip 910 may include active components configured specifically for operation using electrical signals, such as one or more transistors, voltage converters, transimpedance amplifiers (TIAs), clock data recovery (CDR) components, microcontrollers, etc. The electrical chip 910 may include various functions, such as driving, processing, and clearing signals from and to the side-emitting chip 920, and providing the necessary voltage to the side-emitting chip 920. No excessive limitations are placed here regarding the specific types, quantities, and distribution of the electrical chip 910 and the side-emitting chip 920.

[0089] As an example, the electrical chip 910 and the fourth redistribution layer 640 may also have a bottom filler layer 110 to cover the gap between the electrical chip 910 and the fourth redistribution layer 640, thereby protecting the electrical chip 910 and the fourth redistribution layer 640.

[0090] Next, referring to Figures 1 and 14, step S10 is performed to form a metal bump 120 on the first redistribution layer 610, and the metal bump 120 is electrically connected to the first redistribution layer 610. The fabrication and material of the metal bump 120 are not excessively limited here.

[0091] Furthermore, when the glass composite is wafer-level in size, a dicing process can be used after forming the metal bumps 120 to divide the prepared wafer-level packaging structure into multiple independently configured packaging unit structures, thereby improving production efficiency. The dicing process can be mechanical cutting or laser cutting; no excessive restrictions are imposed here.

[0092] Referring to Figures 2 to 14, this embodiment also provides a 3D optoelectronic interconnect packaging structure. The 3D optoelectronic interconnect packaging structure can be directly prepared using the above-described fabrication process. Therefore, the materials, structure, etc. of the 3D optoelectronic interconnect packaging structure can be found in the above description. Of course, the 3D optoelectronic interconnect packaging structure can also be prepared using other fabrication processes as needed.

[0093] In this embodiment, the 3D optoelectronic interconnect packaging structure includes:

[0094] A glass composite comprising a stacked glass substrate 100 and a patterned glass waveguide layer 200, wherein the glass waveguide layer 200 exposes a portion of the glass substrate 100 and the refractive index of the glass waveguide layer 200 is greater than the refractive index of the glass substrate 100.

[0095] A dielectric layer 400 is located on the exposed glass substrate 100 and covers the glass waveguide layer 200, and the refractive index of the dielectric layer 400 is less than the refractive index of the glass waveguide layer 200.

[0096] Metal pillar 500, the metal pillar 500 penetrating the dielectric layer 400 and the glass substrate 100;

[0097] A first redistribution layer 610 is located on the dielectric layer 400 and is electrically connected to the metal pillar 500.

[0098] A second redistribution layer 620 is located on the glass substrate 100 and is electrically connected to the metal pillar 500.

[0099] A through-slot 700 penetrates the first redistribution layer 610, the dielectric layer 400, the glass substrate 100, and the second redistribution layer 620, and the sidewalls of the through-slot 700 expose the glass waveguide layer 200.

[0100] A composite adapter board, which is bonded to the second redistribution layer 620 and located above the through groove 700, includes an adapter board 800 and a third redistribution layer 630 and a fourth redistribution layer 640 located on both sides of the adapter board 800. The adapter board 800, the third redistribution layer 630 and the fourth redistribution layer 640 are electrically connected, and the third redistribution layer 630 is electrically connected to the second redistribution layer 620.

[0101] Electrical chip 910 is bonded to the fourth redistribution layer 640 and is electrically connected to the fourth redistribution layer 640.

[0102] A side-emitting chip 920 is bonded to the through groove 700. The side-emitting chip 920 is electrically connected to the third redistribution layer 630, and the photosensitive area 921 of the side-emitting chip 920 is correspondingly disposed with the glass waveguide layer 200.

[0103] Metal bump 120, the metal bump 120 is located on the first redistribution layer 610 and is electrically connected to the first redistribution layer 610.

[0104] As an example, the dielectric layer 400 may include a polyimide dielectric layer or a silicon oxide dielectric layer.

[0105] Specifically, the dielectric layer 400 can be made of insulating materials such as polyimide (PI) or silicon oxide to avoid subsequent impact on electrical transmission.

[0106] Furthermore, when selecting the material of the dielectric layer 400, the refractive index of the selected material must also be considered so that the dielectric layer 400 can be used as the upper cladding layer of the glass waveguide layer 200.

[0107] As an example, the adapter board 800 may include a TSV adapter board or a TGV adapter board.

[0108] As an example, the electrical chip 910 and the fourth redistribution layer 640 may also have a bottom filler layer 110 to cover the gap between the electrical chip 910 and the fourth redistribution layer 640, thereby protecting the electrical chip 910 and the fourth redistribution layer 640.

[0109] In summary, the 3D optoelectronic interconnect packaging structure and its fabrication method of the present invention can construct a glass waveguide structure by combining a glass composite with a dielectric layer. By forming a through-groove that exposes the glass waveguide layer and bonding a side-emitting chip in the through-groove, the photosensitive area of ​​the side-emitting chip and the glass waveguide layer can form a light transmission path. Furthermore, optoelectronic interconnection can be achieved through the interconnection of metal pillars, a redistribution layer, and an adapter board.

[0110] The 3D optoelectronic interconnect packaging structure and its fabrication method of the present invention can realize optoelectronic interconnect integration, reduce packaging size, reduce power consumption, improve reliability, are suitable for high-density integrated packaging, and can achieve good optoelectronic transmission.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a 3D optoelectronic interconnect packaging structure, characterized in that, Includes the following steps: A glass composite is provided, the glass composite comprising a stacked glass substrate and a glass waveguide layer, wherein the refractive index of the glass waveguide layer is greater than the refractive index of the glass substrate; The glass waveguide layer is patterned to expose a portion of the glass substrate; A dielectric layer is formed on the exposed glass substrate, the dielectric layer covering the glass waveguide layer, and the refractive index of the dielectric layer is less than the refractive index of the glass waveguide layer; A metal pillar is formed that penetrates the dielectric layer and the glass substrate; A first redistribution layer is formed on the dielectric layer and a second redistribution layer is formed on the glass substrate, and both the first redistribution layer and the second redistribution layer are electrically connected to the metal pillar; A through-groove is formed that penetrates the first redistribution layer, the dielectric layer, the glass substrate, and the second redistribution layer, and the sidewalls of the through-groove expose the glass waveguide layer; A composite adapter board is provided, the composite adapter board including an adapter board and a third rewiring layer and a fourth rewiring layer located on both sides of the adapter board, and the adapter board, the third rewiring layer and the fourth rewiring layer are electrically connected. The composite adapter board is bonded to the second redistribution layer and located above the through slot; the third redistribution layer is electrically connected to the second redistribution layer. An electrical chip and a side-emitting chip are provided, and the electrical chip is bonded to the fourth redistribution layer and electrically connected to the fourth redistribution layer. The side-emitting chip is bonded to the through-groove and electrically connected to the third redistribution layer. The photosensitive area of ​​the side-emitting chip is correspondingly disposed with the glass waveguide layer. Metal bumps are formed on the first redistribution layer, and the metal bumps are electrically connected to the first redistribution layer.

2. The method for fabricating the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The glass composite is prepared by a fusion drawing and lamination method.

3. The method for fabricating the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer.

4. The method for fabricating the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The drilling method for forming the metal column includes laser drilling or mechanical drilling; the method for forming the through groove includes laser drilling or mechanical drilling.

5. The method for fabricating the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The adapter board includes a TSV adapter board or a TGV adapter board.

6. The method for fabricating the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: It also includes the step of forming an underfill layer between the electrical chip and the fourth redistribution layer.

7. The method for fabricating the 3D optoelectronic interconnect packaging structure according to claim 1, characterized in that: The glass composite is wafer-level in size, and a cutting process is included after the metal bumps are formed.

8. A 3D optoelectronic interconnect packaging structure, characterized in that, The 3D optoelectronic interconnect packaging structure includes: A glass composite comprising stacked glass substrates and patterned glass waveguide layers, wherein the glass waveguide layers expose a portion of the glass substrates and the refractive index of the glass waveguide layers is greater than the refractive index of the glass substrates. A dielectric layer is located on the exposed glass substrate and covers the glass waveguide layer, and the refractive index of the dielectric layer is less than that of the glass waveguide layer. A metal pillar that penetrates the dielectric layer and the glass substrate; A first redistribution layer is located on the dielectric layer and is electrically connected to the metal pillar. A second redistribution layer is located on the glass substrate and is electrically connected to the metal pillar. A through-slot, the through-slot passing through the first redistribution layer, the dielectric layer, the glass substrate and the second redistribution layer, and the sidewall of the through-slot exposing the glass waveguide layer; A composite adapter board, which is bonded to the second redistribution layer and located above the through slot, includes an adapter board and a third redistribution layer and a fourth redistribution layer located on both sides of the adapter board. The adapter board, the third redistribution layer and the fourth redistribution layer are electrically connected, and the third redistribution layer is electrically connected to the second redistribution layer. An electrical chip, which is bonded to the fourth redistribution layer and electrically connected to the fourth redistribution layer; A side-emitting chip is bonded to the through groove, the side-emitting chip is electrically connected to the third redistribution layer, and the photosensitive area of ​​the side-emitting chip is correspondingly disposed with the glass waveguide layer. A metal bump is located on the first redistribution layer and is electrically connected to the first redistribution layer.

9. The 3D optoelectronic interconnect packaging structure according to claim 8, characterized in that: The dielectric layer includes a polyimide dielectric layer or a silicon oxide dielectric layer; the adapter board includes a TSV adapter board or a TGV adapter board.

10. The 3D optoelectronic interconnect packaging structure according to claim 8, characterized in that: The electrical chip also has an underfill layer between it and the fourth redistribution layer.

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