Power conversion device

Abstract

The present invention addresses the problem of achieving miniaturization while reducing ripple current. In a power conversion device (10), a first half bridge circuit (21) is connected between a positive electrode input terminal (11) and a negative electrode input terminal (12). A second half bridge circuit (22) is connected between a first phase output terminal and the negative electrode input terminal (12). A third half bridge circuit (23) is connected between a second phase output terminal and the negative electrode input terminal (12). A third phase output terminal among the first, the second, and the third phase output terminals is short-circuited to the positive electrode input terminal (11).

Description

Power conversion device

[0001] The present disclosure relates to a power conversion device, and more particularly to a power conversion device including a plurality of switching elements.

[0002] Patent Document 1 discloses a three-phase inverter circuit including three chopper circuits. In the three-phase inverter circuit disclosed in Patent Document 1, the three chopper circuits include a chopper circuit that outputs a U-phase voltage, a chopper circuit that outputs a V-phase voltage, and a chopper circuit that outputs a W-phase voltage. Each of the three chopper circuits has a power supply side half-bridge circuit, a load side half-bridge circuit, and a reactor. The power supply side half-bridge circuit of each of the three chopper circuits consists of two switching elements connected in series with each other. Also, the load side half-bridge circuit of each of the three chopper circuits consists of two switching elements connected in series with each other.

[0003] Further, the three-phase inverter circuit includes three smoothing capacitors (first capacitors) connected between the input terminals of each of the three chopper circuits and three smoothing capacitors (second capacitors) connected between the output terminals of each of the three chopper circuits.

[0004] Also, in the three-phase inverter circuit, each switching element is switched by a control circuit.

[0005] Further, the three-phase inverter circuit generates each-phase AC voltage and each-phase AC current having a substantially sinusoidal waveform with a DC voltage superimposed thereon.

[0006] The three-phase inverter circuit disclosed in Patent Document 1 includes 12 switching elements, which results in an increase in size and an increase in losses.

[0007] Japanese Patent Application Laid-Open No. 2005-295671

[0008] An object of the present disclosure is to provide a power conversion device capable of reducing a ripple current and achieving miniaturization.

[0009] A power converter according to one embodiment of the present disclosure comprises a positive input terminal and a negative input terminal, a first phase output terminal, a second phase output terminal and a third phase output terminal, a first capacitor, a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, a first inductor, a second inductor, a second capacitor, a third capacitor, and a control device. The first capacitor is connected between the positive input terminal and the negative input terminal. The first half-bridge circuit is connected between the positive input terminal and the negative input terminal. The first half-bridge circuit has a first switching element and a second switching element connected in series with each other. The second half-bridge circuit is connected between the first phase output terminal and the negative input terminal. The second half-bridge circuit has a third switching element and a fourth switching element connected in series with each other. The third half-bridge circuit is connected between the second phase output terminal and the negative input terminal. The third half-bridge circuit has a fifth switching element and a sixth switching element connected in series with each other. The first inductor is connected between the first node between the first switching element and the second switching element of the first half-bridge circuit and the second node between the third switching element and the fourth switching element of the second half-bridge circuit. The second inductor is connected between the first node and the third node between the fifth switching element and the sixth switching element of the third half-bridge circuit. The second capacitor is connected in parallel to the second half-bridge circuit. The third capacitor is connected in parallel to the third half-bridge circuit. The control device outputs a first PWM signal, a second PWM signal, a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal to control the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, and the sixth switching element, respectively. In the first half-bridge circuit, the first switching element is connected to the positive input terminal, and the second switching element is connected between the first switching element and the negative input terminal.The third phase output terminal is short-circuited to the positive input terminal.

[0010] Figure 1 is a circuit diagram of a power converter according to Embodiment 1. Figure 2 is a circuit diagram showing a specific example of the configuration of a control device for the same power converter. Figure 3 is an explanatory diagram of the operation of the control device in the same power converter. Figure 4 is a waveform diagram of the command voltage generated by the control device of the same power converter. Figure 5 is a waveform diagram of the reference voltage generated by the control device of the same power converter. Figure 6 is an explanatory diagram of the duty cycle command value generated by the control device of the same power converter. Figure 7 is an operating waveform diagram of the same power converter. Figure 8 is a circuit diagram of a power converter according to Embodiment 2.

[0011] (Embodiment 1) Below, the power conversion device 10 according to Embodiment 1 will be described with reference to Figures 1 to 7.

[0012] (1) Configuration of the power converter As shown in diagram 1, the power converter 10 includes a positive input terminal 11 and a negative input terminal 12, a U-phase output terminal 13u, a V-phase output terminal 13v and a W-phase output terminal 13w, a first capacitor C1, a first half-bridge circuit 21, a second half-bridge circuit 22, a third half-bridge circuit 23, a first inductor L1, a second inductor L2, a second capacitor C2 and a third capacitor C3, and a control device 30. In this embodiment, the U-phase, V-phase and W-phase are the first phase, second phase and third phase, respectively, the U-phase output terminal 13u constitutes the first phase output terminal, the V-phase output terminal 13v constitutes the second phase output terminal, and the W-phase output terminal 13w constitutes the third phase output terminal.

[0013] The first capacitor C1 is connected between the positive input terminal 11 and the negative input terminal 12. The first half-bridge circuit 21 is connected between the positive input terminal 11 and the negative input terminal 12. The first half-bridge circuit 21 has a first switching element 1 and a second switching element 2 connected in series with each other. The second half-bridge circuit 22 is connected between the U-phase output terminal 13u and the negative input terminal 12. The second half-bridge circuit 22 has a third switching element 3u and a fourth switching element 4u connected in series with each other. The third half-bridge circuit 23 is connected between the V-phase output terminal 13v and the negative input terminal 12. The third half-bridge circuit 23 has a fifth switching element 3v and a sixth switching element 4v connected in series with each other. The first inductor L1 is connected between the first node N1 between the first switching element 1 and the second switching element 2 of the first half-bridge circuit 21 and the second node N2 between the third switching element 3u and the fourth switching element 4u of the second half-bridge circuit 22. The second inductor L2 is connected between the first node N1 and the third node N3 between the fifth switching element 3v and the sixth switching element 4v of the third half-bridge circuit 23. The second capacitor C2 is connected in parallel to the second half-bridge circuit 22. The third capacitor C3 is connected in parallel to the third half-bridge circuit 23. The control device 30 outputs a first PWM (Pulse Width Modulation) signal S1, a second PWM signal S2, a third PWM signal S3u, a fourth PWM signal S4u, a fifth PWM signal S3v, and a sixth PWM signal S4v to control the first switching element 1, the second switching element 2, the third switching element 3u, the fourth switching element 4u, the fifth switching element 3v, and the sixth switching element 4v, respectively (see Figure 2). In the first half-bridge circuit 21, the first switching element 1 is connected to the positive input terminal 11, and the second switching element 2 is connected between the first switching element 1 and the negative input terminal 12.

[0014] In this embodiment, the W-phase output terminal 13w is short-circuited with the positive input terminal 11.

[0015] In this embodiment, each of the first switching element 1, second switching element 2, third switching element 3u, fourth switching element 4u, fifth switching element 3v, and sixth switching element 4v is, for example, a normally-off type n-channel MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor). Therefore, the control terminal, first main terminal, and second main terminal of each of the first switching element 1, second switching element 2, third switching element 3u, fourth switching element 4u, fifth switching element 3v, and sixth switching element 4v are the gate terminal, drain terminal, and source terminal, respectively.

[0016] The positive input terminal 11, the negative input terminal 12, the U-phase output terminal 13u, the V-phase output terminal 13v, and the W-phase output terminal 13w do not necessarily have to be physical components (terminals), and may, for example, be part of a conductive portion included in the circuit board of the power converter 10.

[0017] In the power converter 10, a DC power supply E1 is connected between the positive input terminal 11 and the negative input terminal 12, and an AC load 7 is connected to the U-phase output terminal 13u, the V-phase output terminal 13v, and the W-phase output terminal 13w. The AC load 7 is, for example, a three-phase servo motor. The U-phase output terminal 13u is connected to the U-phase terminal (not shown) of the AC load 7. The V-phase output terminal 13v is connected to the V-phase terminal (not shown) of the AC load 7. The W-phase output terminal 13w is connected to the W-phase terminal (not shown) of the AC load 7.

[0018] (2) Details of the power converter The power converter 10 according to Embodiment 1 is a three-phase inverter that converts DC to three-phase AC.

[0019] As shown in Figure 1, for example, the power converter 10 has the high-potential output terminal (positive terminal) of the DC power supply E1 connected to the positive input terminal 11, and the low-potential output terminal (negative terminal) of the DC power supply E1 connected to the negative input terminal 12. The output voltage of the DC power supply E1 is, for example, 48V. The output voltage of the DC power supply E1 is not limited to 48V; for example, it may be 12V, 24V, or 141V obtained by inputting an AC voltage of 100V to a diode bridge. Note that the DC power supply E1 and the AC load 7 are not components of the power converter 10, but may be components of the power converter 10. Also, the DC power supply E1 is not shown in Figure 2.

[0020] As shown in Figure 1, in the first half-bridge circuit 21, the first main terminal of the first switching element 1 is connected to the positive input terminal 11, the second main terminal of the first switching element 1 is connected to the first main terminal of the second switching element 2, and the second main terminal of the second switching element 2 is connected to the negative input terminal 12. Therefore, in the first half-bridge circuit 21, the first switching element 1 is a high-side switching element (P-side switching element), and the second switching element 2 is a low-side switching element (N-side switching element).

[0021] The first half-bridge circuit 21 includes a first diode D1 and a second diode D2. The first diode D1 is connected in antiparallel to the first switching element 1. In the first diode D1, the anode of the first diode D1 is connected to the second main terminal (source terminal) of the first switching element 1, and the cathode of the first diode D1 is connected to the first main terminal (drain terminal) of the first switching element 1. The second diode D2 is connected in antiparallel to the second switching element 2. In the second diode D2, the anode of the second diode D2 is connected to the second main terminal of the second switching element 2, and the cathode of the second diode D2 is connected to the first main terminal of the second switching element 2. The first diode D1 is a parasitic diode of the n-channel MOSFET constituting the first switching element 1, but it is not limited to a parasitic diode and may be an external diode. The second diode D2 is a parasitic diode of the n-channel MOSFET constituting the second switching element 2, but it is not limited to a parasitic diode and may be an external diode.

[0022] In the second half-bridge circuit 22, the first main terminal of the third switching element 3u is connected to the U-phase output terminal 13u, the second main terminal of the third switching element 3u is connected to the first main terminal of the fourth switching element 4u, and the second main terminal of the fourth switching element 4u is connected to the negative input terminal 12. Therefore, in the second half-bridge circuit 22, the third switching element 3u is a high-side switching element, and the fourth switching element 4u is a low-side switching element.

[0023] The second half-bridge circuit 22 includes a third diode D3u and a fourth diode D4u. The third diode D3u is connected in antiparallel to the third switching element 3u. In the third diode D3u, the anode of the third diode D3u is connected to the second main terminal (source terminal) of the third switching element 3u, and the cathode of the third diode D3u is connected to the first main terminal (drain terminal) of the third switching element 3u. The fourth diode D4u is connected in antiparallel to the fourth switching element 4u. In the fourth diode D4u, the anode of the fourth diode D4u is connected to the second main terminal of the fourth switching element 4u, and the cathode of the fourth diode D4u is connected to the first main terminal of the fourth switching element 4u. The third diode D3u is a parasitic diode of the n-channel MOSFET constituting the third switching element 3u, but it is not limited to a parasitic diode and may be an external diode. The fourth diode D4u is a parasitic diode of the n-channel MOSFET that constitutes the fourth switching element 4u, but it is not limited to a parasitic diode and may be an external diode.

[0024] In the third half-bridge circuit 23, the first main terminal of the fifth switching element 3v is connected to the V-phase output terminal 13v, the second main terminal of the fifth switching element 3v is connected to the first main terminal of the sixth switching element 4v, and the second main terminal of the sixth switching element 4v is connected to the negative input terminal 12. Therefore, in the third half-bridge circuit 23, the fifth switching element 3v is a high-side switching element, and the sixth switching element 4v is a low-side switching element.

[0025] The third half-bridge circuit 23 includes a fifth diode D3v and a sixth diode D4v. The fifth diode D3v is connected in antiparallel to the fifth switching element 3v. In the fifth diode D3v, the anode of the fifth diode D3v is connected to the second main terminal (source terminal) of the fifth switching element 3v, and the cathode of the fifth diode D3v is connected to the first main terminal (drain terminal) of the fifth switching element 3v. The sixth diode D4v is connected in antiparallel to the sixth switching element 4v. In the sixth diode D4v, the anode of the sixth diode D4v is connected to the second main terminal of the sixth switching element 4v, and the cathode of the sixth diode D4v is connected to the first main terminal of the sixth switching element 4v. The fifth diode D3v is a parasitic diode of the n-channel MOSFET that constitutes the fifth switching element 3v, but it is not limited to a parasitic diode and may be an external diode. The sixth diode D4v is a parasitic diode of the n-channel MOSFET that constitutes the sixth switching element 4v, but it is not limited to a parasitic diode; an external diode may also be used.

[0026] In this embodiment, the inductance of the second inductor L2 is the same as the inductance of the first inductor L1. "The inductance of the second inductor L2 is the same as the inductance of the first inductor L1" does not mean that the inductance of the second inductor L2 perfectly matches the inductance of the first inductor L1, but rather that it is within the range of 80% to 120% of the inductance of the first inductor L1.

[0027] In this embodiment, the capacitance of the third capacitor C3 is the same as the capacitance of the second capacitor C2. "The capacitance of the third capacitor C3 is the same as the capacitance of the second capacitor C2" does not mean that the capacitance of the third capacitor C3 is exactly the same as the capacitance of the second capacitor, but rather that it is within the range of 80% to 120% of the capacitance of the second capacitor C2.

[0028] The power converter 10 comprises six gate drivers (not shown) corresponding one-to-one to six switching elements (first switching element 1, second switching element 2, third switching element 3u, fourth switching element 4u, fifth switching element 3v, and sixth switching element 4v), and six gate drive circuits (not shown) corresponding one-to-one to the six switching elements. Each of the six gate drivers is, for example, a driver IC (Integrated Circuit). Each of the six gate drive circuits is, for example, a circuit including a gate resistor connected between the output terminal of the gate driver and the control terminal of the switching element. Each of the six gate drivers is connected to the control terminal (gate terminal) of the corresponding switching element among the six switching elements via the corresponding gate drive circuit among the six gate drive circuits.

[0029] The control device 30 controls each of the six switching elements (first switching element 1, second switching element 2, third switching element 3u, fourth switching element 4u, fifth switching element 3v, and sixth switching element 4v) via a gate driver and gate drive circuit corresponding to the switching element.

[0030] The power converter 10 of this embodiment includes a DC-DC converter 20u (hereinafter also referred to as the first DC-DC converter 20u) and a DC-DC converter 20v (hereinafter also referred to as the second DC-DC converter 20v). The first DC-DC converter 20u includes a first half-bridge circuit 21, a second half-bridge circuit 22, and a first inductor L1. The second DC-DC converter 20v includes a first half-bridge circuit 21, a third half-bridge circuit 23, and a second inductor L2.

[0031] The first DC-DC converter 20u and the second DC-DC converter 20v are both boost-buck converters capable of boosting and lowering voltage in both directions. In the power conversion device 10 of this embodiment, the first DC-DC converter 20u and the second DC-DC converter 20v share a common first half-bridge circuit 21. In other words, since the power conversion device 10 shares one first half-bridge circuit 21 between the first DC-DC converter 20u and the second DC-DC converter 20v, the number of switching elements can be reduced from 12 to 6.

[0032] Each of the two DC-DC converters 20u and 20v is capable of a first conversion operation, which converts the first input voltage from the DC power supply E1 to the first half-bridge circuit 21 to a first output voltage, and a second conversion operation, which converts the second input voltage from the AC load 7 (the input voltage to the second half-bridge circuit 22 in the case of DC-DC converter 20u, and the input voltage to the third half-bridge circuit 23 in the case of DC-DC converter 20v) to a second output voltage. Both the first and second conversion operations are capable of either boosting (hereinafter also referred to as boost mode operation) or bucking (hereinafter also referred to as buck mode operation). In the power conversion device 10, for example, when the brakes are applied to the three-phase servo motor, which is the AC load 7, the second conversion operation is performed in order to regenerate the energy of the three-phase servo motor.

[0033] In the power conversion device 10 of this embodiment, the control device 30 controls six switching elements, so the two DC-DC converters 20u and 20v are controlled by the control device 30.

[0034] The control device 30 includes a computer system. The computer system mainly consists of a processor and memory as hardware. The functions of the control device 30 in this disclosure are realized by the processor executing a program recorded in the memory of the computer system. The processor of the computer system is composed of one or more electronic circuits including semiconductor integrated circuits (ICs) or large-scale integrated circuits (LSIs). The integrated circuits such as ICs and LSIs referred to here are named differently depending on the degree of integration, and include integrated circuits called system LSIs, VLSIs (Very Large Scale Integrations), or ULSIs (Ultra Large Scale Integrations). Furthermore, FPGAs (Field-Programmable Gate Arrays) that are programmed after the manufacture of the LSI, or logic devices that allow for the reconfiguration of junction relationships or circuit compartments within the LSI, can also be used as processors. Multiple electronic circuits may be integrated on a single chip or distributed across multiple chips. Multiple chips may be integrated on a single device or distributed across multiple devices. The computer system referred to herein includes a microcontroller having one or more processors and one or more memories. Therefore, the microcontroller also consists of one or more electronic circuits, including semiconductor integrated circuits or large-scale integrated circuits.

[0035] As shown in Figure 2, the control device 30 outputs a plurality of PWM signals (first PWM signal S1, second PWM signal S2, third PWM signal S3u, fourth PWM signal S4u, fifth PWM signal S3v, and sixth PWM signal S4v). Each of the first PWM signal S1, second PWM signal S2, third PWM signal S3u, fourth PWM signal S4u, fifth PWM signal S3v, and sixth PWM signal S4v is a PWM signal whose potential level changes between, for example, a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) which is higher than the first potential level. Each of the plurality of switching elements is turned on when the corresponding PWM signal among the plurality of PWM signals is at a high level, and turned off when it is at a low level.

[0036] The signal generation unit 39 of the control device 30 (see Figure 2) generates the first PWM signal S1, the second PWM signal S2, the third PWM signal S3u, the fourth PWM signal S4u, the fifth PWM signal S3v, and the sixth PWM signal S4v using the triangular wave carrier signal CA1 (see Figure 3). More specifically, as shown in Figure 3, for example, the control device 30 generates the first PWM signal S1 and the second PWM signal S2 to be supplied to the first switching element 1 and the second switching element 2, respectively, based on the carrier signal CA1 and the duty cycle command value d1. Also, as shown in Figure 3, for example, the control device 30 generates the third PWM signal S3u and the fourth PWM signal S4u to be supplied to the third switching element 3u and the fourth switching element 4u, respectively, based on the carrier signal CA1 and the U-phase duty cycle command value d3u. Furthermore, the control device 30 generates a fifth PWM signal S3v and a sixth PWM signal S4v to be supplied to the fifth switching element 3v and the sixth switching element 4v, respectively, based on the carrier signal CA1 (see Figure 3) and the V-phase duty cycle command value d3v (see Figure 2). Note that the waveform of the carrier signal CA1 is not limited to a triangular wave; for example, it may be a sawtooth wave.

[0037] The duty cycles of the first PWM signal S1 and the second PWM signal S2, generated by the signal generation unit 39, change based on the duty cycle command value d1. The signal generation unit 39 generates the first PWM signal S1 by comparing the duty cycle command value d1 with the carrier signal CA1. More specifically, the signal generation unit 39 compares the duty cycle command value d1 with the carrier signal CA1 and generates the first PWM signal S1 which is high level ("1") during periods when the duty cycle command value d1 is greater than or equal to the carrier signal CA1, and low level ("0") during periods when the duty cycle command value d1 is less than or equal to the carrier signal CA1. The signal generation unit 39 also generates the second PWM signal S2 by inverting the first PWM signal S1. The signal generation unit 39 sets a dead time period between the high-level period of the first PWM signal S1 and the high-level period of the second PWM signal S2 so that the ON period of the first switching element 1 and the ON period of the second switching element 2 do not overlap.

[0038] The duty cycles of the third PWM signal S3u and the fourth PWM signal S4u, generated by the signal generation unit 39, change based on the duty cycle command value d3u. The signal generation unit 39 generates the third PWM signal S3u by comparing the duty cycle command value d3u with the carrier signal CA1. The signal generation unit 39 also generates the fourth PWM signal S4u by inverting the third PWM signal S3u. The signal generation unit 39 sets a dead time period between the high-level period of the third PWM signal S3u and the high-level period of the fourth PWM signal S4u so that the on-period of the third switching element 3u and the on-period of the fourth switching element 4u do not overlap. Figure 3 also shows the waveform of the current IL1 (hereinafter also referred to as inductor current IL1) flowing through the first inductor L1 when the duty cycle command value d1 and the duty cycle command value d3u are set as shown in Figure 3.

[0039] The duty cycles of the fifth PWM signal S3v and the sixth PWM signal S4v, generated by the signal generation unit 39, change based on the duty cycle command value d3v. The signal generation unit 39 generates the fifth PWM signal S3v by comparing the duty cycle command value d3v with the carrier signal CA1 (see Figure 3). The signal generation unit 39 also generates the sixth PWM signal S4v by inverting the fifth PWM signal S3v. The signal generation unit 39 sets a dead time period between the high-level period of the fifth PWM signal S3v and the high-level period of the sixth PWM signal S4v so that the on-period of the fifth switching element 3v and the on-period of the sixth switching element 4v do not overlap. The current IL2 (see Figure 1) flowing through the second inductor L2 changes in the same way as the waveform of the current IL1. Hereafter, the current IL2 will also be referred to as the inductor current IL2.

[0040] The control device 30 determines the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 based on the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0, respectively. However, in this embodiment, since the W-phase output terminal 13w is connected to the positive input terminal 11, the control device 30 may predetermine the W-phase reference voltage value Vc1 according to the DC voltage Vdc. When the control device 30 takes Vdc as the DC voltage applied between the positive input terminal 11 and the negative input terminal 12, and the duty cycle command value d1 of the first PWM signal S1, it sets the duty cycle command value d1 such that Vdc × d1 is less than or equal to the minimum value among the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 at each time step.

[0041] In this embodiment, the control device 30 performs feedback control based on at least two of the phase currents including the U-phase current isa output from the U-phase output terminal 13u, the V-phase current isb output from the V-phase output terminal 13v, and the W-phase current isc output from the W-phase output terminal 13w. More specifically, the control device 30 obtains the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0 based on at least two of the phase currents including the phase current isa output from the U-phase output terminal 13u, the phase current isb output from the V-phase output terminal 13v, and the phase current isc output from the W-phase output terminal 13w.

[0042] As shown in FIG. 2, the control device 30 obtains the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 by adding the same bias voltage value (in this embodiment, -Vc0 + Vdc) to each of the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0. In other words, the control device 30 adds, to each of the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0, a value obtained by multiplying the W-phase command voltage value Vc0 corresponding to the W-phase output terminal 13w short-circuited to the positive input terminal 11 by -1, and adds Vdc, thereby obtaining the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1. Therefore, the W-phase reference voltage value Vc1 is equal to Vdc (for example, 48V).

[0043] Hereinafter, the control device 30 will be described in more detail.

[0044] As shown in FIG. 2, the control device 30 includes a first conversion unit 31, a first subtraction unit 32, a second subtraction unit 33, a first PI (Proportional Integral) control unit 34, a second PI control unit 35, a second conversion unit 36, an addition unit 37, a command value generation unit 38, and a signal generation unit 39.

[0045] The first conversion unit 31 acquires a detection value ia from a current sensor 8a that detects the phase current isa (hereinafter also referred to as the U-phase current sensor 8a). Further, the first conversion unit 31 acquires a detection value ib from a current sensor 8b that detects the phase current isb (hereinafter also referred to as the V-phase current sensor 8b). Further, the first conversion unit 31 acquires a detection value ic from a current sensor 8c that detects the phase current isc (hereinafter also referred to as the W-phase current sensor 8c). Note that the U-phase current sensor 8a, the V-phase current sensor 8b, and the W-phase current sensor 8c are not components of the power conversion device 10, but may be components of the power conversion device 10. Each of the three current sensors 8a, 8b, and 8c is a current detection resistor, but is not limited to a current detection resistor and may be a current transformer.

[0046] The first conversion unit 31 includes, for example, a three-phase to two-phase conversion unit and a dq conversion unit, and converts the detection values ia, ib, and ic of the three-phase phase currents isa, isb, and isc in the abc reference coordinate system with the U-phase as the a-phase, the V-phase as the b-phase, and the W-phase as the c-phase into the d-axis current value id and the q-axis current value iq in the dq rotating coordinate system.

[0047] The first subtraction unit 32 obtains a difference value (hereinafter also referred to as the d-axis current difference value) between the reference value id1 of the d-axis current and the d-axis current value id by performing an operation of subtracting the d-axis current value id from the reference value id1 of the d-axis current.

[0048] The second subtraction unit 33 obtains a difference value (hereinafter also referred to as the q-axis current difference value) between the reference value iq1 of the q-axis current and the q-axis current value iq by performing an operation of subtracting the q-axis current value iq from the reference value iq1 of the q-axis current.

[0049] The reference values ​​id1 for the d-axis current and iq1 for the q-axis current described above are determined in the control device 30 by external commands from a higher-level controller (not shown) to the control device 30. In other words, the control device 30 has the function of generating the reference values ​​id1 for the d-axis current and iq1 for the q-axis current based on external commands from the higher-level controller. Alternatively, the reference values ​​id1 for the d-axis current and iq1 for the q-axis current are stored in the control device 30 in advance by a program. Alternatively, the reference values ​​id1 for the d-axis current and iq1 for the q-axis current may be calculated in the control device 30 based on the angle (position) information of the AC load 7, etc.

[0050] The first PI control unit 34 generates a reference value Vd0 for the d-axis voltage to perform feedback control that brings the d-axis current difference value output from the first subtraction unit 32 closer to zero.

[0051] The second PI control unit 35 generates a reference value Vq0 for the q-axis voltage to perform feedback control that brings the q-axis current difference value output from the second subtraction unit 33 closer to zero.

[0052] The second conversion unit 36 ​​includes, for example, an inverse dq conversion unit and a two-phase three-phase conversion unit, and converts the reference value Vd0 of the d-axis voltage and the reference value Vq0 of the q-axis voltage into the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0.

[0053] The addition unit 37 obtains the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 by adding -Vc0 + Vdc to each of the U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0. That is, the addition unit 37 performs the calculations shown in equations (1), (2), and (3) below. Va1 = Va0 - Vc0 + Vdc Equation (1) Vb1 = Vb0 - Vc0 + Vdc Equation (2) Vc1 = Vc0 - Vc0 + Vdc = Vdc Equation (3) Note that the U-phase reference voltage value Va1, the V-phase reference voltage value Vb1, and the W-phase reference voltage value Vc1 correspond to the target values ​​of the U-phase phase voltage Va (output voltage of the DC-DC converter 20u in this embodiment), the V-phase phase voltage Vb (output voltage of the DC-DC converter 20v in this embodiment), and the W-phase phase voltage Vc, respectively.

[0054] The command value generation unit 38 sets the duty cycle command value d1 such that Vdc × d1 is less than or equal to the minimum value among the U-phase reference voltage value Va1, V-phase reference voltage value Vb1, and W-phase reference voltage value Vc1 at any given time, when Vdc is the DC voltage applied between the positive input terminal 11 and the negative input terminal 12, and d1 is the duty cycle command value of the first PWM signal S1 at any given time. In this embodiment, in a steady state, the output voltage of the DC-DC converter 20u approaches Vdc × d1 ÷ d3u. Similarly, the output voltage of the DC-DC converter 20v approaches Vdc × d1 ÷ d3v. If the duty cycle command value d1 is made too small, the duty cycle command values ​​d3u and d3v must also be made small by the same amount, but if the duty cycle command values ​​d3u and d3v are made small, the inductor currents IL1 and IL2 will increase, resulting in increased circuit losses. From the standpoint of improving power conversion efficiency, it is preferable that Vdc × d1 be a larger value.

[0055] The command value generation unit 38 calculates the duty cycle command value d3u using the DC voltage Vdc, the duty cycle command value d1, and the U-phase reference voltage value Va1 according to the following equation (4). Also, the command value generation unit 38 calculates the duty cycle command value d3v using the DC voltage Vdc, the duty cycle command value d1, and the V-phase reference voltage value Vb1 according to the following equation (5). d3u = Vdc × d1 ÷ Va1 Equation (4) d3v = Vdc × d1 ÷ Vb1 Equation (5) The control device 30 may use a value of Vdc that has been stored in advance, or it may use a value detected by a voltage detection circuit or voltage sensor that detects Vdc.

[0056] In this embodiment, as shown in Figure 3, the control device 30 sets the maximum value of the carrier signal CA1 to 1 and the minimum value to 0. Furthermore, the control device 30 sets the maximum value of the duty cycle command values ​​d1, d3u, and d3v to 1 and the minimum value to 0.

[0057] The following describes the operating waveforms of the power converter 10 based on Figures 4 to 7.

[0058] As shown in Figure 4, the waveforms showing the time variation of the U-phase command voltage value Va0, the waveform showing the time variation of the V-phase command voltage value Vb0, and the waveform showing the time variation of the W-phase command voltage value Vc0 are, for example, sinusoidal waves with a phase difference of 120° from each other. The U-phase command voltage value Va0, the V-phase command voltage value Vb0, and the W-phase command voltage value Vc0 are output from the second conversion unit 36 ​​(see Figure 2). The length of one period of the waveforms showing the time variation of the U-phase command voltage value Va0, the waveform showing the time variation of the V-phase command voltage value Vb0, and the waveform showing the time variation of the W-phase command voltage value Vc0 is the same. Also, the length of one period of the waveforms showing the time variation of the U-phase command voltage value Va0, the waveform showing the time variation of the V-phase command voltage value Vb0, and the waveform showing the time variation of the W-phase command voltage value Vc0 is longer than the length of one period of the carrier signal CA1 (see Figure 3).

[0059] As shown in Figure 5, the waveforms showing the time variation of the U-phase reference voltage value Va1 and the waveform showing the time variation of the V-phase reference voltage value Vb1 are sinusoidal, with a phase difference of 60° from each other and biased to the positive side by Vdc (48V in the example of Figure 5). Also, the W-phase reference voltage value Vc1 is equal to Vdc and constant. In this embodiment, the command value generation unit 38 sets the duty cycle command value d1 so that Vdc × d1 is a constant value, as shown in Figure 5. More specifically, in this embodiment, the command value generation unit 38 sets the duty cycle command value d1 so that Vdc × d1 is less than or equal to the minimum value of the U-phase reference voltage value Va1, less than or equal to the minimum value of the V-phase reference voltage value Vb1, and less than or equal to the minimum value of the W-phase reference voltage value Vc1. In this embodiment, the minimum value of the U-phase reference voltage value Va1 and the minimum value of the V-phase reference voltage value Vb1 are the same, and the minimum values ​​of the U-phase reference voltage value Va1 and the V-phase reference voltage value Vb1 are smaller than the minimum value of the W-phase reference voltage value Vc1. The command value generation unit 38 sets the duty cycle command value d1 such that Vdc × d1 is smaller than the minimum value of the U-phase reference voltage value Va1, for example, as shown in Figure 5. In the example in Figure 5, Vdc × d1 = 31V.

[0060] The duty cycle command value d1 generated by the command value generation unit 38 is constant, as shown in Figure 6, while the duty cycle command values ​​d3u and d3v each change over time. The waveforms showing the time change of the duty cycle command value d3u and the waveform showing the time change of the duty cycle command value d3v have different phases.

[0061] As shown in the top row of Figure 7, when the duty cycle command value d1 is constant and the duty cycle command value d3u changes over time, the phase voltages Va of the U-phase, Vb of the V-phase, and Vc of the W-phase become sinusoidal voltages as shown in the second row from the top of Figure 7. However, the phase voltages Va, Vb, and Vc are DC voltages. Furthermore, the line voltages Va-Vb between the U-phase and V-phase, Vb-Vc between the V-phase and W-phase, and Vc-Va between the W-phase and U-phase become sinusoidal AC voltages with a phase difference of 120°, as shown in the third row from the top of Figure 7. Also, the phase currents isa of the U-phase, isb of the V-phase, and isc of the W-phase become sinusoidal AC currents with a phase difference of 120°, as shown in the fourth row from the top of Figure 7. In the power converter 10 of this embodiment, since the phase voltages Va and Vb are each sinusoidal voltages, it is possible to output phase currents isa, isb, and isc with reduced ripple current compared to a three-phase inverter circuit where the phase voltages of each phase are pulsed voltages.

[0062] Figure 7 shows the operating waveform when the carrier signal CA1 frequency is 100 kHz, the inductances of the first inductor L1 and the second inductor L2 are 15 μH each, Vdc is 48 V, the capacitances of the second capacitor C2 and the third capacitor C3 are 10 μF each, the inductance and resistance of the AC load 7 are 340 μH and 1 Ω, respectively, and the frequencies of the U-phase phase current isa, V-phase phase current isb, and W-phase phase current isc are all 250 Hz.

[0063] (3) Advantages The power conversion device 10 according to Embodiment 1 includes a positive input terminal 11 and a negative input terminal 12, a first phase output terminal (U phase output terminal 13u), a second phase output terminal (V phase output terminal 13v), and a third phase output terminal (W phase output terminal 13w), a first capacitor C1, a first half-bridge circuit 21, a second half-bridge circuit 22, a third half-bridge circuit 23, a first inductor L1, a second inductor L2, a second capacitor C2, a third capacitor C3, and a control device 30. The first capacitor C1 is connected between the positive input terminal 11 and the negative input terminal 12. The first half-bridge circuit 21 is connected between the positive input terminal 11 and the negative input terminal 12. The first half-bridge circuit 21 has a first switching element 1 and a second switching element 2 connected in series with each other. The second half-bridge circuit 22 is connected between the first phase output terminal (U phase output terminal 13u) and the negative input terminal 12. The second half-bridge circuit 22 has a third switching element 3u and a fourth switching element 4u connected in series with each other. The third half-bridge circuit 23 is connected between the second phase output terminal (V phase output terminal 13v) and the negative input terminal 12. The third half-bridge circuit 23 has a fifth switching element 3v and a sixth switching element 4v connected in series with each other. The first inductor L1 is connected between the first node N1 between the first switching element 1 and the second switching element 2 of the first half-bridge circuit 21 and the second node N2 between the third switching element 3u and the fourth switching element 4u of the second half-bridge circuit 22. The second inductor L2 is connected between the first node N1 and the third node N3 between the fifth switching element 3v and the sixth switching element 4v of the third half-bridge circuit 23. The second capacitor C2 is connected in parallel with the second half-bridge circuit 22. The third capacitor C3 is connected in parallel to the third half-bridge circuit 23.The control device 30 outputs a first PWM signal S1, a second PWM signal S2, a third PWM signal S3u, a fourth PWM signal S4u, a fifth PWM signal S3v, and a sixth PWM signal S4v, respectively, to control the first switching element 1, the second switching element 2, the third switching element 3u, the fourth switching element 4u, the fifth switching element 3v, and the sixth switching element 4v. In the first half-bridge circuit 21, the first switching element 1 is connected to the positive input terminal 11, and the second switching element 2 is connected between the first switching element 1 and the negative input terminal 12.

[0064] The above configuration makes it possible to miniaturize the device while suppressing current ripple (in other words, reducing ripple current). More specifically, with the above configuration, since the second half-bridge circuit 22 and the third half-bridge circuit 23 are connected to a common first half-bridge circuit 21, it is sufficient to have six switching elements (first switching element 1, second switching element 2, third switching element 3u, fourth switching element 4u, fifth switching element 3v, and sixth switching element 4v). Therefore, with the above configuration, the number of switching elements can be reduced from 12 to 6, resulting in miniaturization and reduced losses. Furthermore, with the above configuration, the DC-DC converter 20u, which includes the first half-bridge circuit 21, the second half-bridge circuit 22, and the first inductor L1, and the DC-DC converter 20v, which includes the first half-bridge circuit 21, the third half-bridge circuit 23, and the second inductor L2, are each DC-DC converters capable of step-up and step-down operation, and can therefore generate a sinusoidal voltage. However, it is important to note that since the DC-DC converter 20u and the DC-DC converter 20v share the first half-bridge circuit 21, it is not possible to control the DC-DC converter 20u and the DC-DC converter 20v independently, and they interact as a single integrated circuit (i.e., a one-input / two-output circuit). Therefore, with the above configuration, in a configuration in which the number of switching elements is reduced from 12 to 6, the phase voltage Va output from the second half-bridge circuit 22 and the phase voltage Vb output from the third half-bridge circuit 23 can each be made sinusoidal voltages. Thus, with the above configuration, it is possible to miniaturize the power converter 10 while suppressing the current ripple of the phase current isa flowing through the first phase output terminal (U-phase output terminal 13u), the phase current isb flowing through the second phase output terminal (V-phase output terminal 13v), and the phase current isc flowing through the third phase output terminal (W-phase output terminal 13w). Furthermore, with the above configuration, when the first phase output terminal (U-phase output terminal 13u), the second phase output terminal (V-phase output terminal 13v), and the third phase output terminal (W-phase output terminal 13w) are connected to a three-phase servo motor (AC load 7) and the three-phase servo motor is being controlled, torque ripple can be reduced.

[0065] Furthermore, in the power converter 10 according to Embodiment 1, the control device 30 determines the first phase reference voltage value (U phase reference voltage value Va1), the second phase reference voltage value (V phase reference voltage value Vb1), and the third phase reference voltage value (W phase reference voltage value Vc1) based on the first phase command voltage value (U phase command voltage value Va0), the second phase command voltage value (V phase command voltage value Vb0), and the third phase command voltage value (W phase command voltage value Vc0), respectively. The control device 30 sets the duty cycle command value d1 such that Vdc × d1 is less than or equal to the minimum value among the first phase reference voltage value (U phase reference voltage value Va1), the second phase reference voltage value (V phase reference voltage value Vb1), and the third phase reference voltage value (W phase reference voltage value Vc1) at each time step.

[0066] The above configuration makes it possible to reduce size while suppressing current ripple.

[0067] Furthermore, with the above configuration, if the control device 30 is configured using, for example, a microcomputer, the number of pins in the microcomputer can be reduced, and the control device 30 can be miniaturized. Also, with the above configuration, if a gate driver and gate drive circuit are further included, the number of each of the gate driver and gate drive circuit can also be reduced.

[0068] (4) Modified Example In the modified example, among the U-phase output terminal 13u, V-phase output terminal 13v, and W-phase output terminal 13w, the U-phase output terminal 13u constitutes a third-phase output terminal that is short-circuited to the positive input terminal 11, the V-phase output terminal 13v constitutes a first-phase output terminal, and the W-phase output terminal 13w constitutes a second-phase output terminal. In this case, a second half-bridge circuit 22 is connected between the V-phase output terminal 13v and the negative input terminal 12, and a third half-bridge circuit 23 is connected between the W-phase output terminal 13w and the negative input terminal 12.

[0069] In another modified configuration, the V-phase output terminal 13v is short-circuited to the positive input terminal 11, forming a third-phase output terminal among the U-phase output terminal 13u, V-phase output terminal 13v, and W-phase output terminal 13w, with the U-phase output terminal 13u forming the first-phase output terminal and the W-phase output terminal 13w forming the second-phase output terminal. In this case, a second half-bridge circuit 22 is connected between the U-phase output terminal 13u and the negative input terminal 12, and a third half-bridge circuit 23 is connected between the W-phase output terminal 13w and the negative input terminal 12.

[0070] (Embodiment 2) The power converter 10A according to Embodiment 2 will be described with reference to Figure 8. With respect to the power converter 10A according to Embodiment 2, components that are the same as those in the power converter 10 according to Embodiment 1 (see Figures 1 and 2) are denoted by the same reference numerals and their description is omitted.

[0071] (1) The power converter 10A according to the second embodiment differs from the power converter 10 according to the first embodiment in that it further comprises a fourth capacitor C4 and a fifth capacitor C5.

[0072] The fourth capacitor C4 is connected between the positive input terminal 11 and the U-phase output terminal 13u. The fifth capacitor C5 is connected between the positive input terminal 11 and the V-phase output terminal 13v. In this embodiment as well, similar to Embodiment 1, the U-phase output terminal 13u constitutes the first-phase output terminal, and the V-phase output terminal 13v constitutes the second-phase output terminal.

[0073] The second capacitor C2, the third capacitor C3, the fourth capacitor C4, and the fifth capacitor C5 are each capacitors having DC bias characteristics. "DC bias characteristics" refers to the characteristic that the capacitance changes depending on the magnitude of the applied DC voltage.

[0074] Each of the second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5 includes a high dielectric constant multilayer ceramic capacitor. The dielectric material of the multilayer ceramic capacitor is a ferroelectric material. The ferroelectric material is, for example, barium titanate (BaTiO2). ３However, this is not limited to barium titanate. The relative permittivity of the dielectric material of a high-dielectric-constant multilayer ceramic capacitor is, for example, 2000 to 12000. A "high-dielectric-constant multilayer ceramic capacitor" is, for example, a multilayer ceramic capacitor classified as "Class 2" in the Japanese Industrial Standards or EIA standards.

[0075] In this embodiment, each of the second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5 includes, for example, a plurality (for example, four) of multilayer ceramic capacitors, and the plurality of multilayer ceramic capacitors are connected in series and parallel. Each of the second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5 is not limited to a configuration that includes a plurality of multilayer ceramic capacitors, but may include at least one multilayer ceramic capacitor.

[0076] In this embodiment, the capacitances of the four capacitors (second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5) are the same. Here, the capacitance of each of the four capacitors refers to the capacitance when no DC voltage is applied. "The capacitances of the four capacitors are the same" does not only mean that the capacitance of each of the four capacitors perfectly matches the capacitance of the remaining capacitor, but also that the capacitance of each of the three capacitors is within the range of 80% to 120% of the capacitance of the remaining capacitor.

[0077] In a capacitor, when a DC voltage is applied between its two terminals, the capacitor's capacitance appears to decrease due to its DC bias characteristics. Hereafter, this reduced capacitance will be referred to as the effective capacitance. For example, in the DC bias characteristics of a high-dielectric-constant multilayer ceramic capacitor, the capacitance change rate when 50V is applied is -75%.

[0078] In the power converter 10A according to Embodiment 2, the sum of the effective capacitance of the second capacitor C2 and the effective capacitance of the fourth capacitor C4 contributes to smoothing the output voltage of the DC-DC converter 20u. For example, when the DC voltage Vdc (see Figure 2), which is the input voltage from the DC power supply E1, is set to 48V, and the phase voltage Va of the U phase is varied in the range of 0V to 48V, as the phase voltage Va increases, the terminal voltage (=Va) of the second capacitor C2 increases, so the effective capacitance of the second capacitor C2 decreases. On the other hand, as the phase voltage Va increases, the terminal voltage (=Va-Vdc) of the fourth capacitor C4 decreases, so the effective capacitance of the fourth capacitor C4 increases. In other words, the rate of change of the sum of the effective capacitance of the second capacitor C2 and the effective capacitance of the fourth capacitor C4 in the power converter 10A is smaller than the rate of change of the effective capacitance of the second capacitor in the comparative example that does not have the fourth capacitor C4.

[0079] Similarly, in the power converter 10A according to Embodiment 2, the sum of the effective capacitance of the third capacitor C3 and the effective capacitance of the fifth capacitor C5 contributes to smoothing the output voltage of the DC-DC converter 20v. For example, when the DC voltage Vdc (see Figure 2), which is the input voltage from the DC power supply E1, is set to 48V, and the phase voltage Vb of the V phase is varied in the range of 0V to 48V, the terminal voltage (=Vb) of the third capacitor C3 increases as the phase voltage Vb increases, so the effective capacitance of the third capacitor C3 decreases. On the other hand, the terminal voltage (=Vb-Vdc) of the fifth capacitor C5 decreases as the phase voltage Vb increases, so the effective capacitance of the fifth capacitor C5 increases. In other words, the rate of change of the sum of the effective capacitance of the third capacitor C3 and the effective capacitance of the fifth capacitor C5 in the power converter 10A is smaller than the rate of change of the effective capacitance of the third capacitor in the comparative example that does not have the fifth capacitor C5.

[0080] In the power converter 10A according to Embodiment 2, the rate of change of the effective capacitance is smaller compared to the power converter of the comparative example, so it is possible to reduce the number of multilayer ceramic capacitors required to secure a predetermined capacitance (for example, 5 μF) as the effective capacitance.

[0081] (2) Advantages The power converter 10A according to Embodiment 2 can be miniaturized while suppressing current ripple, similar to the power converter 10 according to Embodiment 1.

[0082] Furthermore, the power converter 10A according to Embodiment 2 includes a fourth capacitor C4 and a fifth capacitor C5, and each of the second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5 is a capacitor having DC bias characteristics.

[0083] The above configuration makes it possible to miniaturize the power converter 10A. More specifically, in the power converter 10A according to Embodiment 2, when the phase voltages Va and Vb are changed, the DC bias characteristics of the second capacitor C2 and the third capacitor C3 can be mitigated by the DC bias characteristics of the fourth capacitor C4 and the fifth capacitor C5. Therefore, the power converter 10A according to Embodiment 2 can reduce the rate of change of the effective capacitance in the output voltage range of the phase voltages Va and Vb, thereby reducing the voltage ripple of the phase voltages Va and Vb, and making it possible to reduce the capacitance of the second capacitor C2 and the third capacitor C3, thus enabling miniaturization. Furthermore, the above configuration reduces the rate of change of the effective capacitance in the output voltage range, thus reducing the voltage ripple of the phase voltages. Therefore, when the power converter 10A supplies power to the three-phase servo motor (AC load 7) connected to the U-phase output terminal 13u, V-phase output terminal 13v, and W-phase output terminal 13w, torque ripple can also be reduced.

[0084] Furthermore, in the power conversion device 10A according to Embodiment 2, each of the second capacitor C2, third capacitor C3, fourth capacitor C4, and fifth capacitor C5 includes a high dielectric constant multilayer ceramic capacitor.

[0085] The above configuration makes it possible to further miniaturize the device.

[0086] Furthermore, in the power conversion device 10A according to Embodiment 2, when no DC bias voltage is applied to the second capacitor C2 and the fourth capacitor C4, the capacitance of the fourth capacitor C4 is the same as the capacitance of the second capacitor C2.

[0087] With the above configuration, the DC bias characteristics of the second capacitor C2 are more easily canceled out by the DC bias characteristics of the fourth capacitor C4, making it possible to further reduce the rate of change of the effective capacitance when the boost ratio of the first DC-DC converter 20u, which includes the first half-bridge circuit 21, the second half-bridge circuit 22, and the first inductor L1, is 1 or less.

[0088] Furthermore, in the power conversion device 10A according to Embodiment 2, when no DC bias voltage is applied to the third capacitor C3 and the fifth capacitor C5, the capacitance of the fifth capacitor C5 is the same as the capacitance of the third capacitor C3.

[0089] With the above configuration, the DC bias characteristics of the third capacitor C3 are more easily canceled out by the DC bias characteristics of the fifth capacitor C5, making it possible to further reduce the rate of change of the effective capacitance when the boost ratio of the second DC-DC converter 20V, which includes the first half-bridge circuit 21, the third half-bridge circuit 23, and the second inductor L2, is 1 or less.

[0090] (Other Modifications) Embodiments 1 and 2 described above are merely one of many embodiments of the present disclosure. Embodiments 1 and 2 described above can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0091] For example, each of the six switching elements (first switching element 1, second switching element 2, third switching element 3u, fourth switching element 4u, fifth switching element 3v, and sixth switching element 4v) is not limited to an n-channel MOSFET, but may also be a p-channel MOSFET. Also, each of the six switching elements is a Si-based MOSFET, but may also be a SiC-based MOSFET, for example. Furthermore, each of the six switching elements is not limited to a MOSFET, but may also be an IGBT (Insulated Gate Bipolar Transistor) or a GaN-based GIT (Gate Injection Transistor), for example.

[0092] Furthermore, each of the first capacitor C1 to the fifth capacitor C5 is not limited to a configuration including a multilayer ceramic capacitor, but may also be an electrolytic capacitor, for example.

[0093] Furthermore, in addition to the detected values ​​ia of the phase current isa, ib of the phase current isb, and ic of the phase current isc, the control device 30 may also use the detected values ​​of the current IL1 flowing through the first inductor L1 and the detected values ​​of the current IL2 flowing through the second inductor L2 for feedback control. Furthermore, the control device 30 may also use the detected values ​​of the phase voltages Va, Vb, and Vc for feedback control.

[0094] Furthermore, the control device 30 may, instead of the first PI control unit 34 that performs PI (Proportional Integral) control as the first feedback control unit that performs feedback control, include, for example, a P control unit that performs P (Proportional) control or a PID control unit that performs PID (Proportional Integral Differential) control.

[0095] Furthermore, the control device 30 may, instead of the second PI control unit 35 that performs PI control, be equipped with, for example, a P control unit that performs P control or a PID control unit that performs PID control as a second feedback control unit that performs feedback control.

[0096] (Aspects) The following aspects are disclosed in this specification.

[0097] The power converter (10; 10A) according to the first embodiment includes a positive input terminal (11) and a negative input terminal (12), a first phase output terminal (U phase output terminal 13u), a second phase output terminal (V phase output terminal 13v), and a third phase output terminal (W phase output terminal 13w), a first capacitor (C1), a first half-bridge circuit (21), a second half-bridge circuit (22), a third half-bridge circuit (23), a first inductor (L1), a second inductor (L2), a second capacitor (C2), a third capacitor (C3), and a control device (30). The first capacitor (C1) is connected between the positive input terminal (11) and the negative input terminal (12). The first half-bridge circuit (21) is connected between the positive input terminal (11) and the negative input terminal (12). The first half-bridge circuit (21) has a first switching element (1) and a second switching element (2) connected in series with each other. The second half-bridge circuit (22) is connected between the first phase output terminal (U phase output terminal 13u) and the negative input terminal (12). The second half-bridge circuit (22) has a third switching element (3u) and a fourth switching element (4u) connected in series with each other. The third half-bridge circuit (23) is connected between the second phase output terminal (V phase output terminal 13v) and the negative input terminal (12). The third half-bridge circuit (23) has a fifth switching element (3v) and a sixth switching element (4v) connected in series with each other. The first inductor (L1) is connected between the first node (N1) of the first half-bridge circuit (21) between the first switching element (1) and the second switching element (2), and between the second node (N2) of the second half-bridge circuit (22) between the third switching element (3u) and the fourth switching element (4u). The second inductor (L2) is connected between the first node (N1) and the third node (N3) of the third half-bridge circuit (23) between the fifth switching element (3v) and the sixth switching element (4v). The second capacitor (C2) is connected in parallel to the second half-bridge circuit (22). The third capacitor (C3) is connected in parallel to the third half-bridge circuit (23).The control device (30) outputs a first PWM signal (S1), a second PWM signal (S2), a third PWM signal (S3u), a fourth PWM signal (S4u), a fifth PWM signal (S3v), and a sixth PWM signal (S4v) to control the first switching element (1), the second switching element (2), the third switching element (3u), the fourth switching element (4u), the fifth switching element (3v), and the sixth switching element (4v), respectively. In the first half-bridge circuit (21), the first switching element (1) is connected to the positive input terminal (11), and the second switching element (2) is connected between the first switching element (1) and the negative input terminal (12). The third phase output terminal (W phase output terminal 13w) is short-circuited to the positive input terminal (11).

[0098] This embodiment makes it possible to reduce ripple current while miniaturizing the device.

[0099] In the power converter according to the second embodiment (10; 10A), in the first embodiment, the control device (30) determines the first phase reference voltage value (U phase reference voltage value Va1), the second phase reference voltage value (V phase reference voltage value Vb1), and the third phase reference voltage value (W phase reference voltage value Vc1) based on the first phase command voltage value (U phase command voltage value Va0), the second phase command voltage value (V phase command voltage value Vb0), and the third phase command voltage value (W phase command voltage value Vc0), respectively. The control device (30) sets the duty cycle command value d1 such that Vdc × d1 is less than or equal to the minimum value among the first phase reference voltage value (U phase reference voltage value Va1), the second phase reference voltage value (V phase reference voltage value Vb1), and the third phase reference voltage value (W phase reference voltage value Vc1) at each time step, when Vdc × d1 is Vdc and d1 is the duty cycle command value d1 of the first PWM signal (S1).

[0100] This embodiment makes it possible to reduce ripple current while miniaturizing the device.

[0101] In the power converter (10; 10A) according to the third embodiment, in the second embodiment, the control device (30) performs feedback control based on at least two of the following phase currents: the phase current (isa) of the first phase (U phase) output from the first phase output terminal (U phase output terminal 13u), the phase current (isb) of the second phase (V phase) output from the second phase output terminal (V phase output terminal 13v), and the phase current (isc) of the third phase (W phase) output from the third phase output terminal (W phase output terminal 13w).

[0102] In the power converter according to the fourth embodiment (10; 10A), in the third embodiment, the control device (30) determines the first phase command voltage value (U phase command voltage value Va0), the second phase command voltage value (V phase command voltage value Vb0), and the third phase command voltage value (W phase command voltage value Vc0) based on at least two of the phase currents: the first phase (U phase) phase current (isa) output from the first phase output terminal (U phase output terminal 13u), the second phase (V phase) phase current (isb) output from the second phase output terminal (V phase output terminal 13v), and the third phase (W phase) phase current (isc) output from the third phase output terminal (W phase output terminal 13w).

[0103] In the power converter according to the fifth embodiment (10; 10A), in the fourth embodiment, the control device (30) determines the first phase reference voltage value (U phase reference voltage value Va1), the second phase reference voltage value (V phase reference voltage value Vb0), and the third phase reference voltage value (W phase reference voltage value Vc1) by adding the same bias voltage value (-Vc0 + Vdc) to each of the first phase command voltage value (U phase command voltage value Va0), the second phase command voltage value (V phase command voltage value Vb0), and the third phase command voltage value (W phase command voltage value Vc0).

[0104] The power converter (10A) according to the sixth embodiment further comprises a fourth capacitor (C4) and a fifth capacitor (C5) in any one of the first to fifth embodiments. The fourth capacitor (C4) is connected between the positive input terminal (11) and the first phase output terminal (U phase output terminal 13u). The fifth capacitor (C5) is connected between the positive input terminal (11) and the second phase output terminal (V phase output terminal 13v). Each of the second capacitor (C2), third capacitor (C3), fourth capacitor (C4), and fifth capacitor (C5) is a capacitor having DC bias characteristics.

[0105] According to this embodiment, the DC bias characteristics of the second capacitor (C2) and the third capacitor (C3) can be mitigated by the DC bias characteristics of the fourth capacitor (C4) and the fifth capacitor (C5), respectively, making it possible to reduce the voltage ripple of the phase voltage (phase voltage Va) of the first phase (U phase) and the phase voltage (phase voltage Vb) of the second phase (V phase).

[0106] In the power conversion device (10A) according to the seventh embodiment, in the sixth embodiment, each of the second capacitor (C2), third capacitor (C3), fourth capacitor (C4), and fifth capacitor (C5) includes a high dielectric constant multilayer ceramic capacitor.

[0107] This embodiment makes it possible to further miniaturize the product.

[0108] In the power conversion device (10A) according to the eighth embodiment, the dielectric material of the multilayer ceramic capacitor is a ferroelectric material, as in the seventh embodiment.

[0109] The power converter (10A) according to the ninth embodiment is based on any one of the sixth to eighth embodiments. When no DC bias voltage is applied to the second capacitor (C2) and the fourth capacitor (C4), the capacitance of the fourth capacitor (C4) is the same as the capacitance of the second capacitor (C2). When no DC bias voltage is applied to the third capacitor (C3) and the fifth capacitor (C5), the capacitance of the fifth capacitor (C5) is the same as the capacitance of the third capacitor (C3).

[0110] According to this embodiment, the DC bias characteristics of the second capacitor (C2) are more easily canceled out by the DC bias characteristics of the fourth capacitor (C4), making it possible to further reduce the rate of change in effective capacitance when the boost ratio of the DC-DC converter (first DC-DC converter 20u) including the first half-bridge circuit (21), the second half-bridge circuit (22), and the first inductor (L1) is 1 or less. Furthermore, according to this embodiment, the DC bias characteristics of the third capacitor (C3) are more easily canceled out by the DC bias characteristics of the fifth capacitor (C5), making it possible to further reduce the rate of change in effective capacitance when the boost ratio of the DC-DC converter (second DC-DC converter 20v) including the first half-bridge circuit (21), the third half-bridge circuit (23), and the second inductor (L2) is 1 or less.

[0111] 1 First switching element 2 Second switching element 3u Third switching element 4u Fourth switching element 3v Fifth switching element 4v Sixth switching element 10, 10A Power converter 11 Positive input terminal 12 Negative input terminal 13u U-phase output terminal (first phase output terminal) 13v V-phase output terminal (second phase output terminal) 13w W-phase output terminal (third phase output terminal) 21 First half-bridge circuit 22 Second half-bridge circuit 23 Third half-bridge circuit 30 Control device C1 First capacitor C2 Second capacitor C3 Third capacitor C4 Fourth capacitor C5 Fifth capacitor L1 First inductor L2 Second inductor N1 First node N2 Second node N3 Third node S1 First PWM signal S2 Second PWM signal S3u Third PWM signal S4u Fourth PWM signal S3v Fifth PWM signal S4v Sixth PWM signal Va0 U-phase command voltage value Va1 U-phase reference voltage value Vb0 V-phase command voltage value Vb1 V-phase reference voltage value Vc0 W-phase command voltage value Vc1 W-phase reference voltage value Vdc DC voltage

Claims

1. A positive input terminal and a negative input terminal, a first phase output terminal, a second phase output terminal and a third phase output terminal, a first capacitor connected between the positive input terminal and the negative input terminal, a first half-bridge circuit having a first switching element and a second switching element connected in series with each other, a second half-bridge circuit having a third switching element and a fourth switching element connected in series with each other, a third half-bridge circuit having a fifth switching element and a sixth switching element connected in series with each other, a first node between the first switching element and the second switching element of the first half-bridge circuit and a second node between the third switching element and the fourth switching element of the second half-bridge circuit, a second inductor connected between the first node and the third node between the fifth switching element and the sixth switching element of the third half-bridge circuit, A power converter comprising: a second capacitor connected in parallel to the second half-bridge circuit; a third capacitor connected in parallel to the third half-bridge circuit; and a control device that outputs a first PWM signal, a second PWM signal, a third PWM signal, a fourth PWM signal, a fifth PWM signal, and a sixth PWM signal for controlling the first switching element, the second switching element, the third switching element, the fourth switching element, the fifth switching element, and the sixth switching element, respectively, wherein in the first half-bridge circuit, the first switching element is connected to the positive input terminal, the second switching element is connected between the first switching element and the negative input terminal, and the third phase output terminal is short-circuited to the positive input terminal.

2. The power conversion device according to claim 1, wherein the control device determines a first phase reference voltage value, a second phase reference voltage value, and a third phase reference voltage value based on the first phase command voltage value, the second phase command voltage value, and the third phase command voltage value, respectively, and sets the duty cycle command value d1 such that Vdc × d1 is less than or equal to the minimum value of the first phase reference voltage value, the second phase reference voltage value, and the third phase reference voltage value at each time.

3. The power converter according to claim 2, wherein the control device performs feedback control based on at least two phase currents among the first phase phase current output from the first phase output terminal, the second phase phase current output from the second phase output terminal, and the third phase phase current output from the third phase output terminal.

4. The power conversion device according to claim 3, wherein the control device determines the first phase command voltage value, the second phase command voltage value, and the third phase command voltage value based on at least two phase currents among the first phase phase current output from the first phase output terminal, the second phase phase current output from the second phase output terminal, and the third phase phase current output from the third phase output terminal.

5. The power conversion device according to claim 4, wherein the control device determines the first phase reference voltage value, the second phase reference voltage value, and the third phase reference voltage value by adding the same bias voltage value to each of the first phase command voltage value, the second phase command voltage value, and the third phase command voltage value.

6. The power conversion device according to any one of claims 1 to 5, further comprising: a fourth capacitor connected between the positive input terminal and the first phase output terminal; and a fifth capacitor connected between the positive input terminal and the second phase output terminal, wherein each of the second capacitor, the third capacitor, the fourth capacitor and the fifth capacitor is a capacitor having DC bias characteristics.

7. The power conversion device according to claim 6, wherein each of the second capacitor, the third capacitor, the fourth capacitor, and the fifth capacitor includes a high dielectric constant multilayer ceramic capacitor.

8. The power conversion device according to claim 7, wherein the dielectric material of the multilayer ceramic capacitor is a ferroelectric material.

9. The power conversion device according to any one of claims 6 to 8, wherein, when no DC bias voltage is applied to the second capacitor and the fourth capacitor, the capacitance of the fourth capacitor is the same as the capacitance of the second capacitor, and when no DC bias voltage is applied to the third capacitor and the fifth capacitor, the capacitance of the fifth capacitor is the same as the capacitance of the third capacitor.

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