Back-contact solar cell and preparation method therefor

Abstract

The present invention relates to a back-contact solar cell and a preparation method therefor. The back-contact solar cell comprises a monocrystalline silicon substrate, a tunnel oxide layer, a first-doping-type polysilicon layer, a second-doping-type polysilicon layer, an intrinsic amorphous silicon layer, a first electrode, and a second electrode. The tunnel oxide layer is arranged on a first side of the monocrystalline silicon substrate; the first-doping-type polysilicon layer, the second-doping-type polysilicon layer and the intrinsic amorphous silicon layer are all arranged on the tunnel oxide layer; and the intrinsic amorphous silicon layer is arranged between the first-doping-type polysilicon layer and the second-doping-type polysilicon layer. The back-contact solar cell has an isolation trench separating the intrinsic amorphous silicon layer into a first portion connected to the first-doping-type polysilicon layer and a second portion connected to the second-doping-type polysilicon layer.

Description

Back contact solar cells and their fabrication methods

[0001] This application claims priority to Chinese Patent Application No. 202411524690.0, filed on October 29, 2024, entitled “Back Contact Solar Cell and Method for Preparing the Same”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of photovoltaic technology, and in particular to a back-contact solar cell and its fabrication method. Background Technology

[0003] Fully back-contact crystalline silicon solar cells (BC cells) place all metal electrodes on the back of the cell. Since there are no metal electrodes obstructing the front, this maximizes the area of ​​the cell that absorbs sunlight, reduces optical losses, and thus improves photoelectric conversion efficiency. However, these cells also have P-regions and N-regions on the back. During the fabrication process of the N-regions and P-regions, leakage channels can easily form, reducing the cell's efficiency. Summary of the Invention

[0004] Therefore, it is necessary to provide a back-contact solar cell and its fabrication method to solve the problem of leakage current channels forming between the P-region and N-region of a BC cell.

[0005] The first aspect of the present invention is to provide a back-contact solar cell, the solution of which is as follows:

[0006] A back-contact solar cell includes a monocrystalline silicon substrate, a tunneling oxide layer, a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, a first electrode, and a second electrode.

[0007] The tunneling oxide layer is disposed on a first side of the monocrystalline silicon substrate. The first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer are respectively disposed on the tunneling oxide layer. The intrinsic amorphous silicon layer is disposed between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer. The first electrode is connected to the first doped polycrystalline silicon layer, and the second electrode is connected to the second doped polycrystalline silicon layer. The back contact solar cell has an isolation trench that divides the intrinsic amorphous silicon layer into a first portion connected to the first doped polycrystalline silicon layer and a second portion connected to the second doped polycrystalline silicon layer. The first electrode is connected to the first doped polycrystalline silicon layer, and the second electrode is connected to the second doped polycrystalline silicon layer.

[0008] In one embodiment, the isolation trench extends through the intrinsic amorphous silicon layer and the tunneling oxide layer to the monocrystalline silicon substrate.

[0009] In one embodiment, the thickness of the tunneling oxide layer is 1 nm to 3 nm.

[0010] In one embodiment, the thickness of the first doped polysilicon layer is 80 nm to 300 nm.

[0011] In one embodiment, the thickness of the second doped polysilicon layer is 80 nm to 300 nm.

[0012] In one embodiment, the thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

[0013] In one embodiment, the width of the isolation groove is 50 μm to 150 μm.

[0014] In one embodiment, the back-contact solar cell includes a front passivation antireflection layer disposed on a second side of the monocrystalline silicon substrate.

[0015] In one embodiment, the back-contact solar cell includes a back passivation antireflection layer that covers the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, the intrinsic amorphous silicon layer, and the wall of the isolation trench.

[0016] A second aspect of the present invention is to provide a method for fabricating a back-contact solar cell, the scheme of which is as follows:

[0017] A method for fabricating a back-contact solar cell includes the following steps:

[0018] A tunneling oxide layer is prepared on one side of a single-crystal silicon substrate;

[0019] A first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer are fabricated on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is located between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer.

[0020] An isolation trench is prepared, wherein the isolation trench divides the intrinsic amorphous silicon layer into a first portion connected to the first doped polycrystalline silicon layer and a second portion connected to the second doped polycrystalline silicon layer;

[0021] A first electrode is fabricated and connected to the first doped type polycrystalline silicon layer;

[0022] A second electrode is prepared and connected to the second type of doped polycrystalline silicon layer.

[0023] In one embodiment, the step of fabricating a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is disposed between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer, includes:

[0024] An intrinsic amorphous silicon layer is prepared on the tunneling oxide layer;

[0025] A first doped paste is disposed on the intrinsic amorphous silicon layer in the first region, and a second doped paste is disposed on the intrinsic amorphous silicon layer in the second region;

[0026] A silicon wafer with the first doping type paste and the second doping type paste is subjected to hydrogen plasma treatment, so that the intrinsic amorphous silicon layer in the first region is doped to form the first doping type polycrystalline silicon layer, and the intrinsic amorphous silicon layer in the second region is doped to form the second doping type polycrystalline silicon layer, wherein the first doping type polycrystalline silicon layer and the second doping type polycrystalline silicon layer are separated by the intrinsic amorphous silicon layer.

[0027] In one embodiment, the radio frequency power density of the hydrogen plasma treatment is 30 mW / cm². 2 ~80mw / cm 2 The process pressure is 0.9 Torr to 1.2 Torr, the process temperature is 300℃ to 800℃, and the process time is 30s to 180s.

[0028] In one embodiment, the step of preparing the isolation trench includes:

[0029] An etching protection layer is prepared in the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the intrinsic amorphous silicon layer, the etching protection layer exposing the intrinsic amorphous silicon layer in a third region, the third region being located between the first region and the second region;

[0030] The intrinsic amorphous silicon layer in the third region is etched away to form the isolation trench.

[0031] In one embodiment, the thickness of the tunneling oxide layer is 1 nm to 3 nm.

[0032] In one embodiment, the thickness of the first doped polysilicon layer is 80 nm to 300 nm.

[0033] In one embodiment, the thickness of the second doped polysilicon layer is 80 nm to 300 nm.

[0034] In one embodiment, the thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

[0035] In one embodiment, the width of the isolation groove is 50 μm to 150 μm.

[0036] In one embodiment, the fabrication method further includes the step of fabricating a front passivation antireflection layer disposed on a second side of the monocrystalline silicon substrate.

[0037] In one embodiment, the fabrication method further includes the step of fabricating a back passivation antireflection layer, wherein the back passivation antireflection layer is integrally covered on the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, the intrinsic amorphous silicon layer, and the trench wall of the isolation trench.

[0038] Compared with traditional technologies, the above-mentioned back-contact solar cells and their fabrication methods have the following advantages:

[0039] The aforementioned back-contact solar cell and its fabrication method incorporate an intrinsic amorphous silicon layer between the first and second doped polycrystalline silicon layers on the back side. This layer prevents the formation of leakage channels and chemically passivates the monocrystalline silicon substrate, repairing interfacial dangling bonds and eliminating internal recombination centers, thereby improving the cell's conversion efficiency. The back-contact solar cell also features an isolation trench that divides the intrinsic amorphous silicon layer into a first portion connected to the first doped polycrystalline silicon layer and a second portion connected to the second doped polycrystalline silicon layer. This not only compensates for interfacial defects in the monocrystalline silicon substrate at this location but also achieves insulation between the two different doped dielectrics, preventing mutual conductivity. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the structure of a back-contact solar cell according to an embodiment;

[0041] Figure 2 is a schematic diagram of the fabrication of a tunneling oxide layer and an intrinsic amorphous silicon layer on a single-crystal silicon substrate;

[0042] Figure 3 is a schematic diagram of setting a first doping type paste and a second doping type paste on an intrinsic amorphous silicon layer;

[0043] Figure 4 is a schematic diagram of hydrogen plasma treatment, which causes the intrinsic amorphous silicon layer in the first region to be doped to form a first type of polycrystalline silicon layer, and the intrinsic amorphous silicon layer in the second region to be doped to form a second type of polycrystalline silicon layer.

[0044] Figure 5 is a schematic diagram of the etching protection layer fabricated on the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the intrinsic amorphous silicon layer.

[0045] Figure 6 is a schematic diagram of laser processing to remove the etched protective film on the third region;

[0046] Figure 7 is a schematic diagram of etching away the intrinsic amorphous silicon layer in the third region to form an isolation trench;

[0047] Figure 8 is a schematic diagram of the fabrication of the back passivation antireflection layer and the front passivation antireflection layer.

[0048] Explanation of reference numerals in the attached figures: 100, back contact solar cell; 110, monocrystalline silicon substrate; 120, tunneling oxide layer; 130, first doped polycrystalline silicon layer; 140, second doped polycrystalline silicon layer; 150, intrinsic amorphous silicon layer; 151, first portion; 152, second portion; 161, first electrode; 162, second electrode; 170, isolation trench; 180, front passivation antireflection layer; 190, back passivation antireflection layer; 111, first region; 112, second region; 113, third region; 114, textured surface; 131, first doped paste; 141, second doped paste; 200, etching protection layer. Detailed Implementation

[0049] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0051] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0053] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0054] As shown in FIG1, a back-contact solar cell 100 of one embodiment includes a monocrystalline silicon substrate 110, a tunneling oxide layer 120, a first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, an intrinsic amorphous silicon layer 150, a first electrode 161, and a second electrode 162.

[0055] A tunneling oxide layer 120 is disposed on a first side of a monocrystalline silicon substrate 110. A first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, and an intrinsic amorphous silicon layer 150 are respectively disposed on the tunneling oxide layer 120. The intrinsic amorphous silicon layer 150 is disposed between the first-doped polycrystalline silicon layer 130 and the second-doped polycrystalline silicon layer 140. A first electrode 161 is connected to the first-doped polycrystalline silicon layer 130, and a second electrode 162 is connected to the second-doped polycrystalline silicon layer 140. The back-contact solar cell 100 has an isolation trench 170, which divides the intrinsic amorphous silicon layer 150 into a first portion 151 connected to the first-doped polycrystalline silicon layer 130 and a second portion 152 connected to the second-doped polycrystalline silicon layer 140.

[0056] The first electrode 161 is connected to the first doped polysilicon layer 130, and the second electrode 162 is connected to the second doped polysilicon layer 140.

[0057] The single-crystal silicon substrate 110 can be either N-type doped or P-type doped.

[0058] The monocrystalline silicon substrate 110 has a first side and a second side disposed opposite to each other. The tunneling oxide layer 120, the first-doped polycrystalline silicon layer 130, the second-doped polycrystalline silicon layer 140, the intrinsic amorphous silicon layer 150, the first electrode 161, and the second electrode 162 are all disposed on the first side of the monocrystalline silicon substrate 110. The second side of the monocrystalline silicon substrate 110 may be configured as a textured surface 114.

[0059] The material of the tunnel oxide layer 120 can be, but is not limited to, SiO2. x The thickness of the tunneling oxide layer 120 is, for example, 1 to 3 nm, specifically 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, etc.

[0060] The first doped polysilicon layer 130 and the second doped polysilicon layer 140 have opposite doping types. For example, the first doped polysilicon layer 130 is P-type doped and the second doped polysilicon layer 140 is N-type doped. Alternatively, the first doped polysilicon layer 130 is N-type doped and the second doped polysilicon layer 140 is P-type doped.

[0061] In some of these examples, the first doped polysilicon layer 130 and the second doped polysilicon layer 140 are arranged in an interdigitated pattern. This design can reduce the current transmission path, lower the resistance, and improve the battery conversion efficiency.

[0062] The thickness of the first doped polycrystalline silicon layer 130 is, for example, 80nm to 300nm, specifically 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.

[0063] The thickness of the second type of doped polycrystalline silicon layer 140 is, for example, 80nm to 300nm, specifically 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.

[0064] The thickness of the intrinsic amorphous silicon layer 150 is, for example, 80nm to 300nm, specifically 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.

[0065] In some of these examples, the isolation trench 170 extends through the intrinsic amorphous silicon layer 150 and the tunnel oxide layer 120, all the way to the monocrystalline silicon substrate 110.

[0066] In some of these examples, the width of the isolation trench 170 is 50μm to 150μm, specifically 50nm, 70nm, 90nm, 110nm, 130nm, 150nm, etc.

[0067] In some examples, the back-contact solar cell 100 includes a front passivation antireflection layer 180 disposed on a second side of the monocrystalline silicon substrate 110. The material of the front passivation antireflection layer 180 can be, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0068] In some examples, the back-contact solar cell 100 includes a back passivation antireflection layer 190, which covers the walls of a first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, an intrinsic amorphous silicon layer 150, and an isolation trench 170. The material of the back passivation antireflection layer 190 can be, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0069] Optionally, the first electrode 161 and the second electrode 162 may be made of metal materials such as silver or aluminum.

[0070] The aforementioned back-contact solar cell 100 has an intrinsic amorphous silicon layer 150 disposed between the first doped polycrystalline silicon layer 130 and the second doped polycrystalline silicon layer 140 on the back side. This prevents the formation of leakage channels, and the intrinsic amorphous silicon layer 150 can chemically passivate the monocrystalline silicon substrate 110, repair interface dangling bonds, and eliminate internal recombination centers, thereby improving the cell's conversion efficiency. The back-contact solar cell 100 also has an isolation trench 170, which divides the intrinsic amorphous silicon layer 150 into a first portion 151 connected to the first doped polycrystalline silicon layer 130 and a second portion 152 connected to the second doped polycrystalline silicon layer 140. This not only compensates for interface defects in the monocrystalline silicon substrate 110 at this location but also achieves insulation between the two different doped dielectrics, preventing mutual conduction.

[0071] Furthermore, the present invention also provides a method for preparing a back-contact solar cell 100 according to any of the above examples.

[0072] One embodiment of the method for fabricating a back-contact solar cell 100 includes the following steps:

[0073] Step S10: A tunneling oxide layer 120 is prepared on one side of a single-crystal silicon substrate 110.

[0074] In step S20, a first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, and an intrinsic amorphous silicon layer 150 are prepared on the tunneling oxide layer 120, wherein the intrinsic amorphous silicon layer 150 is located between the first-doped polycrystalline silicon layer 130 and the second-doped polycrystalline silicon layer 140.

[0075] Step S30: Prepare an isolation trench 170, which divides the intrinsic amorphous silicon layer 150 into a first portion 151 connected to the first doped polycrystalline silicon layer 130 and a second portion 152 connected to the second doped polycrystalline silicon layer 140.

[0076] Step S40: Prepare a first electrode 161 connected to the first doped polycrystalline silicon layer 130.

[0077] Step S50: Prepare a second electrode 162 connected to the second doped polycrystalline silicon layer 140.

[0078] Before fabricating the tunneling oxide layer 120 on the monocrystalline silicon substrate 110, it is preferable to chemically clean the monocrystalline silicon substrate 110. Chemical cleaning may be performed using an alkaline solution, and chemical polishing may be carried out at 65°C to 90°C for, for example, 180 s to 420 s. The alkaline solution may be, for example, KOH or NaOH. Then, oxygen or nitrogen is introduced for high-temperature drying to obtain a double-sided polished monocrystalline silicon substrate 110.

[0079] Optionally, in step S10, the method for preparing the tunneling oxide layer 120 can be, but is not limited to, high-temperature oxidation, nitric acid oxidation, ozone oxidation, etc.

[0080] In some of these examples, step S20 includes:

[0081] Step S21, as shown in Figure 2, involves preparing an intrinsic amorphous silicon layer 150 on the tunneling oxide layer 120.

[0082] Step S22, as shown in Figure 3, involves depositing a first doped type paste 131 on the intrinsic amorphous silicon layer 150 in the first region 111 and depositing a second doped type paste 141 on the intrinsic amorphous silicon layer 150 in the second region 112.

[0083] Step S23, as shown in Figure 4, involves treating the silicon wafer with the first doped type paste 131 and the second doped type paste 141 using hydrogen plasma. This process dops the intrinsic amorphous silicon layer 150 in the first region 111 to form the first doped type polycrystalline silicon layer 130, and the intrinsic amorphous silicon layer 150 in the second region 112 to form the second doped type polycrystalline silicon layer 140. The first doped type polycrystalline silicon layer 130 and the second doped type polycrystalline silicon layer 140 are separated by the intrinsic amorphous silicon layer 150.

[0084] Optionally, in step S21, the method for preparing the intrinsic amorphous silicon layer 150 can be, but is not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, hot filamentation vapor deposition, physical vapor deposition, etc.

[0085] In some of these examples, in step S22, the first doped type paste 131 and the second doped type paste 141 are printed using a mask with a specific stiffness and pattern.

[0086] In some examples, the first doped type paste 131 is a phosphorus paste. The phosphorus paste has a solid content of 10%–40% and a viscosity of 20 Pa–50 Pa. The width of the phosphorus paste is approximately 350 μm–650 μm. The second doped type paste 141 is a boron paste. The boron paste has a solid content of 10%–50% and a viscosity of 20 Pa–50 Pa. The width of the boron paste is 250 μm–450 μm.

[0087] In some of these examples, in step S23, the radio frequency power density of the hydrogen plasma treatment is 30 mW / cm². 2 ~80mw / cm 2 For example, 30mw / cm 2 40mw / cm 2 50mw / cm 2 60mw / cm 2 70mw / cm 2 80mw / cm 2 wait.

[0088] In some of these examples, in step S23, the process pressure of the hydrogen plasma treatment is 0.9 Torr to 1.2 Torr, specifically, for example, 0.9 Torr, 1 Torr, 1.1 Torr, 1.2 Torr, etc.

[0089] In some examples, in step S23, the process temperature of the hydrogen plasma treatment is 300°C to 800°C, specifically, for example, 300°C, 400°C, 500°C, 600°C, 700°C, 800°C, etc.

[0090] In some examples, the process time for hydrogen plasma treatment in step S23 is 30s to 180s, specifically 30s, 50s, 70s, 90s, 110s, 130s, 150s, 170s, etc.

[0091] After hydrogen plasma treatment, the doping concentration of the first-type doped polycrystalline silicon layer 130 is approximately 1 × 10⁻⁶. 15 cm -3 The doping concentration of the second type of polycrystalline silicon layer 140 is approximately 7 × 10⁻⁶. 18 cm -3 .

[0092] In some of these examples, step S30 includes:

[0093] In step S31, as shown in Figures 5 and 6, an etch protection layer 200 is prepared on the first doped polycrystalline silicon layer 130, the second doped polycrystalline silicon layer 140, and the intrinsic amorphous silicon layer 150. The etch protection layer 200 exposes the intrinsic amorphous silicon layer 150 in the third region 113, which is located between the first region 111 and the second region 112.

[0094] Step S32, as shown in Figure 7, involves etching away the intrinsic amorphous silicon layer 150 in the third region 113 to form an isolation trench 170.

[0095] Optionally, the etched protective film can be, but is not limited to, silicon oxide (SiO2). x ), silicon oxynitride (SiO) x N y Materials include borosilicate glass (BSG), etc. The thickness of the etched protective film is, for example, 2 nm to 50 nm.

[0096] Alternatively, the method for preparing the etched protective film can be, but is not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.

[0097] As shown in Figure 6, in step S31, the etched protective film can be partially removed from the third region 113 by deposition over the entire surface followed by laser processing. The laser processing may use, for example, a laser with a wavelength of 355 nm and a power of 30 W to 80 W. The width of the laser-processed region may be, for example, 30 μm to 50 μm.

[0098] In step S32, the etching solution used to etch away the intrinsic amorphous silicon layer 150 of the third region 113 can be an alkaline etching solution. For example, an alkaline etching solution may contain an alkali, an additive, and water in a volume ratio of 2:1:10. The alkali may be, for example, NaOH or KOH. The etching time is, for example, 300 s to 500 s.

[0099] In some examples, in step S32, the tunneling oxide layer 120 of the third region 113 is further etched away to expose the monocrystalline silicon substrate 110. At this time, the alkaline etching solution increases the opening width by 2 μm to 5 μm based on the width of the laser-processed region, ultimately retaining an intrinsic polycrystalline silicon layer with a width of 70 μm to 150 μm.

[0100] In some examples, as shown in Figure 8, the method for fabricating a back contact solar cell 100 further includes the step of fabricating a back passivation antireflection layer 190, which covers the first doped polycrystalline silicon layer 130, the second doped polycrystalline silicon layer 140, the intrinsic amorphous silicon layer 150, and the trench wall of the isolation trench 170.

[0101] In some examples, as shown in Figure 8, the fabrication method of the back contact solar cell 100 further includes the step of fabricating a front passivation antireflection layer 180, which is disposed on the second side of the monocrystalline silicon substrate 110.

[0102] In some examples, an aluminum oxide layer with a thickness of approximately 3 nm to 10 nm is deposited on both the front and back sides of the battery. Atomic-layer passivation film deposition can be achieved using one of PEALD, ALD, or PVD, and trimethylaluminum and H₂O or trimethylaluminum and O₃ can be used as the reaction gas. Then, a passivation antireflection film with a thickness of 70 nm to 110 nm and a refractive index of 2.0% to 2.4% is deposited on both the front and back sides of the battery. This passivation antireflection film can be at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0103] In steps S40 and S50, the first electrode 161 and the second electrode 162 can be printed with silver paste, aluminum paste, etc. using a printing process, and then sintered at 700℃~900℃ to achieve metallization.

[0104] When fabricating emitters in two heavily doped regions on the back side, it is also necessary to avoid direct contact between the P-region and N-region to prevent short circuits. Therefore, multiple mask fabrication and laser delamination processes are inevitably required. The above-mentioned fabrication method achieves precise local doping on the back side by printing doping paste, and then effectively improves the passivation performance of the printed area through hydrogen plasma treatment. Moreover, it reduces the number of process steps and lowers production costs, making it more conducive to large-scale production. The above-mentioned fabrication method sets an intrinsic amorphous silicon layer 150 between the two types of emitters on the back side and uses only one laser process to create a groove. This not only compensates for the interface defects of the single-crystal silicon substrate 110 at this location, but also achieves insulation between the two different doped dielectrics, preventing mutual conduction.

[0105] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0106] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A back-contact solar cell, characterized in that, It includes a single-crystal silicon substrate, a tunneling oxide layer, a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, a first electrode, and a second electrode; The tunneling oxide layer is disposed on a first side of the monocrystalline silicon substrate. The first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer are respectively disposed on the tunneling oxide layer. The intrinsic amorphous silicon layer is disposed between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer. The first electrode is connected to the first doped polycrystalline silicon layer, and the second electrode is connected to the second doped polycrystalline silicon layer. The back contact solar cell has an isolation trench that divides the intrinsic amorphous silicon layer into a first portion connected to the first doped polycrystalline silicon layer and a second portion connected to the second doped polycrystalline silicon layer. The first electrode is connected to the first doped polycrystalline silicon layer, and the second electrode is connected to the second doped polycrystalline silicon layer.

2. The back-contact solar cell as described in claim 1, characterized in that, The isolation trench penetrates the intrinsic amorphous silicon layer and the tunneling oxide layer, extending to the monocrystalline silicon substrate.

3. The back-contact solar cell as described in claim 1, characterized in that, The width of the isolation groove is 50μm to 150μm.

4. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the tunneling oxide layer is 1 nm to 3 nm.

5. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the first doped polycrystalline silicon layer is 80 nm to 300 nm.

6. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the second type of doped polycrystalline silicon layer is 80nm to 300nm.

7. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

8. The back-contact solar cell as described in claim 1, characterized in that, The back-contact solar cell includes a front passivation antireflection layer disposed on the second side of the monocrystalline silicon substrate.

9. The back-contact solar cell according to any one of claims 1 to 8, characterized in that, The back-contact solar cell includes a back passivation antireflection layer, which covers the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, the intrinsic amorphous silicon layer, and the wall of the isolation trench.

10. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: A tunneling oxide layer is prepared on the first side of a single-crystal silicon substrate; A first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer are fabricated on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is located between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer. An isolation trench is prepared, wherein the isolation trench divides the intrinsic amorphous silicon layer into a first portion connected to the first doped polycrystalline silicon layer and a second portion connected to the second doped polycrystalline silicon layer; A first electrode is fabricated and connected to the first doped type polycrystalline silicon layer; A second electrode is prepared and connected to the second type of doped polycrystalline silicon layer.

11. The method for fabricating a back-contact solar cell as described in claim 10, characterized in that, The step of fabricating a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is disposed between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer, includes: An intrinsic amorphous silicon layer is prepared on the tunneling oxide layer; A first doped paste is disposed on the intrinsic amorphous silicon layer in the first region, and a second doped paste is disposed on the intrinsic amorphous silicon layer in the second region; A silicon wafer with the first doping type paste and the second doping type paste is subjected to hydrogen plasma treatment, so that the intrinsic amorphous silicon layer in the first region is doped to form the first doping type polycrystalline silicon layer, and the intrinsic amorphous silicon layer in the second region is doped to form the second doping type polycrystalline silicon layer, wherein the first doping type polycrystalline silicon layer and the second doping type polycrystalline silicon layer are separated by the intrinsic amorphous silicon layer.

12. The method for fabricating a back-contact solar cell as described in claim 11, characterized in that, The radio frequency power density of the hydrogen plasma treatment is 30 mW / cm². 2 ~80mw / cm 2 The process pressure is 0.9 Torr to 1.2 Torr, the process temperature is 300℃ to 800℃, and the process time is 30s to 180s.

13. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The steps for preparing the isolation trench include: An etching protection layer is prepared in the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer and the intrinsic amorphous silicon layer, the etching protection layer exposing the intrinsic amorphous silicon layer in a third region, the third region being located between the first region and the second region; The intrinsic amorphous silicon layer in the third region is etched away to form the isolation trench.

14. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The width of the isolation groove is 50μm to 150μm.

15. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The thickness of the tunneling oxide layer is 1 nm to 3 nm.

16. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The thickness of the first doped polycrystalline silicon layer is 80 nm to 300 nm.

17. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The thickness of the second type of doped polycrystalline silicon layer is 80nm to 300nm.

18. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

19. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The preparation method further includes the step of preparing a front passivation antireflection layer, wherein the front passivation antireflection layer is disposed on the second side of the monocrystalline silicon substrate.

20. The method for preparing a back-contact solar cell according to any one of claims 10 to 12, characterized in that, The preparation method further includes the step of preparing a back passivation antireflection layer, wherein the back passivation antireflection layer is integrally covered on the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, the intrinsic amorphous silicon layer, and the trench wall of the isolation trench.

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