Back-contact solar cell and manufacturing method therefor

Abstract

The present invention relates to a back-contact solar cell and a manufacturing method therefor. The back-contact solar cell comprises a monocrystalline silicon substrate, a tunnel oxide layer, a first doped type polycrystalline silicon layer, a second doped type polycrystalline silicon layer, an intrinsic amorphous silicon layer, a first electrode and a second electrode; the tunnel oxide layer is arranged on one side of the monocrystalline silicon substrate; the first doped type polycrystalline silicon layer, the second doped type polycrystalline silicon layer and the intrinsic amorphous silicon layer are separately arranged on the tunnel oxide layer, the intrinsic amorphous silicon layer being arranged between the first doped type polycrystalline silicon layer and the second doped type polycrystalline silicon layer; the first electrode is connected to the first doped type polycrystalline silicon layer, and the second electrode is connected to the second doped type polycrystalline silicon layer.

Description

Back contact solar cells and their fabrication methods

[0001] This application claims priority to Chinese Patent Application No. 202411525775.0, filed on October 29, 2024, entitled “Back Contact Solar Cell and Method for Preparing the Same”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of photovoltaic technology, and in particular to a back-contact solar cell and its fabrication method. Background Technology

[0003] Energy is the foundation of world economic and social development. Future energy demand will increase with the development of the world economy. Photovoltaic power generation, as a sustainable energy alternative, has developed rapidly in recent years.

[0004] Currently, the solar cells used in photovoltaic power plants are mainly crystalline silicon solar cells. With improvements in front-side light trapping, metallization performance, and silicon wafer quality, the cells have evolved from aluminum back-field cells to the TOPCon cells of today. In order to pursue the theoretical conversion efficiency of crystalline silicon solar cells to the extreme, full back-electrode contact crystalline silicon solar cells (BC cells) are gradually being considered as the most likely cells to become mass-produced cells with high conversion efficiency.

[0005] All-back contact crystalline silicon solar cells (BC cells) place all metal electrodes on the back of the cell. Since there are no metal electrodes obstructing the front, this maximizes the area of ​​the cell that absorbs sunlight, reduces optical losses, and thus improves photoelectric conversion efficiency. However, these cells also have both P-regions and N-regions on the back, which can easily create leakage paths between them, reducing cell efficiency. Therefore, the formation of these leakage paths is a key technological challenge limiting maximum efficiency. Summary of the Invention

[0006] Therefore, it is necessary to provide a back-contact solar cell and its fabrication method to solve the problem of leakage current channels forming between the P-region and N-region of a BC cell.

[0007] The first aspect of the present invention is to provide a back-contact solar cell, the solution of which is as follows:

[0008] A back-contact solar cell includes a monocrystalline silicon substrate, a tunneling oxide layer, a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, a first electrode, and a second electrode. The tunneling oxide layer is disposed on one side of the monocrystalline silicon substrate. The first-doped polycrystalline silicon layer, the second-doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer are respectively disposed on the tunneling oxide layer. The intrinsic amorphous silicon layer is disposed between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer. The first electrode is connected to the first-doped polycrystalline silicon layer, and the second electrode is connected to the second-doped polycrystalline silicon layer.

[0009] In one embodiment, the thickness of the tunneling oxide layer is 1 nm to 3 nm.

[0010] In one embodiment, the thickness of the first doped polysilicon layer is 80 nm to 300 nm.

[0011] In one embodiment, the thickness of the second doped polysilicon layer is 80 nm to 300 nm.

[0012] In one embodiment, the thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

[0013] In one embodiment, the back-contact solar cell includes a front passivation antireflection layer disposed on a second side of the monocrystalline silicon substrate.

[0014] In one embodiment, the back-contact solar cell includes a back passivation antireflection layer that covers the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer.

[0015] A second aspect of the present invention is to provide a method for fabricating a back-contact solar cell, the scheme of which is as follows:

[0016] A method for fabricating a back-contact solar cell includes the following steps:

[0017] A tunneling oxide layer is prepared on one side of a single-crystal silicon substrate, and a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer are prepared on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is located between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer.

[0018] A first electrode is fabricated and connected to the first doped type polycrystalline silicon layer;

[0019] A second electrode is prepared and connected to the second type of doped polycrystalline silicon layer.

[0020] In one embodiment, the step of fabricating a tunneling oxide layer on a first side of a single-crystal silicon substrate, and fabricating a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is disposed between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer, includes:

[0021] A first tunneling oxide layer is prepared on a first side of a single-crystal silicon substrate;

[0022] A first intrinsic amorphous silicon layer is prepared on the first tunneling oxide layer;

[0023] Remove the first intrinsic amorphous silicon layer in the first region to expose the first tunneling oxide layer in the first region;

[0024] A first-doped polycrystalline silicon layer is prepared on the first tunneling oxide layer in the first region;

[0025] The first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region are removed, while the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the third region are retained. The third region is located between the first region and the second region.

[0026] A second tunneling oxide layer and a second doped polycrystalline silicon layer are prepared on the single-crystal silicon substrate in the second region.

[0027] In one embodiment, the step of removing the first intrinsic amorphous silicon layer in the first region includes:

[0028] An etching protective film is prepared on the first intrinsic amorphous silicon layer, the etching protective film exposing the first intrinsic amorphous silicon layer in the first region;

[0029] The first intrinsic amorphous silicon layer in the first region is removed by etching.

[0030] In one embodiment, the step of fabricating a first doped polysilicon layer on the first tunneling oxide layer in the first region includes:

[0031] A second intrinsic amorphous silicon layer is prepared on the first tunneling oxide layer in the first region;

[0032] A first doping diffusion process is performed to transform the second intrinsic amorphous silicon layer into a first doped polycrystalline silicon layer, the etching protective film is transformed into a doped protective film, and a first doped oxide layer is formed on the surface of the doped protective film.

[0033] In one embodiment, the step of removing the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region includes:

[0034] Remove the doped protective film and the first doped oxide layer in the second region, and retain the doped protective film and the first doped oxide layer in the third region;

[0035] Under the protection of the first doped oxide layer and the doped protective film, the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region are etched away.

[0036] In one embodiment, the step of fabricating a second tunneling oxide layer and a second doped polycrystalline silicon layer on the single-crystal silicon substrate in the second region includes:

[0037] A second tunneling oxide layer is prepared by deposition on the entire surface of the first side;

[0038] A third intrinsic amorphous silicon layer is prepared on the second tunneling oxide layer;

[0039] A second doping diffusion process is performed to transform the third intrinsic amorphous silicon layer into a second doped polycrystalline silicon layer, and a second doped oxide layer is formed on the surface of the second doped polycrystalline silicon layer.

[0040] Remove the second doped oxide layer on the first and third regions;

[0041] Under the protection of the first doped oxide layer, the doped protective film and the second doped oxide layer, the second tunneling oxide layer and the second doped polysilicon layer on the first region and the third region are etched away.

[0042] Remove the first doped oxide layer, the doped protective film, and the second doped oxide layer in the second region.

[0043] In one embodiment, the thickness of the tunneling oxide layer is 1 nm to 3 nm.

[0044] In one embodiment, the thickness of the first doped polysilicon layer is 80 nm to 300 nm.

[0045] In one embodiment, the thickness of the second doped polysilicon layer is 80 nm to 300 nm.

[0046] In one embodiment, the thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

[0047] In one embodiment, the fabrication method further includes the step of fabricating a front passivation antireflection layer disposed on a second side of the monocrystalline silicon substrate.

[0048] In one embodiment, the fabrication method further includes the step of fabricating a back passivation antireflection layer, wherein the back passivation antireflection layer is integrally covered on the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer.

[0049] Compared with traditional technologies, the above-mentioned back-contact solar cells and their fabrication methods have the following advantages:

[0050] The aforementioned back-contact solar cell and its fabrication method have an intrinsic amorphous silicon layer between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on the back side to prevent the generation of leakage channels. Furthermore, the intrinsic amorphous silicon layer can chemically passivate the monocrystalline silicon substrate, repair interfacial dangling bonds, and eliminate internal recombination centers, thereby improving the cell's conversion efficiency. Attached Figure Description

[0051] Figure 1 is a schematic diagram of the structure of a back-contact solar cell according to an embodiment;

[0052] Figure 2 is a schematic diagram of the fabrication of the first tunneling oxide layer and the first intrinsic amorphous silicon layer on a single-crystal silicon substrate;

[0053] Figure 3 is a schematic diagram of the etching protective film fabricated on the first intrinsic amorphous silicon layer;

[0054] Figure 4 is a schematic diagram of removing the etched protective film on the first region;

[0055] Figure 5 is a schematic diagram of the first doping diffusion process;

[0056] Figure 6 is a schematic diagram of removing the doped protective film and the first doped oxide layer from the second region;

[0057] Figure 7 is a schematic diagram of the removal of the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region;

[0058] Figure 8 is a schematic diagram of the fabrication of the second tunneling oxide layer and the second doped polycrystalline silicon layer;

[0059] Figure 9 is a schematic diagram of the removal of the second doped oxide layer on the first and third regions;

[0060] Figure 10 is a schematic diagram of etching to remove the second tunneling oxide layer and the second doped polysilicon layer on the first and third regions, and removing the first doped oxide layer, the doped protective film, and the second doped oxide layer in the second region.

[0061] Figure 11 is a schematic diagram of the fabrication of the back passivation antireflection layer and the front passivation antireflection layer.

[0062] Explanation of reference numerals in the attached figures: 100, back contact solar cell; 110, monocrystalline silicon substrate; 114, textured surface; 120, tunneling oxide layer; 130, first doped polycrystalline silicon layer; 140, second doped polycrystalline silicon layer; 150, intrinsic amorphous silicon layer; 160, first electrode; 170, second electrode; 180, back passivation antireflection layer; 190, front passivation antireflection layer; 111, first region; 112, second region; 113, third region; 121, first tunneling oxide layer; 150, first intrinsic amorphous silicon layer; 200, etching protective film; 201, doping protective film; 202, first doped oxide layer; 122, second tunneling oxide layer; 142, second doped oxide layer. Detailed Implementation

[0063] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0065] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0067] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0068] As shown in FIG1, a back-contact solar cell 100 according to an embodiment of the present invention includes a monocrystalline silicon substrate 110, a tunneling oxide layer 120, a first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, an intrinsic amorphous silicon layer 150, a first electrode 160, and a second electrode 170.

[0069] A tunneling oxide layer 120 is disposed on one side of a single-crystal silicon substrate 110. A first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, and an intrinsic amorphous silicon layer 150 are disposed on the tunneling oxide layer 120, with the intrinsic amorphous silicon layer 150 disposed between the first-doped polycrystalline silicon layer 130 and the second-doped polycrystalline silicon layer 140.

[0070] The first electrode 160 is connected to the first doped polysilicon layer 130, and the second electrode 170 is connected to the second doped polysilicon layer 140.

[0071] The single-crystal silicon substrate 110 can be either N-type doped or P-type doped.

[0072] The monocrystalline silicon substrate 110 has a first side and a second side disposed opposite to each other. The tunneling oxide layer 120, the first-doped polycrystalline silicon layer 130, the second-doped polycrystalline silicon layer 140, the intrinsic amorphous silicon layer 150, the first electrode 160, and the second electrode 170 are all disposed on the first side of the monocrystalline silicon substrate 110. The second side of the monocrystalline silicon substrate 110 may be configured as a textured surface 114.

[0073] The first side of the monocrystalline silicon substrate 110 includes a first region, a second region, and a third region. The third region is located between the first and second regions. A first-doped polycrystalline silicon layer 130 is disposed in the first region. A second-doped polycrystalline silicon layer 140 is disposed in the second region. An intrinsic amorphous silicon layer 150 is disposed in the third region.

[0074] The material of the tunnel oxide layer 120 can be, but is not limited to, SiO2. x The thickness of the tunneling oxide layer 120 is, for example, 1 to 3 nm, specifically 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, etc.

[0075] The thickness of the first doped polycrystalline silicon layer 130 is, for example, 80nm to 300nm, specifically 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.

[0076] The thickness of the second type of doped polycrystalline silicon layer 140 is, for example, 80nm to 300nm, specifically 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.

[0077] The first doped polysilicon layer 130 and the second doped polysilicon layer 140 have opposite doping types. For example, the first doped polysilicon layer 130 is P-type doped and the second doped polysilicon layer 140 is N-type doped. Alternatively, the first doped polysilicon layer 130 is N-type doped and the second doped polysilicon layer 140 is P-type doped.

[0078] The thickness of the intrinsic amorphous silicon layer 150 is, for example, 80nm to 300nm, specifically 80nm, 100nm, 150nm, 200nm, 250nm, 300nm, etc.

[0079] In some examples, the back-contact solar cell 100 includes a back passivation antireflection layer 180, which is integrally overlaid on a first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, and an intrinsic amorphous silicon layer 150. The material of the back passivation antireflection layer 180 can be, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0080] In some examples, the back-contact solar cell 100 includes a front passivation antireflection layer 190 disposed on a second side of the monocrystalline silicon substrate 110. The material of the front passivation antireflection layer 190 can be, but is not limited to, aluminum oxide, silicon nitride, silicon oxide, silicon oxynitride, etc.

[0081] Optionally, the first electrode 160 and the second electrode 170 may be made of metal materials such as silver or aluminum.

[0082] Furthermore, the present invention also provides a method for preparing a back-contact solar cell 100 according to any of the above examples.

[0083] The aforementioned back-contact solar cell has an intrinsic amorphous silicon layer between the first doped polycrystalline silicon layer and the second doped polycrystalline silicon layer on the back side to prevent the generation of leakage channels. Furthermore, the intrinsic amorphous silicon layer can chemically passivate the monocrystalline silicon substrate, repair interface dangling bonds, and eliminate internal recombination centers, thereby improving the cell's conversion efficiency.

[0084] One embodiment of the method for fabricating a back-contact solar cell 100 includes the following steps:

[0085] In step S10, a tunneling oxide layer 120 is prepared on the first side of the single-crystal silicon substrate 110, and a first-doped polycrystalline silicon layer 130, a second-doped polycrystalline silicon layer 140, and an intrinsic amorphous silicon layer 150 are prepared on the tunneling oxide layer 120, wherein the intrinsic amorphous silicon layer 150 is located between the first-doped polycrystalline silicon layer 130 and the second-doped polycrystalline silicon layer 140.

[0086] Step S20: Prepare a first electrode 160 connected to the first doped polycrystalline silicon layer 130.

[0087] Step S30: Prepare a second electrode 170 connected to the second doped polycrystalline silicon layer 140.

[0088] Before fabricating the tunneling oxide layer 120 on the monocrystalline silicon substrate 110, it is preferable to perform chemical polishing on the monocrystalline silicon substrate 110 to remove impurity ions such as metal ions. The processing solution may be at least one of NH4OH solution, NaOH solution, or KOH solution. The temperature of the processing solution is above 60°C.

[0089] In some of these examples, step S10 includes:

[0090] Step S11, as shown in Figure 2, involves preparing a first tunneling oxide layer 121 on the first side of a single-crystal silicon substrate 110.

[0091] Optionally, the preparation method of the first tunneling oxide layer 121 can be, but is not limited to, high-temperature oxidation, nitric acid oxidation, ozone oxidation, etc.

[0092] Step S12, as shown in Figure 2, involves preparing a first intrinsic amorphous silicon layer 150 on the first tunneling oxide layer 121.

[0093] Optionally, the preparation method of the first intrinsic amorphous silicon layer 150 can be, but is not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, hot filamentation vapor deposition, physical vapor deposition, etc.

[0094] Step S13: Remove the first intrinsic amorphous silicon layer 150 of the first region 111 to expose the first tunneling oxide layer 121 of the first region 111.

[0095] In some of these examples, step S13 includes:

[0096] Step S131, as shown in Figures 3 and 4, involves preparing an etch protection film 200 on the first intrinsic amorphous silicon layer 150, with the etch protection film 200 exposing the first intrinsic amorphous silicon layer 150 in the first region 111.

[0097] Optionally, the etched protective film 200 can be, but is not limited to, silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiO) x N y The thickness of the etched protective film 200 is, for example, 10 nm to 100 nm.

[0098] Optionally, the etching protective film 200 can be prepared by, but is not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, physical vapor deposition, etc.

[0099] As shown in Figure 4, the etched protective film 200 can be partially removed from the first region 111 by deposition over the entire surface followed by laser processing. For example, a laser with a wavelength of 355 nm and a working power of 50 W is used for laser processing. The width of the laser-processed region is, for example, 300 μm to 500 μm.

[0100] Step S132: Etch away the first intrinsic amorphous silicon layer 150 of the first region 111.

[0101] The etching solution used for etching may contain alkali, additives, and water. Alkali examples include NaOH and KOH.

[0102] Step S14: Prepare a first doped polysilicon layer 130 on the first tunneling oxide layer 121 in the first region 111.

[0103] In some of these examples, step S14 includes:

[0104] Step S141: Prepare a second intrinsic amorphous silicon layer 150 on the first tunneling oxide layer 121 of the first region 111.

[0105] Step S142, as shown in Figure 5, involves performing a first doping diffusion process to transform the second intrinsic amorphous silicon layer 150 into a first doped polycrystalline silicon layer 130, to transform the etched protective film 200 into a doped protective film 201, and to form a first doped oxide layer 202 on the surface of the doped protective film 201.

[0106] The first doping diffusion process is, for example, a boron diffusion process. The etched protective film 200 is also doped with boron atoms, becoming borosilicate glass (BSG), i.e., the doped protective film 201, which effectively blocks the diffusion of boron atoms to the first intrinsic amorphous silicon layer 150, and forms boron-rich silicon oxide on the surface of the doped protective film 201, i.e., the first doped oxide layer 202. The thickness of the first doped oxide layer 202 is 10 nm to 100 nm.

[0107] The doping concentration of the first type of polycrystalline silicon layer 130 is approximately 3 × 10⁻⁶. 20 cm -3 .

[0108] Step S15: Remove the first tunneling oxide layer 121 and the first intrinsic amorphous silicon layer 150 from the second region 112, and retain the first tunneling oxide layer 121 and the first intrinsic amorphous silicon layer 150 in the third region 113. The third region 113 is located between the first region 111 and the second region 112.

[0109] In some of these examples, step S15 includes:

[0110] Step S151, as shown in Figure 6, remove the doped protective film 201 and the first doped oxide layer 202 of the second region 112, and retain the doped protective film 201 and the first doped oxide layer 202 of the third region 113.

[0111] In step S152, as shown in Figure 7, under the protection of the first doped oxide layer 202 and the doped protective film 201, the first tunneling oxide layer 121 and the first intrinsic amorphous silicon layer 150 of the second region 112 are etched away.

[0112] The method for removing the doped protective film 201 and the first doped oxide layer 202 of the second region 112 is, for example, laser processing. The laser processing may employ, for example, a laser with a wavelength of 532 nm and a working power of 30 W. The width of the laser-processed region is, for example, 150 μm to 350 μm.

[0113] The etching solution used to etch away the first tunneling oxide layer 121 and the first intrinsic amorphous silicon layer 150 in the second region 112 may contain, for example, an alkali, additives, and water. The alkali may be, for example, NaOH, KOH, etc.

[0114] Step S16, as shown in Figure 8, involves preparing a second tunneling oxide layer 122 and a second doped polycrystalline silicon layer 140 on a single-crystal silicon substrate 110 in the second region 112.

[0115] In some of these examples, step S16 includes:

[0116] Step S161: Deposit the second tunneling oxide layer 122 on the entire surface of the first side.

[0117] Optionally, the preparation method of the second tunneling oxide layer 122 can be, but is not limited to, high-temperature oxidation, nitric acid oxidation, ozone oxidation, etc.

[0118] Step S162: Prepare a third intrinsic amorphous silicon layer 150 on the second tunneling oxide layer 122.

[0119] Optionally, the preparation method of the first intrinsic amorphous silicon layer 150 can be, but is not limited to, low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, hot filamentation vapor deposition, physical vapor deposition, etc.

[0120] Step S163: Perform a second doping diffusion process to transform the third intrinsic amorphous silicon layer 150 into a second doped polycrystalline silicon layer 140, and form a second doped oxide layer 142 on the surface of the second doped polycrystalline silicon layer 140.

[0121] The second doping diffusion process is, for example, a phosphorus diffusion process. A phosphorus-rich silicon oxide (PSG) layer, i.e., a second doped oxide layer 142, is formed on the surface of the polysilicon layer 140 of the second doping type. The thickness of the second doped oxide layer 142 is 10 nm to 40 nm.

[0122] The doping concentration of the second type of polycrystalline silicon layer 140 is approximately 3 × 10⁻⁶. 21 cm -3 .

[0123] Step S164, as shown in Figure 9, remove the second doped oxide layer 142 on the first region 111 and the third region 113.

[0124] The method for removing the second doped oxide layer 142 from the first region 111 is, for example, laser processing. The laser processing may employ, for example, a laser with a wavelength of 532 nm and an operating power of 30 W. The width of the laser-processed region is, for example, 100 μm to 300 μm.

[0125] In step S165, as shown in FIG10, under the protection of the first doped oxide layer 202, the doped protective film 201 and the second doped oxide layer 142, the second tunneling oxide layer 122 and the second doped polysilicon layer 140 on the first region 111 and the third region 113 are etched away.

[0126] The etching solution may contain, for example, alkali, additives, and water. Alkali examples include NaOH and KOH. The processing temperature is above 70°C, and the process time is 200–500 s. While etching away the second tunneling oxide layer 122 and the second doped polysilicon layer 140 on the first region 111 and the third region 113, a pyramidal textured surface 114 is formed on the second side of the single-crystal silicon substrate 110.

[0127] Step S166, as shown in Figure 10, remove the first doped oxide layer 202, the doped protective film 201, and the second doped oxide layer 142 of the second region 112.

[0128] The first doped oxide layer 202, the doped protective film 201, and the second doped oxide layer 142 of the second region 112 can be removed by cleaning with a 2wt% HF solution.

[0129] In some examples, as shown in Figure 11, the method for fabricating a back contact solar cell 100 further includes the step of fabricating a back passivation antireflection layer 180, which is integrally covered on a first doped polycrystalline silicon layer 130, a second doped polycrystalline silicon layer 140, and an intrinsic amorphous silicon layer 150.

[0130] In some examples, as shown in Figure 11, the fabrication method of the back contact solar cell 100 further includes the step of fabricating a front passivation antireflection layer 190, which is disposed on the second side of the monocrystalline silicon substrate 110.

[0131] In some examples, an aluminum oxide layer with a thickness of approximately 3 nm to 10 nm is deposited on both the front and back sides of the battery. Atomic-layer passivation film deposition can be achieved using one of PEALD, ALD, or PVD, and trimethylaluminum and H₂O or trimethylaluminum and O₃ can be used as the reaction gas. Then, a passivation antireflection film with a thickness of 70 nm to 110 nm and a refractive index of 2.0% to 2.4% is deposited on both the front and back sides of the battery. This passivation antireflection film can be at least one of silicon nitride, silicon oxide, or silicon oxynitride.

[0132] In steps S20 and S30, the first electrode 160 and the second electrode 170 can be printed with silver paste, aluminum paste, etc. using a printing process, and then sintered at 700℃~900℃ to achieve metallization.

[0133] The aforementioned method for fabricating back-contact solar cells involves depositing a specific film layer under a particular process, followed by selective ion diffusion for doping to prepare the emitter. This process can lead to unlocalized ion diffusion, and if a second type of emitter is then fabricated, leakage channels can form. By using laser selective processing and chemical etching to form an intrinsic amorphous silicon layer between the first and second doped polycrystalline silicon layers, leakage channels can be prevented. Furthermore, the intrinsic amorphous silicon layer can chemically passivate the monocrystalline silicon substrate, repair interfacial dangling bonds, and eliminate internal recombination centers, thereby improving the cell's conversion efficiency.

[0134] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims, and the specification can be used to interpret the content of the claims.

Claims

1. A back-contact solar cell, characterized in that, The device includes a monocrystalline silicon substrate, a tunneling oxide layer, a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, an intrinsic amorphous silicon layer, a first electrode, and a second electrode. The tunneling oxide layer is disposed on a first side of the monocrystalline silicon substrate. The first-doped polycrystalline silicon layer, the second-doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer are respectively disposed on the tunneling oxide layer. The intrinsic amorphous silicon layer is disposed between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer. The first electrode is connected to the first-doped polycrystalline silicon layer, and the second electrode is connected to the second-doped polycrystalline silicon layer.

2. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the tunneling oxide layer is 1 nm to 3 nm.

3. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the first doped polycrystalline silicon layer is 80 nm to 300 nm.

4. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the second type of doped polycrystalline silicon layer is 80nm to 300nm.

5. The back-contact solar cell as described in claim 1, characterized in that, The thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

6. The back-contact solar cell as described in claim 1, characterized in that, The back-contact solar cell includes a front passivation antireflection layer disposed on the second side of the monocrystalline silicon substrate.

7. The back-contact solar cell according to any one of claims 1 to 6, characterized in that, The back-contact solar cell includes a back passivation antireflection layer, which covers the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer.

8. A method for fabricating a back-contact solar cell, characterized in that, Includes the following steps: A tunneling oxide layer is prepared on a first side of a single-crystal silicon substrate, and a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer are prepared on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is located between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer. A first electrode is fabricated and connected to the first doped type polycrystalline silicon layer; A second electrode is prepared and connected to the second type of doped polycrystalline silicon layer.

9. The preparation method according to claim 8, characterized in that, The step of preparing a tunneling oxide layer on a first side of a single-crystal silicon substrate, and preparing a first-doped polycrystalline silicon layer, a second-doped polycrystalline silicon layer, and an intrinsic amorphous silicon layer on the tunneling oxide layer, wherein the intrinsic amorphous silicon layer is located between the first-doped polycrystalline silicon layer and the second-doped polycrystalline silicon layer, includes: A first tunneling oxide layer is prepared on a first side of a single-crystal silicon substrate; A first intrinsic amorphous silicon layer is prepared on the first tunneling oxide layer; Remove the first intrinsic amorphous silicon layer in the first region to expose the first tunneling oxide layer in the first region; A first-doped polycrystalline silicon layer is prepared on the first tunneling oxide layer in the first region; The first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region are removed, while the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the third region are retained. The third region is located between the first region and the second region. A second tunneling oxide layer and a second doped polycrystalline silicon layer are prepared on the single-crystal silicon substrate in the second region.

10. The preparation method according to claim 9, characterized in that, The step of removing the first intrinsic amorphous silicon layer in the first region includes: An etching protective film is prepared on the first intrinsic amorphous silicon layer, the etching protective film exposing the first intrinsic amorphous silicon layer in the first region; The first intrinsic amorphous silicon layer in the first region is removed by etching.

11. The preparation method according to claim 10, characterized in that, The step of preparing a first doped polycrystalline silicon layer on the first tunneling oxide layer in the first region includes: A second intrinsic amorphous silicon layer is prepared on the first tunneling oxide layer in the first region; A first doping diffusion process is performed to transform the second intrinsic amorphous silicon layer into a first doped polycrystalline silicon layer, the etching protective film is transformed into a doped protective film, and a first doped oxide layer is formed on the surface of the doped protective film.

12. The preparation method according to claim 11, characterized in that, The step of removing the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region includes: Remove the doped protective film and the first doped oxide layer in the second region, and retain the doped protective film and the first doped oxide layer in the third region; Under the protection of the first doped oxide layer and the doped protective film, the first tunneling oxide layer and the first intrinsic amorphous silicon layer in the second region are etched away.

13. The preparation method according to claim 12, characterized in that, The step of fabricating the second tunneling oxide layer and the second doped polycrystalline silicon layer on the single-crystal silicon substrate in the second region includes: A second tunneling oxide layer is prepared by deposition on the entire surface of the first side; A third intrinsic amorphous silicon layer is prepared on the second tunneling oxide layer; A second doping diffusion process is performed to transform the third intrinsic amorphous silicon layer into a second doped polycrystalline silicon layer, and a second doped oxide layer is formed on the surface of the second doped polycrystalline silicon layer. Remove the second doped oxide layer on the first and third regions; Under the protection of the first doped oxide layer, the doped protective film and the second doped oxide layer, the second tunneling oxide layer and the second doped polysilicon layer on the first region and the third region are etched away. Remove the first doped oxide layer, the doped protective film, and the second doped oxide layer in the second region.

14. The preparation method according to any one of claims 8 to 13, characterized in that, The thickness of the tunneling oxide layer is 1 nm to 3 nm.

15. The preparation method according to any one of claims 8 to 13, characterized in that, The thickness of the first doped polycrystalline silicon layer is 80 nm to 300 nm.

16. The preparation method according to any one of claims 8 to 13, characterized in that, The thickness of the second type of doped polycrystalline silicon layer is 80nm to 300nm.

17. The preparation method according to any one of claims 8 to 13, characterized in that, The thickness of the intrinsic amorphous silicon layer is 80 nm to 300 nm.

18. The preparation method according to any one of claims 8 to 13, characterized in that, The preparation method further includes the step of preparing a front passivation antireflection layer, wherein the front passivation antireflection layer is disposed on the second side of the monocrystalline silicon substrate.

19. The preparation method according to any one of claims 8 to 13, characterized in that, The preparation method further includes the step of preparing a back passivation antireflection layer, wherein the back passivation antireflection layer is entirely covered on the first doped polycrystalline silicon layer, the second doped polycrystalline silicon layer, and the intrinsic amorphous silicon layer.

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