Solar cell and preparation method therefor

Abstract

Disclosed in the present application is a preparation method for a solar cell. The method comprises: providing a silicon substrate, wherein the silicon substrate has a first surface and a second surface, the first surface and the second surface being opposite each other; forming a tunnel oxide layer on the first surface of the silicon substrate; forming a first-conductivity-type semiconductor layer on the tunnel oxide layer; forming a first transparent conductive layer on the first-conductivity-type semiconductor layer; forming a first metal electrode layer on the first transparent conductive layer, and forming an ohmic contact between a first metal electrode in the first metal electrode layer and the first transparent conductive layer; forming an intrinsic passivation layer on the second surface of the silicon substrate; forming a second-conductivity-type semiconductor layer on the intrinsic passivation layer; forming a second transparent conductive layer on the second-conductivity-type semiconductor layer; and forming a second metal electrode layer on the second transparent conductive layer, and forming an ohmic contact between a second metal electrode in the second metal electrode layer and the second transparent conductive layer. Further disclosed in the present application is a solar cell.

Description

Solar cell and method for manufacturing the same

[0001] Cross-reference to related applications

[0002] The present application claims priority to the Chinese patent application with the application number 2024115273734, the application date of October 30, 2024, and the invention title of "Solar cell and method for manufacturing the same". TECHNICAL FIELD

[0003] The present application relates to the technical field of solar cells, in particular to a solar cell and a method for manufacturing the same. BACKGROUND

[0004] In the process of manufacturing a solar cell, factors such as dopants, process impurities, and crystal defects of the film layer can cause abnormal recombination of carriers such as electrons and holes in various forms, thereby seriously reducing the power generation efficiency of the solar cell. At present, one of the important means to reduce carrier recombination is to set a passivation contact film layer structure to achieve interface passivation.

[0005] However, for different types of solar cells, the structure setting method, film layer material, and preparation means of the passivation contact film layer are significantly different and cannot be directly converted for use. For example, the tunnel oxide passivated contact solar cell (TOPCon) requires materials and equipment that can withstand high temperatures to prepare the passivation film, while the heterojunction solar cell (HJT) requires materials and equipment that can withstand lower temperatures to prepare the passivation film.

[0006] How to provide a new structure of photovoltaic cell can make full use of the mature structure and manufacturing production line of existing photovoltaic cells, improve and improve the passivation contact effect, and also reasonably control the preparation cost, which has a positive significance for further improving the market competitiveness of photovoltaic cells. SUMMARY

[0007] The present application aims to solve one of the technical problems in the related art to some extent. To this end, the present application provides a solar cell and a method for manufacturing the same.

[0008] In order to achieve the above-mentioned purpose, the present application provides a method for manufacturing a solar cell, wherein the method comprises:

[0009] providing a silicon substrate, the silicon substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other;

[0010] A tunneling oxide layer is formed on the first surface of the silicon substrate;

[0011] A first conductivity type semiconductor layer is formed on the tunneling oxide layer, wherein the first conductivity type is selected from p-type and n-type.

[0012] A first transparent conductive layer is formed on the first conductivity type semiconductor layer;

[0013] A first metal electrode layer is formed on the first transparent conductive layer, and an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer.

[0014] An intrinsic passivation layer is formed on the second surface of the silicon substrate;

[0015] A second conductivity type semiconductor layer is formed on the intrinsic passivation layer, wherein the second conductivity type is selected from p-type and n-type.

[0016] A second transparent conductive layer is formed on the second conductivity type semiconductor layer;

[0017] A second metal electrode layer is formed on the second transparent conductive layer, and an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer.

[0018] Optionally, a tunneling oxide layer is formed on the first surface of the silicon substrate, comprising:

[0019] An initial tunneling oxide layer is formed on the first surface of the silicon substrate;

[0020] The initial tunneling oxide layer is annealed to obtain the tunneling oxide layer; the thickness of the tunneling oxide layer includes 1 nm to 5 nm.

[0021] Optionally, the process temperature for forming the initial tunneling oxide layer on the first surface of the silicon substrate includes 200°C to 1050°C, and the initial tunneling oxide layer is formed using any one of the following processes:

[0022] Atomic layer deposition process, thermal oxidation process, plasma-enhanced chemical vapor deposition process, low-pressure chemical vapor deposition and low-temperature wet oxidation process.

[0023] Optionally, the annealing temperature for annealing the initial tunneling oxide layer includes 200°C to 800°C.

[0024] Optionally, the first conductivity type semiconductor layer is an n-type semiconductor layer.

[0025] Optionally, a first conductivity type semiconductor layer is formed on the tunneling oxide layer, comprising:

[0026] Phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into a silicon thin film using a predefined deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer. The predefined deposition process is selected from any one of tubular plasma-enhanced chemical vapor deposition, plate-type plasma-enhanced chemical vapor deposition, and low-pressure chemical vapor deposition.

[0027] The n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductivity type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes 10 nm to 60 nm; wherein the process temperature of the set deposition process includes 200 °C to 800 °C.

[0028] Optionally, a first conductivity type semiconductor layer is formed on the tunneling oxide layer, comprising:

[0029] Phosphorus, hydrogen and oxygen atoms are doped into silicon thin films using a low-temperature atomic layer deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer.

[0030] The n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductivity type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes 10 nm to 60 nm; wherein the process temperature of the low-temperature atomic layer deposition process includes 100 °C to 300 °C.

[0031] Optionally, an intrinsic passivation layer is formed on the second surface of the silicon substrate, comprising:

[0032] The intrinsic passivation layer is obtained by depositing a silicon thin film using a first-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously incorporating hydrogen atoms; wherein the process temperature of the first-type plate-type plasma-enhanced chemical vapor deposition process includes 150°C to 200°C; and the thickness of the intrinsic passivation layer includes 1 nm to 5 nm.

[0033] Optionally, a second conductivity type semiconductor layer is formed on the intrinsic passivation layer, including:

[0034] A second type of conductive semiconductor layer is obtained by depositing a silicon thin film using a second-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously doping it with boron, hydrogen, and oxygen atoms. The process temperature of the second-type plate-type plasma-enhanced chemical vapor deposition process ranges from 100°C to 200°C, and the thickness of the second conductive semiconductor layer ranges from 5 nm to 30 nm.

[0035] Optionally, a first metal electrode layer is formed on the first transparent conductive layer, comprising:

[0036] A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste;

[0037] An initial first metal electrode layer is formed on the first transparent conductive layer using a printing process;

[0038] A sintering and curing process is performed on the initial first metal electrode layer to form the first metal electrode layer including the first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein, the process temperature of the sintering and curing process includes 100°C to 200°C; and the mass percentage of copper in the silver-copper paste includes (0% to 80%).

[0039] Optionally, a first metal electrode layer is formed on the first transparent conductive layer, comprising:

[0040] A first copper seed layer is formed on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact;

[0041] A first patterned mask layer is formed on the first copper seed layer, the first patterned mask layer having a first opening pattern, the first opening pattern matching the first metal electrode layer;

[0042] A copper material layer is formed that partially fills the pattern of the first opening.

[0043] A silver material layer is formed that covers the copper material layer and fills the first opening pattern;

[0044] Remove the first patterned mask layer and the first copper seed layer not covered by the copper material layer; the remaining first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

[0045] Optionally, a second metal electrode layer is formed on the second transparent conductive layer, comprising:

[0046] A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste;

[0047] An initial second metal electrode layer is formed on the second transparent conductive layer using a printing process;

[0048] A sintering and curing process is performed on the initial second metal electrode layer to form a second metal electrode layer including a second metal electrode, such that the second metal electrode portion penetrates below the surface of the second transparent conductive layer to form an ohmic contact; wherein, in the silver-copper paste, the mass percentage of copper includes (0%, 80%); the process temperature of the sintering and curing process includes 100°C to 200°C.

[0049] Optionally, a second metal electrode layer is formed on the second transparent conductive layer, comprising:

[0050] A second copper seed layer is formed on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact;

[0051] A second patterned mask layer is formed on the second copper seed layer, the second patterned mask layer having a second opening pattern that matches the second metal electrode layer;

[0052] A copper material layer is formed that partially fills the second opening pattern;

[0053] A silver material layer is formed that covers the copper material layer and fills the second opening pattern;

[0054] Remove the second patterned mask layer and the second copper seed layer not covered by the copper material layer; the remaining second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

[0055] As a second aspect of this application, a solar cell is provided, the solar cell comprising a silicon substrate having opposing first and second surfaces; wherein, it further comprises:

[0056] A first film layer structure is disposed on the first surface side of the silicon substrate; the first film layer structure includes a tunneling oxide layer, a first conductivity type semiconductor layer, a first transparent conductive layer, and a first metal electrode layer;

[0057] A second film layer structure is disposed on the second surface side of the silicon substrate. The second film layer structure includes an intrinsic passivation layer, a second conductivity type semiconductor layer, a second transparent conductive layer, and a second metal electrode layer.

[0058] The tunneling oxide layer is disposed above the first surface, the first conductive semiconductor layer is disposed above the surface of the tunneling oxide layer opposite to the silicon substrate, the first transparent conductive layer is disposed above the surface of the first conductive semiconductor layer opposite to the silicon substrate, and the first metal electrode layer is disposed above the surface of the first transparent conductive layer opposite to the first conductive semiconductor layer; an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer.

[0059] The intrinsic passivation layer is disposed below the second surface, the second conductivity type semiconductor layer is disposed on the side of the intrinsic passivation layer away from the second surface, the second transparent conductive layer is disposed on the side of the second conductivity type semiconductor layer away from the intrinsic passivation layer, and the second metal electrode layer is disposed above the surface of the second transparent conductive layer away from the second conductivity type semiconductor layer; an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer; the first conductivity type is selected from p-type and n-type, and the second conductivity type is selected from the other p-type and n-type.

[0060] Optionally, the silicon substrate includes an n-type silicon substrate; the first conductivity type semiconductor layer includes an n-type oxygen-containing polycrystalline silicon layer; and the thickness of the first conductivity type semiconductor layer includes 10 nm to 60 nm.

[0061] Optionally, the material of the first metal electrode forming the first metal electrode layer includes at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste.

[0062] Optionally, the material of the second metal electrode forming the second metal electrode layer includes at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste.

[0063] Optionally, the material of the tunneling oxide layer includes silicon dioxide, and the thickness of the tunneling oxide layer includes 1 nm to 5 nm.

[0064] Optionally, the first surface is the light-incident surface of the solar cell, and the second surface is the back-light surface of the solar cell; or,

[0065] The first surface is the back surface of the solar cell, and the second surface is the light-incident surface of the solar cell.

[0066] Optionally, the second conductivity type semiconductor layer includes a p-type amorphous silicon layer, and the intrinsic passivation layer includes an intrinsic silicon layer; the thickness of the second conductivity type semiconductor layer includes 5 nm to 30 nm.

[0067] In the solar cell provided in this application embodiment, a tunneling oxide layer forms a passivation contact structure with a first conductivity type semiconductor layer. The tunneling oxide layer reduces the interface state density between the silicon substrate and the first conductivity type semiconductor layer through chemical passivation. A high concentration of majority carriers (majority carriers) passes through in the form of quantum tunneling and blocks minority carriers (minority carriers), reducing the probability of electron-hole recombination while increasing conductivity, thus forming a selective contact for majority carriers. Therefore, the passivation contact structure formed by the tunneling oxide layer and the first conductivity type semiconductor layer enables the solar cell to have good passivation capability and further improves the electrical performance of the solar cell (e.g., better open-circuit voltage and fill factor).

[0068] In fabricating the first film layer structure of the solar cell, a first transparent conductive layer is formed first, followed by a first metal electrode layer. The first transparent conductive layer possesses superior carrier transport performance, thus requiring only the surface of the first transparent conductive layer to be burned through to achieve good ohmic contact between the first metal electrode and the first transparent conductive layer. This eliminates the need, as in related technologies, to use higher sintering temperatures to burn through all the film layers on the silicon substrate to achieve direct electrical contact between the metal electrode and the silicon substrate. Correspondingly, the process method provided in this application results in a lower degree of oxidation of the conductive paste used to form the first metal electrode layer, leading to a lower resistivity for the first metal electrode and thus improving the power generation efficiency of the solar cell. Furthermore, due to the lower temperature in this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can be used, further reducing the fabrication cost of the solar cell.

[0069] Similarly, in fabricating the second film layer structure of the solar cell, a second transparent conductive layer is formed first, followed by a second metal electrode layer. Likewise, the second transparent conductive layer possesses superior carrier transport properties, thus requiring only the surface of the second transparent conductive layer to be burned through to achieve good ohmic contact between the second metal electrode and the second transparent conductive layer in the second metal electrode layer. This eliminates the need, as in related technologies, to use higher sintering temperatures to burn through all the film layers on the silicon substrate to achieve direct electrical contact between the metal electrode and the silicon substrate. Correspondingly, the process method provided in this application results in a lower degree of oxidation of the conductive paste used to form the second metal electrode layer, leading to a lower resistivity of the second metal electrode in the final second metal electrode layer and ultimately improving the power generation efficiency of the solar cell. Furthermore, due to the lower temperature in this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can be used, further reducing the fabrication cost of the solar cell.

[0070] These features and advantages of this application will be disclosed in detail in the following specific embodiments and accompanying drawings. The best embodiments or means of this application will be shown in detail in conjunction with the accompanying drawings, but are not intended to limit the technical solutions of this application. In addition, each of these features, elements and components appearing in the following text and drawings is multiple and is labeled with different symbols or numbers for convenience, but all represent parts with the same or similar structure or function. Attached Figure Description

[0071] The following description, in conjunction with the accompanying drawings, further illustrates this application:

[0072] Figure 1 is a flowchart of one embodiment of the preparation method provided in this application;

[0073] Figure 2 is a flowchart of one embodiment of step S120;

[0074] Figure 3 is a flowchart of one embodiment of step S130;

[0075] Figure 4 is a flowchart of another implementation of step S130;

[0076] Figure 5 is a flowchart of one implementation of step S150;

[0077] Figure 6 is a flowchart of another implementation of step S150;

[0078] Figure 7 is a flowchart of one implementation of step S190;

[0079] Figure 8 is a flowchart of another implementation of step S190;

[0080] Figure 9 is a structural schematic diagram of one embodiment of the solar cell provided in this application.

[0081] Explanation of reference numerals: 100: First film layer structure; 110: Passivation layer; 120: First conductivity type semiconductor layer; 130: First transparent conductive layer; 140: First metal electrode layer; 141: First metal electrode; 200: Second film layer structure; 210: Intrinsic passivation layer; 220: Second conductivity type semiconductor layer; 230: Second transparent conductive layer; 240: Second metal electrode layer; 241: Second metal electrode; 300: Silicon substrate. Detailed Implementation

[0082] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described are intended to explain this application and should not be construed as limiting it.

[0083] The terms "an embodiment," "example," or "trademark" used in this specification refer to a particular feature, structure, or characteristic described in connection with the embodiment itself that may be included in at least one embodiment disclosed in this patent. The phrase "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment.

[0084] As a first aspect of this application, a method for preparing a solar cell is provided, wherein, as shown in FIG1, the preparation method includes:

[0085] In step S110, a silicon substrate is provided, the silicon substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other;

[0086] In step S120, a tunneling oxide layer is formed on the first surface of the silicon substrate;

[0087] In step S130, a first conductivity type semiconductor layer is formed on the tunneling oxide layer, wherein the first conductivity type is selected from p-type and n-type.

[0088] In step S140, a first transparent conductive layer is formed on the first conductivity type semiconductor layer;

[0089] In step S150, a first metal electrode layer is formed on the first transparent conductive layer, and an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer.

[0090] In step S160, an intrinsic passivation layer is formed on the second surface of the silicon substrate;

[0091] In step S170, a second conductivity type semiconductor layer is formed on the intrinsic passivation layer, wherein the second conductivity type is selected from p-type and n-type.

[0092] In step S180, a second transparent conductive layer is formed on the second conductivity type semiconductor layer;

[0093] In step S190, a second metal electrode layer is formed on the second transparent conductive layer, and an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer.

[0094] In the solar cell prepared according to the embodiments of this application, a tunneling oxide layer forms a passivation contact structure with a first conductivity type semiconductor layer. The tunneling oxide layer reduces the interface state density between the silicon substrate and the first conductivity type semiconductor layer through chemical passivation. A high concentration of majority carriers (majority carriers) passes through in the form of quantum tunneling and blocks minority carriers (minority carriers), reducing the probability of electron-hole recombination while increasing resistivity, thus forming a selective contact for majority carriers. Therefore, the passivation contact structure formed by the tunneling oxide layer and the first conductivity type semiconductor layer enables the solar cell to have good passivation capability.

[0095] For ease of description, the film structure located on one side of the first surface of the silicon substrate is referred to as the "first film layer group structure," and the film structure located on one side of the second surface of the silicon substrate is referred to as the "second film layer group structure." It should be noted that the above designations of "first film layer group structure" and "second film layer group structure" are merely for ease of description in the specification and do not constitute a classification of the related film layers' functional implementation, fabrication sequence, or fabrication process. For example, the first film layer group structure can be formed first, followed by the second film layer group structure, or vice versa; alternatively, individual films in the first film layer group structure and individual films in the second film layer group structure can be fabricated simultaneously using the same fabrication process.

[0096] In fabricating the first film layer structure of the solar cell, a first transparent conductive layer is formed first, followed by a first metal electrode layer. The first transparent conductive layer possesses superior carrier transport performance, allowing for good ohmic contact between the first metal electrode and the first transparent conductive layer simply by burning through its surface. This eliminates the need for higher sintering temperatures, as in related technologies, to burn through all the film layers on the silicon substrate to achieve direct electrical contact between the metal electrode and the silicon substrate. This means that the process temperature in step S150 is lower, resulting in less oxidation of the conductive paste forming the first metal electrode layer. Consequently, the first metal electrode of the final first metal electrode layer has a lower resistivity, thereby improving the power generation efficiency of the solar cell. Furthermore, due to the lower temperature in this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can be used, further reducing the fabrication cost of the solar cell.

[0097] Similarly, in fabricating the second film layer structure of the solar cell, a second transparent conductive layer is formed first, followed by a second metal electrode layer. Likewise, the second transparent conductive layer possesses superior carrier transport performance, thus requiring only the surface of the second transparent conductive layer to be burned through to achieve good ohmic contact between the second metal electrode and the second transparent conductive layer in the second metal electrode layer. This eliminates the need, as in related technologies, to use higher sintering temperatures to burn through all the film layers on the silicon substrate to achieve direct electrical contact between the metal electrode and the silicon substrate. This means that the process temperature in step S190 is lower, and correspondingly, the degree of oxidation caused by the conductive paste forming the second metal electrode layer during the process is also lower. Consequently, the second metal electrode of the final second metal electrode layer has a lower resistivity, ultimately improving the power generation efficiency of the solar cell. Furthermore, due to the lower temperature in this step, relatively low-cost electrode materials such as low-temperature silver-copper paste can be used, further reducing the fabrication cost of the solar cell.

[0098] In the embodiments of this application, the specific structure of the silicon substrate is not specifically limited. For example, at least one of the first surface and the second surface of the silicon substrate may have a textured structure. That is, in the step of providing the silicon substrate, the silicon substrate may be textured on one side or both sides.

[0099] In this embodiment, the tunneling oxide layer is a silicon dioxide layer (i.e., SiO2). As an optional implementation, as shown in FIG2, a tunneling oxide layer is formed on the first surface of the silicon substrate, comprising:

[0100] In step S121, an initial tunneling oxide layer is formed on the first surface of the silicon substrate;

[0101] In step S122, the initial tunneling oxide layer is annealed to obtain the tunneling oxide layer.

[0102] Optionally, the thickness of the tunneling oxide layer includes 1 nm to 5 nm.

[0103] It should be noted that the initial tunneling oxide layer is also made of silicon dioxide. In this embodiment, no special limitation is made on how the initial tunneling oxide layer is formed on the first surface of the silicon substrate. For example, the initial tunneling oxide layer can be formed on the surface of the silicon substrate using chemical vapor deposition. The annealing process in step S121b can increase the thickness of the final tunneling oxide layer. Furthermore, annealing the initial tunneling oxide layer can, to some extent, remove getter elements (e.g., remove iron), resulting in a higher purity and a denser, more uniform structure in the final tunneling oxide layer.

[0104] As an optional implementation, the process temperature for forming the initial tunneling oxide layer on the first surface of the silicon substrate is between 200°C and 1050°C, and the initial tunneling oxide layer can be formed using any of the following processes:

[0105] Atomic Layer Deposition (ALD) process, thermal oxidation process, Plasma Enhanced Chemical Vapor Deposition (PECVD) process, Low Pressure Chemical Vapor Deposition (LPCVD) process, and low temperature wet oxidation process.

[0106] In this embodiment of the application, the duration of step S121a is not specifically limited, as long as an initial tunneling oxide layer with a thickness between 1 nm and 5 nm can be obtained.

[0107] In the embodiment of preparing the initial tunneling oxide layer using plasma-enhanced chemical vapor deposition, the grain size of the tunneling oxide layer obtained by annealing the initial tunneling oxide layer is at the micrometer level. The larger size results in better light transmission of the tunneling oxide layer, thereby improving the short-wavelength response of the solar cell and thus enhancing the light utilization efficiency of the solar cell.

[0108] In step S122, there are no special requirements for the annealing temperature, as long as the obtained tunneling oxide layer has a uniform thickness and uniform structure. Optionally, the annealing temperature for annealing the initial tunneling oxide layer is between 200°C and 800°C.

[0109] As mentioned above, since the first conductivity type is selected from either n-type or p-type, as an optional implementation, the first conductivity type semiconductor layer is an n-type semiconductor layer. Furthermore, this application also improves the fabrication process of the first conductivity type semiconductor layer to enhance its light transmittance, thereby ensuring and improving the power generation efficiency of the solar cell. For example, as shown in FIG3, forming the first conductivity type semiconductor layer on the tunneling oxide layer includes:

[0110] In step S131, phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into a silicon thin film while depositing it using a set deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer. The set deposition process is selected from any one of tubular plasma-enhanced chemical vapor deposition, plate plasma-enhanced chemical vapor deposition, and low-pressure chemical vapor deposition.

[0111] In step S132, the n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductivity type semiconductor layer.

[0112] In step S131, the doping element includes oxygen. Therefore, a small amount of silicon oxide is formed in step S131. Consequently, a small amount of silicon oxide is also formed in the n-type doped oxygen-containing polycrystalline silicon layer obtained in step S132. Accordingly, compared with oxygen-free n-type doped polycrystalline silicon, the n-type doped oxygen-containing polycrystalline silicon layer in this embodiment has a wider optical bandgap and higher light transmittance. Therefore, the n-type doped oxygen-containing polycrystalline silicon layer obtained by using steps S131 and S132 provided in this embodiment has higher light transmittance, thereby improving the power generation efficiency of the finally obtained solar cell.

[0113] In this embodiment of the application, the process temperature of step S131 is not specifically limited. Optionally, the process temperature of the deposition process is set between 200°C and 800°C.

[0114] Optionally, the gas pressure used in the low-pressure chemical vapor deposition process is between 30 Pa and 130 Pa.

[0115] Optionally, the thickness of the first conductivity type semiconductor layer is between 10 nm and 60 nm. In the embodiments of this application, the duration of step S131 is not specifically limited, as long as the thickness of the obtained n-type doped oxygen-containing polycrystalline silicon layer is between 10 nm and 60 nm.

[0116] As another optional implementation, as shown in FIG4, a first conductivity type semiconductor layer is formed on the tunneling oxide layer, including:

[0117] In step S133, phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into a silicon thin film while a low-temperature atomic layer deposition process is used to obtain an n-type doped oxygen-containing amorphous silicon layer.

[0118] In step S134, the n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductivity type semiconductor layer.

[0119] Similarly, in step S133, the doping element includes oxygen, and a small amount of silicon oxide will be formed in step S133. Therefore, the n-type doped oxygen-containing polycrystalline silicon layer obtained in step S134 will also form a small amount of silicon oxide, making the optical band gap of the n-type doped oxygen-containing polycrystalline silicon layer wider, thereby obtaining higher light transmittance.

[0120] Optionally, in step S133, the process temperature of the low-temperature atomic layer deposition process is between 100°C and 300°C.

[0121] In the above embodiment, the thickness of the n-type doped oxygen-containing polycrystalline silicon layer obtained in step S134 includes 10 nm to 60 nm.

[0122] In this embodiment, the intrinsic passivation layer is an intrinsic silicon layer. Accordingly, step S170 can be specifically performed as follows:

[0123] The intrinsic passivation layer is obtained by depositing a silicon thin film using a first-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously incorporating hydrogen atoms.

[0124] As an optional implementation, the process temperature of the first type of plate-type plasma-enhanced chemical vapor deposition process includes 150°C to 200°C, and the thickness of the intrinsic passivation layer includes 1 nm to 5 nm.

[0125] As an optional implementation, in step S180, a second type of conductive semiconductor layer can be fabricated using a second-type plate-type PECVD process. Specifically, step S170 is performed as follows:

[0126] A second type of conductive semiconductor layer is obtained by depositing a silicon thin film using a second-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously doping it with boron, hydrogen, and oxygen atoms.

[0127] In other words, hydrogen (H) atoms, boron atoms, and oxygen atoms are incorporated during the deposition of microcrystalline silicon thin films or nanocrystalline silicon thin films.

[0128] Optionally, the deposition temperature range of the second type of plate-type plasma-enhanced chemical vapor deposition process includes 100°C to 200°C. The thickness of the second conductivity type semiconductor layer is between 5 nm and 30 nm.

[0129] As an optional implementation, as shown in FIG5, a first metal electrode layer is formed on the first transparent conductive layer, including:

[0130] In step S151, a metal paste is provided, the metal paste being selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste;

[0131] Here, the term "low-temperature slurry" is a common term known to those skilled in the art, used to distinguish metal slurries with different sintering temperature ranges. For example, the sintering temperature of low-temperature slurries is typically below 200°C; while the sintering temperature of high-temperature slurries is generally above 500°C.

[0132] In step S152, an initial first metal electrode layer is formed on the first transparent conductive layer using a printing process;

[0133] In step S153, a sintering and curing process is performed on the initial first metal electrode layer to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein, the process temperature of the sintering and curing process includes 100°C to 200°C; the mass percentage of copper in the silver-copper paste includes (0%, 80%), that is, the mass percentage of copper in the silver-copper paste falls within the range of 0% to 80%, and does not include 0%.

[0134] In this step, by controlling parameters such as sintering temperature and sintering time, it can be ensured that the first metal electrode only partially penetrates below the surface of the first transparent conductive layer, without burning through the entire first transparent conductive layer.

[0135] As another optional implementation, as shown in FIG6, a first metal electrode layer is formed on the first transparent conductive layer, including:

[0136] In step S154, a first copper seed layer is formed on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact;

[0137] In this step, by controlling the deposition depth of the first copper seed layer, it can be ensured that the first copper seed layer only partially penetrates below the surface of the first transparent conductive layer.

[0138] In step S155, a first patterned mask layer is formed on the first copper seed layer. The first patterned mask layer has a first opening pattern, which matches the first metal electrode layer.

[0139] In step S156, a copper material layer is formed that partially fills the first opening pattern;

[0140] In step S157, a silver material layer is formed that covers the copper material layer and fills the first opening pattern;

[0141] In step S158, the first patterned mask layer and the first copper seed layer not covered by the copper material layer are removed; the remaining first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

[0142] Similarly, as shown in FIG7, a second metal electrode layer is formed on the second transparent conductive layer, including:

[0143] In step S191, a metal paste is provided, the metal paste being selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste;

[0144] Here, the term "low-temperature" slurry is a common term known to those skilled in the art, used to distinguish metal slurries with different sintering temperature ranges. For example, the sintering temperature of low-temperature slurries is typically below 200°C, while the sintering temperature of high-temperature slurries is generally above 500°C.

[0145] In step S192, an initial second metal electrode layer is formed on the second transparent conductive layer using a printing process;

[0146] In step S193, a sintering and curing process is performed on the initial second metal electrode layer to form a second metal electrode layer including a second metal electrode, such that the second metal electrode portion penetrates below the surface of the second transparent conductive layer to form an ohmic contact. In the silver-copper paste, the mass percentage of copper is (0%, 80%), meaning the mass percentage of copper in the silver-copper paste falls within the range of 0% to 80%, excluding 0%. The process temperature of the sintering and curing process is between 100°C and 200°C.

[0147] In this step, by controlling parameters such as sintering temperature and sintering time, it can be ensured that the second metal electrode only partially penetrates below the surface of the second transparent conductive layer, without burning through the entire second transparent conductive layer.

[0148] As another optional implementation, as shown in FIG8, a second metal electrode layer is formed on the second transparent conductive layer, including:

[0149] In step S194, a second copper seed layer is formed on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact;

[0150] In this step, by controlling the deposition depth of the first copper seed layer, it can be ensured that the first copper seed layer only partially penetrates below the surface of the first transparent conductive layer.

[0151] In step S195, a second patterned mask layer is formed on the second copper seed layer. The second patterned mask layer has a second opening pattern, which matches the second metal electrode layer.

[0152] In step S196, a copper material layer is formed that partially fills the second opening pattern;

[0153] In step S197, a silver material layer is formed that covers the copper material layer and fills the second opening pattern;

[0154] In step S198, the second patterned mask layer and the second copper seed layer not covered by the copper material layer are removed; the remaining second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

[0155] The photovoltaic cell and its fabrication method provided in this application reduce the precision requirements for thin film deposition during the fabrication of the tunneling oxide layer and the first conductivity type semiconductor layer. This allows for full utilization of the tubular PECVD equipment currently used in Topcon cell fabrication, effectively reducing fabrication costs. Calculations show that 50% of the TOPCon cell manufacturing equipment and 50% of the HJT cell manufacturing equipment can be used, with an equipment investment cost of approximately 200 million RMB / GW. In comparison, the equipment investment cost for traditional HJT cells is 300 million RMB / GW.

[0156] Furthermore, since the front surface of the solar cell provided in this application embodiment uses a tunneling oxide layer (i.e., an n-type silicon oxide layer) with a grain size larger than that prepared by PECVD in conventional HJT cells, it can provide superior conductivity compared to conventional HJT cells. Moreover, since the front surface electrode of this solar cell is passivated with oxygen-containing polycrystalline silicon, it also provides a passivation effect superior to that of the emitter prepared by diffusion method on the front surface of conventional Topcon cells.

[0157] Traditional HJT solar cells use an intrinsic amorphous silicon layer for passivation on the light-incident surface of the silicon wafer (i.e., the first surface referred to in this application). The silicon-hydrogen bonds in this passivation layer are weak and break under ultraviolet light irradiation, leading to ultraviolet light degradation. In contrast, this application uses a tunneling oxide layer (i.e., an n-type silicon oxide layer) to passivate the front surface, effectively reflecting ultraviolet light and maintaining stable performance, thereby significantly improving the solar cell's resistance to ultraviolet light degradation.

[0158] As a second aspect of this application, a solar cell is provided, as shown in FIG9. The solar cell includes a silicon substrate 300, a first film layer structure 100 disposed on a first surface of the silicon substrate 300, and a second film layer structure 200 disposed on a second surface of the silicon substrate 100, wherein the first surface and the second surface are opposite to each other.

[0159] The first film layer structure 100 includes a tunneling oxide layer 110, a first conductivity type semiconductor layer 120, a first transparent conductive layer 130, and a first metal electrode layer 140. The tunneling oxide layer 110 is disposed above a first surface of the silicon substrate 300. The first conductivity type semiconductor layer 120 is disposed above the surface of the tunneling oxide layer 110 facing away from the silicon substrate 300. The first transparent conductive layer 130 is disposed above the surface of the first conductivity type semiconductor layer 120 facing away from the tunneling oxide layer 110. The first metal electrode layer 140 is disposed above the surface of the first transparent conductive layer 130 facing away from the first conductivity type semiconductor layer 120. An ohmic contact is formed between the first metal electrode in the first metal electrode layer 140 and the first transparent conductive layer 130. It should be noted that the "first conductivity type" mentioned above is selected from p-type and n-type.

[0160] The second film layer structure 200 may include an intrinsic passivation layer 210, a second conductivity type semiconductor layer, a second transparent conductive layer 230, and a second metal electrode layer 240.

[0161] An intrinsic passivation layer 210 is disposed below the second surface of the silicon substrate 300. A second conductivity type semiconductor layer 220 is disposed on the side of the intrinsic passivation layer 210 away from the silicon substrate 300. A second transparent conductive layer 230 is disposed on the side of the second conductivity type semiconductor layer 220 away from the intrinsic passivation layer 210. A second metal electrode layer 240 is disposed above the surface of the second transparent conductive layer 230 away from the surface of the second conductivity type semiconductor layer 220. An ohmic contact is formed between the second metal electrode in the second metal electrode layer 240 and the second transparent conductive layer 230. The second conductivity type is selected from either p-type or n-type.

[0162] In the solar cell provided in this embodiment, the tunneling oxide layer 110 and the first conductivity type semiconductor layer 120 form a passivation contact structure. The tunneling oxide layer 110 reduces the interface state density between the silicon substrate 300 and the first conductivity type semiconductor layer 120 through chemical passivation. The high concentration of majority carriers (majority carriers) passes through in the form of quantum tunneling and blocks minority carriers (minority carriers), reducing the probability of electron-hole recombination while increasing conductivity, thus forming a selective contact for majority carriers. Therefore, the passivation contact structure formed by the tunneling oxide layer 110 and the first conductivity type semiconductor layer 120 enables the solar cell to have good passivation capability.

[0163] In fabricating the first film layer structure of a solar cell, a first transparent conductive layer 130 is formed first, followed by a first metal electrode layer 140. When fabricating the first metal electrode layer 140, it is only necessary to melt and burn through the surface layer of the first transparent conductive layer 130 to achieve ohmic contact between the first metal electrode 141 and the first transparent conductive layer 130. The temperature required to burn through the surface layer of the first transparent conductive layer 130 is relatively low; that is, the process temperature for forming the first metal electrode layer 140 is low. This results in a lower degree of oxidation of the conductive paste used to form the first metal electrode layer 140, leading to a lower resistivity for the first metal electrode in the final first metal electrode layer 140, thereby improving the power generation efficiency of the solar cell. Furthermore, due to the low temperature at which the first metal electrode layer 140 is formed, relatively low-cost electrode materials such as low-temperature silver-copper paste can be used, further reducing the fabrication cost of the solar cell.

[0164] Similarly, in fabricating the second film layer structure of a solar cell, a second transparent conductive layer 230 is formed first, followed by a second metal electrode layer 240. When fabricating the second metal electrode layer 240, only the electrode paste needs to be melted and burned through the surface of the second transparent conductive layer 230, rather than burning through the entire second transparent conductive layer 230, to achieve ohmic contact between the second metal electrode 241 and the second transparent conductive layer 230. The temperature required to burn through the surface of the second transparent conductive layer 230 is relatively low; that is, the process temperature for forming the second metal electrode layer 240 is low. This results in a lower degree of oxidation of the conductive paste used to form the second metal electrode layer 240, allowing the second metal electrode 241 of the final second metal electrode layer 240 to have a lower resistivity, thereby improving the power generation efficiency of the solar cell. Furthermore, due to the lower temperature at which the second metal electrode layer 240 is formed, relatively low-cost electrode materials such as low-temperature silver-copper paste can be used, further reducing the fabrication cost of the solar cell.

[0165] In other words, this application can utilize tubular PECVD, ALD equipment, etc., to prepare the relevant film layers (including at least a tunneling oxide layer 110 and a first conductivity type semiconductor layer 120) in the first film layer structure of a solar cell, which offers a significant cost advantage compared to the plate-type PECVD equipment used in the HJT process. Calculations show that this application can utilize 50% of the TOPCon cell manufacturing equipment and 50% of the HJT cell manufacturing equipment, with an equipment investment cost of RMB 200 million / GW. In contrast, the equipment investment cost for traditional HJT cells is RMB 300 million / GW.

[0166] As an alternative implementation, the first transparent conductive layer 130 can be made using a TCO material (e.g., ITO or AZO).

[0167] Accordingly, the first metal electrode layer 140 includes a plurality of first metal electrodes 141. To reduce costs, the material of the first metal electrodes 141 may optionally be silver and / or copper. That is, the first metal electrode layer 140 can be prepared using at least one of low-temperature silver paste, low-temperature silver-copper paste, and low-temperature copper paste, thereby reducing the material cost of the metal electrodes.

[0168] The second metal electrode layer 240 includes a plurality of second metal electrodes 242. To reduce costs, the material of the second metal electrodes 242 can be silver and / or copper. That is, the second metal electrode layer 240 can be prepared using at least one of low-temperature silver paste, low-temperature silver-copper paste, and low-temperature copper paste, thereby reducing the material cost of the metal electrodes.

[0169] In the above embodiments, the term "low-temperature" slurry is a common term well-known to those skilled in the art, used to distinguish metal slurries with different sintering temperature ranges. For example, the sintering temperature of low-temperature slurries is typically below 200°C, while the sintering temperature of high-temperature slurries is generally above 500°C.

[0170] In this embodiment, the silicon substrate 300 can be an n-type silicon substrate, and correspondingly, the first conductivity type semiconductor layer 120 can be an n-type oxygen-containing polycrystalline silicon layer. That is, at least one of low-temperature silver paste, low-temperature silver-copper paste, and low-temperature copper paste can be used to prepare the first metal electrode layer 240, thereby reducing the material cost of the metal electrode.

[0171] Optionally, the thickness of the first conductivity type semiconductor layer is between 10 nm and 60 nm.

[0172] Optionally, the material of the tunneling oxide layer 110 is silicon dioxide, and the thickness of the tunneling oxide layer 110 is between 1 nm and 5 nm.

[0173] The tunneling oxide layer 110 made of silicon dioxide is relatively dense and has a higher tolerance to ultraviolet light (e.g., it has more stable chemical properties under ultraviolet irradiation). Therefore, the first surface of the silicon substrate 300 can be the light-incident surface of the solar cell, and the second surface of the silicon substrate 300 can be the back surface of the solar cell, thereby reducing the ultraviolet degradation characteristics of the solar cell and improving the light utilization efficiency of the solar cell. Specifically, in this application, a tunneling oxide layer (i.e., an n-type silicon oxide layer) is used to passivate the front surface (i.e., the first surface) of the silicon substrate, effectively reflecting ultraviolet light and maintaining its own performance stability, thereby effectively improving the anti-ultraviolet degradation performance of the solar cell.

[0174] Of course, the embodiments of this application are not limited to this. The first surface of the silicon substrate 300 can be the back surface of the solar cell, and the second surface of the silicon substrate 300 can be the light-incident surface of the solar cell.

[0175] As an optional implementation, the second conductivity type semiconductor layer 220 is a p-type microcrystalline silicon layer (i.e., p-μc-Si:H layer), and the intrinsic passivation layer 210 is an intrinsic silicon layer (i.e., i-Si layer).

[0176] Optionally, the thickness of the second conductivity type semiconductor layer 220 is between 5 nm and 30 nm.

[0177] Of course, the embodiments of this application are not limited thereto. For example, the first conductivity type semiconductor layer 120 can be a p-type polysilicon layer, and the second conductivity type semiconductor layer 220 can be an n-type polysilicon layer.

[0178] In the embodiments of this application, the specific form of the silicon substrate 300 is not specifically limited. For example, at least one of the first surface and the second surface of the silicon substrate 300 may have a textured structure.

[0179] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Those skilled in the art should understand that this application includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications that do not depart from the functional and structural principles of this application will be included within the scope of the claims.

Claims

1. A method for preparing a solar cell, characterized in that, The preparation method includes: A silicon substrate is provided, the silicon substrate having a first surface and a second surface, the first surface and the second surface being opposite to each other; A tunneling oxide layer is formed on the first surface of the silicon substrate; A first conductivity type semiconductor layer is formed on the tunneling oxide layer, wherein the first conductivity type is selected from p-type and n-type. A first transparent conductive layer is formed on the first conductivity type semiconductor layer; A first metal electrode layer is formed on the first transparent conductive layer, and an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer. An intrinsic passivation layer is formed on the second surface of the silicon substrate; A second conductivity type semiconductor layer is formed on the intrinsic passivation layer, wherein the second conductivity type is selected from p-type and n-type. A second transparent conductive layer is formed on the second conductivity type semiconductor layer; A second metal electrode layer is formed on the second transparent conductive layer, and an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer.

2. The preparation method according to claim 1, characterized in that, A tunneling oxide layer is formed on the first surface of the silicon substrate, comprising: An initial tunneling oxide layer is formed on the first surface of the silicon substrate; The initial tunneling oxide layer is annealed to obtain the tunneling oxide layer; the thickness of the tunneling oxide layer includes 1 nm to 5 nm.

3. The preparation method according to claim 2, characterized in that, The process temperature for forming the initial tunneling oxide layer on the first surface of the silicon substrate includes 200°C to 1050°C, and the initial tunneling oxide layer is formed using any one of the following processes: Atomic layer deposition process, thermal oxidation process, plasma-enhanced chemical vapor deposition process, low-pressure chemical vapor deposition and low-temperature wet oxidation process; The annealing temperature for annealing the initial tunneling oxide layer ranges from 200°C to 800°C.

4. The preparation method according to claim 1, characterized in that, The first conductivity type semiconductor layer is an n-type semiconductor layer, and the first conductivity type semiconductor layer is formed on the tunneling oxide layer, including: Phosphorus atoms, hydrogen atoms, and oxygen atoms are doped into a silicon thin film using a predetermined deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer. The predetermined deposition process is selected from any one of tubular plasma-enhanced chemical vapor deposition, plate-type plasma-enhanced chemical vapor deposition, and low-pressure chemical vapor deposition. The n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductivity type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes 10 nm to 60 nm; wherein the process temperature of the set deposition process includes 200 °C to 800 °C. or, Forming a first conductivity type semiconductor layer on the tunneling oxide layer includes: Phosphorus, hydrogen, and oxygen atoms are doped into silicon thin films using a low-temperature atomic layer deposition process to obtain an n-type doped oxygen-containing amorphous silicon layer. The n-type doped oxygen-containing amorphous silicon layer is subjected to annealing and crystallization treatment to obtain an n-type doped oxygen-containing polycrystalline silicon layer used as the first conductivity type semiconductor layer; the thickness of the n-type doped oxygen-containing polycrystalline silicon layer includes 10 nm to 60 nm; wherein the process temperature of the low-temperature atomic layer deposition process includes 100 °C to 300 °C.

5. The preparation method according to claim 1, characterized in that, An intrinsic passivation layer is formed on the second surface of the silicon substrate, comprising: The intrinsic passivation layer is obtained by depositing a silicon thin film using a first-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously incorporating hydrogen atoms; wherein the process temperature of the first-type plate-type plasma-enhanced chemical vapor deposition process includes 150°C to 200°C; and the thickness of the intrinsic passivation layer includes 1 nm to 5 nm.

6. The preparation method according to claim 3, characterized in that, An intrinsic passivation layer is formed on the second surface of the silicon substrate, comprising: The intrinsic passivation layer is obtained by depositing a silicon thin film using a first-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously incorporating hydrogen atoms; wherein the process temperature of the first-type plate-type plasma-enhanced chemical vapor deposition process includes 150°C to 200°C; and the thickness of the intrinsic passivation layer includes 1 nm to 5 nm.

7. The preparation method according to claim 4, characterized in that, An intrinsic passivation layer is formed on the second surface of the silicon substrate, comprising: The intrinsic passivation layer is obtained by depositing a silicon thin film using a first-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously incorporating hydrogen atoms; wherein the process temperature of the first-type plate-type plasma-enhanced chemical vapor deposition process includes 150°C to 200°C; and the thickness of the intrinsic passivation layer includes 1 nm to 5 nm.

8. The preparation method according to claim 1, characterized in that, A second conductivity type semiconductor layer is formed on the intrinsic passivation layer, including: A second type of conductive semiconductor layer is obtained by depositing a silicon thin film using a second-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously doping it with boron, hydrogen, and oxygen atoms. The process temperature of the second-type plate-type plasma-enhanced chemical vapor deposition process ranges from 100°C to 200°C, and the thickness of the second conductive semiconductor layer ranges from 5 nm to 30 nm.

9. The preparation method according to claim 3, characterized in that, A second conductivity type semiconductor layer is formed on the intrinsic passivation layer, including: A second type of conductive semiconductor layer is obtained by depositing a silicon thin film using a second-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously doping it with boron, hydrogen, and oxygen atoms. The process temperature of the second-type plate-type plasma-enhanced chemical vapor deposition process ranges from 100°C to 200°C, and the thickness of the second conductive semiconductor layer ranges from 5 nm to 30 nm.

10. The preparation method according to claim 4, characterized in that, A second conductivity type semiconductor layer is formed on the intrinsic passivation layer, including: A second type of conductive semiconductor layer is obtained by depositing a silicon thin film using a second-type plate-type plasma-enhanced chemical vapor deposition process while simultaneously doping it with boron, hydrogen, and oxygen atoms. The process temperature of the second-type plate-type plasma-enhanced chemical vapor deposition process ranges from 100°C to 200°C, and the thickness of the second conductive semiconductor layer ranges from 5 nm to 30 nm.

11. The preparation method according to claim 1, characterized in that, Forming a first metal electrode layer on the first transparent conductive layer includes: A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; An initial first metal electrode layer is formed on the first transparent conductive layer using a printing process; A sintering and curing process is performed on the initial first metal electrode layer to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein, the process temperature of the sintering and curing process includes 100°C to 200°C; and the mass percentage of copper in the silver-copper paste includes (0% to 80%). or, Forming a first metal electrode layer on the first transparent conductive layer includes: A first copper seed layer is formed on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact; A first patterned mask layer is formed on the first copper seed layer, the first patterned mask layer having a first opening pattern, the first opening pattern matching the first metal electrode layer; A copper material layer is formed that partially fills the pattern of the first opening. A silver material layer is formed that covers the copper material layer and fills the first opening pattern; Remove the first patterned mask layer and the first copper seed layer not covered by the copper material layer; the remaining first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

12. The preparation method according to claim 3, characterized in that, Forming a first metal electrode layer on the first transparent conductive layer includes: A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; An initial first metal electrode layer is formed on the first transparent conductive layer using a printing process; A sintering and curing process is performed on the initial first metal electrode layer to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein, the process temperature of the sintering and curing process includes 100°C to 200°C; and the mass percentage of copper in the silver-copper paste includes (0% to 80%). or, Forming a first metal electrode layer on the first transparent conductive layer includes: A first copper seed layer is formed on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact; A first patterned mask layer is formed on the first copper seed layer, the first patterned mask layer having a first opening pattern, the first opening pattern matching the first metal electrode layer; A copper material layer is formed that partially fills the pattern of the first opening. A silver material layer is formed that covers the copper material layer and fills the first opening pattern; Remove the first patterned mask layer and the first copper seed layer not covered by the copper material layer; the remaining first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

13. The preparation method according to claim 4, characterized in that, Forming a first metal electrode layer on the first transparent conductive layer includes: A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; An initial first metal electrode layer is formed on the first transparent conductive layer using a printing process; A sintering and curing process is performed on the initial first metal electrode layer to form a first metal electrode layer including a first metal electrode, and the first metal electrode portion penetrates below the surface of the first transparent conductive layer to form an ohmic contact; wherein, the process temperature of the sintering and curing process includes 100°C to 200°C; and the mass percentage of copper in the silver-copper paste includes (0% to 80%). or, Forming a first metal electrode layer on the first transparent conductive layer includes: A first copper seed layer is formed on the first transparent conductive layer; the first copper seed layer partially penetrates below the surface of the first transparent conductive layer to form an ohmic contact; A first patterned mask layer is formed on the first copper seed layer, the first patterned mask layer having a first opening pattern, the first opening pattern matching the first metal electrode layer; A copper material layer is formed that partially fills the pattern of the first opening. A silver material layer is formed that covers the copper material layer and fills the first opening pattern; Remove the first patterned mask layer and the first copper seed layer not covered by the copper material layer; the remaining first copper seed layer, copper material layer and silver material layer together constitute the first metal electrode layer.

14. The preparation method according to claim 1, characterized in that, Forming a second metal electrode layer on the second transparent conductive layer includes: A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; An initial second metal electrode layer is formed on the second transparent conductive layer using a printing process; A sintering and curing process is performed on the initial second metal electrode layer to form a second metal electrode layer including a second metal electrode, and the second metal electrode portion penetrates below the surface of the second transparent conductive layer to form an ohmic contact; wherein, in the silver-copper paste, the mass percentage of copper is (0%, 80%); the process temperature of the sintering and curing process is 100°C to 200°C. or, Forming a second metal electrode layer on the second transparent conductive layer includes: A second copper seed layer is formed on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact; A second patterned mask layer is formed on the second copper seed layer, the second patterned mask layer having a second opening pattern that matches the second metal electrode layer; A copper material layer is formed that partially fills the second opening pattern; A silver material layer is formed that covers the copper material layer and fills the second opening pattern; Remove the second patterned mask layer and the second copper seed layer not covered by the copper material layer; the remaining second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

15. The preparation method according to claim 3, characterized in that, Forming a second metal electrode layer on the second transparent conductive layer includes: A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; An initial second metal electrode layer is formed on the second transparent conductive layer using a printing process; A sintering and curing process is performed on the initial second metal electrode layer to form a second metal electrode layer including a second metal electrode, and the second metal electrode portion penetrates below the surface of the second transparent conductive layer to form an ohmic contact; wherein, in the silver-copper paste, the mass percentage of copper is (0%, 80%); the process temperature of the sintering and curing process is 100°C to 200°C. or, Forming a second metal electrode layer on the second transparent conductive layer includes: A second copper seed layer is formed on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact; A second patterned mask layer is formed on the second copper seed layer, the second patterned mask layer having a second opening pattern that matches the second metal electrode layer; A copper material layer is formed that partially fills the second opening pattern; A silver material layer is formed that covers the copper material layer and fills the second opening pattern; Remove the second patterned mask layer and the second copper seed layer not covered by the copper material layer; the remaining second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

16. The preparation method according to claim 4, characterized in that, Forming a second metal electrode layer on the second transparent conductive layer includes: A metal paste is provided, wherein the metal paste is selected from at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; An initial second metal electrode layer is formed on the second transparent conductive layer using a printing process; A sintering and curing process is performed on the initial second metal electrode layer to form a second metal electrode layer including a second metal electrode, and the second metal electrode portion penetrates below the surface of the second transparent conductive layer to form an ohmic contact; wherein, in the silver-copper paste, the mass percentage of copper is (0%, 80%); the process temperature of the sintering and curing process is 100°C to 200°C. or, Forming a second metal electrode layer on the second transparent conductive layer includes: A second copper seed layer is formed on the second transparent conductive layer; the second copper seed layer partially penetrates below the surface of the second transparent conductive layer to form an ohmic contact; A second patterned mask layer is formed on the second copper seed layer, the second patterned mask layer having a second opening pattern that matches the second metal electrode layer; A copper material layer is formed that partially fills the second opening pattern; A silver material layer is formed that covers the copper material layer and fills the second opening pattern; Remove the second patterned mask layer and the second copper seed layer not covered by the copper material layer; the remaining second copper seed layer, copper material layer and silver material layer together constitute the second metal electrode layer.

17. A solar cell comprising a silicon substrate having opposing first and second surfaces; characterized in that, Also includes: A first film layer structure is disposed on the first surface side of the silicon substrate; The first film layer structure includes a tunneling oxide layer, a first conductivity type semiconductor layer, a first transparent conductive layer, and a first metal electrode layer; A second film layer structure is disposed on the second surface side of the silicon substrate. The second film layer structure includes an intrinsic passivation layer, a second conductivity type semiconductor layer, a second transparent conductive layer, and a second metal electrode layer. in, The tunneling oxide layer is disposed above the first surface, the first conductive semiconductor layer is disposed above the surface of the tunneling oxide layer facing away from the silicon substrate, the first transparent conductive layer is disposed above the surface of the first conductive semiconductor layer facing away from the silicon substrate, and the first metal electrode layer is disposed above the surface of the first transparent conductive layer facing away from the first conductive semiconductor layer; an ohmic contact is formed between the first metal electrode in the first metal electrode layer and the first transparent conductive layer. The intrinsic passivation layer is disposed below the second surface, the second conductivity type semiconductor layer is disposed on the side of the intrinsic passivation layer away from the second surface, the second transparent conductive layer is disposed on the side of the second conductivity type semiconductor layer away from the intrinsic passivation layer, and the second metal electrode layer is disposed above the surface of the second transparent conductive layer away from the second conductivity type semiconductor layer; an ohmic contact is formed between the second metal electrode in the second metal electrode layer and the second transparent conductive layer; the first conductivity type is selected from p-type and n-type, and the second conductivity type is selected from the other p-type and n-type.

18. The solar cell according to claim 17, characterized in that, The silicon substrate includes an n-type silicon substrate; The first type of conductive semiconductor layer includes an n-type oxygen-containing polycrystalline silicon layer; the thickness of the first type of conductive semiconductor layer includes 10 nm to 60 nm. The second type of conductive semiconductor layer includes a p-type amorphous silicon layer, and the intrinsic passivation layer includes an intrinsic silicon layer; the thickness of the second type of conductive semiconductor layer includes 5 nm to 30 nm.

19. The solar cell according to claim 17, characterized in that, The material of the first metal electrode forming the first metal electrode layer includes at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; The material of the second metal electrode forming the second metal electrode layer includes at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; The material of the tunneling oxide layer includes silicon dioxide, and the thickness of the tunneling oxide layer includes 1 nm to 5 nm.

20. The solar cell according to claim 18, characterized in that, The material of the first metal electrode forming the first metal electrode layer includes at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; The material of the second metal electrode forming the second metal electrode layer includes at least one of low-temperature silver paste, low-temperature copper paste, and low-temperature silver-copper paste; The material of the tunneling oxide layer includes silicon dioxide, and the thickness of the tunneling oxide layer includes 1 nm to 5 nm.

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