Electronic device and manufacturing method therefor, and electronic apparatus

Abstract

Embodiments of the present application provide an electronic device and a manufacturing method therefor, and an electronic apparatus, aiming at enhancing the heat dissipation capability of electronic devices. In the electronic device provided in the embodiments of the present application, a first chip and a second chip are stacked in a plastic packaging member, a thermally conductive structure is located between the first chip and the second chip, and one end of the thermally conductive structure is exposed on the surface of the plastic packaging member, such that the heat generated by the first chip and the second chip is transferred to the thermally conductive structure, and transferred to the outside of the plastic packaging member through the end of the thermally conductive structure exposed on the surface of the plastic packaging member, improving the heat dissipation of the first chip and the second chip inside the plastic packaging member in the vertical direction, thereby enhancing the heat dissipation capability of the electronic device.

Description

Electronic devices and their manufacturing methods, electronic equipment

[0001] This application claims priority to Chinese Patent Application No. 202411554244.4, filed with the State Intellectual Property Office of China on October 31, 2024, entitled "Electronic Devices and Methods of Manufacturing Thereof, Electronic Devices", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, specifically to an electronic device and its manufacturing method, and an electronic device. Background Technology

[0003] Fan-out package on package (FOPOP) technology can stack chips of different specifications to form electronic devices, but the heat dissipation capacity of two or more chips after stacking is reduced. Summary of the Invention

[0004] This application provides an electronic device and its manufacturing method, as well as an electronic device, which aims to improve the heat dissipation capability of the electronic device.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] On one hand, embodiments of this application provide an electronic device, which includes a molding compound, a first chip, a second chip, and a thermally conductive structure. The first chip and the second chip are both located within the molding compound and are stacked. The thermally conductive structure is located between the first chip and the second chip, with one end of the thermally conductive structure exposed on the surface of the molding compound.

[0007] This application provides an electronic device in which a first chip and a second chip are stacked within a plastic package, and a thermally conductive structure is located between the first chip and the second chip. One end of the thermally conductive structure is exposed on the surface of the plastic package, so that the heat generated by the first chip and the second chip is transferred to the thermally conductive structure and then transferred to the outside of the plastic package through the end of the thermally conductive structure exposed on the surface of the plastic package. This improves the heat dissipation of the first chip and the second chip inside the plastic package in the vertical direction, thereby improving the heat dissipation capability of the electronic device.

[0008] In some embodiments, the electronic device further includes a first wiring layer located between a first chip and a second chip, the first chip and the second chip being connected through the first wiring layer, and a thermally conductive structure located between the first wiring layer and the first chip.

[0009] With the above configuration, the heat generated by the first chip can be transferred to the heat-conducting structure, and then to the outside of the molded component through one end of the heat-conducting structure exposed on the surface of the molded component, thereby achieving heat dissipation for the first chip inside the molded component; the heat generated by the second chip can be indirectly transferred to the heat-conducting structure through the first wiring layer, and then to the outside of the molded component through one end of the heat-conducting structure exposed on the surface of the molded component, thereby achieving heat dissipation for the second chip inside the molded component; and the heat dissipation for both the first and second chips can improve the heat dissipation capability of the electronic device.

[0010] In some embodiments, the first chip has a first sub-pad and a second sub-pad on the side facing the first wiring layer. Both the first sub-pad and the second sub-pad are connected to the first wiring layer. The first sub-pad and the second sub-pad are spaced apart, and a heat-conducting structure is located between the first sub-pad and the second sub-pad.

[0011] The above settings achieve the spacing between the heat-conducting structure, the first sub-pad, and the second sub-pad, allowing the first chip and the first wiring layer to be connected through the first and second sub-pads, while preventing the heat-conducting structure located between the first chip and the first wiring layer from contacting the first sub-pad or the second sub-pad, thus preventing leakage of the first chip caused by the heat-conducting structure.

[0012] In some embodiments, the thermally conductive structure includes a first thermally conductive portion located between the first wiring layer and the first chip. The extension direction of the first thermally conductive portion is perpendicular to the arrangement direction of the first sub-pad and the second sub-pad, and one end of the first thermally conductive portion in its extension direction is exposed on the surface of the molding compound.

[0013] With the above configuration, the first heat-conducting part, with one end exposed on the surface of the molding compound in its extension direction, can achieve heat dissipation for the first chip and the second chip in the shortest distance.

[0014] In some embodiments, the thermally conductive structure further includes a first thermally conductive portion and a second thermally conductive portion, the second thermally conductive portion being connected to one end of the thermally conductive structure, and the end of the second thermally conductive portion away from the first thermally conductive portion being exposed on the surface of the molding compound away from the second chip.

[0015] With the above configuration, the heat from the first chip and the second chip is transferred to the first heat-conducting part, and then through the second heat-conducting part to the side of the molding compound away from the second chip, so as to achieve heat dissipation for the first chip and the second chip.

[0016] In some embodiments, the thermally conductive structure further includes a third thermally conductive portion, the first thermally conductive portion having a first end and a second end in its extending direction, the second thermally conductive portion being connected to the first end, the third thermally conductive portion being connected to the second end, and the end of the third thermally conductive portion away from the first thermally conductive portion being exposed on the surface of the molding compound away from the second chip.

[0017] With the above configuration, both the second and third heat-conducting portions are used to transfer the heat from the first heat-conducting portion to the side of the molding compound away from the second chip, increasing the area of ​​the heat-conducting structure exposed on the surface of the molding compound and improving the heat dissipation capability of the heat-conducting structure for the first and second chips.

[0018] In some embodiments, the extension direction of the first heat-conducting portion is perpendicular to the arrangement direction of the first sub-pad and the second sub-pad; the extension direction of the second heat-conducting portion is perpendicular to the extension direction of the first heat-conducting portion; and the extension direction of the third heat-conducting portion is perpendicular to the extension direction of the first heat-conducting portion.

[0019] With the above configuration, the first chip is positioned between the second and third heat-conducting portions, allowing the second and third heat-conducting portions to bypass the first chip and transfer the heat from the first heat-conducting portion to the surface of the molding compound away from the second chip.

[0020] In some embodiments, the electronic device further includes a first wiring layer located between a first chip and a second chip, the first chip and the second chip being connected through the first wiring layer, and a thermally conductive structure located between the first wiring layer and the second chip.

[0021] With the above configuration, the heat generated by the second chip can be directly or indirectly transferred to the heat-conducting structure, and then transferred to the outside of the molded component through one end of the heat-conducting structure exposed on the surface of the molded component, thereby achieving heat dissipation for the second chip inside the molded component; the heat generated by the first chip can be indirectly transferred to the heat-conducting structure through the first wiring layer, and also transferred to the outside of the molded component through one end of the heat-conducting structure exposed on the surface of the molded component, thereby achieving heat dissipation for the first chip inside the molded component; and the heat dissipation for both the first chip and the second chip can improve the heat dissipation capability of the electronic device.

[0022] In some embodiments, the electronic device further includes a second wiring layer and a contact structure. The second wiring layer is located on the side of the second chip opposite to the first chip. The second chip is connected to the second wiring layer, and the contact structure connects the second wiring layer and the first wiring layer.

[0023] With the above configuration, the first chip is connected to the first wiring layer, the first wiring layer is connected to the second wiring layer through a contact structure, and the second wiring layer is used to connect with other devices, thus realizing the lead-out of the first chip in the electronic device; at the same time, the second chip is also connected to the second wiring layer, thus realizing the lead-out of the second chip in the electronic device.

[0024] In some embodiments, the electronic device further includes an adhesive layer located between the second chip and the first wiring layer.

[0025] With the above configuration, the adhesive layer can fix the relative position between the first wiring layer and the second chip. The second chip is fixed by the first wiring layer, which facilitates the formation of a second wiring layer on the second chip that is connected to the second chip.

[0026] On the other hand, embodiments of this application provide a method for manufacturing an electronic device, the method comprising:

[0027] Install a second chip;

[0028] A thermally conductive structure is formed on the second chip;

[0029] A first chip is mounted on a heat-conducting structure, such that the heat-conducting structure is located between the first chip and the second chip.

[0030] The first chip, the thermal conductive structure, and the second chip are encapsulated to form a molded component, with one end of the thermal conductive structure exposed on the surface of the molded component; both the first chip and the second chip are located inside the molded component.

[0031] In some embodiments, forming a thermally conductive structure includes:

[0032] A first heat-conducting portion is formed, the extension direction of the first heat-conducting portion is parallel to the plane where the second chip is located, and the first heat-conducting portion has a first end and a second end in its extension direction.

[0033] A second heat-conducting portion is formed, and the second heat-conducting portion is connected to the first end. The extension direction of the second heat-conducting portion is perpendicular to the plane where the second chip is located.

[0034] A third heat-conducting portion is formed, which is connected to the second end. The extension direction of the third heat-conducting portion is perpendicular to the plane where the second chip is located.

[0035] With the above configuration, the heat on the first heat-conducting part can be transferred to the second and third heat-conducting parts, improving the heat dissipation capability of the heat-conducting structure for the first and second chips.

[0036] In some embodiments, installing the second chip includes:

[0037] Provide a first substrate;

[0038] A first wiring layer is formed on a first substrate;

[0039] A contact structure is formed, and a second chip is mounted on the first wiring layer;

[0040] A second wiring layer is formed, and the formed second wiring layer is connected to the first wiring layer through a contact structure.

[0041] In some embodiments, forming a thermally conductive structure on the second chip includes:

[0042] A second substrate is formed on the second wiring layer, and the first substrate is removed;

[0043] A thermally conductive structure is formed on the first wiring layer.

[0044] In some embodiments, installing the second chip includes:

[0045] Provide a second substrate;

[0046] A second wiring layer is formed on the second substrate;

[0047] A second chip is mounted on the second wiring layer, and a contact structure is formed thereon;

[0048] A first wiring layer is formed, and the first wiring layer is connected to the second wiring layer through a contact structure.

[0049] In some embodiments, forming a thermally conductive structure on the second chip includes forming a thermally conductive structure on the first wiring layer.

[0050] Furthermore, this application also provides an electronic device including a heat sink and the aforementioned electronic components, wherein the heat sink is connected to a heat-conducting structure. The heat-conducting structure transfers heat from the first chip and the second chip to the heat sink, thereby further improving the heat dissipation capacity of the electronic components.

[0051] It is understood that the beneficial effects of the manufacturing method and electronic device provided in the above embodiments of this application can be referred to the beneficial effects of the electronic device described above, and will not be repeated here. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this application.

[0053] Figure 1 is a schematic diagram of the structure of the electronic device in an embodiment of this application;

[0054] Figure 2 is a schematic diagram of the structure of the electronic device in an embodiment of this application;

[0055] Figure 3 is a schematic diagram of the structure of the electronic device in an embodiment of this application;

[0056] Figure 4 is a schematic diagram of the structure of the electronic device in the embodiment of this application;

[0057] Figure 5 is a schematic diagram of the structure of the electronic device in the embodiment of this application;

[0058] Figure 6 is a flowchart of the method for manufacturing electronic devices in an embodiment of this application;

[0059] Figure 7 is a schematic diagram of the structure after providing the first substrate in an embodiment of this application;

[0060] Figure 8 is a schematic diagram of the structure after the contact structure is formed in an embodiment of this application;

[0061] Figure 9 is a schematic diagram of the structure after the second chip is installed in an embodiment of this application;

[0062] Figure 10 is a schematic diagram of the structure after the second wiring layer is formed in an embodiment of this application;

[0063] Figure 11 is a schematic diagram of the structure after the second substrate is formed in an embodiment of this application;

[0064] Figure 12 is a schematic diagram of the structure after removing the first substrate in an embodiment of this application;

[0065] Figure 13 is a schematic diagram of the structure after the second substrate is formed in an embodiment of this application;

[0066] Figure 14 is a second schematic diagram of the structure after the contact structure is formed in an embodiment of this application;

[0067] Figure 15 is a schematic diagram of the structure after the second chip is installed in an embodiment of this application;

[0068] Figure 16 is a schematic diagram of the structure after the first wiring layer is formed in an embodiment of this application;

[0069] Figure 17 is a schematic diagram of the structure after the first chip is installed in an embodiment of this application;

[0070] Figure 18 is a schematic diagram of the structure after the first chip is installed in an embodiment of this application;

[0071] Figure 19 is a schematic diagram of the structure after the molding compound is formed in an embodiment of this application;

[0072] Figure 20 is a schematic diagram of the structure after the second and fourth pads are formed in the embodiment of this application.

[0073] Explanation of reference numerals in the attached drawings: 200, electronic device; 100, electronic component; 101, heat sink; 10, first substrate; 11, first glass; 12, first release layer; 13, first buffer layer; 20, first wiring layer; 21, first line; 221, through-hole; 22, contact structure; 30, second chip; 31, adhesive layer; 32, third pad; 40, second wiring layer; 41, second line; 411, second pad; 42, third line; 421, third pad; 50, second substrate; 51, second glass; 52, second release layer; 53, second buffer layer; 60, thermally conductive structure; 61, first section; 62, second thermally conductive section; 63, third thermally conductive section; 70, first chip; 71, first pad; 711, first sub-pad; 712, second sub-pad; 80, molding compound. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0075] Hereinafter, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature.

[0076] Furthermore, in the embodiments of this application, directional terms such as "up," "down," "left," "right," "horizontal," and "vertical" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0077] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium.

[0078] It should be noted that, in the description of the embodiments of this application, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection or an integral connection; they can also refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; or they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0079] Referring to Figures 1 and 2, this application provides an electronic device 100, which can encapsulate multiple chips, which can be stacked. The chips can include system-on-chips (SOCs), dynamic random-access memory (DRAM), etc. In some embodiments, the electronic device 100 includes a first chip 70 and a second chip 30, which are stacked to reduce the size of the electronic device 100. The electronic device 100 also includes a molding compound 80, within which both the first chip 70 and the second chip 30 are located, and the molding compound 80 protects the first chip 70 and the second chip 30.

[0080] In the above embodiments, the electronic device 100 further includes a first wiring layer 20, which is located between the first chip 70 and the second chip 30. It is understood that the first wiring layer 20 is also located within the molding compound 80. The first chip 70 has a first pad 71 (as shown in Figure 5) on the side facing the first wiring layer 20. A first line 21 is provided within the first wiring layer 20, and the first pad 71 is connected to the first line 21 in the first wiring layer 20. For example, the first chip 70 has a filler layer 701 on the side facing the second chip 30, which covers the first pad 71 and protects it. A circuit can be formed in the filler layer 701, and the first chip 70 can be connected to the first pad 71 through the circuit in the filler layer 701.

[0081] The electronic device 100 also includes a second wiring layer 40 and a contact structure 22. The second wiring layer 40 is located on the side of the second chip 30 opposite to the first chip 70, and is adjacent to the molding compound 80. The second wiring layer 40 contains a second line 41. The contact structure 22 passes through the molding compound 80 located between the first wiring layer 20 and the second wiring layer 40. One end of the contact structure 22 is connected to the first line 21 of the first wiring layer 20, and the other end is connected to the second line 41 in the second wiring layer 40. The side of the second wiring layer 40 opposite to the second chip 30 has a second pad 411 connected to the second line 41. The second pad 411 is used to connect other devices. The first chip 70 is connected to the first wiring layer 20 via the first pad 71, the first wiring layer 20 is connected to the second wiring layer 40 via the contact structure 22, and the second wiring layer 40 is connected to other devices via the second pad 411, thus enabling the lead-out of the first chip 70 in the electronic device 100. Both the first routing layer 20 and the second routing layer 40 can be redistribution layers (RDLs).

[0082] In the above embodiment, the second chip 30 has a third pad 32 on the side facing the second wiring layer 40, and a third line 42 is provided in the second wiring layer 40. The third pad 32 is connected to the third line 42 in the second wiring layer 40. The second wiring layer 40 has a fourth pad 421 on the side away from the second chip 30, which is connected to the third line 42. The fourth pad 421 is also used to connect other devices. The second chip 30 is connected to the second wiring layer 40 through the third pad 32, and the second wiring layer 40 is connected to other devices through the fourth pad 421, thus realizing the extraction of the second chip 30 in the electronic device 100.

[0083] In embodiments where the second wiring layer 40 includes a second line 41 and a third line 42, the second line 41 and the third line 42 can be connected to achieve an electrical connection between the first chip 70 and the second chip 30.

[0084] In the above embodiments, due to the different processes in forming the electronic device 100, the structure between the second chip 30 and the first wiring layer 20 is also different, for example: chip first and chip last. The difference between chip first and chip last is that the second chip 30 and the second wiring layer 40 are formed in different orders.

[0085] In the chip-first process, referring to Figure 1, the second chip 30 is formed first, followed by the formation of the second wiring layer 40. The electronic device 100 also includes an adhesive layer 31 located between the second chip 30 and the first wiring layer 20. After the first wiring layer 20 is formed on the substrate, the adhesive layer 31 is formed on one side of the first wiring layer 20. Then, the second chip 30 is formed on the adhesive layer 31, and finally, the second wiring layer 40, connected to the second chip 30, is formed. Since there is no electrical connection between the first wiring layer 20 and the second chip 30, the adhesive layer 31, through the above arrangement, can fix the relative position between the first wiring layer 20 and the second chip 30. Fixing the second chip 30 with the first wiring layer 20 facilitates the formation of the second wiring layer 40, which is connected to the second chip 30.

[0086] In the chip-last process, referring to Figure 2, the second wiring layer 40 is formed first, followed by the formation of the second chip 30. After the second wiring layer 40 is formed on the substrate, its position is fixed. Then, the second chip 30, connected to the second wiring layer 40, is formed on the second wiring layer 40. After filling with insulating material, the first wiring layer 20 is formed. Compared to the chip-first process, there is no adhesive layer 31 between the second wiring layer 40 and the first wiring layer 20 in the chip-last process.

[0087] Referring again to Figures 1 and 2, in some embodiments, the electronic device 100 further includes a thermally conductive structure 60. The thermally conductive structure 60 may be located between the first chip 70 and the second chip 30. In conjunction with the embodiments described above where the electronic device 100 includes a first wiring layer 20, the thermally conductive structure 60 may be located between the first chip 70 and the first wiring layer 20, or between the second chip 30 and the first wiring layer 20; wherein one end of the thermally conductive structure 60 is exposed on the surface of the molding compound 80. The thermally conductive structure 60 may include materials with thermal conductivity, such as copper, silver, diamond, alloys, etc.

[0088] In some embodiments of the above examples, the heat-conducting structure 60 is located between the first chip 70 and the first wiring layer 20. The heat-conducting structure 60 is insulated from the first chip 70 and also from the first wiring layer 20. The heat generated by the first chip 70 can be directly transferred to the heat-conducting structure 60 and then to the outside of the molding compound 80 through one end of the heat-conducting structure 60 exposed on the surface of the molding compound 80, thereby achieving heat dissipation of the first chip 70 inside the molding compound 80 and improving the heat dissipation capability of the electronic device 100. The heat generated by the second chip 30 can be indirectly transferred to the heat-conducting structure 60 through the first wiring layer 20 and then to the outside of the molding compound 80 through one end of the heat-conducting structure 60 exposed on the surface of the molding compound 80, thereby achieving heat dissipation of the second chip 30 inside the molding compound 80 and improving the heat dissipation capability of the electronic device 100.

[0089] In other embodiments of the above examples, the thermally conductive structure 60 is located between the second chip 30 and the first wiring layer 20, and is insulated from both the second chip 30 and the first wiring layer 20. In the electronic device 100 formed by a chip-last process, the thermally conductive structure 60 is located within the insulating material filled between the second chip 30 and the first wiring layer 20, allowing heat generated by the second chip 30 to be directly transferred to the thermally conductive structure 60. In the electronic device 100 formed by a chip-first process, the thermally conductive structure 60 is located between the adhesive layer 31 and the first wiring layer 20, allowing heat generated by the second chip 30 to be transferred to the thermally conductive structure 60 through the adhesive layer 31. Regardless of how the heat from the second chip 30 is transferred to the thermally conductive structure 60, it can be transferred to the outside of the molding compound 80 through the end of the thermally conductive structure 60 exposed on the surface of the molding compound 80, thereby achieving heat dissipation of the second chip 30 inside the molding compound 80 and improving the heat dissipation capability of the electronic device 100. The heat generated by the first chip 70 can be indirectly transferred to the heat-conducting structure 60 through the first wiring layer 20, and also transferred to the outside of the molding compound 80 through one end of the heat-conducting structure 60 exposed on the surface of the molding compound 80, so as to achieve heat dissipation of the first chip 70 inside the molding compound 80, thereby improving the heat dissipation capability of the electronic device 100.

[0090] In the embodiment where the heat-conducting structure 60 is located between the first chip 70 and the first wiring layer 20, the first chip 70 is closer to the heat-conducting structure 60 than the second chip 30, and the heat-conducting structure 60 provides better heat dissipation for the first chip 70; in the embodiment where the heat-conducting layer is located between the second chip 30 and the first wiring layer 20, the second chip 30 is closer to the heat-conducting structure 60 than the first chip 70, and the heat-conducting structure 60 provides better heat dissipation for the second chip 30.

[0091] The electronic device 100 provided in this application embodiment has a first chip 70 and a second chip 30 stacked inside a molding compound 80, and a heat-conducting structure 60 located between the first chip 70 and the second chip 30. One end of the heat-conducting structure 60 is exposed on the surface of the molding compound 80, so that the heat generated by the first chip 70 and the second chip 30 is transferred to the heat-conducting structure 60, and then transferred to the outside of the molding compound 80 through the end of the heat-conducting structure 60 exposed on the surface of the molding compound 80. This improves the heat dissipation of the first chip 70 and the second chip 30 inside the molding compound 80 in the vertical direction, thereby improving the heat dissipation capability of the electronic device 100.

[0092] Referring to Figure 3, based on the electronic device 100 described above, this application embodiment also provides an electronic device 200. The electronic device 200 includes the electronic device 100 and a heat sink 101. The heat sink 101 is disposed on the surface of a molding compound 80. One end of a thermally conductive structure 60 exposed on the surface of the molding compound 80 is connected to the heat sink 101. The thermally conductive structure 60 transfers heat from the first chip 70 and the second chip 30 to the heat sink 101, further improving the heat dissipation capacity of the electronic device 100. The electronic device 200 includes devices having the electronic device 100, such as mobile phones and computers.

[0093] In some embodiments, in conjunction with the thermal conductive structure 60 being located between the first chip 70 and the first wiring layer 20, the first pad 71 may include a first sub-pad 711 and a second sub-pad 712. Both the first sub-pad 711 and the second sub-pad 712 are located on the side of the first chip 70 facing the first wiring layer 20 and are both connected to the first wiring layer 20. The first sub-pad 711 and the second sub-pad 712 are spaced apart, and the thermal conductive structure 60 is located between the first sub-pad 711 and the second sub-pad 712. This arrangement achieves the spaced arrangement of the thermal conductive structure 60, the first sub-pad 711, and the second sub-pad 712, allowing the first chip 70 and the first wiring layer 20 to be connected through the first sub-pad 711 and the second sub-pad 712, while preventing the thermal conductive structure 60 located between the first chip 70 and the first wiring layer 20 from contacting the first sub-pad 711 or the second sub-pad 712, thus preventing leakage of the first chip 70 caused by the thermal conductive structure 60.

[0094] Referring to Figures 4 and 5, in some embodiments, the thermally conductive structure 60 includes a first thermally conductive portion 61 located between the first wiring layer 20 and the first chip 70. The extending direction of the first thermally conductive portion 61 is perpendicular to the arrangement direction of the first sub-pad 711 and the second sub-pad 712. In the extending direction of the first thermally conductive portion 61, one or both ends of the first thermally conductive portion 61 are exposed on the surface of the molding compound 80 (understandably, one or both ends of the first thermally conductive portion 61 are exposed on the side of the molding compound 80). With this configuration, the first thermally conductive portion 61, with one end exposed on the surface of the molding compound 80 in its extending direction, can achieve heat dissipation for the first chip 70 and the second chip 30 in the shortest possible distance.

[0095] Referring again to Figures 1 and 2, in some embodiments, the thermally conductive structure 60 includes a first thermally conductive portion 61 located between the first wiring layer 20 and the first chip 70, entirely within the molding compound 80. The thermally conductive structure 60 also includes a second thermally conductive portion 62 connected to one end of the first thermally conductive structure 60, with the end of the second thermally conductive portion 62 away from the first thermally conductive portion 61 exposed on the surface of the molding compound 80 away from the second chip 30. Through this arrangement, heat from the first chip 70 and the second chip 30 is transferred to the first thermally conductive portion 61, and then through the second thermally conductive portion 62 to the side of the molding compound 80 away from the second chip 30, thereby achieving heat dissipation for the first chip 70 and the second chip 30.

[0096] In the above embodiment, the heat-conducting structure 60 further includes a third heat-conducting portion 63; the first heat-conducting portion 61 has a first end and a second end in its extending direction, both the first end and the second end of the first heat-conducting portion 61 are located in the molding compound 80, the second heat-conducting portion 62 is connected to the first end, and the third heat-conducting portion 63 is connected to the second end, with the end of the third heat-conducting portion 63 away from the first heat-conducting portion 61 exposed on the surface of the molding compound 80 away from the second chip 30. Through this arrangement, both the second heat-conducting portion 62 and the third heat-conducting portion 63 are used to transfer the heat from the first heat-conducting portion 61 to the side of the molding compound 80 away from the second chip 30, increasing the area of ​​the heat-conducting structure 60 exposed on the surface of the molding compound 80, and improving the heat dissipation capability of the heat-conducting structure 60 for the first chip 70 and the second chip 30.

[0097] In the above embodiment, the extension direction of the first heat-conducting portion 61 is perpendicular to the arrangement direction of the first sub-pad 711 and the second sub-pad 712; the extension direction of the second heat-conducting portion 62 is perpendicular to the extension direction of the first heat-conducting portion 61; and the extension direction of the third heat-conducting portion 63 is perpendicular to the extension direction of the first heat-conducting portion 61. Within the plane containing the first heat-conducting portion 61, the second heat-conducting portion 62, and the third heat-conducting portion 63, the second heat-conducting portion 62, the first heat-conducting portion 61, and the third heat-conducting portion 63 are sequentially connected and arranged in a "U" shape. Through this arrangement, the first chip 70 is located between the second heat-conducting portion 62 and the third heat-conducting portion 63, allowing the second heat-conducting portion 62 and the third heat-conducting portion 63 to bypass the first chip 70 and transfer the heat from the first heat-conducting portion 61 to the surface of the molding compound 80 away from the second chip 30.

[0098] Referring to FIG3, in an embodiment of an electronic device including an electronic component 100 and a heat sink 101, the heat sink 101 may be located on the side surface of the molding compound 80 away from the second chip 30. One exposed end of the second heat-conducting portion 62 and one exposed end of the third heat-conducting portion 63 are both connected to the heat sink, which can further improve the heat dissipation capability of the electronic component 100.

[0099] On the other hand, this application embodiment also provides a method for manufacturing an electronic device 100. Please refer to FIG6. The manufacturing method may include steps S100-S400.

[0100] S100: Install the second chip.

[0101] The installation of the second chip 30 includes the aforementioned chip first process and chip last process.

[0102] Referring to Figure 7, in the chip-first process, mounting the second chip 30 includes providing a first substrate 10. The first substrate 10 includes a first glass 11 and a first separation layer 12 stacked together. The first glass 11 can provide a flat surface during the fabrication of the electronic device 100. The first separation layer 12 can be carbonized and detached under high-temperature processing to remove the first glass 11 during the fabrication of the electronic device 100. In some embodiments, the first substrate 10 further includes a first buffer layer 13 (BL). The first buffer layer 13 is located on the side of the first separation layer 12 opposite to the first glass 11. Subsequently, the electronic device 100 is formed on the first buffer layer 13. The first buffer layer 13 is used to reduce the stress generated during the fabrication of the electronic device 100.

[0103] Referring to Figure 8, after providing a first substrate 10, a first wiring layer 20 is formed on the first substrate 10. Forming the first wiring layer 20 includes spin-coating an organic material onto the first substrate 10 and curing it. The organic material includes polyimide (PI). Then, a circuit pattern is formed on the organic material by photolithography and etching, and a first line 21 is formed by electroplating to fill it, thereby forming the first wiring layer 20. In conjunction with the previous step, the first wiring layer 20 and the first buffer layer 13 can be formed from the same material.

[0104] Referring to Figures 8 and 9, after the first wiring layer 20 is formed and before the second chip 30 is mounted on the first wiring layer 20, an adhesive layer 31 can be formed on the side of the first wiring layer 20 facing away from the first substrate 10. The adhesive layer 31 is used to fix the relative position of the second chip 30 and the first wiring layer 20. This prevents the position of the second chip 30 from changing during the formation of the second wiring layer on the second chip 30 after mounting. After the adhesive layer 31 is formed, the second chip 30 is mounted on the first wiring layer 20.

[0105] Then, an insulating material (which may include an epoxy molding compound (EMC)) is filled onto the first wiring layer 20, completely covering the second chip 30. Through-mold-via (TMV) holes 221 are formed in the insulating material, penetrating the insulating material and connecting to the first line 21 in the first wiring layer 20. Conductive material (e.g., copper) is filled into the TMV holes 221 to form contact structures 22. The extension direction of the contact structures 22 is perpendicular to the plane of the first wiring layer 20, and one end of the contact structure 22 near the first wiring layer 20 is connected to the first line 21 in the first wiring layer 20. Exemplarily, two contact structures 22 are provided, arranged opposite to each other. In an embodiment with two contact structures 22, the second chip 30 is mounted between the two contact structures 22.

[0106] By grinding, some of the filling insulating material is removed to expose the third pad 32 located on the side of the second chip 30 away from the first wiring layer 20, which facilitates the connection of the second chip 30 to the subsequently fabricated second wiring layer. At the same time, the end of the contact structure 22 away from the first wiring layer 20 is exposed, which facilitates the connection of the contact structure 22 to the subsequently fabricated second wiring layer.

[0107] Referring to Figure 10, a second wiring layer 40 is formed on the second chip 30. Similarly, forming the second wiring layer 40 may also include spin-coating an organic material onto the second chip 30 and the contact structure 22 and curing it, then forming a circuit pattern on the organic material by photolithography and etching, and forming a second line 41 and a third line 42 by electroplating to form the second wiring layer 40. The second line 41 is connected to the exposed end of the contact structure 22, so that the first line 21 in the first wiring layer 20 is connected to the second line 41 in the second wiring layer 40 through the contact structure 22; the third line 42 is connected to the exposed third pad 32 of the second chip 30.

[0108] Referring to FIG11, after the second wiring layer 40 is formed, a second substrate 50 is temporarily bonded (TB) on the second wiring layer 40. The second substrate 50 includes a second glass 51 and a second separation layer 52 stacked together. The second separation layer 52 is located between the second wiring layer 40 and the second glass 51. The second separation layer 52 can be carbonized and detached under high temperature treatment to remove the second glass 51 during the fabrication process of the electronic device 100.

[0109] Referring to Figure 12, after forming the second substrate 50, the entire device is flipped over, and the first substrate 10 is removed. Removing the first substrate 10 may include laser debonding (DB) the first separation layer 12 to remove the first glass 11; in embodiments where the first substrate 10 includes a first buffer layer 13, removing the first substrate 10 may further include removing a portion of the first buffer layer 13 by grinding, exposing the first line 21 located in the first wiring layer 20, facilitating subsequent connection of the first chip 70 to the first line 21.

[0110] Referring to FIG13, in the chip last process, mounting the second chip 30 includes providing a second substrate 50. Similar to the chip first process, the second substrate 50 includes a second glass 51 and a second separation layer 52. In some embodiments, the second substrate 50 may include a second buffer layer 53 located on the side of the second separation layer 52 opposite to the second glass 51. Subsequently, an electronic device 100 is formed on the second buffer layer 53, which is used to reduce stress generated during the fabrication of the electronic device 100.

[0111] Referring to FIG14, after providing the second substrate 50, a second wiring layer 40 is formed on the second substrate 50. The formation of the second wiring layer 40 includes spin-coating an organic material on the second substrate 50 and curing it, then forming a circuit pattern on the organic material by photolithography and etching, and forming a second line 41 and a third line 42 by electroplating to form the second wiring layer 40.

[0112] Referring to Figures 14 and 15, after forming the second wiring layer 40, a second chip 30 is mounted on the second wiring layer 40, such that the third pad 32 of the second chip 30 is connected to the third line 42 in the second wiring layer 40. Then, an insulating material is filled into the second wiring layer 40, completely covering the second chip 30. Similarly, through-holes 221 are formed in the insulating material, penetrating the insulating material and connecting to the second line 41 in the second wiring layer 40. Conductive material is filled into the through-holes 221 to form contact structures 22. The extension direction of the contact structures 22 is perpendicular to the plane of the second wiring layer 40, and one end of the contact structure 22 near the second wiring layer 40 is connected to the second line 41 in the second wiring layer 40. Exemplarily, two contact structures 22 are provided, arranged opposite to each other. In an embodiment where two contact structures 22 are provided, the second chip 30 is mounted between the two contact structures 22.

[0113] By grinding, some of the insulating material is removed, exposing the end of the contact structure 22 away from the second wiring layer 40, which facilitates the connection of the contact structure 22 to the first wiring layer that is subsequently fabricated.

[0114] Referring to Figure 16, a first wiring layer 20 is formed on the second chip 30. Forming the first wiring layer 20 may include spin-coating an organic material onto the second chip 30 and the contact structure 22 and curing it, then forming a circuit pattern on the organic material by photolithography and etching, and forming a first line 21 by electroplating to form the first wiring layer 20. The first line 21 is connected to the exposed end of the contact structure 22, so that the first line 21 in the first wiring layer 20 is connected to the second line 41 in the second wiring layer 40 through the contact structure 22.

[0115] After the first wiring layer 20 is formed, the first line 21 located in the first wiring layer 20 is exposed, which facilitates the subsequent connection of the first chip 70 on the first line 21.

[0116] S200: A thermally conductive structure is formed on the second chip.

[0117] Referring to Figure 12, in the chip first process, forming a thermally conductive structure on the second chip 30 includes forming a second substrate 50 on the second wiring layer 40 and, after removing the first substrate 10, forming a thermally conductive structure on the first wiring layer 20.

[0118] Referring to Figure 16, in the chip last process, forming a thermally conductive structure on the second chip 30 includes directly forming the thermally conductive structure on the first wiring layer 20. Up to this point, the difference between the chip first and chip last processes is that in the chip first process, there is an adhesive layer 31 between the second chip 30 and the first wiring layer 20; in the chip last process, there is no adhesive layer 31 between the second chip 30 and the first wiring layer 20. However, the steps for forming the thermally conductive structure are the same in both processes. The following description will use the chip first process as an example.

[0119] Referring to Figure 17, in the two processes described above, a thermally conductive structure 60 is formed on the first wiring layer 20 using surface-mount technology (SMT). Since the first wiring layer 20 includes an insulating organic material PI and a conductive first line 21, it is understood that the formed thermally conductive structure 60 is insulated from the first line 21 in the first wiring layer 20.

[0120] The formation of the thermally conductive structure 60 includes forming a first thermally conductive portion 61 on the first wiring layer 20. The extension direction of the first thermally conductive portion 61 is parallel to the plane where the second chip 30 is located. The first thermally conductive portion 61 is strip-shaped and its extension direction is parallel to the plane where the second chip 30 is located. The first thermally conductive portion 61 has a first end and a second end in its extension direction.

[0121] A second thermally conductive portion 62 is formed at the first end of the first thermally conductive portion 61, so that the second thermally conductive portion 62 is connected to the first end, and the extending direction of the second thermally conductive portion 62 is perpendicular to the plane where the second chip 30 is located.

[0122] A third heat-conducting portion 63 is formed at the second end of the first heat-conducting portion 61, and the third heat-conducting portion 63 is connected to the second end. The extension direction of the third heat-conducting portion 63 is perpendicular to the plane where the second chip 30 is located.

[0123] Within the plane containing the first heat-conducting portion 61, the second heat-conducting portion 62, and the third heat-conducting portion 63, the second heat-conducting portion 62, the first heat-conducting portion 61, and the third heat-conducting portion 63 are connected sequentially and arranged in a "U" shape. Through this arrangement, heat from the first heat-conducting portion 61 can be transferred to the second heat-conducting portion 62 and the third heat-conducting portion 63, improving the heat dissipation capability of the heat-conducting structure 60 for the first chip 70 and the second chip 30.

[0124] S300: A first chip is mounted on a thermally conductive structure, such that the thermally conductive structure is located between the first chip and the second chip.

[0125] Compare Figures 17 and 18, which are two schematic diagrams with perpendicular viewing angles. In S300, before mounting the first chip 70, a first pad 71 connected to the first line 21 in the first wiring layer 20 is formed. The first pad 71 includes a first sub-pad 711 and a second sub-pad 712. The arrangement direction of the first sub-pad 711 and the second sub-pad 712 is perpendicular to the extension direction of the first heat-conducting portion 61; that is, the first sub-pad 711 and the second sub-pad 712 are located on both sides of the first heat-conducting portion 61, respectively. Then, an underfill (UF) layer 701 is formed on the heat-conducting structure 60 to protect the first sub-pad 711 and the second sub-pad 712. The first chip 70 is then mounted on the underfill layer 701, and the first chip 70 and the first pad 71 are connected. The filler layer 701 can form circuits, and the first chip 70 can be connected to the first pad 71 through the circuits in the filler layer 701.

[0126] The arrangement direction of the first sub-pad 711 and the second sub-pad 712 is perpendicular to the extension direction of the first heat-conducting portion 61, so that the arrangement of the first heat-conducting portion 61 between the first chip 70 and the second chip 30 does not affect the connection between the first chip 70 and the first wiring layer 20.

[0127] S400: The first chip, the thermal conductive structure, and the second chip are encapsulated to form a molded component, and one end of the thermal conductive structure is exposed on the surface of the molded component; both the first chip and the second chip are located inside the molded component.

[0128] Referring to Figure 19, in S400, after forming the molding compound 80, the side of the molding compound 80 near the first chip 70 is ground to expose the end of the second heat-conducting portion 62 away from the first heat-conducting portion 61, and the end of the third heat-conducting portion 63 away from the first heat-conducting portion 61. Since the first heat-conducting portion 61 is located between the first chip 70 and the second chip 30, the heat from the first chip 70 and the second chip 30 can be transferred to the first heat-conducting portion 61, and the heat on the first heat-conducting portion 61 can be transferred to the second heat-conducting portion 62 and the third heat-conducting portion 63, and then transferred to the outside of the molding compound 80 through the exposed end of the second heat-conducting portion 62 and the exposed end of the third heat-conducting portion 63, thereby improving the heat dissipation capability of the heat-conducting structure 60 for the first chip 70 and the second chip 30.

[0129] Referring to FIG20, the manufacturing method of the electronic device 100 provided in this embodiment further includes backend processing, namely, removing the second substrate 50. The method of removing the second substrate 50 may include lasering the second separation layer 52 to remove the second glass 51. In the embodiment where the second substrate 50 includes a second buffer layer 53, removing the second substrate 50 may also include removing part of the second buffer layer 53 by grinding to expose the second line 41 and the third line 42 located in the second wiring layer 40.

[0130] In the above embodiments, the manufacturing method further includes ball mounting (BM) on the side of the second wiring layer 40 away from the first wiring layer 20.

[0131] The second wiring layer 40 includes a second pad 411 formed on the side opposite to the first wiring layer 20, which is connected to the second line 41. The second pad 411 is used to connect other devices. The first chip 70 is connected to the first wiring layer 20 through the first pad 71. The first wiring layer 20 is connected to the second wiring layer 40 through the contact structure 22. The second wiring layer 40 is connected to other devices through the second pad 411, thus realizing the lead-out of the first chip 70 in the electronic device 100.

[0132] It also includes forming a fourth pad 421 on the side of the second wiring layer 40 opposite to the first wiring layer 20, which is connected to the third line 42. The fourth pad 421 is used to connect other devices. The second chip 30 is connected to the second wiring layer 40 through the third pad 32, and the second wiring layer 40 is connected to other devices through the fourth pad 421, realizing the extraction of the second chip 30 in the electronic device 100.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An electronic device, characterized in that, include: Plastic-sealed parts; A first chip and a second chip, both located within the plastic package, are stacked together. A thermally conductive structure is located between the first chip and the second chip, with one end of the thermally conductive structure exposed on the surface of the molding compound.

2. The electronic device according to claim 1, characterized in that, The electronic device further includes a first wiring layer, which is located between the first chip and the second chip, and the first chip and the second chip are connected through the first wiring layer. The thermal conductive structure is located between the first wiring layer and the first chip.

3. The electronic device according to claim 2, characterized in that, The first chip has a first sub-pad and a second sub-pad on the side facing the first wiring layer. Both the first sub-pad and the second sub-pad are connected to the first wiring layer. The first sub-pad and the second sub-pad are spaced apart. The heat-conducting structure is located between the first sub-pad and the second sub-pad.

4. The electronic device according to claim 3, characterized in that, The thermally conductive structure includes a first thermally conductive portion located between the first wiring layer and the first chip. The extension direction of the first thermally conductive portion is perpendicular to the arrangement direction of the first sub-pad and the second sub-pad. One end of the first thermally conductive portion in its extension direction is exposed on the surface of the molding compound.

5. The electronic device according to claim 3, characterized in that, The thermally conductive structure further includes a first thermally conductive portion and a second thermally conductive portion. The second thermally conductive portion is connected to one end of the thermally conductive structure, and the end of the second thermally conductive portion away from the first thermally conductive portion is exposed on the surface of the molding compound away from the second chip.

6. The electronic device according to claim 5, characterized in that, The thermally conductive structure further includes a third thermally conductive portion. The first thermally conductive portion has a first end and a second end in its extending direction. The second thermally conductive portion is connected to the first end. The third thermally conductive portion is connected to the second end. One end of the third thermally conductive portion away from the first thermally conductive portion is exposed on the surface of the molding compound away from the second chip.

7. The electronic device according to claim 6, characterized in that, The extension direction of the first heat-conducting portion is perpendicular to the arrangement direction of the first sub-pad and the second sub-pad; the extension direction of the second heat-conducting portion is perpendicular to the extension direction of the first heat-conducting portion. The extension direction of the third heat-conducting part is perpendicular to the extension direction of the first heat-conducting part.

8. The electronic device according to claim 1, characterized in that, The electronic device further includes a first wiring layer, which is located between the first chip and the second chip, and the first chip and the second chip are connected through the first wiring layer. The thermal conductive structure is located between the first wiring layer and the second chip.

9. The electronic device according to any one of claims 2-8, characterized in that, The electronic device further includes a second wiring layer and a contact structure. The second wiring layer is located on the side of the second chip opposite to the first chip. The second chip is connected to the second wiring layer. The contact structure connects the second wiring layer and the first wiring layer.

10. The electronic device according to claim 9, characterized in that, The electronic device further includes an adhesive layer located between the second chip and the first wiring layer.

11. A method for manufacturing an electronic device, characterized in that, include: Install a second chip; A thermally conductive structure is formed on the second chip; A first chip is mounted on the heat-conducting structure, such that the heat-conducting structure is located between the first chip and the second chip; The first chip, the thermal conductive structure, and the second chip are encapsulated to form a molded package, with one end of the thermal conductive structure exposed on the surface of the molded package; both the first chip and the second chip are located inside the molded package.

12. The method for manufacturing an electronic device according to claim 11, characterized in that, The formation of the thermally conductive structure includes: A first heat-conducting portion is formed, the extension direction of the first heat-conducting portion is parallel to the plane where the second chip is located, and the first heat-conducting portion has a first end and a second end in its extension direction. A second heat-conducting portion is formed, and the second heat-conducting portion is connected to the first end. The extension direction of the second heat-conducting portion is perpendicular to the plane where the second chip is located. A third heat-conducting portion is formed, and the third heat-conducting portion is connected to the second end. The extension direction of the third heat-conducting portion is perpendicular to the plane where the second chip is located.

13. The method for manufacturing an electronic device according to claim 11, characterized in that, The installation of the second chip includes: Provide a first substrate; A first wiring layer is formed on the first substrate; A contact structure is formed, and a second chip is mounted on the first wiring layer; A second wiring layer is formed, and the formed second wiring layer is connected to the first wiring layer through the contact structure.

14. The method for manufacturing an electronic device according to claim 13, characterized in that, The formation of the thermally conductive structure on the second chip includes: A second substrate is formed on the second wiring layer, and the first substrate is removed; A thermally conductive structure is formed on the first wiring layer.

15. The method for manufacturing an electronic device according to claim 11, characterized in that, The installation of the second chip includes: Provide a second substrate; A second wiring layer is formed on the second substrate; A second chip is mounted on the second wiring layer, and a contact structure is formed thereon; A first wiring layer is formed, and the first wiring layer is connected to the second wiring layer through the contact structure.

16. The method for manufacturing an electronic device according to claim 15, characterized in that, The step of forming a thermally conductive structure on the second chip includes forming a thermally conductive structure on the first wiring layer.

17. An electronic device, characterized in that, The electronic device includes a heat sink and an electronic device as described in any one of claims 1-10, wherein the heat sink is connected to the heat-conducting structure.

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