Simulation method and apparatus for semiconductor device containing quantum confinement region, and device

Abstract

Disclosed in the embodiments of the present disclosure are a simulation method and apparatus for a semiconductor device containing a quantum confinement region, and a device. The method comprises: on the basis of information of a target location in which at least one quantum confinement region is located, partitioning into at least two structural sub-models a structural model corresponding to a semiconductor device to be simulated; for an interface region between the structural sub-models, the spatial locations of which are adjacent, generating at least one low-dimensional mesh element, so as to form a low-dimensional mesh, and on the basis of the low-dimensional mesh, generating a high-dimensional mesh element for the adjacent structural sub-models, so as to form a high-dimensional mesh, such that a target structural model corresponding to said semiconductor device is obtained when the meshes are constructed; and determining, on the basis of a preset electrical energy equation set, the electrical energy distribution at each mesh point in the target structural model corresponding to said semiconductor device. Performance loss caused by interpolation between two meshes in different dimensions during the numerical simulation solving of a semiconductor device is avoided, thereby improving the computational efficiency and numerical accuracy of the simulation of the semiconductor device.

Description

Simulation methods, apparatus and equipment for semiconductor devices containing quantum bound regions

[0001] This invention claims priority to Chinese Patent Application No. 2024115445586, filed with the Chinese Patent Office on October 31, 2024, entitled “Simulation Method, Apparatus and Device for Semiconductor Devices Containing Quantum Binding Regions”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor simulation technology, and in particular to a method, apparatus and device for simulating semiconductor devices containing quantum-bound regions. Background Technology

[0003] With the rapid development of computer technology, semiconductor device models corresponding to physical semiconductor devices can be designed in semiconductor device simulation platforms. The performance of these models can then be explored through numerical simulation algorithms, helping engineers and scientists better understand and optimize semiconductor device designs. Near the interfaces of different materials in many semiconductor devices, due to their small size or drastic changes in band structure, quantum confinement effects exhibit significant influences on device performance. These effects can be modeled and calculated in semiconductor device simulation platforms.

[0004] Currently, for semiconductor devices exhibiting quantum binding effects, a common simulation method involves solving an additional low-dimensional partial differential equation besides the overall high-dimensional equations for the device. For example, an additional low-dimensional grid is generated within the quantum binding region of a high-dimensional grid (representing the semiconductor device model); the overall high-dimensional equations for the device are solved on the high-dimensional grid, and the quantum binding equations are solved on the low-dimensional grid; interpolation is performed between the two grids, using the solution from one grid as the parameter for the other; this process is repeated until a self-consistent solution is found.

[0005] However, existing techniques require repeated interpolation between two different dimensional grids, resulting in a loss of simulation efficiency and accuracy. Furthermore, the process of simulating semiconductor devices involves solving equations separately on two different dimensional grids, slowing down the convergence speed. Therefore, there are technical problems with slow simulation efficiency and low accuracy for semiconductor devices containing quantum-bound regions. Summary of the Invention

[0006] This invention provides a method, apparatus, and device for simulating semiconductor devices containing quantum-bound regions, in order to avoid performance loss caused by interpolation between two different dimensional grids during the numerical simulation of semiconductor devices, thereby improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0007] In a first aspect, embodiments of the present invention provide a simulation method for a semiconductor device including a quantum-bound region, the method comprising:

[0008] Based on the target location information of at least one quantum confinement region, the structural model of the semiconductor device to be simulated is divided into at least two structural sub-models.

[0009] For the boundary region between spatially adjacent structural sub-models, at least one low-dimensional mesh cell is generated in the boundary region to form a low-dimensional mesh. Based on the low-dimensional mesh, at least one high-dimensional mesh cell is generated for each of the adjacent structural sub-models to form a high-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional mesh cell includes at least two mesh points and connecting edges between each mesh point, and the high-dimensional mesh cell includes at least three mesh points and connecting edges between each mesh point.

[0010] Based on a preset set of electrical energy equations, the electrical energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated is determined.

[0011] Secondly, embodiments of the present invention also provide a simulation apparatus comprising a semiconductor device with a quantum binding region, the apparatus comprising:

[0012] The sub-model partitioning module is used to divide the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region.

[0013] A mesh cell generation module is used to generate at least one low-dimensional mesh cell in the boundary region between spatially adjacent structural sub-models to form a low-dimensional mesh, and to generate at least one high-dimensional mesh cell for each of the adjacent structural sub-models based on the low-dimensional mesh to form a high-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional mesh cell includes at least two mesh points and connecting edges between each mesh point, and the high-dimensional mesh cell includes at least three mesh points and connecting edges between each mesh point.

[0014] The model simulation module is used to determine the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated, based on a preset set of power equations.

[0015] Thirdly, embodiments of the present invention also provide an electronic device, the electronic device comprising:

[0016] One or more processors;

[0017] Storage device for storing one or more programs.

[0018] When one or more programs are executed by one or more processors, the one or more processors implement a simulation method for a semiconductor device containing a quantum-bound region, as described in any of the embodiments of the present invention.

[0019] Fourthly, embodiments of the present invention also provide a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a simulation method for a semiconductor device containing a quantum-bound region as described in any of the embodiments of the present invention.

[0020] The technical solution of this invention divides the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region. Then, for the boundary region between spatially adjacent structural sub-models, at least one low-dimensional grid cell is generated in the boundary region to form a low-dimensional grid. Based on the low-dimensional grid, at least one high-dimensional grid cell is generated for each adjacent structural sub-model to form a high-dimensional grid. When the grid construction is complete, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional grid cell includes at least two grid points and connecting edges between each grid point, and the high-dimensional grid cell includes at least three grid points and connecting edges between each grid point. Thus, based on a preset set of electrical energy equations, the electrical energy distribution information at each grid point in the target structural model corresponding to the semiconductor device to be simulated is determined. In this embodiment, when generating grid cells for the structural model corresponding to the semiconductor device, the quantum confinement region is used as a reference for grid generation, ensuring that the high-dimensional grid of the device in the semiconductor device model matches the low-dimensional grid corresponding to the quantum confinement region. This avoids performance loss caused by interpolation between two different dimensional grids, improving the computational efficiency and numerical accuracy of semiconductor device simulation. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of exemplary embodiments of the present invention, the accompanying drawings used in describing the embodiments are briefly introduced below. Obviously, the accompanying drawings described are only a portion of the drawings of the embodiments to be described in this invention, and not all of the drawings. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0022] Figure 1 is a schematic flowchart of a simulation method for a semiconductor device containing a quantum confinement region provided in an embodiment of the present invention;

[0023] Figure 2 is a schematic diagram of the structural model division including a quantum confinement region involved in the embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of the structural model division including two quantum binding regions involved in the embodiment of the present invention;

[0025] Figure 4 is a schematic flowchart of another simulation method for a semiconductor device containing a quantum-bound region provided by an embodiment of the present invention;

[0026] Figure 5 is a schematic flowchart of another simulation method for a semiconductor device containing a quantum-bound region provided by an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of the structure of a simulation device containing a quantum-bound region semiconductor device provided in an embodiment of the present invention;

[0028] Figure 7 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0029] Figure 1 is a schematic flowchart of a simulation method for a semiconductor device containing a quantum bound region provided by an embodiment of the present invention. This embodiment is applicable to situations where numerical simulation of a semiconductor device containing a quantum bound region is required. The method can be executed by a simulation device, which can be implemented in the form of software, hardware, or a combination of software and hardware. The hardware can be an electronic device, such as a mobile terminal, a PC, or a server.

[0030] As shown in Figure 1, the simulation method for this semiconductor device containing a quantum-bound region includes:

[0031] S110. Based on the target location information of at least one quantum confinement region, the structural model of the semiconductor device to be simulated is divided into at least two structural sub-models.

[0032] Near the interfaces between different materials in many semiconductor devices, due to their small size or drastic changes in band structure, a quantum binding effect that significantly impacts device performance can occur. This specific region is called the quantum bound region. It's important to note that if the semiconductor device is three-dimensional, the quantum bound region is a two-dimensional surface; if the semiconductor device is two-dimensional, the quantum bound region is a one-dimensional point. In other words, the quantum bound region necessarily has one less dimension than the semiconductor device itself.

[0033] The semiconductor device to be simulated is the semiconductor device that will be subjected to numerical simulation. The structural model is a model used to characterize the structure of the semiconductor device to be simulated. For example, the structural model corresponding to the semiconductor device to be simulated can be a three-dimensional structural model, with the quantum confinement region being a two-dimensional surface; or it can be a two-dimensional structural model, with the quantum confinement region being a one-dimensional point. Target location information indicates the location of the quantum confinement region within the structural model. The structural model can be divided into two or more structural sub-models.

[0034] Specifically, a structural model corresponding to the semiconductor device to be simulated can be drawn in the semiconductor device simulation platform based on the actual spatial shape of the semiconductor device to be simulated. According to the characteristics of the quantum binding region (the quantum binding region is located in a narrow transition region), it is possible to determine which quantum binding regions are included in the model structure. Therefore, the structural model can be divided into two or more structural sub-models based on the quantum binding regions.

[0035] Optionally, based on the target location information of at least one quantum confinement region, the structural model corresponding to the semiconductor device to be simulated is divided into at least two structural sub-models, including: obtaining the structural model corresponding to the semiconductor device to be simulated; in response to the triggering operation on the structural model, determining the triggered position as the target location information of the quantum confinement region; and dividing the structural model into at least two structural sub-models based on at least one target location information.

[0036] In the following embodiments, a three-dimensional structural model corresponding to the semiconductor device to be simulated is used as an example for illustration. Based on the structural model corresponding to the semiconductor device to be simulated drawn in the semiconductor device simulation platform, this structural model can be obtained and displayed on the current display page. The user can trigger any position on the structural model in the current display. When a click is detected at a certain position, the position coordinates corresponding to this triggered position can be determined as the target position information of the quantum binding region. If the structural model includes multiple quantum binding regions, the user can perform multiple trigger operations to obtain the target position information corresponding to multiple quantum binding regions. Based on this, the cross-sections corresponding to the target position information can be determined, and the structural model can be divided into two or more structural sub-models based on these cross-sections. More specifically, if it is determined that the structural model includes one quantum binding region, the structural model can be divided into two structural sub-models; if it is determined that the structural model includes two quantum binding regions, the structural model can be divided into three structural sub-models; if it is determined that the structural model includes three quantum binding regions, the structural model can be divided into four structural sub-models, and so on.

[0037] For example, a schematic diagram of the structural model partitioning including one quantum binding region is shown in Figure 2. As shown in Figure 2, one quantum binding region divides the structural model into structural sub-model A and structural sub-model B. A schematic diagram of the structural model partitioning including two quantum binding regions is shown in Figure 3. As shown in Figure 3, two quantum binding regions divide the structural model into structural sub-model R, structural sub-model T, and structural sub-model Y.

[0038] S120. For the boundary region between adjacent structural sub-models in spatial location, generate at least one low-dimensional mesh unit in the boundary region to form a low-dimensional mesh, and generate at least one high-dimensional mesh unit for each adjacent structural sub-model based on the low-dimensional mesh to form a high-dimensional mesh. When the mesh construction is completed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0039] In this design, the spatial dimension of the high-dimensional mesh is consistent with the spatial dimension of the structural model corresponding to the semiconductor device being simulated. The spatial dimension of the low-dimensional mesh is one dimension lower than that of the high-dimensional mesh.

[0040] Low-dimensional mesh cells are the basic units that make up low-dimensional networks. High-dimensional mesh cells are the basic units that make up high-dimensional networks. A low-dimensional mesh cell consists of at least two mesh points and connecting edges between them, while a high-dimensional mesh cell consists of at least three mesh points and connecting edges between them. For example, a three-dimensional mesh cell can be a triangular prism or a tetrahedron; a two-dimensional mesh cell can be a triangular facet, a quadrilateral facet, etc.; and a one-dimensional mesh cell can be a line. Each vertex in a mesh cell can be called a mesh point.

[0041] More specifically, if the structural model corresponding to the semiconductor device to be simulated is a two-dimensional structural model, then a high-dimensional mesh refers to a two-dimensional mesh, and a high-dimensional mesh cell includes at least 3 mesh points and connecting edges between each mesh point; a low-dimensional mesh refers to a one-dimensional mesh, and a low-dimensional mesh cell includes at least 2 mesh points and connecting edges between each mesh point.

[0042] If the structural model of the semiconductor device to be simulated is a three-dimensional structural model, then the high-dimensional mesh refers to the three-dimensional mesh, and the high-dimensional mesh cell includes at least 4 mesh points and the connecting edges between each mesh point. The low-dimensional mesh refers to the two-dimensional mesh, and the low-dimensional mesh cell includes at least 3 mesh points and the connecting edges between each mesh point.

[0043] The target structural model is the model generated by processing the structural model of the semiconductor device to be simulated with high-dimensional mesh and low-dimensional generation.

[0044] Specifically, the following section will take the three-dimensional structural model of the semiconductor device to be simulated as an example to illustrate how to generate and construct low-dimensional and high-dimensional meshes to obtain the target structural model corresponding to the semiconductor device to be simulated.

[0045] If a 3D structural model includes a quantum binding surface, multiple reference grid points can be determined on this surface. Connection edges between these reference grid points are then established, resulting in multiple 2D grid cells, which together form a 2D mesh. The structural sub-model with the quantum binding surface as its right face can be called the first structural sub-model, and the structural sub-model with the quantum binding surface as its left face can be called the second structural sub-model. For the first structural sub-model, multiple 3D grid cells are generated to the left, starting from the reference grid points on these 2D grids, forming a 3D mesh. For the second structural sub-model, multiple 3D grid cells are generated to the right, starting from the reference grid points on these 2D grids, forming a 3D mesh. When all 3D and 2D meshes are constructed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0046] If the structural model includes two quantum bound surfaces, multiple reference grid points can be determined on each quantum bound surface. Connection edges between these reference grid points are then established, resulting in multiple two-dimensional grid cells. These two-dimensional grid cells constitute a two-dimensional grid corresponding to each quantum bound surface. For the leftmost structural sub-model, multiple three-dimensional grid cells are generated to the left, starting from the multiple reference grid points on the two-dimensional grid to the right of the sub-model. For the middle structural sub-model, three-dimensional grid cells are generated to the right, starting from the reference grid points on the two-dimensional grid to the left of the sub-model, with the generation endpoint coinciding with the reference grid points on the two-dimensional grid to the right of the sub-model. For the rightmost structural sub-model, multiple three-dimensional grid cells are generated to the right, starting from the multiple reference grid points on the two-dimensional grid to the left of the sub-model. Similarly, when the structural model includes more than two quantum bound surfaces, how to generate and construct low-dimensional and high-dimensional grids to obtain the target structural model corresponding to the semiconductor device to be simulated is also discussed.

[0047] S130. Based on the preset set of electrical energy equations, determine the electrical energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated.

[0048] The preset electrical energy equations are a set of pre-defined equations used to determine the electrical energy simulation parameters of the semiconductor device to be simulated. The electrical energy distribution information includes the potential information, electron concentration information, and hole concentration information for each grid point.

[0049] In this embodiment, the preset set of electrical energy equations can be expressed as:

[0050]

[0051] The preset set of electrical energy equations includes: first equation (1), second equation (2), third equation (3), fourth equation (4), and fifth equation (5).

[0052] In the formula, This represents the permittivity of the material used in the semiconductor device being simulated. This represents the potential information at the i-th grid point. Indicates the amount of charge in the elementary element. =1.6021892 × 10 -19 C, This represents the first electron concentration information at the i-th grid point. This represents the second electron concentration information at the i-th grid point. This represents the hole concentration information at the i-th grid point. This represents the second hole concentration information at the i-th grid point. This indicates the concentration of the acceptor dopant in the semiconductor device to be simulated. This indicates the concentration of the donor-type dopant in the semiconductor device to be simulated. A function representing the amount of electrons generated and recombine. A function representing the generation and recombination of holes. A function representing the electric current intensity of electrons. A function representing the current intensity of holes. A function representing the quantum well trapping rate of electrons. This represents a function of the quantum well trapping rate of holes. It should be noted that... , , , as well as Each of them has a fixed physical expression, which will not be elaborated here.

[0053] It should be noted that if the structural model of the semiconductor device to be simulated is a three-dimensional structural model, then the first hole concentration information is the hole concentration information corresponding to the three-dimensional grid point, and the second hole concentration information is the hole concentration information corresponding to the two-dimensional grid point; if the structural model of the semiconductor device to be simulated is a two-dimensional structural model, then the first hole concentration information is the hole concentration information corresponding to the two-dimensional grid point, and the second hole concentration information is the hole concentration information corresponding to the one-dimensional grid point.

[0054] In this embodiment, based on the target structure model corresponding to the semiconductor device to be simulated, certain processing conditions can be given. For example, under a specified voltage, the power distribution information at each grid point in the target structure model can be calculated by solving a set of preset power equations.

[0055] Optionally, the specific implementation method for determining the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated, based on a preset set of power equations, may include: for each grid point in the target structure model, if the current grid point is located on a low-dimensional grid, then the potential information, first electron concentration information, second electron concentration information, first hole concentration information, and second hole concentration information corresponding to the current grid point are calculated based on the preset set of power equations; if the current grid point is located on a non-low-dimensional grid, then the second electron concentration information and second hole concentration information in the preset set of power equations are initialized, and the potential information, first electron concentration information, and first hole concentration information corresponding to the current grid point are calculated based on the first equation, the second equation, and a third-party program.

[0056] In this embodiment, the processing procedure for each grid point is the same. Here, we take any one of the grid points as the current grid point and illustrate it as an example. If the current grid point is located on a low-dimensional grid, that is, the current grid point is the reference grid point on the quantum bound surface, then according to the given processing conditions and the preset set of electrical energy equations (5 equations), the potential information, first electron concentration information, second electron concentration information, first hole concentration information, and second hole concentration information (5 independent variables) corresponding to the current grid point are calculated.

[0057] It is understandable that, taking a three-dimensional structural model of the semiconductor device to be simulated as an example, the reference grid point located on the quantum binding surface is both the grid point corresponding to the corresponding structural sub-model (three-dimensional model) and the grid point corresponding to the quantum binding surface (two-dimensional surface). Based on this, the first electron concentration information represents the electron concentration distribution information of the current grid point in the corresponding structural sub-model, and the second electron concentration information represents the electron concentration distribution information of the current grid point on the corresponding quantum binding surface. Similarly, the first hole concentration information represents the hole concentration distribution information of the current grid point in the corresponding structural sub-model, and the second hole concentration information represents the hole concentration distribution information of the current grid point on the corresponding quantum binding surface.

[0058] If the current grid point is located on a non-low-dimensional grid, the second electron concentration information and the second hole concentration information in the preset energy equations can be initialized. For example, the initialization process can include, but is not limited to, zeroing initialization. In this case, the preset energy equations can be expressed as:

[0059]

[0060] Therefore, based on the given processing conditions and the preset set of electrical energy equations (3 equations), the potential information, first electron concentration information, and first hole concentration information (3 independent variables) corresponding to the current grid point can be calculated.

[0061] The technical solution of this invention divides the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region. Then, for the boundary region between spatially adjacent structural sub-models, at least one low-dimensional grid cell is generated in the boundary region to form a low-dimensional grid. Based on the low-dimensional grid, at least one high-dimensional grid cell is generated for each adjacent structural sub-model to form a high-dimensional grid. When the grid construction is complete, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional grid cell includes at least two grid points and connecting edges between each grid point, and the high-dimensional grid cell includes at least three grid points and connecting edges between each grid point. Thus, based on a preset set of electrical energy equations, the electrical energy distribution information at each grid point in the target structural model corresponding to the semiconductor device to be simulated is determined. In this embodiment, when generating grid cells for the structural model corresponding to the semiconductor device, the quantum confinement region is used as a reference for grid generation, ensuring that the high-dimensional grid of the device in the semiconductor device model matches the low-dimensional grid corresponding to the quantum confinement region. This avoids performance loss caused by interpolation between two different dimensional grids, improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0062] Example 2

[0063] Figure 4 is a schematic diagram of a simulation method for a semiconductor device containing a quantum bound region provided by an embodiment of the present invention. Based on the foregoing embodiment, S120 is further refined, and its specific implementation can be found in the technical solution of this embodiment. Technical terms that are the same as or corresponding to those in the above embodiments will not be repeated here.

[0064] As shown in Figure 4, the method specifically includes the following steps:

[0065] S210. Based on the target location information of at least one quantum confinement region, the structural model of the semiconductor device to be simulated is divided into at least two structural sub-models.

[0066] In this embodiment, when the structural model is a three-dimensional structural model and the semiconductor device to be simulated includes a quantum confinement region, the specific implementation method of the target structural model corresponding to the semiconductor device to be simulated is determined as shown in S220-S240.

[0067] S220. For the first and second structural sub-models that are spatially adjacent, the boundary region between the two structural sub-models is defined as the quantum binding surface.

[0068] In this embodiment, the first structural sub-model is distinguished from the second structural sub-model. For example, continuing to refer to Figure 2, the structural sub-model located on the left can be designated as the first structural sub-model, and the structural sub-model located on the right can be designated as the second structural sub-model. The boundary region between these two structural sub-models is defined as the quantum binding surface.

[0069] S230. Based on multiple reference grid points on the quantum bound surface, generate at least one two-dimensional grid cell to form a two-dimensional grid.

[0070] In this embodiment, multiple grid reference points can be determined on the quantum confinement surface according to a preset method. For example, the preset method could be: randomly determining a preset number of reference grid points, or determining a preset number of reference grid points at equal intervals. Furthermore, connection edges are established between these reference grid points to obtain multiple two-dimensional grid cells, which together constitute a two-dimensional grid.

[0071] S240. Based on the two-dimensional mesh, at least one three-dimensional mesh element is generated for the first structural sub-model and the second structural sub-model to form a three-dimensional mesh. When all the three-dimensional meshes and two-dimensional meshes are completed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0072] In this embodiment, multiple reference grid points on a two-dimensional grid can be used as the starting point for generation to generate multiple three-dimensional grid units for the first structural sub-model and the second structural sub-model. After the grid generation is completed, the target three-dimensional structural model corresponding to the semiconductor device to be simulated is obtained.

[0073] Specifically, the specific implementation of generating at least one three-dimensional mesh unit for the first structural sub-model and the second structural sub-model based on a two-dimensional mesh may include: for the first structural sub-model, generating at least one three-dimensional mesh unit for the first structural sub-model by taking each reference mesh point on the two-dimensional mesh as the generation starting point and along the direction toward the first structural sub-model; for the second structural sub-model, generating at least one three-dimensional mesh unit for the second structural sub-model by taking each reference mesh point on the two-dimensional mesh as the generation starting point and along the direction toward the second structural sub-model.

[0074] Based on the above example, referring to Figure 2, for the first structural sub-model, multiple three-dimensional mesh elements can be generated from each reference mesh point on the two-dimensional mesh along the leftward direction. For the second structural sub-model, multiple three-dimensional mesh elements can be generated from each reference mesh point on the two-dimensional mesh along the rightward direction. When all the three-dimensional and two-dimensional meshes are constructed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0075] Specifically, if the structural model is a two-dimensional structural model, and the semiconductor device to be simulated includes a quantum binding region, at least one low-dimensional grid cell is generated in the boundary region between spatially adjacent structural sub-models to form a low-dimensional grid. Based on the low-dimensional grid, at least one high-dimensional grid cell is generated for each adjacent structural sub-model to form a high-dimensional grid. When the grid construction is completed, the target structural model corresponding to the semiconductor device to be simulated can also include: for spatially adjacent first and second structural sub-models, the boundary region between the two structural sub-models is determined as a quantum binding line; based on multiple reference grid points on the quantum binding line, at least one one-dimensional grid cell is generated to form a one-dimensional grid; based on the one-dimensional grid, at least one two-dimensional grid cell is generated for each of the first and second structural sub-models to form a two-dimensional grid. When the grid construction is completed, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0076] S250. Based on the preset set of electrical energy equations, determine the electrical energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated.

[0077] The technical solution of this invention, when generating at least one mesh element for each structural sub-model based on the boundary region between spatially adjacent structural sub-models, includes a quantum-bound region in the semiconductor device to be simulated. For a first and a second structural sub-model that are spatially adjacent, the boundary region between the two structural sub-models is defined as a quantum-bound surface. Then, based on multiple reference mesh points on the quantum-bound surface, at least one two-dimensional mesh element is generated to form a two-dimensional mesh. Subsequently, based on the two-dimensional mesh, at least one three-dimensional mesh element is generated for each of the first and second structural sub-models to form a three-dimensional mesh. When the mesh construction is complete, a target structural model corresponding to the semiconductor device to be simulated is obtained. The technical solution provided in this embodiment, when including a quantum-bound region, allows mesh generation using this quantum-bound region as a reference, ensuring that the high-dimensional mesh of the semiconductor device model matches the low-dimensional mesh corresponding to the quantum-bound region. This avoids performance loss caused by interpolation between two different-dimensional meshes, improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0078] Example 3

[0079] Figure 5 is a schematic diagram of a simulation method for a semiconductor device containing a quantum bound region provided by an embodiment of the present invention. Based on the foregoing embodiment, S120 is further refined, and its specific implementation can be found in the technical solution of this embodiment. Technical terms that are the same as or corresponding to those in the above embodiments will not be repeated here.

[0080] As shown in Figure 5, the method specifically includes the following steps:

[0081] S310. Based on the target location information of at least one quantum confinement region, the structural model of the semiconductor device to be simulated is divided into at least two structural sub-models.

[0082] In this embodiment, when the structural model is a three-dimensional structural model and the semiconductor device to be simulated includes two or more quantum confinement regions, the specific implementation method of the target structural model corresponding to the semiconductor device to be simulated is determined as shown in S320-S240.

[0083] S320. For each structural sub-model, the boundary region between two spatially adjacent structural sub-models is defined as a quantum binding surface, and multiple reference grid points are defined on each quantum binding surface to form a two-dimensional grid.

[0084] In this embodiment, for each structural sub-model included in the structural model, the boundary region between two spatially adjacent structural sub-models can be defined as a quantum binding surface, thereby obtaining multiple quantum binding surfaces. For example, referring to Figure 3, a first quantum binding surface between structural sub-model R and structural sub-model T, and a second quantum binding surface between structural sub-model T and structural sub-model Y can be obtained. Furthermore, multiple reference grid points can be determined on each quantum binding surface based on a preset method, and then connection edges can be established between these reference grid points to obtain multiple two-dimensional grid cells, which constitute a two-dimensional grid corresponding to each quantum binding surface.

[0085] S330. For the third structural sub-model of the first side, generate multiple three-dimensional mesh elements for the third structural sub-model based on the reference mesh points of the corresponding two-dimensional mesh.

[0086] In this embodiment, for the third structural sub-model located on the first edge side, multiple three-dimensional mesh units can be generated for the third structural sub-model by taking the reference mesh points on the quantum binding surface corresponding to the third structural sub-model as the generation starting point and moving along the direction toward the third structural sub-model. For example, continuing to refer to Figure 3, for the leftmost structural sub-model R, multiple three-dimensional mesh units can be generated for the structural sub-model R by taking the reference mesh points on the first quantum binding surface (two-dimensional mesh) as the generation starting point and moving along the leftward direction.

[0087] S340. For the fourth structural sub-model on the second side, generate multiple three-dimensional mesh elements for the fourth structural sub-model based on the reference mesh points on the corresponding two-dimensional mesh.

[0088] In this embodiment, for the fourth structural sub-model located on the second edge side, multiple four-dimensional mesh elements can be generated for the fourth structural sub-model by using the reference mesh points on the corresponding two-dimensional mesh as the generation starting point and moving along the direction towards the fourth structural sub-model. For example, continuing to refer to Figure 3, for the rightmost structural sub-model Y, multiple three-dimensional mesh elements can be generated for the structural sub-model Y by using the reference mesh points on the second quantum binding surface (two-dimensional mesh) as the generation starting point and moving along the direction to the right.

[0089] S350. For each intermediate structural sub-model located between two structural sub-models, generate at least one mesh element for the intermediate structural sub-model based on the reference mesh points on the two two-dimensional meshes corresponding to the intermediate structural sub-model.

[0090] In this embodiment, for each intermediate structural sub-model, a three-dimensional mesh cell is generated from a reference mesh point on the two-dimensional mesh on one side of the intermediate structural sub-model as the generation starting point, and the generation endpoint of the intermediate structural sub-model coincides with the reference mesh point on the two-dimensional mesh on the other side of the intermediate structural sub-model. For example, continuing to refer to Figure 3, for the structural sub-model T between structural sub-model R and structural sub-model Y, three-dimensional mesh cells can be generated to the right from each reference mesh point on the first quantum binding surface (two-dimensional mesh), and the generation endpoint of the structural sub-model T coincides with the reference mesh point on the second quantum binding surface (two-dimensional mesh).

[0091] S360. When each structural sub-model completes mesh generation, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0092] Specifically, if the structural model is a two-dimensional structural model, and the semiconductor device to be simulated includes at least two quantum binding regions, for the boundary regions between spatially adjacent structural sub-models, at least one low-dimensional grid cell is generated in the boundary regions to form a low-dimensional grid, and based on the low-dimensional grid, at least one high-dimensional grid cell is generated for each adjacent structural sub-model to form a high-dimensional grid. Obtaining the target structural model corresponding to the semiconductor device to be simulated when the grid construction is completed may also include: for each structural sub-model, determining the boundary region between two spatially adjacent structural sub-models as a quantum binding line, and determining multiple reference grid points on each quantum binding line to form a quantum binding line. One-dimensional mesh; for the third structural sub-model on the first side, multiple two-dimensional mesh elements are generated for the third structural sub-model based on the reference mesh points on the corresponding one-dimensional mesh; for the fourth structural sub-model on the second side, multiple two-dimensional mesh elements are generated for the fourth structural sub-model based on the reference mesh points on the corresponding one-dimensional mesh; for each intermediate structural sub-model located between two structural sub-models, multiple two-dimensional mesh elements are generated for the intermediate structural sub-model based on the reference mesh points on the two one-dimensional meshes corresponding to the intermediate structural sub-model; when each structural sub-model completes mesh generation, the target structural model corresponding to the semiconductor device to be simulated is obtained.

[0093] S370. Based on the preset set of electrical energy equations, determine the electrical energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated.

[0094] The technical solution of this invention, when generating at least one mesh element for each structural sub-model based on the boundary region between spatially adjacent structural sub-models, defines the boundary region between two spatially adjacent structural sub-models as a quantum binding surface, and determines multiple reference mesh points on each quantum binding surface to form a two-dimensional mesh; for the third structural sub-model on the first side, multiple three-dimensional mesh elements are generated for the third structural sub-model based on the reference mesh points on the corresponding two-dimensional mesh; for the fourth structural sub-model on the second side, multiple three-dimensional mesh elements are generated for the fourth structural sub-model based on the reference mesh points on the corresponding two-dimensional mesh; for each intermediate structural sub-model located between two structural sub-models, multiple three-dimensional mesh elements are generated for the intermediate structural sub-model based on the reference mesh points on the two two-dimensional meshes corresponding to the intermediate structural sub-model; when each structural sub-model completes mesh generation, a target structural model corresponding to the semiconductor device to be simulated is obtained. The technical solution provided in this embodiment, when including at least one quantum confinement region, can generate a mesh using each quantum confinement region as a reference benchmark, so that the high-dimensional mesh of the semiconductor device model matches the low-dimensional mesh corresponding to the quantum confinement region, avoiding the performance loss caused by interpolation between two different-dimensional meshes, and further improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0095] Example 4

[0096] Figure 6 is a schematic diagram of a simulation device for a semiconductor device containing a quantum bound region provided in an embodiment of the present invention. The device includes: a sub-model partitioning module 410, a mesh cell generation module 420, and a model simulation module 430.

[0097] The sub-model partitioning module 410 is used to divide the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region.

[0098] The mesh cell generation module 420 is used to generate at least one low-dimensional mesh cell in the boundary region between spatially adjacent structural sub-models to form a low-dimensional mesh, and to generate at least one high-dimensional mesh cell for each of the adjacent structural sub-models based on the low-dimensional mesh to form a high-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional mesh cell includes at least two mesh points and connecting edges between each mesh point, and the high-dimensional mesh cell includes at least three mesh points and connecting edges between each mesh point.

[0099] The model simulation module 430 is used to determine the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated, based on a preset set of power equations.

[0100] Based on the above-mentioned device, optionally, the sub-model partitioning module 410 includes:

[0101] The structural model acquisition unit is used to acquire the structural model corresponding to the semiconductor device to be simulated.

[0102] The target location determination unit is used to determine the triggered location as the target location information of the quantum binding region in response to the triggering operation on the structural model;

[0103] Sub-model partitioning unit, used to divide the structural model into at least two structural sub-models based on at least one target location information.

[0104] Based on the above-mentioned device, optionally, the structural model is a three-dimensional structural model, the semiconductor device to be simulated includes a quantum confinement region, and the mesh cell generation module 420 includes:

[0105] The quantum binding surface determination unit is used to determine the boundary region between two spatially adjacent first and second structural sub-models as the quantum binding surface.

[0106] A two-dimensional mesh generation unit is used to generate at least one two-dimensional mesh unit based on multiple reference mesh points on the quantum confinement surface to form a two-dimensional mesh;

[0107] The mesh unit is used to generate at least one three-dimensional mesh unit for the first structural sub-model and the second structural sub-model based on the two-dimensional mesh, so as to form a three-dimensional mesh, and obtain a target structural model corresponding to the semiconductor device to be simulated when the mesh is completed.

[0108] Based on the above-mentioned device, optionally, a mesh element generation unit is used to generate at least one three-dimensional mesh element for the first structural sub-model, taking each of the reference mesh points on the two-dimensional mesh as the generation starting point and along the direction toward the first structural sub-model; and to generate at least one three-dimensional mesh element for the second structural sub-model, taking each of the reference mesh points on the two-dimensional mesh as the generation starting point and along the direction toward the second structural sub-model.

[0109] Based on the above-mentioned device, optionally, the structural model is a three-dimensional structural model, the semiconductor device to be simulated includes at least two quantum confinement regions, and the mesh unit generation module 420 also includes:

[0110] A two-dimensional mesh determination unit is used to determine the boundary region between two spatially adjacent structural sub-models as a quantum binding surface for each of the structural sub-models, and to determine multiple reference mesh points on each quantum binding surface to form a two-dimensional mesh;

[0111] The first generation unit is used to generate multiple three-dimensional mesh units for the third structural sub-model on the first side, based on the reference mesh points on the corresponding two-dimensional mesh of the third structural sub-model.

[0112] The second generation unit is used to generate multiple three-dimensional mesh units for the fourth structural sub-model on the second side, based on the reference mesh points on the corresponding two-dimensional mesh of the fourth structural sub-model.

[0113] The third generation unit is used to generate multiple three-dimensional mesh units for each intermediate structural sub-model located between two structural sub-models, based on the reference mesh points on the two two-dimensional meshes corresponding to the intermediate structural sub-model.

[0114] The target model determination unit is used to obtain the target structural model corresponding to the semiconductor device to be simulated when each structural sub-model completes mesh generation.

[0115] Based on the above device, the optional preset set of electrical energy equations includes:

[0116] First equation: ;

[0117] Second equation: ;

[0118] Third equation: ;

[0119] Fourth equation: ;

[0120] Equation 5: ;

[0121] In the formula, This represents the permittivity of the material used in the semiconductor device being simulated. This represents the potential information at the i-th grid point. Indicates the amount of charge in the elementary element. =1.6021892 × 10 -19 C, This represents the first electron concentration information at the i-th grid point. This represents the second electron concentration information at the i-th grid point. This represents the hole concentration information at the i-th grid point. This represents the second hole concentration information at the i-th grid point. This indicates the concentration of the acceptor dopant in the semiconductor device to be simulated. This indicates the concentration of the donor-type dopant in the semiconductor device to be simulated. A function representing the amount of electrons generated and recombine. A function representing the generation and recombination of holes. A function representing the electric current intensity of electrons. A function representing the current intensity of holes. A function representing the quantum well trapping rate of electrons. A function representing the quantum well trapping rate of holes.

[0122] Based on the above-mentioned device, optionally, the model simulation module 430 is used to calculate the potential information, first electron concentration information, second electron concentration information, first hole concentration information, and second hole concentration information corresponding to each grid point in the target structure model if the current grid point is located on a low-dimensional grid; if the current grid point is located on a non-low-dimensional grid, the second electron concentration information and second hole concentration information in the preset energy equation set are initialized, and the potential information, first electron concentration information, and first hole concentration information corresponding to the current grid point are calculated based on the first equation, the second equation, and a third-party program.

[0123] The technical solution of this invention divides the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region. Then, for the boundary region between spatially adjacent structural sub-models, at least one low-dimensional grid cell is generated in the boundary region to form a low-dimensional grid. Based on the low-dimensional grid, at least one high-dimensional grid cell is generated for each adjacent structural sub-model to form a high-dimensional grid. When the grid construction is complete, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional grid cell includes at least two grid points and connecting edges between each grid point, and the high-dimensional grid cell includes at least three grid points and connecting edges between each grid point. Thus, based on a preset set of electrical energy equations, the electrical energy distribution information at each grid point in the target structural model corresponding to the semiconductor device to be simulated is determined. In this embodiment, when generating grid cells for the structural model corresponding to the semiconductor device, the quantum confinement region is used as a reference for grid generation, ensuring that the high-dimensional grid of the device in the semiconductor device model matches the low-dimensional grid corresponding to the quantum confinement region. This avoids performance loss caused by interpolation between two different dimensional grids, improving the computational efficiency and numerical accuracy of semiconductor device simulation.

[0124] The simulation apparatus for semiconductor devices containing quantum-bound regions provided in the embodiments of the present invention can execute the simulation method for semiconductor devices containing quantum-bound regions provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0125] It is worth noting that the various units and modules included in the above system are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of each functional unit are only for easy differentiation and are not used to limit the protection scope of the embodiments of the present invention.

[0126] Example 5

[0127] Figure 7 illustrates a schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described or claimed herein.

[0128] As shown in Figure 7, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0129] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet, various telecommunications networks, or combinations of computer networks and various telecommunications networks.

[0130] Processor 11 can be a variety of processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as target control object attitude control methods.

[0131] In some embodiments, the target object attitude control method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded or installed on electronic device 10 via ROM 12 or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the target object attitude control method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to execute the target object attitude control method by any other suitable means (e.g., by means of firmware).

[0132] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0133] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts or block diagrams to be performed. The computer programs can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0134] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0135] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0136] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0137] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0138] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0139] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

[0140] Example 6

[0141] This invention also provides a storage medium containing computer-executable instructions, which, when executed by a computer processor, are used to perform a simulation method for a semiconductor device containing a quantum-bound region, the method comprising:

[0142] Based on the target location information of at least one quantum confinement region, the structural model of the semiconductor device to be simulated is divided into at least two structural sub-models.

[0143] For the boundary region between spatially adjacent structural sub-models, at least one low-dimensional mesh cell is generated in the boundary region to form a low-dimensional mesh. Based on the low-dimensional mesh, at least one high-dimensional mesh cell is generated for each of the adjacent structural sub-models to form a high-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional mesh cell includes at least two mesh points and connecting edges between each mesh point, and the high-dimensional mesh cell includes at least three mesh points and connecting edges between each mesh point.

[0144] Based on a preset set of electrical energy equations, the electrical energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated is determined.

[0145] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0146] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0147] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0148] Computer program code for performing the operations of embodiments of the present invention can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, and C++—as well as conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0149] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A simulation method for a semiconductor device containing a quantum-bound region, comprising: Based on the target location information of at least one quantum confinement region, the structural model of the semiconductor device to be simulated is divided into at least two structural sub-models. For the boundary region between spatially adjacent structural sub-models, at least one low-dimensional mesh cell is generated in the boundary region to form a low-dimensional mesh. Based on the low-dimensional mesh, at least one high-dimensional mesh cell is generated for each of the adjacent structural sub-models to form a high-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional mesh cell includes at least two mesh points and connecting edges between each mesh point, and the high-dimensional mesh cell includes at least three mesh points and connecting edges between each mesh point. Based on a preset set of electrical energy equations, the electrical energy distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated is determined.

2. The method according to claim 1, characterized in that, The step involves dividing the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region, including: Obtain the structural model of the semiconductor device to be simulated; In response to a triggering operation on the structural model, the triggered location is determined as the target location information of the quantum binding region; The structure model is divided into at least two structural sub-models based on at least one of the target location information.

3. The method according to claim 1, characterized in that, The structural model is a three-dimensional structural model. The semiconductor device to be simulated includes a quantum confinement region. At least one low-dimensional mesh cell is generated in the boundary region between spatially adjacent structural sub-models to form a low-dimensional mesh. Based on the low-dimensional mesh, at least one high-dimensional mesh cell is generated for each of the adjacent structural sub-models to form a high-dimensional mesh. Upon completion of the mesh construction, a target structural model corresponding to the semiconductor device to be simulated is obtained, including: For the first and second structural sub-models that are spatially adjacent, the boundary region between the two structural sub-models is defined as the quantum binding surface. Based on multiple reference grid points on the quantum-bound surface, at least one two-dimensional grid cell is generated to form a two-dimensional grid; Based on the two-dimensional mesh, at least one three-dimensional mesh element is generated for the first structural sub-model and the second structural sub-model respectively to form a three-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained.

4. The method according to claim 3, characterized in that, The step of generating at least one three-dimensional mesh element for the first structural sub-model and the second structural sub-model based on the two-dimensional mesh includes: For the first structural sub-model, taking each of the reference grid points on the two-dimensional grid as the generation starting point, at least one three-dimensional grid cell is generated for the first structural sub-model along the direction toward the first structural sub-model. For the second structural sub-model, taking each of the reference grid points on the two-dimensional grid as the generation starting point, at least one three-dimensional grid cell is generated for the second structural sub-model along the direction toward the second structural sub-model.

5. The method according to claim 1, characterized in that, The structural model is a three-dimensional structural model. The semiconductor device to be simulated includes at least two quantum confinement regions. At least one low-dimensional mesh cell is generated in the boundary region between spatially adjacent structural sub-models to form a low-dimensional mesh. Based on the low-dimensional mesh, at least one high-dimensional mesh cell is generated for each adjacent structural sub-model to form a high-dimensional mesh. Upon completion of the mesh construction, a target structural model corresponding to the semiconductor device to be simulated is obtained, including: For each of the structural sub-models, the boundary region between two spatially adjacent structural sub-models is defined as a quantum binding surface, and multiple reference grid points are defined on each of the quantum binding surfaces to form a two-dimensional grid; For the third structural sub-model of the first side, multiple three-dimensional mesh elements are generated for the third structural sub-model based on the reference mesh points on the corresponding two-dimensional mesh. For the fourth structural sub-model on the second side, multiple three-dimensional mesh elements are generated for the fourth structural sub-model based on the reference mesh points on the corresponding two-dimensional mesh. For each intermediate structural sub-model located between two structural sub-models, multiple three-dimensional mesh elements are generated for the intermediate structural sub-model based on the reference mesh points on the two two-dimensional meshes corresponding to the intermediate structural sub-model. When each of the structural sub-models completes mesh generation, a target structural model corresponding to the semiconductor device to be simulated is obtained.

6. The method according to claim 1, characterized in that, The preset set of electrical energy equations includes: First equation: ； Second equation: ； Third equation: ； Fourth equation: ； Equation 5: ； In the formula, This represents the permittivity of the material used in the semiconductor device being simulated. This represents the potential information at the i-th grid point. Indicates the amount of charge in the elementary element. =1.6021892 × 10 -19 C， This represents the first electron concentration information at the i-th grid point. This represents the second electron concentration information at the i-th grid point. This represents the hole concentration information at the i-th grid point. This represents the second hole concentration information at the i-th grid point. This indicates the concentration of the acceptor dopant in the semiconductor device to be simulated. This indicates the concentration of the donor-type dopant in the semiconductor device to be simulated. A function representing the amount of electrons generated and recombine. A function representing the generation and recombination of holes. A function representing the electric current intensity of electrons. A function representing the current intensity of holes. A function representing the quantum well trapping rate of electrons. A function representing the quantum well trapping rate of holes.

7. The method according to claim 6, characterized in that, The step of determining the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated, based on a preset set of power equations, includes: For each grid point in the target structure model, if the current grid point is located on a low-dimensional grid, the potential information, first electron concentration information, second electron concentration information, first hole concentration information and second hole concentration information corresponding to the current grid point are calculated based on the preset electrical energy equations. If the current grid point is located on a non-low-dimensional grid, the second electron concentration information and the second hole concentration information in the preset electrical energy equation set are initialized, and the potential information, the first electron concentration information and the first hole concentration information corresponding to the current grid point are calculated based on the first equation, the second equation and the third-party program.

8. A simulation device comprising a semiconductor device with a quantum binding region, characterized in that, The device includes: The sub-model partitioning module is used to divide the structural model of the semiconductor device to be simulated into at least two structural sub-models based on the target location information of at least one quantum confinement region. A mesh cell generation module is used to generate at least one low-dimensional mesh cell in the boundary region between spatially adjacent structural sub-models to form a low-dimensional mesh, and to generate at least one high-dimensional mesh cell for each of the adjacent structural sub-models based on the low-dimensional mesh to form a high-dimensional mesh. When the mesh construction is completed, a target structural model corresponding to the semiconductor device to be simulated is obtained. The low-dimensional mesh cell includes at least two mesh points and connecting edges between each mesh point, and the high-dimensional mesh cell includes at least three mesh points and connecting edges between each mesh point. The model simulation module is used to determine the power distribution information at each grid point in the target structure model corresponding to the semiconductor device to be simulated, based on a preset set of power equations.

9. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor to enable the at least one processor to perform the simulation method of the semiconductor device containing the quantum-bound region according to any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the simulation method of any one of claims 1-7 for a semiconductor device containing a quantum-bound region.

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