Grid connection control method and apparatus for voltage conversion circuit, and storage medium

Abstract

The present application relates to a grid connection control method and apparatus for a voltage conversion circuit, and a storage medium. The method comprises: when a voltage conversion circuit is connected to a power grid, detecting whether an output bus voltage of the voltage conversion circuit is less than a peak voltage of the power grid; and when the output bus voltage is less than the peak voltage, controlling switching transistors comprised in a primary-side full-bridge circuit and switching transistors comprised in a secondary-side full-bridge circuit to a preset switching state, so that the primary-side full-bridge circuit, a transformer, a resonant circuit, the secondary-side full-bridge circuit and an output capacitor form a boost circuit, and the boost circuit is used for boosting the output bus voltage to be equal to the peak voltage. The method can improve the grid connection adaptability of the voltage conversion circuit.

Description

Grid-connected control methods, devices, and storage media for voltage conversion circuits

[0001] Related applications

[0002] This application claims priority to Chinese patent application filed on November 1, 2024, application number 2024115465240, entitled "Grid-connected control method, apparatus and storage medium for voltage conversion circuit", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of voltage conversion circuit technology, and in particular to a grid-connected control method, apparatus and storage medium for a voltage conversion circuit. Background Technology

[0004] Currently, when open-loop LLC circuits are used in inverters, the output bus voltage gain of the open-loop LLC circuit is fixed. During the process of the inverter being connected to the grid, device damage is likely to occur, resulting in poor grid connection adaptability of the inverter. Summary of the Invention

[0005] Therefore, it is necessary to provide a grid-connection control method, device, and storage medium for voltage conversion circuits that can improve the grid-connection adaptability of voltage conversion circuits, in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a grid-connected control method for a voltage conversion circuit, the voltage conversion circuit including an open-loop LLC circuit, the open-loop LLC circuit including a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence, the method including:

[0007] During the process of the voltage conversion circuit being connected to the power grid, it is detected whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid.

[0008] When the output bus voltage is less than the peak voltage, the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit are controlled to a preset switching state, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, which is used to boost the output bus voltage to be equal to the peak voltage.

[0009] In one embodiment, controlling the switching transistors included in the primary-side full-bridge circuit and the switching transistors included in the secondary-side full-bridge circuit to a preset switching state includes:

[0010] The phase difference between the primary and secondary switching transistors is determined based on the peak voltage and the output bus voltage.

[0011] Based on the phase difference between the primary and secondary switching transistors, the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit are controlled to the preset switching state.

[0012] In one embodiment, determining the phase difference between the primary and secondary switching transistors based on the peak voltage and the output bus voltage includes:

[0013] The output bus voltage is regulated using a PI control algorithm to obtain the phase difference between the primary and secondary switching transistors, wherein the reference voltage in the PI control algorithm is configured as the peak voltage.

[0014] In one embodiment, the primary-side full-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and the secondary-side full-bridge circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The step of controlling the switches in the primary-side and secondary-side full-bridge circuits to the preset switching state based on the phase difference between the primary and secondary-side switches includes:

[0015] Control the fifth and sixth switching transistors to turn off;

[0016] Based on the phase difference between the primary and secondary switching transistors, the first, second, third, fourth, seventh, and eighth switching transistors are controlled to the preset switching state.

[0017] In one embodiment, controlling the first switch, the second switch, the third switch, the fourth switch, the seventh switch, and the eighth switch to the preset switching state based on the phase difference between the primary and secondary switches includes:

[0018] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned on within a first time period, so that the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, and the eighth switching transistor form a first energy storage circuit. The first energy storage circuit is used to charge the energy storage element included in the resonant circuit.

[0019] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the second time period. This causes the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, the seventh switching transistor, and the output capacitor to form a first charging circuit. The first charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The second time period is after the first time period in terms of timing.

[0020] In one embodiment, controlling the first switch, the second switch, the third switch, the fourth switch, the seventh switch, and the eighth switch to the preset switching state based on the phase difference between the primary and secondary switches further includes:

[0021] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned on, and the eighth switching transistor is turned off during the third time period, so that the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, and the seventh switching transistor form a second energy storage circuit, which is used to charge the energy storage element;

[0022] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the fourth time period. This causes the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, the eighth switching transistor, and the output capacitor to form a second charging circuit. The second charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The third time period is after the second time period in timing, and the fourth time period is after the third time period in timing.

[0023] In one embodiment, the voltage conversion circuit further includes an inverter circuit connected between the open-loop LLC circuit and the power grid. After controlling the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state, the method further includes:

[0024] The switching transistors included in the inverter circuit are controlled to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

[0025] In one embodiment, the method further includes:

[0026] When the grid voltage is detected to be zero-crossing, the AC side relay of the inverter circuit is controlled to close, and the switching transistors of the primary full-bridge circuit and the secondary full-bridge circuit are controlled to the normal switching state.

[0027] Secondly, this application provides a grid-connected control device for a voltage conversion circuit, the voltage conversion circuit including an open-loop LLC circuit, the open-loop LLC circuit including a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence, the device comprising:

[0028] The detection module is used to detect whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid during the process of the voltage conversion circuit being connected to the power grid.

[0029] The control module is used to control the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state when the output bus voltage is less than the peak voltage, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, and the boost circuit is used to boost the output bus voltage to be equal to the peak voltage.

[0030] Thirdly, this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described in the first aspect above.

[0031] Fourthly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in the first aspect above.

[0032] Fifthly, this application provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the method described in the first aspect above.

[0033] The above-mentioned grid-connected control method, device, and storage medium for the voltage conversion circuit include an open-loop LLC circuit. The open-loop LLC circuit comprises a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence. During the grid connection process, the output bus voltage of the voltage conversion circuit is detected to be less than the peak voltage of the grid. If the output bus voltage is less than the peak voltage, the switching transistors in the primary-side and secondary-side full-bridge circuits are controlled to preset switching states, thereby enabling the primary-side full-bridge circuit, transformer, resonant circuit, and secondary-side full-bridge circuit to... The output capacitor forms a boost circuit, which boosts the output bus voltage to be equal to the peak voltage. Thus, when the output bus voltage of the voltage conversion circuit is lower than the peak voltage of the grid, the boost circuit formed by the primary-side full-bridge circuit, transformer, resonant circuit, secondary-side full-bridge circuit, and output capacitor boosts the output bus voltage of the voltage conversion circuit. This avoids excessive inrush current caused by a large difference between the output bus voltage and the peak voltage of the grid when the voltage conversion circuit is connected to the grid, thereby preventing damage to the components of the voltage conversion circuit and improving the grid connection adaptability of the voltage conversion circuit. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 is an application environment diagram of the grid-connected control method of the voltage conversion circuit in one embodiment;

[0036] Figure 2 is a schematic flowchart of a grid-connected control method for a voltage conversion circuit in one embodiment;

[0037] Figure 3 is a schematic diagram of the open-loop LLC circuit in another embodiment;

[0038] Figure 4 is a schematic diagram of the process of controlling the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state by a computer device in another embodiment.

[0039] Figure 5 is a circuit diagram of an open-loop LLC circuit in another embodiment;

[0040] Figure 6 is a schematic diagram of the waveform generation method of each switching transistor in the open-loop LLC circuit in the related technology;

[0041] Figure 7 is a flowchart of step 402 in another embodiment;

[0042] Figure 8 is a circuit diagram of an open-loop LLC circuit in another embodiment;

[0043] Figure 9 is a schematic diagram of the switching transistor current waveform in an open-loop LLC circuit in another embodiment;

[0044] Figure 10 is a schematic diagram of the switching transistor voltage waveform in an open-loop LLC circuit in another embodiment;

[0045] Figure 11 is a circuit diagram of an open-loop LLC circuit in another embodiment;

[0046] Figure 12 is a circuit diagram of an open-loop LLC circuit in another embodiment;

[0047] Figure 13 is a circuit diagram of an open-loop LLC circuit in another embodiment;

[0048] Figure 14 is a schematic diagram of the waveform generation method of each switch in the open-loop LLC circuit in another embodiment;

[0049] Figure 15 is a schematic diagram of the voltage conversion circuit in another embodiment;

[0050] Figure 16 is a flowchart illustrating the grid-connected control method of the voltage conversion circuit in another embodiment;

[0051] Figure 17 is a circuit diagram of the inverter circuit in another embodiment;

[0052] Figure 18 is a structural block diagram of a grid-connected control device for a voltage conversion circuit in one embodiment;

[0053] Figure 19 is an internal structure diagram of a computer device in one embodiment. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0055] When an open-loop LLC circuit is used in an inverter, the output bus voltage gain is fixed. If the input voltage (i.e., battery voltage) on the primary side of the open-loop LLC circuit is too low, the output bus voltage will be much lower than the peak voltage of the grid. If the inverter is forcibly connected to the grid (or simply connected to the grid), the large difference between the output bus voltage and the peak voltage of the grid will cause an excessively large inrush current during grid connection, which can easily damage the inverter components and result in poor grid connection adaptability of the inverter. Conversely, if the inverter is not connected to the grid, the grid connection adaptability of the inverter will also be weakened, meaning that the problem of poor grid connection adaptability of the inverter will also exist.

[0056] Therefore, embodiments of this application provide a grid-connected control method, apparatus, and storage medium for a voltage conversion circuit, which can improve the grid-connected adaptability of the voltage conversion circuit.

[0057] The grid-connected control method for the voltage conversion circuit provided in this application embodiment can be applied to the application environment shown in Figure 1. The battery is connected to the voltage conversion circuit, the voltage conversion circuit is connected to the power grid, and the voltage conversion circuit is also connected to computer equipment. The voltage conversion circuit can be installed in an inverter to perform voltage conversion, such as converting direct current (DC) to alternating current (AC).

[0058] Computer equipment can be a server, which can be a standalone physical server, a server cluster or distributed system consisting of multiple physical servers, or a cloud server that provides cloud computing services.

[0059] In an exemplary embodiment, as shown in FIG2, a grid-connected control method for a voltage conversion circuit is provided. Taking the application of this method to the computer device in FIG1 as an example, the method includes steps 201 and 202:

[0060] Step 201: During the process of the voltage conversion circuit being connected to the power grid, detect whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid.

[0061] In this embodiment, the voltage conversion circuit includes an open-loop LLC circuit. For example, referring to Figure 3, which is a schematic diagram of an open-loop LLC circuit module, the open-loop LLC circuit includes a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence. The primary-side full-bridge circuit is connected to the battery, and the voltage across the output capacitor is the output bus voltage of the voltage conversion circuit.

[0062] The output bus voltage of the voltage conversion circuit is affected by the input voltage (i.e., battery voltage) on the primary side of the open-loop LLC circuit. If the battery voltage is too low, the output bus voltage of the open-loop LLC circuit may be lower than the peak voltage of the grid, resulting in an excessive surge current during grid connection.

[0063] In this embodiment, the computer device can sample the output bus voltage of the voltage conversion circuit through a sampling circuit, and then detect whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid. If the output bus voltage of the voltage conversion circuit is greater than or equal to the peak voltage of the power grid, it indicates that the instantaneous inrush current during grid connection will not be too large. Therefore, existing control strategies can be used to control the voltage conversion circuit to connect to the power grid.

[0064] If the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid, the following steps of the grid connection control method of the voltage conversion circuit in this application embodiment will continue to be executed to avoid the situation where the instantaneous inrush current is too large when the voltage conversion circuit is connected to the grid due to the large difference between the output bus voltage and the peak voltage of the power grid.

[0065] Step 202: When the output bus voltage is less than the peak voltage, control the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state, so that the primary-side full-bridge circuit, transformer, resonant circuit, secondary-side full-bridge circuit and output capacitor form a boost circuit.

[0066] The boost circuit is used to boost the output bus voltage to be equal to the peak voltage.

[0067] The aforementioned preset switching states differ from the conventional switching states of the switching transistors in the primary-side full-bridge circuit and the secondary-side full-bridge circuit during the grid connection process of a traditional voltage conversion circuit. Specifically, in this embodiment, when the output bus voltage of the voltage conversion circuit is lower than the peak voltage of the grid, the computer device alters the conduction control logic of the switching transistors in both the primary-side and secondary-side full-bridge circuits. It utilizes the primary-side full-bridge circuit, transformer, resonant circuit, secondary-side full-bridge circuit, and output capacitor to form a boost circuit, thereby increasing the output bus voltage.

[0068] For example, the boost circuit may include an energy storage stage and a charging stage. In the energy storage stage, energy is stored by charging the energy storage element included in the resonant circuit. In the charging stage, the energy storage element included in the resonant circuit discharges to charge the output capacitor, thereby increasing the voltage across the output capacitor, that is, increasing the output bus voltage of the voltage conversion circuit. The boost circuit is realized through the charging and discharging of the energy storage element included in the resonant circuit.

[0069] In the above embodiment, when the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid, the output bus voltage of the voltage conversion circuit is boosted by a boost circuit formed by the primary-side full-bridge circuit, transformer, resonant circuit, secondary-side full-bridge circuit, and output capacitor. That is, by improving the design of existing circuit components, the voltage conversion circuit avoids the situation where the output bus voltage is too far from the peak voltage of the power grid, which would cause an excessively large inrush current when connected to the grid. This can avoid damage to the components of the voltage conversion circuit and improve the grid connection adaptability of the voltage conversion circuit.

[0070] In one embodiment, based on the embodiment shown in FIG2, referring to FIG4, this embodiment exemplarily describes an implementation method for a computer device to control the switching transistors included in the primary-side full-bridge circuit and the switching transistors included in the secondary-side full-bridge circuit to a preset switching state. As shown in FIG4, the computer device can execute steps 401 and 402 shown in FIG4, including:

[0071] Step 401: Determine the phase difference between the primary and secondary switching transistors based on the peak voltage and the output bus voltage.

[0072] Please refer to Figure 5, which is a schematic diagram of an exemplary open-loop LLC circuit. In the open-loop LLC circuit shown in Figure 5, the primary-side full-bridge circuit includes the first switch MOS1, the second switch MOS2, the third switch MOS3, and the fourth switch MOS4. The transformer is T1 as shown in Figure 5. The resonant circuit includes the resonant inductor Lr and the resonant capacitor Cr as shown in Figure 5. The secondary-side full-bridge circuit includes the fifth switch MOS5, the sixth switch MOS6, the seventh switch MOS7, and the eighth switch MOS8. The output capacitor is Cbus as shown in Figure 5. R1 is the output dummy load of the open-loop LLC circuit. The resistance value of R1 is relatively large. Vbus is the output bus voltage of the voltage conversion circuit.

[0073] In related technologies, MOS1 / MOS4 and MOS5 / MOS8 are used as the E-group bridge arms on the primary and secondary sides, respectively, with the same waveform generation method; MOS2 / MOS3 and MOS6 / MOS7 are used as the F-group bridge arms on the primary and secondary sides, respectively, with the same waveform generation method. MOS1 / MOS2, MOS3 / MOS4, MOS5 / MOS6, and MOS7 / MOS8 are four complementary drives. The effective driving level (high level) and duty cycle of the E-group bridge arms and the F-group bridge arms are the same, with a phase difference of 180 degrees. After the open-loop LLC circuit is started, the output bus voltage Vbus reaches its maximum value. The waveform generation method of each switch in the open-loop LLC circuit is shown in Figure 6. When all the switches (MOS1, MOS4, MOS5, MOS8) in the E-group bridge arms are turned on, all the switches (MOS2, MOS3, MOS6, MOS7) in the F-group bridge arms are turned off; when all the switches in the F-group bridge arms are turned on, all the switches in the E-group bridge arms are turned off.

[0074] In the related art, since Vbus≈Vbat*Ns / Np (where Vbus is the output bus voltage, Vbat is the battery voltage, Ns is the primary turns ratio of the transformer in the open-loop LLC circuit, and Np is the secondary turns ratio of the transformer in the open-loop LLC circuit), when the battery voltage Vbat decreases as the battery power decreases, Vbus also decreases accordingly. ΔV = Vgridpeak - Vbus (where Vgridpeak is the peak voltage of the power grid). When Vbus < Vgridpeak, ΔV > 0, and Ic = Cbus*ΔV / ΔT1 (where Ic is the inrush current at grid connection, Cbus is the capacitance value of the output capacitor, and ΔT1 is the instant time at grid connection). The larger ΔV is, the larger the inrush current Ic at grid connection is. When it exceeds the rated current threshold of the device, the device will be damaged.

[0075] In the embodiments of the present application, the computer device determines the phase difference between the primary and secondary switching transistors according to the peak voltage of the power grid and the output bus voltage of the voltage conversion circuit. Referring to FIG. 5, the phase difference Angle between the primary and secondary switching transistors may refer to the phase difference between the first switching transistor MOS1 and the eighth switching transistor MOS8, and the phase difference between the second switching transistor MOS2 and the seventh switching transistor MOS7. As ΔV increases, the phase difference Angle between the primary and secondary switching transistors also increases. That is, the magnitude of ΔV is positively correlated with the magnitude of the phase difference Angle between the primary and secondary switching transistors. The larger the phase difference Angle between the primary and secondary switching transistors is, the greater the boost amplitude of the boost circuit formed by the primary full-bridge circuit, the transformer, the resonant circuit, the secondary full-bridge circuit, and the output capacitor is.

[0076] As an implementation, the computer device can use the P (Proportional) I (Integral) regulation algorithm to adjust the output bus voltage, that is, perform PI regulation on the output bus voltage. For the phase difference Angle between the primary and secondary switching transistors, the reference voltage (Vref) in the PI regulation algorithm is set to the peak voltage of the power grid. Based on the PI regulation algorithm, a high-precision phase difference between the primary and secondary switching transistors can be obtained.

[0077] Step 402: Control the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit to a preset switching state according to the phase difference between the primary and secondary switching transistors.

[0078] After the computer device obtains the phase difference Angle between the primary and secondary switching transistors, the computer device then controls the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit to a preset switching state according to the phase difference Angle between the primary and secondary switching transistors.

[0079] In a possible implementation of step 402, referring to FIG. 7, step 402 may include steps 701 and 702 shown in FIG. 7:

[0080] Step 701: Control the fifth and sixth switching transistors to turn off.

[0081] The computer equipment controls the fifth switch MOS5 and the sixth switch MOS6 to turn off. After the fifth switch MOS5 and the sixth switch MOS6 are turned off, they are equivalent to diode D in the open-loop LLC circuit by utilizing the unidirectional conduction characteristics of the internal diodes of the fifth switch MOS5 and the sixth switch MOS6.

[0082] Step 702: Based on the phase difference between the primary and secondary switching transistors, control the first, second, third, fourth, seventh, and eighth switching transistors to a preset switching state.

[0083] After the computer equipment controls the fifth switch MOS5 and the sixth switch MOS6 to turn off, the other switches in the open-loop LLC circuit can be turned on normally. Therefore, the computer equipment controls the remaining first switch MOS1, second switch MOS2, third switch MOS3, fourth switch MOS4, seventh switch MOS7 and eighth switch MOS8 in the open-loop LLC circuit to the preset switching state according to the phase difference between the primary and secondary switches.

[0084] The above embodiments do not require additional hardware circuits. Based on the existing switching transistors and energy storage elements in the existing open-loop LLC circuit topology, the phase difference between the primary and secondary switching transistors is obtained through PI regulation. The grid-connected control method of this application embodiment can be executed based on the phase difference between the primary and secondary switching transistors, so that the output bus voltage of the voltage conversion circuit is stabilized at the peak voltage of the grid. The implementation method is simple and easy to implement, and it is beneficial to cost control.

[0085] The following describes the implementation of step 702 using the open-loop LLC circuit shown in Figure 5 as an example.

[0086] During the first time period, the computer equipment controls the first switch MOS1 to turn off, the second switch MOS2 to turn on, the third switch MOS3 to turn on, the fourth switch MOS4 to turn off, the seventh switch MOS7 to turn off, and the eighth switch MOS8 to turn on, based on the phase difference between the primary and secondary switch transistors.

[0087] Please refer to Figure 8. The computer device controls the conduction time of the second switch MOS2 and the eighth switch MOS8 to overlap based on the phase difference value Angle between the primary and secondary switches. That is, during the first time period, both the second switch MOS2 and the eighth switch MOS8 are in the conducting state. At this time, the second switch MOS2, the third switch MOS3, the transformer, the resonant circuit of the transformer secondary, the sixth switch MOS6 (i.e., diode D6 shown in Figure 8), and the eighth switch MOS8 form the first energy storage circuit. The first energy storage circuit is used to charge the energy storage elements (i.e., Lr and Cr) included in the resonant circuit. The current flow direction in the first energy storage circuit is indicated by the red dashed arrow in Figure 8. During the first time period, the output capacitor discharges a small amount, and the output capacitor and R1 form a current loop.

[0088] Please refer to Figures 9 and 10. After the computer device turns off the fifth switch MOS5 and the sixth switch MOS6, as the phase difference Angle of the primary and secondary switches changes, the current waveform of the switch in the open-loop LLC circuit is shown in Figure 9, and the voltage waveform of the switch in the open-loop LLC circuit is shown in Figure 10. The time period t1-t2 shown in Figures 9 and 10 can be the first time period mentioned above in this embodiment.

[0089] Where I(Moss6) / I(Moss7) / I(Moss8) are the currents of the sixth switch MOS6 / seventh switch MOS7 / eighth switch MOS8 respectively (the direction from D to S is the positive direction of the current), I(CR) / V(CR) are the current / voltage of the resonant capacitor Cr (the same terminal is the positive direction), I(LR) / V(LR) are the current / voltage of the resonant inductor Lr (the same terminal is the positive direction), Vs is the secondary voltage of the transformer, and Vs1 is the voltage at the secondary side of the transformer, the resonant capacitor Cr, and the resonant inductor Lr.

[0090] Under the influence of Vs, the energy storage elements (i.e., Lr and Cr) included in the resonant circuit begin to be charged and store energy during the first time period (t1-t2).

[0091] During the second time period, the computer device controls the first switch MOS1 to turn off, the second switch MOS2 to turn on, the third switch MOS3 to turn on, the fourth switch MOS4 to turn off, the seventh switch MOS7 to turn off, and the eighth switch MOS8 to turn off, based on the phase difference between the primary and secondary switches.

[0092] Please refer to Figure 11. The computer device controls the seventh switch MOS7 to turn off according to the phase difference value Angle between the primary and secondary switch transistors. At this time, the seventh switch MOS7 is equivalent to a diode (i.e., D7 shown in Figure 11). The second switch MOS2, the third switch MOS3, the transformer, the resonant circuit, the sixth switch MOS6, the seventh switch MOS7, and the output capacitor form the first charging circuit. The current in the first charging circuit flows in the direction indicated by the red dashed arrow in Figure 11. The first charging circuit is used to charge the output capacitor through the energy storage element. The circuit current flows periodically to the output capacitor through the diode inside the seventh switch MOS7 to charge the output capacitor, thereby boosting the output bus voltage across the output capacitor.

[0093] In this embodiment, the second time period follows the first time period in chronological order. Please refer to Figures 9 and 10; the t2-t3 time period shown in Figures 9 and 10 can be the second time period described above in this embodiment.

[0094] Assuming the boost voltage of the first charging circuit for boosting the output bus voltage across the output capacitor is ΔV bus Indicate, then

[0095] During the third time period, the computer equipment controls the first switch MOS1 to turn on, the second switch MOS2 to turn off, the third switch MOS3 to turn off, the fourth switch MOS4 to turn on, the seventh switch MOS7 to turn on, and the eighth switch MOS8 to turn off, based on the phase difference between the primary and secondary switches.

[0096] Please refer to Figure 12. The computer device controls the conduction time of the first switch MOS1 and the seventh switch MOS7 to overlap based on the phase difference value Angle between the primary and secondary switches. That is, during the third time period, both the first switch MOS1 and the seventh switch MOS7 are in the conducting state. At this time, the first switch MOS1, the fourth switch MOS4, the transformer, the resonant circuit, the fifth switch MOS5 (i.e., diode D5 shown in Figure 12) and the seventh switch MOS7 form the second energy storage circuit. The second energy storage circuit is used to charge the energy storage elements (i.e., Lr and Cr). The current flow direction in the second energy storage circuit is as indicated by the red dashed arrow in Figure 12. During the third time period, the output capacitor discharges slightly, and the output capacitor and R1 form a current loop.

[0097] Please continue to refer to Figures 9 and 10. The t4-t5 time period shown in Figures 9 and 10 can be the third time period mentioned above in this embodiment. The third time period is after the second time period in terms of time sequence.

[0098] During the fourth time period, the computer equipment controls the first switch MOS1 to turn on, the second switch MOS2 to turn off, the third switch MOS3 to turn off, the fourth switch MOS4 to turn on, the seventh switch MOS7 to turn off, and the eighth switch MOS8 to turn off, based on the phase difference between the primary and secondary switches.

[0099] Please refer to Figure 13. The computer device controls the eighth switch MOS8 to turn off according to the phase difference value Angle between the primary and secondary switch transistors. At this time, the turn-off of the eighth switch MOS8 is equivalent to a diode (i.e., D8 shown in Figure 13). The first switch MOS1, the fourth switch MOS4, the transformer, the resonant circuit, the fifth switch MOS5, the eighth switch MOS8, and the output capacitor form the second charging circuit. The current in the second charging circuit flows in the direction indicated by the red dashed arrow in Figure 13. The second charging circuit is used to charge the output capacitor through the energy storage element. The circuit current flows periodically to the output capacitor through the diode inside the eighth switch MOS8 to charge the output capacitor, thereby boosting the output bus voltage across the output capacitor.

[0100] In this embodiment, the fourth time period follows the third time period in sequence. Please refer to Figures 9 and 10; the t5-t6 time period shown in Figures 9 and 10 can be the aforementioned fourth time period in this embodiment.

[0101] Assuming the boost voltage of the second charging circuit for boosting the output bus voltage across the output capacitor is ΔV bus Indicate, then

[0102] Please refer to Figure 14. The waveform generation method of each switch in the open-loop LLC circuit of this embodiment is shown in Figure 14. The fifth switch MOS5 and the sixth switch MOS6 are controlled to turn off (these two switches are equivalent to two diodes in the circuit). The control waveforms of the first switch MOS1-the fourth switch MOS4, the seventh switch MOS7, and the eighth switch MOS8 are adjusted by changing the phase difference between the primary and secondary switches. This ensures that the first switch MOS1 and the seventh switch MOS7, and the second switch MOS2 and the eighth switch MOS8, will have a simultaneous conduction period. When the second switch MOS2 and the eighth switch MOS8 are simultaneously on, the first energy storage circuit supplies energy to the energy storage elements included in the resonant circuit. The first switch MOS1 and the seventh switch MOS7 are simultaneously turned on, and the second energy storage circuit charges the energy storage element included in the resonant circuit. The energy storage element is then charged and can discharge to charge the output capacitor, thereby boosting the output bus voltage across the output capacitor. In this way, a boost circuit is formed based on the existing switches and energy storage elements in the open-loop LLC circuit topology to boost the output bus voltage, thus achieving the effect of increasing the output bus voltage.

[0103] In one embodiment, based on any of the above embodiments, taking the embodiment shown in FIG3 as an example and referring to FIG15, the voltage conversion circuit of this application embodiment further includes an inverter circuit, which is connected between the open-loop LLC circuit and the power grid.

[0104] Referring to Figure 16, after the computer device controls the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state, the grid-connected control method of the voltage conversion circuit further includes step 1601 shown in Figure 16:

[0105] Step 1601: Control the switching transistors included in the inverter circuit to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

[0106] For example, referring to Figure 17, which is a circuit diagram of an exemplary inverter circuit, the inverter circuit may include, for example, the ninth switch MOS9, the tenth switch MOS10, the eleventh switch MOS11, and the twelfth switch MOS12 shown in Figure 17.

[0107] When the output bus voltage of the open-loop LLC circuit is less than the peak voltage, the computer equipment controls the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state to form a boost circuit that boosts the output bus voltage to be equal to the peak voltage. At this time, the switching transistors included in the inverter circuit are turned off to lock the phase to the grid. The four switching transistors shown in Figure 17 are equivalent to four diodes in the circuit, forming a rectifier circuit to rectify the grid input.

[0108] Please refer to Figure 16. The grid-connected control method for this voltage conversion circuit also includes step 1602 as shown in Figure 16:

[0109] Step 1602: When the grid voltage is detected to be zero-crossing, the AC side relay of the inverter circuit is closed, and the switching transistors of the primary full-bridge circuit and the secondary full-bridge circuit are switched to normal switching state.

[0110] Relay S11 is activated at the zero-crossing point of the grid voltage. At this time, since there is no voltage difference between the output bus voltage and the peak grid voltage, the grid-connected inrush current can be ignored. At the same time, the grid-connected control of the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit is canceled, and the normal waveform mode of each switching transistor is restored. After rectification by the uncontrolled rectification characteristics of the inverter circuit, the bus capacitor is charged. At this time, the battery charging current is minimal, and the battery voltage gradually increases. When the charging current at the battery terminal is small, the full-bridge drive of the inverter circuit is activated to perform PFC (Power Factor Correction) boost regulation charging.

[0111] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0112] Based on the same inventive concept, this application also provides a grid-connected control device for a voltage conversion circuit to implement the grid-connected control method for the voltage conversion circuit described above. The solution provided by this device is similar to the solution described in the above method. Therefore, the specific limitations in one or more embodiments of the grid-connected control device for voltage conversion circuits provided below can be found in the limitations of the grid-connected control method for voltage conversion circuits described above, and will not be repeated here.

[0113] In an exemplary embodiment, as shown in FIG18, a grid-connected control device for a voltage conversion circuit is provided. The voltage conversion circuit includes an open-loop LLC circuit, which comprises a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence. The device includes:

[0114] The detection module 1801 is used to detect whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid during the process of the voltage conversion circuit being connected to the power grid.

[0115] The control module 1802 is used to control the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state when the output bus voltage is less than the peak voltage, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, and the boost circuit is used to boost the output bus voltage to be equal to the peak voltage.

[0116] In one embodiment, the control module 1802 includes:

[0117] The determining unit is used to determine the phase difference between the primary and secondary switching transistors based on the peak voltage and the output bus voltage.

[0118] The control unit is configured to control the switching transistors included in the primary-side full-bridge circuit and the switching transistors included in the secondary-side full-bridge circuit to the preset switching state based on the phase difference value of the primary and secondary-side switching transistors.

[0119] In one embodiment, the determining unit is specifically used to adjust the output bus voltage using a PI regulation algorithm to obtain the phase difference value of the primary and secondary side switches, wherein the reference voltage in the PI regulation algorithm is configured as the peak voltage.

[0120] In one embodiment, the primary-side full-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and the secondary-side full-bridge circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The control unit is specifically used to control the fifth switch and the sixth switch to turn off; and to control the first switch, the second switch, the third switch, the fourth switch, the seventh switch, and the eighth switch to the preset switching state according to the phase difference between the primary and secondary switches.

[0121] In one embodiment, the control unit is specifically configured to, based on the phase difference between the primary and secondary switching transistors, control the first switch to turn off, the second switch to turn on, the third switch to turn on, the fourth switch to turn off, the seventh switch to turn off, and the eighth switch to turn on within a first time period, so that the second switch, the third switch, the transformer, the resonant circuit, the sixth switch, and the eighth switch form a first energy storage circuit, the first energy storage circuit being used to charge the energy storage element included in the resonant circuit; and based on the phase difference between the primary and secondary switching transistors, control the first switch to turn off, the second switch to turn on, the third switch to turn on, the fourth switch to turn off, the seventh switch to turn off, and the eighth switch to turn off within a second time period, so that the second switch, the third switch, the transformer, the resonant circuit, the sixth switch, the seventh switch, and the output capacitor form a first charging circuit, the first charging circuit being used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor, the second time period being sequentially after the first time period.

[0122] In one embodiment, the control unit is specifically configured to control the first switch to turn on, the second switch to turn off, the third switch to turn off, the fourth switch to turn on, the seventh switch to turn on, and the eighth switch to turn off within a third time period based on the phase difference between the primary and secondary switches, so that the first switch, the fourth switch, the transformer, the resonant circuit, the fifth switch, and the seventh switch form a second energy storage circuit, which is used to charge the energy storage element; and to control the first switch to turn on within a fourth time period based on the phase difference between the primary and secondary switches. The second switch is turned off, the third switch is turned off, the fourth switch is turned on, the seventh switch is turned off, and the eighth switch is turned off, so that the first switch, the fourth switch, the transformer, the resonant circuit, the fifth switch, the eighth switch, and the output capacitor form a second charging circuit. The second charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The third time period is after the second time period in timing, and the fourth time period is after the third time period in timing.

[0123] In one embodiment, the voltage conversion circuit further includes an inverter circuit connected between the open-loop LLC circuit and the power grid. The control module 1802 is also used to control the switching transistors included in the inverter circuit to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

[0124] In one embodiment, the control module 1802 is further configured to, upon detecting a zero-crossing point in the grid voltage, control the AC-side relay of the inverter circuit to close, and control the switching transistors of the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a normal switching state.

[0125] Each module in the grid-connected control device of the aforementioned voltage conversion circuit can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0126] In an exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram is shown in Figure 19. The computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is connected to the system bus via the I / O interfaces. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database of the computer device stores grid-connected control data for voltage conversion circuits. The I / O interfaces of the computer device are used for exchanging information between the processor and external devices. The communication interface of the computer device is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a grid-connected control method for a voltage conversion circuit.

[0127] Those skilled in the art will understand that the structure shown in Figure 19 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or may combine certain components, or may have different component arrangements.

[0128] In one exemplary embodiment, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0129] During the process of the voltage conversion circuit being connected to the power grid, it is detected whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid.

[0130] When the output bus voltage is less than the peak voltage, the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit are controlled to a preset switching state, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, which is used to boost the output bus voltage to be equal to the peak voltage.

[0131] In one embodiment, the processor executes the following steps when executing a computer program:

[0132] The phase difference between the primary and secondary switching transistors is determined based on the peak voltage and the output bus voltage.

[0133] Based on the phase difference between the primary and secondary switching transistors, the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit are controlled to the preset switching state.

[0134] In one embodiment, the processor executes the following steps when executing a computer program:

[0135] The output bus voltage is regulated using a PI control algorithm to obtain the phase difference between the primary and secondary switching transistors, wherein the reference voltage in the PI control algorithm is configured as the peak voltage.

[0136] In one embodiment, the primary-side full-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and the secondary-side full-bridge circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. The processor, when executing the computer program, specifically implements the following steps:

[0137] Control the fifth and sixth switching transistors to turn off;

[0138] Based on the phase difference between the primary and secondary switching transistors, the first, second, third, fourth, seventh, and eighth switching transistors are controlled to the preset switching state.

[0139] In one embodiment, the processor executes the following steps when executing a computer program:

[0140] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned on within a first time period, so that the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, and the eighth switching transistor form a first energy storage circuit. The first energy storage circuit is used to charge the energy storage element included in the resonant circuit.

[0141] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the second time period. This causes the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, the seventh switching transistor, and the output capacitor to form a first charging circuit. The first charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The second time period is after the first time period in terms of timing.

[0142] In one embodiment, when the processor executes a computer program, it further implements the following steps:

[0143] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned on, and the eighth switching transistor is turned off during the third time period, so that the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, and the seventh switching transistor form a second energy storage circuit, which is used to charge the energy storage element;

[0144] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the fourth time period. This causes the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, the eighth switching transistor, and the output capacitor to form a second charging circuit. The second charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The third time period is after the second time period in timing, and the fourth time period is after the third time period in timing.

[0145] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0146] The switching transistors included in the inverter circuit are controlled to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

[0147] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0148] When the grid voltage is detected to be zero-crossing, the AC side relay of the inverter circuit is controlled to close, and the switching transistors of the primary full-bridge circuit and the secondary full-bridge circuit are controlled to the normal switching state.

[0149] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0150] During the process of the voltage conversion circuit being connected to the power grid, it is detected whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid.

[0151] When the output bus voltage is less than the peak voltage, the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit are controlled to a preset switching state, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, which is used to boost the output bus voltage to be equal to the peak voltage.

[0152] In one embodiment, when a computer program is executed by a processor, it specifically implements the following steps:

[0153] The phase difference between the primary and secondary switching transistors is determined based on the peak voltage and the output bus voltage.

[0154] Based on the phase difference between the primary and secondary switching transistors, the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit are controlled to the preset switching state.

[0155] In one embodiment, when a computer program is executed by a processor, it specifically implements the following steps:

[0156] The output bus voltage is regulated using a PI control algorithm to obtain the phase difference between the primary and secondary switching transistors, wherein the reference voltage in the PI control algorithm is configured as the peak voltage.

[0157] In one embodiment, the primary-side full-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and the secondary-side full-bridge circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. When the computer program is executed by the processor, it specifically implements the following steps:

[0158] Control the fifth and sixth switching transistors to turn off;

[0159] Based on the phase difference between the primary and secondary switching transistors, the first, second, third, fourth, seventh, and eighth switching transistors are controlled to the preset switching state.

[0160] In one embodiment, when a computer program is executed by a processor, it specifically implements the following steps:

[0161] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned on within a first time period, so that the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, and the eighth switching transistor form a first energy storage circuit. The first energy storage circuit is used to charge the energy storage element included in the resonant circuit.

[0162] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the second time period. This causes the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, the seventh switching transistor, and the output capacitor to form a first charging circuit. The first charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The second time period is after the first time period in terms of timing.

[0163] In one embodiment, when the computer program is executed by a processor, it further implements the following steps:

[0164] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned on, and the eighth switching transistor is turned off during the third time period, so that the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, and the seventh switching transistor form a second energy storage circuit, which is used to charge the energy storage element;

[0165] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the fourth time period. This causes the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, the eighth switching transistor, and the output capacitor to form a second charging circuit. The second charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The third time period is after the second time period in timing, and the fourth time period is after the third time period in timing.

[0166] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0167] The switching transistors included in the inverter circuit are controlled to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

[0168] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0169] When the grid voltage is detected to be zero-crossing, the AC side relay of the inverter circuit is controlled to close, and the switching transistors of the primary full-bridge circuit and the secondary full-bridge circuit are controlled to the normal switching state.

[0170] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0171] During the process of the voltage conversion circuit being connected to the power grid, it is detected whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid.

[0172] When the output bus voltage is less than the peak voltage, the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit are controlled to a preset switching state, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, which is used to boost the output bus voltage to be equal to the peak voltage.

[0173] In one embodiment, when a computer program is executed by a processor, it specifically implements the following steps:

[0174] The phase difference between the primary and secondary switching transistors is determined based on the peak voltage and the output bus voltage.

[0175] Based on the phase difference between the primary and secondary switching transistors, the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit are controlled to the preset switching state.

[0176] In one embodiment, when a computer program is executed by a processor, it specifically implements the following steps:

[0177] The output bus voltage is regulated using a PI control algorithm to obtain the phase difference between the primary and secondary switching transistors, wherein the reference voltage in the PI control algorithm is configured as the peak voltage.

[0178] In one embodiment, the primary-side full-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch, and the secondary-side full-bridge circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch. When the computer program is executed by the processor, it specifically implements the following steps:

[0179] Control the fifth and sixth switching transistors to turn off;

[0180] Based on the phase difference between the primary and secondary switching transistors, the first, second, third, fourth, seventh, and eighth switching transistors are controlled to the preset switching state.

[0181] In one embodiment, when a computer program is executed by a processor, it specifically implements the following steps:

[0182] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned on within a first time period, so that the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, and the eighth switching transistor form a first energy storage circuit. The first energy storage circuit is used to charge the energy storage element included in the resonant circuit.

[0183] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the second time period. This causes the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, the seventh switching transistor, and the output capacitor to form a first charging circuit. The first charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The second time period is after the first time period in terms of timing.

[0184] In one embodiment, when the computer program is executed by a processor, it further implements the following steps:

[0185] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned on, and the eighth switching transistor is turned off during the third time period, so that the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, and the seventh switching transistor form a second energy storage circuit, which is used to charge the energy storage element;

[0186] Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the fourth time period. This causes the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, the eighth switching transistor, and the output capacitor to form a second charging circuit. The second charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The third time period is after the second time period in timing, and the fourth time period is after the third time period in timing.

[0187] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0188] The switching transistors included in the inverter circuit are controlled to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

[0189] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0190] When the grid voltage is detected to be zero-crossing, the AC side relay of the inverter circuit is controlled to close, and the switching transistors of the primary full-bridge circuit and the secondary full-bridge circuit are controlled to the normal switching state.

[0191] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0192] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0193] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A grid-connected control method for a voltage conversion circuit, wherein, The voltage conversion circuit includes an open-loop LLC circuit, which comprises a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence. The method includes: During the process of the voltage conversion circuit being connected to the power grid, it is detected whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid. When the output bus voltage is less than the peak voltage, the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit are controlled to a preset switching state, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, which is used to boost the output bus voltage to be equal to the peak voltage.

2. The method according to claim 1, wherein, Controlling the switching transistors included in the primary-side full-bridge circuit and the switching transistors included in the secondary-side full-bridge circuit to a preset switching state includes: The phase difference between the primary and secondary switching transistors is determined based on the peak voltage and the output bus voltage. Based on the phase difference between the primary and secondary switching transistors, the switching transistors included in the primary full-bridge circuit and the switching transistors included in the secondary full-bridge circuit are controlled to the preset switching state.

3. The method according to claim 2, wherein, Determining the phase difference between the primary and secondary switching transistors based on the peak voltage and the output bus voltage includes: The output bus voltage is regulated using a PI control algorithm to obtain the phase difference between the primary and secondary switching transistors, wherein the reference voltage in the PI control algorithm is configured as the peak voltage.

4. The method according to claim 2, wherein, The primary-side full-bridge circuit includes a first switch, a second switch, a third switch, and a fourth switch; the secondary-side full-bridge circuit includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; and controlling the switches in the primary-side and secondary-side full-bridge circuits to the preset switching state based on the phase difference between the primary and secondary-side switches includes: Control the fifth and sixth switching transistors to turn off; Based on the phase difference between the primary and secondary switching transistors, the first, second, third, fourth, seventh, and eighth switching transistors are controlled to the preset switching state.

5. The method according to claim 4, wherein, The step of controlling the first switch, the second switch, the third switch, the fourth switch, the seventh switch, and the eighth switch to the preset switching state based on the phase difference between the primary and secondary switch transistors includes: Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned on within a first time period, so that the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, and the eighth switching transistor form a first energy storage circuit. The first energy storage circuit is used to charge the energy storage element included in the resonant circuit. Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned off, the second switching transistor is turned on, the third switching transistor is turned on, the fourth switching transistor is turned off, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the second time period. This causes the second switching transistor, the third switching transistor, the transformer, the resonant circuit, the sixth switching transistor, the seventh switching transistor, and the output capacitor to form a first charging circuit. The first charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The second time period is after the first time period in terms of timing.

6. The method according to claim 5, wherein, The step of controlling the first switch, the second switch, the third switch, the fourth switch, the seventh switch, and the eighth switch to the preset switching state based on the phase difference value of the primary and secondary switch transistors further includes: Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned on, and the eighth switching transistor is turned off during the third time period, so that the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, and the seventh switching transistor form a second energy storage circuit, which is used to charge the energy storage element; Based on the phase difference between the primary and secondary switching transistors, the first switching transistor is turned on, the second switching transistor is turned off, the third switching transistor is turned off, the fourth switching transistor is turned on, the seventh switching transistor is turned off, and the eighth switching transistor is turned off during the fourth time period. This causes the first switching transistor, the fourth switching transistor, the transformer, the resonant circuit, the fifth switching transistor, the eighth switching transistor, and the output capacitor to form a second charging circuit. The second charging circuit is used to charge the output capacitor through the energy storage element to boost the output bus voltage across the output capacitor. The third time period is after the second time period in timing, and the fourth time period is after the third time period in timing.

7. The method according to any one of claims 1-6, wherein, The voltage conversion circuit further includes an inverter circuit, which is connected between the open-loop LLC circuit and the power grid. After controlling the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state, the method further includes: The switching transistors included in the inverter circuit are controlled to turn off, so that the switching transistors included in the inverter circuit form a rectifier circuit.

8. The method according to claim 7, wherein, The method further includes: When the grid voltage is detected to be zero-crossing, the AC side relay of the inverter circuit is controlled to close, and the switching transistors of the primary full-bridge circuit and the secondary full-bridge circuit are controlled to the normal switching state.

9. A grid-connected control device for a voltage conversion circuit, wherein, The voltage conversion circuit includes an open-loop LLC circuit, which comprises a primary-side full-bridge circuit, a transformer, a resonant circuit, a secondary-side full-bridge circuit, and an output capacitor connected in sequence. The device includes: The detection module is used to detect whether the output bus voltage of the voltage conversion circuit is less than the peak voltage of the power grid during the process of the voltage conversion circuit being connected to the power grid. The control module is used to control the switching transistors included in the primary-side full-bridge circuit and the secondary-side full-bridge circuit to a preset switching state when the output bus voltage is less than the peak voltage, so that the primary-side full-bridge circuit, the transformer, the resonant circuit, the secondary-side full-bridge circuit and the output capacitor form a boost circuit, and the boost circuit is used to boost the output bus voltage to be equal to the peak voltage.

10. A computer-readable storage medium having a computer program stored thereon, wherein, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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