Bc battery, module and system

Abstract

The present disclosure provides a BC battery, a module and a system. An extension section of an insulating dielectric layer, a first doped layer and a silicon substrate form a deposition space at a preset position. The extension section, the first doped layer and the silicon substrate form a closed profile at a first cross-section. An electric-leakage doped portion in the deposition space forms an electric-leakage contact with the first doped layer and a conductive contact with a first extension portion of a second doped layer.

Description

BC batteries, components and systems

[0001] Cross-references to related applications

[0002] This disclosure claims priority to Chinese patent application No. 202422676897.1, filed on November 1, 2024, with the China National Intellectual Property Administration, entitled “Back Contact Battery, Battery Module and Photovoltaic System”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of solar cell technology, and more particularly to a back-contact cell, a cell module, and a photovoltaic system. Background Technology

[0004] Currently, in solar cells, back contact cells (BC cells) are a type of cell in which both the emitter and base contact electrodes are placed on the back (not the front) of the cell. The front of the cell is not obstructed by any metal electrodes, thus effectively improving the efficiency of back contact cells.

[0005] During module operation, when external obstructions block the solar cells, hot spots can appear on the blocked cells. At high temperatures, this can easily lead to carbonization of the encapsulation film and even cause a fire. In back-contact solar cells of relevant technologies, two different doped layers are typically electrically connected at a local location to form a leakage point, reducing the reverse breakdown voltage and thus improving the hot spot resistance and reducing the risk of hot spots. However, while current back-contact solar cells can improve hot spot resistance, they also result in poor performance and low conversion efficiency.

[0006] Therefore, how to improve the heat spot resistance of back contact batteries while ensuring their conversion efficiency has become a technical problem that engineers urgently need to solve.

[0007] Public content

[0008] This disclosure provides a back-contact battery, a battery module, and a photovoltaic system.

[0009] This disclosure is implemented as follows: the back contact battery of the embodiments of this disclosure includes:

[0010] The silicon substrate has a front side and a back side, the back side including a plurality of first regions and a plurality of second regions arranged alternately along a first direction, and a spacer region between the first regions and the second regions, the first regions, the second regions and the spacer region all extending along a second direction, the second direction intersecting the first direction;

[0011] The first doped layer is disposed on the first region;

[0012] An insulating dielectric layer is disposed on at least a portion of the first doped layer. At a predetermined location in the spacer region, the insulating dielectric layer has an extension that extends out of the first region and bends at least partially toward the side where the silicon substrate is located. The end of the extension is at least partially overlapped on the spacer region so that the extension, the first doped layer, and the silicon substrate together form a deposition space. In a first cross-section along the first direction, the extension, the first doped layer, and the silicon substrate together form a closed pattern.

[0013] The leakage doped portion is disposed within the deposition space and forms a leakage contact with the first doped layer; the polarity of the leakage doped portion is opposite to that of the first doped layer.

[0014] A second doped layer is disposed on a portion of the second region and the spacer region. The polarity of the second doped layer is opposite to that of the first doped layer. At a predetermined position, the second doped layer has a first extension that extends and covers at least a portion of the extension. The first extension is in conductive contact with the leakage doped portion. The first extension also extends along the first extension and covers at least a portion of the portion of the insulating dielectric layer corresponding to the first doped layer.

[0015] In some embodiments, a through hole is formed on the extension, and the first extension makes conductive contact with the leakage doped portion through the through hole.

[0016] In some embodiments, at a second cross section along the first direction, the end of the extension is suspended over the spacer region, the extension, together with the first doped layer and the silicon substrate, forms a non-closed pattern with an opening, the second doped layer and the leakage doped portion are in conductive contact at the opening, and the first cross section and the second cross section are parallel to each other in the second direction.

[0017] In some embodiments, in the second direction, the extension has a first portion with its end overlapping the spacer region and a second portion with its end suspended over the spacer region, the second portion having a gap with the surface of the spacer region, and the second doped layer making conductive contact with the leakage doped portion through the gap.

[0018] In some embodiments, the gap between the second portion and the surface of the spacer region is 5nm-800nm.

[0019] In some embodiments, a cavity is provided within the leakage doping portion at a third cross-section along the first direction.

[0020] In some embodiments, the outer diameter of the cavity is 10 nm-500 nm.

[0021] In some embodiments, the angle between the surface of the first doped layer and the leakage doped portion forming a leakage contact and the surface of the first region is an acute angle, and the surface of the first doped layer and the leakage doped portion forming a leakage contact has a first recessed region.

[0022] In some embodiments, the surface on which the first doped layer and the leakage doped portion form a leakage contact is a curved surface.

[0023] In some embodiments, the first doped layer has a second extension that extends along a first direction and is suspended over a spacer region, an insulating dielectric layer covers the surface of the second extension facing away from the silicon substrate, the extension, the second extension, and the silicon substrate together form a deposition space, and the leakage doped portion forms a leakage contact with the second extension.

[0024] In some embodiments, the back contact battery satisfies at least one of the following: the leakage doped portion and the surface of the second extension toward the spacer region form a leakage contact; the leakage doped portion and the end face of the second extension in a first direction form a leakage contact.

[0025] In some embodiments, the leakage doped portion and the end face of the second extension portion form a leakage contact in the first direction, the angle between the end face of the second extension portion and the surface of the first region is an acute angle, and the end face of the second extension portion has a second recessed region.

[0026] In some embodiments, the extension length of the second extension in the first direction is 0.1 μm-3 μm.

[0027] In some embodiments, a first dielectric layer is provided on the surface where the first doped layer and the leakage doped portion form a leakage contact, and the leakage doped portion and the first doped layer form a leakage contact through the first dielectric layer.

[0028] In some embodiments, a second dielectric layer is provided at least at a predetermined location on the spacer region, the end of the extension is at least partially overlapped on the second dielectric layer, and a leakage doped portion is also provided on the second dielectric layer.

[0029] In some embodiments, at a fourth cross section along the first direction, the extension has an overlap portion that overlaps the spacer region, and the second doped layer and the leakage doped portion are separated by the extension.

[0030] In some embodiments, the length of the portion of the silicon substrate covered by the overlapping portion in the first direction is less than 150 nm.

[0031] In some embodiments, at the fourth cross section, the overlap is a discontinuous structure, such that the overlap at the fourth cross section includes a first portion close to the leakage doped portion and a second portion spaced apart from the first portion;

[0032] The second doped layer is conductive to the silicon substrate at the gap between the first and second portions.

[0033] In some embodiments, the length of the portion of the silicon substrate correspondingly covered by the first portion in the first direction is less than 150 nm.

[0034] In some embodiments, in a first direction, the silicon substrate has a silicon wafer extension that extends and hangs over the spacer region, the silicon wafer extension also having a first doped layer, the cross-sectional profile of the silicon wafer extension being triangular, and the angle between the surface of the silicon wafer extension facing the spacer region and the surface of the first region being an acute angle.

[0035] In some embodiments, the extension length of the silicon wafer extension in the first direction is 0.1 μm-3 μm.

[0036] This disclosure also provides a battery assembly, which includes the back contact battery of any of the above.

[0037] This disclosure also provides a photovoltaic system, which includes the aforementioned battery module.

[0038] In the back-contact battery, battery module, and photovoltaic system of this disclosure, a first doped layer is disposed on a first region, and a second doped layer is disposed on a portion of the second region and a spacer region. An insulating dielectric layer is disposed on at least a portion of the first doped layer. At a predetermined position in the spacer region, the insulating dielectric layer has an extension extending out of the first region and bending at least partially toward the side where the silicon substrate is located. The end of the extension at least partially overlaps the spacer region, so that the extension, the first doped layer, and the silicon substrate together form a deposition space. At a first cross-section along a first direction, the extension, the first doped layer, and the silicon substrate together form a closed pattern. A leakage doped portion is disposed within the deposition space enclosed by the extension, the first doped layer, and the silicon substrate and forms a leakage contact with the first doped layer. At a predetermined position, the second doped layer has a first extension extending and covering at least a portion of the extension, the first extension making conductive contact with the leakage doped portion, and the first extension also extending along the first extension to cover at least a portion of the portion of the insulating dielectric layer corresponding to the first doped layer. Thus, by placing the leakage doped portion within the deposition space enclosed by the extension of the insulating dielectric layer, the first doped layer, and the silicon substrate, and by forming a closed pattern together with the first doped layer and the silicon substrate at the first cross-section along the first direction, the efficiency loss of the back contact battery due to leakage contact can be effectively reduced. At the same time, the passivation effect at the leakage contact location can be improved by the extension of the insulating dielectric layer, thereby optimizing the efficiency of the back contact battery.

[0039] Additional aspects and advantages of this disclosure will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this disclosure. Attached Figure Description

[0040] Figure 1 is a schematic diagram of the modules of the photovoltaic system provided in an embodiment of this disclosure;

[0041] Figure 2 is a schematic diagram of the battery assembly provided in an embodiment of this disclosure;

[0042] Figure 3 is a schematic diagram of the planar structure of the back contact battery provided in an embodiment of this disclosure;

[0043] Figure 4 is a cross-sectional view of the back contact battery along line L1-L1 in Figure 3.

[0044] Figure 5 is a cross-sectional view of the back contact battery along line L2-L2 in Figure 3;

[0045] Figure 6 is a cross-sectional view of the back contact battery along line L3-L3 in Figure 3;

[0046] Figure 7 is a schematic diagram of the back contact battery provided in the embodiments of this disclosure at different cross sections;

[0047] Figure 8 is another cross-sectional view of the back contact battery provided in an embodiment of this disclosure;

[0048] Figure 9 is another cross-sectional schematic diagram of the back contact battery provided in the embodiment of this disclosure;

[0049] Figure 10 is a test diagram of the back contact battery at a preset position provided in an embodiment of this disclosure;

[0050] Figure 11 is another test diagram of the back contact battery at a preset position provided in an embodiment of this disclosure. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this disclosure, and should not be construed as limiting this disclosure. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this disclosure and are not intended to limit this disclosure.

[0052] In the description of this disclosure, it should be understood that the terms “length”, “width”, “upper”, “lower”, “top”, “bottom”, “lateral”, “longitudinal”, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0053] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this disclosure, "a plurality of" means two or more, unless otherwise explicitly specified.

[0054] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0055] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0056] The following disclosure provides numerous different embodiments or examples for implementing various structures of this disclosure. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this disclosure. Furthermore, at least one of the reference numerals and letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and arrangements discussed. In addition, various specific examples of processes and materials are provided in this disclosure, but those skilled in the art will recognize at least one other application of processes and use cases for other materials.

[0057] Please refer to Figures 1-2. The photovoltaic system 1000 in this embodiment may include the battery module 200 in this embodiment, and the battery module 200 in this embodiment may include a plurality of back contact batteries 100 in this embodiment.

[0058] In embodiments of this disclosure, multiple back-contact cells 100 in the battery assembly 200 can be connected in series to form multiple battery strings. Each battery string can achieve current output by one of the following methods: series connection, parallel connection, or a combination of series and parallel connection. For example, the connection between individual cells can be achieved by welding solder strips, or the connection between individual battery strings can be achieved by busbars. In some embodiments, the individual battery strings can form a cell array, and then be packaged together by a front plate, a front adhesive film, a rear adhesive film, and a back plate to form the battery assembly 200.

[0059] Please refer to Figures 3 and 4. The back contact battery 100 in this embodiment may include a silicon substrate 10, a first doped layer 20, an insulating dielectric layer 30, a leakage doped portion 40, and a second doped layer 50.

[0060] The silicon substrate 10 may have a front side 11 and a back side 12. The back side 12 includes a plurality of first regions 121 and a plurality of second regions 122, as shown in FIG3. The plurality of first regions 121 and the plurality of second regions 122 are arranged alternately along a first direction. The back side 12 also includes a spacer region 123 located between the first regions 121 and the second regions 122, that is, adjacent first regions 121 and second regions 122 are separated by the spacer region 123. The first regions 121, the second regions 122 and the spacer region 123 all extend along a second direction, which intersects the first direction.

[0061] Specifically, as shown in Figure 3, the first direction can be the lateral direction of the back contact battery 100, and the second direction can be the longitudinal direction of the back contact battery 100. The two directions are perpendicular to each other. That is, the first region 121 and the second region 122 can be alternately arranged along the lateral direction of the silicon substrate 10 and extend along the longitudinal direction, and the spacing region 123 also extends along the longitudinal direction. Of course, it is understood that in other embodiments, the first direction and the second direction can also be other directions. For example, they can be the directions of the two diagonals of the back contact battery 100, respectively. There is no specific limitation here, and they can be selected according to the actual manufacturing process.

[0062] As shown in Figure 4, in one scenario, the surface of the first region 121 may be higher than the surface of the spacer region 123 and the surface of the second region 122 in the direction from the front side 11 to the back side 12. That is, in the thickness direction of the silicon substrate 10, the spacer region 123 and the second region 122 are closer to the front side 11 of the silicon substrate 10 than the first region 121.

[0063] A first doped layer 20 is disposed on a first region 121, and an insulating dielectric layer 30 is disposed on at least a portion of the first doped layer 20. At a predetermined position 1231 of the spacer region 123 (as shown in FIG3), the insulating dielectric layer 30 has an extension 31 extending out of the first region 121 and bending at least partially toward the side where the silicon substrate 10 is located. The end of the extension 31 is at least partially overlapped on the spacer region 123, so that the extension 31, the first doped layer 20, and the silicon substrate 10 together form a deposition space 301.

[0064] As shown in Figure 4, at the first cross-section along the first direction (Figure 4 is a schematic cross-sectional view of the first cross-section, which is the cross-section formed along line L1-L1 in Figure 3), the extension segment 31, together with the first doped layer 20 and the silicon substrate 10, forms a closed pattern 302. That is, along the first direction, the extension segment 31 has multiple cross-sections, which are arranged parallel to each other along the second direction. At one of the cross-sections of the extension segment 31, the extension segment 31, together with the first doped layer 20 and the silicon substrate 10, forms a closed pattern 302. It should be noted that, in this document, the cross-section along the first direction refers to the cross-section taken from the back contact cell 100 along the first direction.

[0065] A leakage doped portion 40 is disposed within the deposition space 301 and forms a leakage contact with the first doped layer 20. The leakage doped portion 40 has the opposite polarity to the first doped layer 20. A second doped layer 50 is disposed on a portion of the second region 122 and the spacer region 123. The polarity of the second doped layer 50 is opposite to that of the first doped layer 20. At a predetermined position 1231, the second doped layer 50 has a first extension portion 51 extending and covering at least a portion of the extension section 31. The first extension portion 51 is in conductive contact with the leakage doped portion 40, and the first extension portion 51 also extends and covers at least a portion of the portion of the insulating dielectric layer 30 corresponding to the first doped layer 20. That is, at the predetermined position 1231 of the spacer region 123, the first doped layer 20 and the second doped layer 50 form a leakage contact through the leakage doped portion 40.

[0066] It should be noted that, in this document, the description of a film layer being disposed on a certain surface region or a part or all of a certain film layer can refer to the film layer being directly stacked on the surface region or a certain film layer, or it can refer to the film layer being disposed with other film layers between the film layer and the surface or film layers. The term "coverage" is merely used to define the specific placement range of the film layer. For example, in some embodiments, a dielectric layer may be present between the surface of the first doped layer 20 and the first region 121, a dielectric layer may also be present between the surface of the second doped layer 50 and the second region 122, and a dielectric layer may also be present between the leakage doped portion 40 and the silicon substrate 10. Specific details are not limited here.

[0067] In addition, it should be noted that in this article, "leakage contact" refers to the fact that there is no insulation between the leakage doped part 40 and the first doped layer 20, but leakage conduction forms a leakage point. The two can be in direct contact to form a leakage point, or they can achieve the function of leakage contact by tunneling through other dielectric layers. No specific restrictions are made here.

[0068] In the back contact battery 100, battery module 200, and photovoltaic system 1000 of this disclosure embodiment, a first doped layer 20 is disposed on a first region 121, and a second doped layer 50 is disposed on a portion of the second region 122 and the spacer region 123. An insulating dielectric layer 30 is disposed on at least a portion of the first doped layer 20. At a predetermined position 1231 in the spacer region 123, the insulating dielectric layer 30 has an extension 31 extending out of the first region 121 and bending at least partially toward the side where the silicon substrate 10 is located. The end of the extension 31 is at least partially overlapped on the spacer region 123, so that the extension 31, the first doped layer 20, and the silicon substrate 10 together form a deposition space 301. At a first cross-section along a first direction, the extension 31, the first doped layer 20, and the silicon substrate 10 together form a closed pattern 302. A leakage doped portion 40 is disposed within the deposition space 301 enclosed by the extension 31, the first doped layer 20, and the silicon substrate 10 and forms a leakage contact with the first doped layer 20. At a preset position 1231, the second doped layer 50 has a first extension 51 extending over at least a portion of the extension 31, the first extension 51 being in conductive contact with the leakage doped portion 40, and the first extension 51 also extending along the first extension 51 to cover at least a portion of the portion of the insulating dielectric layer 30 corresponding to the first doped layer 20. Thus, the leakage doped portion 40 makes leakage contact with the first doped layer 20 and conductive contact with the first extension portion 51 of the second doped layer 50. It can form a leakage point at the preset position 1231 of the spacer region 123, thereby improving the hot spot resistance of the back contact battery 100. By setting the leakage doped portion 40 in the deposition space 301 formed by the extension 31 of the insulating dielectric layer 30, the first doped layer 20, and the silicon substrate 10, and forming a closed pattern 302 together with the first doped layer 20 and the silicon substrate 10 at the first cross section along the first direction, the efficiency loss of the back contact battery 100 due to leakage contact can be effectively reduced. At the same time, the passivation effect at the leakage contact position can be improved by the extension 31 of the insulating dielectric layer 30, thereby optimizing the efficiency of the back contact battery 100. Furthermore, as a possible scenario, by using the closed design of the extension section 31 at a portion of the cross-section, the doping concentration of the leakage doped portion 40 can be made lower than the doping concentration of the second doped layer 50 during the deposition process, thereby reducing the efficiency loss after the formation of the leakage contact and improving the efficiency of the back contact battery 100.

[0069] In other words, in this disclosure, by designing the extension 31 of the insulating dielectric layer 30 to form a deposition space 301 with the first doped layer 20 and the silicon substrate 10, the pattern formed at the first cross section is a closed pattern 302. Then, by designing the leakage doped portion 40, the hot spot resistance performance of the back contact battery 100 can be improved while reducing the efficiency loss caused by leakage contact, thereby ensuring the efficiency of the back contact battery 100.

[0070] Specifically, in the embodiments of this disclosure, the silicon substrate 10 can be a P-type silicon substrate 10 or an N-type silicon substrate 10, preferably an N-type silicon substrate 10, but no specific limitation is made here.

[0071] The first doped layer 20 is a P-type doped layer, and the second doped layer 50 is an N-type doped layer. Alternatively, the first doped layer 20 can be an N-type doped layer, and the second doped layer 50 can be a P-type doped layer. No specific restrictions are imposed here, as long as their polarities are opposite. The leakage doped portion 40 has the opposite doping type to the first doped layer 20 and the same doping type as the second doped layer 50.

[0072] It should be noted that in the embodiments of this disclosure, "preset position 1231" can be understood as the entire interval 123 or a part of the interval 123, and there is no specific limitation here. As shown in FIG3, in some embodiments, the preset position 1231 is preferably a part of the interval 123. In this case, the number of preset positions 1231 in each interval 123 can be single or multiple. As shown in FIG3, in a single interval 123, multiple preset positions 1231 can be spaced apart along the second direction, and there is no specific limitation here.

[0073] Furthermore, in the embodiments of this disclosure, the number of interval regions 123 with preset positions 1231 can be single or multiple, and there is no specific limitation herein. Further, in some embodiments, the number of preset positions 1231 can be multiple, and they can be evenly distributed on the back surface 12 of the back contact battery 100.

[0074] The insulating dielectric layer 30 may be a dielectric layer with insulating function. For example, in some embodiments, the insulating dielectric layer 30 may be one of the following: a borosilicate glass layer, a phosphosilicate glass layer, and a borosilicate phosphosilicate glass layer. In other embodiments, the insulating dielectric layer 30 may have an insulating silicon oxide layer, a silicon nitride layer, etc. Furthermore, in some embodiments, the insulating dielectric layer 30 may be a single-layer structure or a multi-layer structure; no specific limitation is made herein.

[0075] Furthermore, in embodiments of this disclosure, the back contact battery 100 may further include a first electrode (not shown) and a second electrode (not shown). A back passivation film layer (not shown) may also be provided on the back side 12 of the silicon substrate 10, which may cover the entire back side 12. The first electrode may be located in the first region 121 and penetrate the back passivation film layer to form an ohmic contact with the first doped layer 20 and be insulated from the second doped layer 50. For example, the first electrode may be located at a position where the first doped layer 20 is not covered by the first extension 51, and the second electrode may be located in the second region 122 and penetrate the back passivation film layer to form an ohmic contact with the second doped layer 50.

[0076] Referring to Figure 4, in some embodiments, a first dielectric layer 60 is provided on the surface where the first doped layer 20 and the leakage doped portion 40 form a leakage contact, and the leakage doped portion 40 and the first doped layer 20 form a leakage contact through the first dielectric layer 60.

[0077] Thus, by setting the first dielectric layer 60, the passivation effect at the leakage contact point can be improved, reducing efficiency loss.

[0078] Specifically, the first dielectric layer 60 may be a film layer with passivation and conductivity functions, such as a tunneling oxide layer (e.g., a tunneling silicon oxide film layer) and an intrinsic amorphous silicon layer, etc., without any specific limitations.

[0079] Please refer to Figure 4. In the spacer region 123, a second dielectric layer 70 is provided at least at a preset position 1231. The end of the extension segment 31 is at least partially overlapped on the second dielectric layer 70, and the leakage doped portion 40 is also provided on the second dielectric layer 70.

[0080] Thus, by setting the second dielectric layer 70, the passivation effect of the spacer region 123 can be improved, thereby increasing efficiency.

[0081] Specifically, the second dielectric layer 70 may be, for example, a tunneling oxide layer (e.g., a tunneling silicon oxide film) and an intrinsic amorphous silicon layer.

[0082] In addition, in some embodiments, a third dielectric layer (not shown) is provided between the first doped layer 20 and the silicon substrate 10, and a fourth dielectric layer 80 is provided between the second doped layer 50 and the silicon substrate 10.

[0083] This can improve the passivation effect of Zone 121 and Zone 122, thereby enhancing the overall effect.

[0084] Specifically, the third dielectric layer and the fourth dielectric layer 80 can both be, for example, tunneling oxide layers (e.g., tunneling silicon oxide films) and intrinsic amorphous silicon layers.

[0085] In some embodiments, a through hole (not shown) may be formed on the extension 31 of the insulating dielectric layer 30, and the first extension 51 makes conductive contact with the leakage doped portion 40 through the through hole.

[0086] Thus, by forming several through holes on the extension 31, it is convenient to deposit the leakage doped portion 40 in the deposition space 301. At the same time, the first extension 51 can form a conductive contact with the leakage doped portion 40 through the through holes. At other continuous positions, the first extension 51 and the leakage doped portion 40 are isolated by the extension 31, which can avoid the first extension 51 and the leakage doped portion 40 from forming contact and causing excessive efficiency loss, and can also improve the passivation effect.

[0087] Specifically, in such an embodiment, the through hole on the extension 31 can be single or multiple, and there is no specific limitation here.

[0088] Referring to Figure 5, in some embodiments, at the second cross-section along the first direction (Figure 5 is a schematic cross-sectional view of the second cross-section, which is the cross-section formed along line L2-L2 in Figure 3), the end of the extension 31 is suspended on the spacer region 123. The extension 31, together with the first doped layer 20 and the silicon substrate 10, forms a non-closed pattern 303 with an opening 304. The second doped layer 50 and the leakage doped portion 40 are in conductive contact at the opening 304. The first cross-section and the second cross-section are parallel to each other in the second direction.

[0089] Thus, at the first cross-section, the extension 31, the first doped layer 20, and the silicon substrate 10 form a closed pattern 302. At the second cross-section, the extension 31, the first doped layer 20, and the silicon substrate 10 together form a non-closed pattern 303 with an opening. This allows the leakage doped portion 40 to make conductive contact with the second doped layer 50 at the opening of the non-closed pattern 303, thereby enabling the first doped layer 20 and the second doped layer 50 to form a leakage contact. This design of the extension 31 reduces the efficiency loss caused by leakage contact.

[0090] Referring to Figures 4 and 5, in some embodiments, in the second direction, the extension 31 has a first portion 311 with its end overlapping the spacer region 123 and a second portion 312 with its end suspended on the spacer region 123. The second portion 312 has a gap 305 with the surface of the spacer region 123, and the second doped layer 50 makes conductive contact with the leakage doped portion 40 through the gap.

[0091] Thus, at the cross-section of the first portion 311, the first portion 311, together with the first doped layer 20 and the silicon substrate 10, forms a closed pattern 302, isolating the leakage doped portion 40 and the second doped layer 50. At the cross-section of the second portion 312, the second portion 312, together with the first doped layer 20 and the silicon substrate 10, forms a non-closed pattern 303. The second doped layer 50 forms a conductive contact with the leakage doped portion 40 through the gap at the non-closed pattern 303. In this way, while achieving conductivity between the second doped layer 50 and the leakage doped portion 40, the size of the conductive area between the second doped layer 50 and the leakage doped portion 40 can be controlled, reducing the efficiency loss caused by leakage contact.

[0092] Furthermore, in such an embodiment, the gap 305 between the second portion 312 and the surface of the spacer region 123 is 5nm-800nm, that is, in the thickness direction of the silicon substrate 10, the gap between the end of the second portion 312 and the silicon substrate 10 is 5nm-800nm.

[0093] In this way, the conduction area between the leakage doped part 40 and the second doped layer 50 can be controlled within a reasonable range while achieving conduction between them, thereby reducing efficiency loss.

[0094] Specifically, the gap between the end of the second part 312 and the silicon substrate 10 can be any value between 5nm and 800nm, for example, one of the following: 5nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm.

[0095] Referring to Figure 6, in some embodiments, at the third cross-section along the first direction (Figure 6 is a cross-sectional view of the second cross-section, and the third cross-section is the cross-section formed along line L3-L3 in Figure 3), the leakage doped portion 40 has a cavity 41, and the third cross-section is parallel to the first cross-section in the second direction. That is, in some embodiments, a cavity 41 may be formed within the leakage doped portion 40.

[0096] Thus, the cavity 41 can effectively release the local stress generated during the fabrication of the leakage doped portion 40, effectively reduce the probability of the leakage doped portion 40 expanding into the silicon substrate 10 through the second dielectric layer 70 during the high-temperature doping process, reduce interface defects between the silicon substrate 10 and the second dielectric layer 70, reduce the surface recombination rate, and increase the collection probability of photogenerated carriers.

[0097] Specifically, in such embodiments, the third section may be the same as the first section, or the third section may be the same as the second section. Of course, in some embodiments, the third section may also be a section different from both the first and second sections. In such cases, the first, second, and third sections are parallel to each other in the second direction.

[0098] In some embodiments, the outer diameter of cavity 41 is 10nm-500nm.

[0099] In this way, while ensuring that the cavity 41 can release the local stress of the leakage doped part 40, the contact area of ​​the leakage doped part 40 forming a leakage contact with the first doped layer 20 through the first dielectric layer 60 can be maintained.

[0100] Specifically, in such an embodiment, the outer diameter of the cavity 41 can be any value between 10nm and 500nm, for example, one of the following: 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm.

[0101] In summary, as shown in Figure 7, which illustrates the cross-sectional structure at different cross-sections, it can be seen from Figure 7 that in this disclosure, at different cross-sections, the extension 31, the first doped layer 20, and the silicon substrate 10 form different patterns. At some cross-sections, the three form a closed pattern, and at some cross-sections, they form a non-closed pattern.

[0102] Referring to Figure 4, in some embodiments, the angle between the surface of the first doped layer 20 and the leakage doped portion 40 forming a leakage contact and the surface of the first region 121 is an acute angle, and the surface of the first doped layer 20 and the leakage doped portion 40 forming a leakage contact has a first recessed region 201.

[0103] Thus, by setting the angle between the leakage contact surface of the first doped layer 20 and the surface of the first region 121 to an acute angle and forming a first recessed region 201 on the leakage contact surface, the leakage doped portion 40 can be deposited more easily to form a leakage contact with the first doped layer 20 more easily.

[0104] Furthermore, in such an embodiment, the surface where the first doped layer 20 and the leakage doped portion 40 form a leakage contact is curved. This increases the leakage contact area between the first doped layer 20 and the leakage doped portion 40, thereby improving the resistance to hot spots.

[0105] Referring to FIG8, in some embodiments, the first doped layer 20 has a second extension 21 extending along a first direction and suspended on the spacer region 123. The insulating dielectric layer 30 covers the surface of the second extension 21 facing away from the silicon substrate 10. The extension 31, the second extension 21, and the silicon substrate 10 together form a deposition space 301. The leakage doped portion 40 forms a leakage contact with the second extension 21.

[0106] Thus, by providing the second extension 21, the leakage contact area between the first doped layer 20 and the leakage doped portion 40 can be increased, so as to avoid the contact area between the first doped layer 20 and the leakage doped portion 40 being too small and failing to achieve the expected hot spot resistance effect.

[0107] Simultaneously, through the provision of the second extension 21, there are relatively spaced deposition regions between the second extension 21 and the silicon substrate 10. During the subsequent deposition of the back passivation film, the provision of such deposition regions can suppress the full exchange of plasma components between this region and the plasma components outside this region, thereby achieving a localized distribution of the mobile hydrogen content in the back passivation film on the back side 12. This results in a lower mobile hydrogen content in the back passivation film within the deposition region and a higher mobile hydrogen content in the back passivation film in other regions, achieving optimal passivation and anti-attenuation effects. In addition, it can also reduce the direct bombardment of the silicon substrate 10 by the plasma, reducing bombardment damage.

[0108] In some embodiments, the leakage doped portion 40 may form a leakage contact with at least one of the following: the surface of the second extension 21 facing the spacer region 123 (i.e., the lower surface of the second extension 21 shown in FIG8), and the end face of the second extension 21 in the first direction (i.e., the side face of the second extension 21 located at the end and connecting the upper and lower surfaces of the second extension 21).

[0109] This design allows for a stable leakage contact to be formed between the leakage doped portion 40 and the first doped layer 20.

[0110] In some embodiments, the extension length of the second extension 21 in the first direction may be 0.1 μm-3 μm.

[0111] Thus, by setting the length of the second extension 21 within the aforementioned range, efficiency can be guaranteed while enhancing the heat spot resistance of the back contact battery 100, which means that the efficiency and heat spot resistance of the back contact battery 100 can be balanced.

[0112] Specifically, the extension length of the second extension 21 in the first direction can be any value between 0.1μm and 3μm, for example, 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, or 3μm.

[0113] Please refer to Figure 8. The leakage doped portion 40 and the end face of the second extension portion 21 form a leakage contact in the first direction. The angle between the end face of the second extension portion 21 and the surface of the first region 121 is an acute angle, and the end face of the second extension portion 21 has a second recessed region 211.

[0114] Thus, by setting the angle between the end face of the second extension 21 and the surface of the first region 121 to an acute angle and forming a second recessed region 211 on the end face, the leakage doped portion 40 can be deposited more easily to form a leakage contact with the second extension 21.

[0115] Referring to Figure 9, in some embodiments, at a fourth cross-section along the first direction (the fourth cross-section may be the same as the first cross-section and the third cross-section, or the fourth cross-section may be different from the first cross-section and the third cross-section, which is not limited here), the extension 31 has an overlap portion 313 that overlaps the spacer region 123. The second doped layer 50 and the leakage doped portion 40 are separated by the extension 31. Specifically, at the fourth cross-section, the extension 31 forms a closed pattern with the first doped layer 20 and the silicon substrate 10.

[0116] As shown in FIG9, in some embodiments, the length of the portion of the silicon substrate 10 covered by the overlapping portion 313 in the first direction is less than 150nm, for example 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, 100nm, or 150nm.

[0117] Thus, even if the extension 31 forms a closed pattern with the first doped layer 20 and the silicon substrate 10 at all cross sections, the length of the substrate portion covered by the overlap 313 can be set within a narrow range of less than 150 nm, so that the second doped layer 50 can be directly connected to the leakage doped portion 40, thereby forming a leakage path among the first doped layer 20, the leakage doped portion 40, and the second doped layer 50, thereby improving the hot spot resistance performance.

[0118] Of course, referring to Figures 10 and 11, in some embodiments, at the fourth cross section, the overlap 313 may be a discontinuous structure, such that the overlap 313 at the fourth cross section includes a first portion 3131 near the leakage doped portion 40 and a second portion 3132 spaced apart from the first portion 3131.

[0119] The second doped layer 50 is connected to the silicon substrate 10 at the gap 3133 between the first portion 3131 and the second portion 3132.

[0120] In such an embodiment, the portion of the silicon substrate 10 correspondingly covered by the first portion 3131 has a length of less than 150 nm in the first direction, such as 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, or 150 nm.

[0121] Thus, by setting the overlap portion 313 as a discontinuous structure, it is only necessary to control the length of the substrate portion covered by the first portion 3131 in the first direction to be less than 150nm, so that the second doped layer 50 is equivalent to being directly connected to the leakage doped portion 40. This allows the first doped layer 20, the leakage doped portion 40, and the second doped layer 50 to form a leakage path, thereby reducing the control requirements on the overall length of the entire overlap portion 313 and reducing the manufacturing process difficulty.

[0122] It is easy to understand that this embodiment differs from the previous embodiment in that: in this embodiment, the overlap portion 313 is configured as an intermittent first portion 3113 and second portion 3132 at the fourth cross-section, and the length of the silicon base portion corresponding to the first portion 3131 in the first direction is controlled to allow the second doped layer 50 to directly conduct through the silicon substrate 10 to the leakage doped portion 40. In the previous embodiment, the second doped layer 50 was directly connected to the leakage doped portion 40 through the silicon substrate 10 by directly controlling the overall length of the overlap portion 313 at the fourth cross-section.

[0123] Specifically, in these two embodiments, although the second doped layer 50 is not in direct contact with the leakage doped portion 40 at the fourth cross section, by controlling the length of the portion of the silicon substrate 10 covered by the overlapping portion 313 or the first portion 3131 of the overlapping portion 313 in the first direction to a very small range of less than 150nm, it is equivalent to the second doped layer 50 and the leakage doped portion 40 being directly connected. In this way, it is also possible for the two to directly form a leakage connection.

[0124] Referring to Figures 8, 10, and 11, in the first direction, the silicon substrate 10 has a silicon wafer extension 13 extending and suspended over the spacer region 123. A first doped layer 20 is also provided on the silicon wafer extension 13 (i.e., the upper surface of the silicon wafer extension 13 shown in the figures is provided with the first doped layer 20, for example, the second extension 21 mentioned above). The cross-sectional profile of the silicon wafer extension 13 is triangular, and the angle between the surface of the silicon wafer extension 13 facing the spacer region 123 and the surface of the first region 121 (i.e., the lower surface of the silicon wafer extension 13 shown in the figures) is an acute angle.

[0125] Thus, by controlling the etching process, the side of the spacer region 123 of the silicon substrate 10 can have a recessed structure, which can play a role in limiting the gas source during the deposition process of the leakage doped part 40. The diffusion of the gas source is restricted here, which can effectively reduce the doping concentration of the leakage doped part 40 and the silicon substrate contact surface, reduce the interface recombination rate, and increase the collection probability of charge carriers. At the same time, it is also conducive to the formation of the cavity 41, which can effectively eliminate local stress.

[0126] In some embodiments, the extension length of the silicon wafer extension 13 in the first direction may be 0.1 μm-3 μm.

[0127] Thus, by controlling the extension length of the silicon wafer extension 13 within this reasonable range, the interface recombination rate can be further optimized to achieve better carrier collection efficiency.

[0128] Specifically, the extension length of the silicon wafer extension 13 in the first direction can be any value between 0.1μm and 3μm, for example, 0.1μm, 0.2μm, 0.4μm, 0.6μm, 0.8μm, 1μm, 1.2μm, 1.4μm, 1.6μm, 1.8μm, 2μm, 2.2μm, 2.4μm, 2.6μm, 2.8μm, or 3μm.

[0129] In the description of this specification, references to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0130] Furthermore, the above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A back-contact battery, comprising: A silicon substrate having opposing front and back sides, the back side including a plurality of first regions and a plurality of second regions arranged alternately along a first direction, and a spacer region between the first regions and the second regions, the first regions, the second regions and the spacer region all extending along a second direction, the second direction intersecting the first direction; A first doped layer disposed on the first region; An insulating dielectric layer is disposed on at least a portion of the first doped layer. At a predetermined position in the spacer region, the insulating dielectric layer has an extension extending out of the first region and bending at least partially toward the side where the silicon substrate is located. The end of the extension at least partially overlaps the spacer region, so that the extension, the first doped layer, and the silicon substrate together form a deposition space. In a first cross-section along the first direction, the extension, the first doped layer, and the silicon substrate together form a closed pattern. A leakage doped portion, wherein the leakage doped portion is disposed within the deposition space and forms a leakage contact with the first doped layer, and the polarity of the leakage doped portion is opposite to that of the first doped layer; and A second doped layer is disposed on a portion of the second region and the spacer region, the polarity of the second doped layer being opposite to that of the first doped layer. At the preset position, the second doped layer has a first extension extending over at least a portion of the extension, the first extension being in conductive contact with the leakage doped portion, and the first extension also extending along the first extension to cover at least a portion of the portion of the insulating dielectric layer corresponding to the first doped layer.

2. The back contact battery according to claim 1, wherein, A through hole is formed on the extension section, and the first extension makes conductive contact with the leakage doped part through the through hole.

3. The back contact battery according to claim 1, wherein, At a second cross section along the first direction, the end of the extension is suspended over the spacer region. The extension, together with the first doped layer and the silicon substrate, forms a non-closed pattern with an opening. The second doped layer and the leakage doped portion are in conductive contact at the opening. The first cross section and the second cross section are parallel to each other in the second direction.

4. The back contact battery according to claim 1, wherein, In the second direction, the extension has a first portion with its end overlapping the spacer region and a second portion with its end suspended in the spacer region, the second portion having a gap with the surface of the spacer region, and the second doped layer making conductive contact with the leakage doped portion through the gap.

5. The back contact battery according to claim 4, wherein, The gap between the second part and the surface of the spacer region is 5nm-800nm.

6. The back contact battery according to claim 1, wherein, At the third cross section along the first direction, the leakage doped portion has a cavity.

7. The back contact battery according to claim 6, wherein, The outer diameter of the cavity is 10nm-500nm.

8. The back contact battery according to claim 1, wherein, The angle between the surface of the first doped layer and the leakage doped portion forming a leakage contact and the surface of the first region is an acute angle, and the surface of the first doped layer and the leakage doped portion forming a leakage contact has a first recessed region.

9. The back contact battery according to claim 8, wherein, The surface on which the first doped layer and the leakage doped portion form a leakage contact is a curved surface.

10. The back contact battery according to claim 1, wherein, The first doped layer has a second extension that extends along the first direction and is suspended over the spacer region. The insulating dielectric layer covers the surface of the second extension facing away from the silicon substrate. The extension, the second extension, and the silicon substrate together form the deposition space. The leakage doped portion forms a leakage contact with the second extension.

11. The back contact battery according to claim 10, wherein, The back contact battery satisfies at least one of the following: the leakage doped portion and the surface of the second extension portion facing the spacer region form a leakage contact; the leakage doped portion and the end face of the second extension portion in the first direction form a leakage contact.

12. The back contact battery according to claim 11, wherein, The leakage doped portion and the end face of the second extension portion form a leakage contact in the first direction, the angle between the end face of the second extension portion and the surface of the first region is an acute angle, and the end face of the second extension portion has a second recessed region.

13. The back contact battery according to claim 10, wherein, The extension length of the second extension in the first direction is 0.1μm-3μm.

14. The back contact battery according to claim 1, wherein, A first dielectric layer is provided on the surface where the first doped layer and the leakage doped portion form a leakage contact, and the leakage doped portion and the first doped layer form a leakage contact through the first dielectric layer.

15. The back contact battery according to claim 1, wherein, A second dielectric layer is provided at least at the preset position on the interval region, and the end of the extension section is at least partially overlapped on the second dielectric layer. The leakage doped portion is also provided on the second dielectric layer.

16. The back contact battery according to claim 1, wherein, At a fourth cross section along the first direction, the extension has an overlap portion that overlaps the spacer region, and the second doped layer and the leakage doped portion are separated by the extension.

17. The back contact battery according to claim 16, wherein, The length of the portion of the silicon substrate covered by the overlapping portion in the first direction is less than 150 nm.

18. The back contact battery according to claim 16, wherein, At the fourth cross-section, the overlapping portion is a discontinuous structure, such that the overlapping portion at the fourth cross-section includes a first portion close to the leakage doped portion and a second portion spaced apart from the first portion; The second doped layer is conductive to the silicon substrate at the gap between the first portion and the second portion.

19. The back contact battery according to claim 18, wherein, The portion of the silicon substrate covered by the first portion has a length of less than 150 nm in the first direction.

20. The back contact battery according to claim 1, wherein, In the first direction, the silicon substrate has a silicon wafer extension that extends and is suspended over the spacer region. The silicon wafer extension is also provided with the first doped layer. The cross-sectional profile of the silicon wafer extension is triangular, and the angle between the surface of the silicon wafer extension facing the spacer region and the surface of the first region is an acute angle.

21. The back contact battery according to claim 20, wherein, The silicon wafer extension has an extension length of 0.1 μm to 3 μm in the first direction.

22. A battery assembly comprising a back contact battery as described in any one of claims 1-21.

23. A photovoltaic system comprising the battery module of claim 22.

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