Capacitor

Abstract

This capacitor comprises a silicon substrate, a dielectric layer, and a conductor layer. The silicon substrate includes a porous part having a plurality of holes. The dielectric layer covers the surface of the porous part of the silicon substrate. The conductor layer covers the dielectric layer. The dielectric layer includes a first dielectric part and a second dielectric part. The first dielectric part is in contact with the surface of the porous part and has a plurality of through holes. The second dielectric part is in contact with the surface of the porous part and is positioned inside each of the plurality of through holes. The material of the second dielectric part is silicon oxide. The material of the first dielectric part includes a first dielectric material having a dielectric constant higher than that of silicon oxide.

Description

Capacitor

[0001] This disclosure relates to a capacitor, and more particularly to a capacitor comprising a silicon substrate.

[0002] The capacitor disclosed in Patent Document 1 comprises a silicon substrate, a dielectric layer, and a conductive layer. The silicon substrate has a porous portion provided in the thickness direction. The porous portion has a plurality of pores. The dielectric layer covers the inner surface of the plurality of pores in the porous portion. The conductive layer covers the dielectric layer.

[0003] International Publication No. 2020 / 184517

[0004] A capacitor according to one aspect of the present disclosure comprises a silicon substrate, a dielectric layer, and a conductive layer. The silicon substrate includes a porous portion having a plurality of holes. The dielectric layer covers the surface of the porous portion on the silicon substrate. The conductive layer covers the dielectric layer. The dielectric layer includes a first dielectric portion and a second dielectric portion. The first dielectric portion is in contact with the surface of the porous portion and has a plurality of through holes. The second dielectric portion is in contact with the surface of the porous portion and is located inside each of the plurality of through holes. The material of the second dielectric portion is silicon oxide. The material of the first dielectric portion includes a first dielectric material having a higher dielectric constant than silicon oxide.

[0005] According to the capacitor of the above embodiment of this disclosure, it is possible to reduce the occurrence of cracks in the dielectric layer caused by thermal stress.

[0006] Figure 1 is a partially broken perspective view showing a capacitor according to the embodiment. Figure 2 is a cross-sectional view of the main part of the capacitor according to the embodiment. Figure 3 is an enlarged view of the main part of Figure 2 showing a capacitor according to the embodiment. Figure 4 is a plan view of a part of the dielectric layer in the capacitor according to the embodiment, viewed from the direction of stacking of the dielectric layer on the surface of the porous part. Figure 5 is a plan view of the capacitor according to the embodiment. Figure 6 is a cross-sectional view illustrating a method for manufacturing the capacitor according to the embodiment. Figure 7 is a cross-sectional view illustrating the first step in the method for manufacturing the capacitor according to the embodiment. Figure 8 is a cross-sectional view illustrating the second step in the method for manufacturing the capacitor according to the embodiment. Figure 9 is a cross-sectional view illustrating the third step in the method for manufacturing the capacitor according to the embodiment. Figure 10 is a cross-sectional view illustrating the fourth step in the method for manufacturing the capacitor according to the embodiment. Figure 11 is a cross-sectional view illustrating the fifth step in the method for manufacturing the capacitor according to the embodiment. Figure 12 is an explanatory diagram of thermal stress generated in the dielectric layer in the capacitor according to the embodiment. Figure 13 is a cross-sectional view of the main part of a capacitor according to modified example 1 of the embodiment. Figure 14 is an explanatory diagram of thermal stress generated in the dielectric layer in a capacitor according to modified example 1 of the embodiment. Figure 15 is a cross-sectional view of the main part of a capacitor according to modified example 2 of the embodiment. Figure 16 is an explanatory diagram of thermal stress generated in the dielectric layer of a capacitor according to modified example 2 of the embodiment. Figure 17 is a cross-sectional view of the main part of a capacitor according to modified example 3 of the embodiment. Figure 18 is a cross-sectional view of the main part of a capacitor according to modified example 4 of the embodiment.

[0007] In capacitors, cracks can occur in the dielectric layer due to thermal stress.

[0008] This disclosure provides a capacitor capable of reducing the occurrence of cracks in the dielectric layer caused by thermal stress.

[0009] The embodiments will be described below with reference to the drawings. The drawings referenced in the following embodiments are schematic, and the size and thickness of the components shown in the drawings do not necessarily reflect the actual dimensions, nor do the size ratios and thickness ratios between components necessarily reflect the actual dimensional ratios.

[0010] (Embodiment) (1) Capacitor Hereinafter, the capacitor 1 according to the embodiment will be described with reference to Figures 1 to 5. Note that the cross-section in Figure 1 corresponds to the cross-section along line X-X in Figure 5.

[0011] The capacitor 1 comprises a silicon substrate 2, a dielectric layer 4, and a conductive layer 5. The silicon substrate 2 includes a porous portion 23 having a plurality of holes 24. The dielectric layer 4 covers the surface 231 of the porous portion 23. The conductive layer 5 covers the dielectric layer 4.

[0012] In capacitor 1, the silicon substrate 2 constitutes the first electrode of capacitor 1, and the conductive layer 5 constitutes the second electrode of capacitor 1. Therefore, in capacitor 1, the dielectric layer 4 is interposed between the first electrode and the second electrode.

[0013] Furthermore, the capacitor 1 comprises a first external connection electrode 7 and a second external connection electrode 8. The first external connection electrode 7 is connected to the silicon substrate 2. The second external connection electrode 8 is connected to the conductive layer 5.

[0014] (2) Components of the Capacitor Below, each component of capacitor 1 will be described in more detail.

[0015] (2.1) Silicon Substrate As shown in Figure 1, the silicon substrate 2 has a first main surface 21 and a second main surface 22 opposite to the first main surface 21. In a plan view from the thickness direction D1 of the silicon substrate 2, the outer edge of the silicon substrate 2 is rectangular. The thickness of the silicon substrate 2 is, for example, 300 μm or more and 1 mm or less.

[0016] The first main surface 21 of the silicon substrate 2 includes a first region A1 on which a porous portion 23 is formed, and a second region A2 surrounding the first region A1. In a plan view from the thickness direction D1 of the silicon substrate 2, the first region A1 is a rectangular region and is surrounded by the second region A2 (see Figure 5). The first region A1 is not limited to a rectangular region when viewed from the thickness direction D1 of the silicon substrate 2, but may also be a circular region, a polygonal region other than a rectangle, or a polygonal region other than a convex polygon.

[0017] As shown in Figures 1 and 2, the porous portion 23 has a plurality of holes 24 (hereinafter also referred to as pores 24) extending along the thickness direction D1 of the silicon substrate 2. The plurality of pores 24 are formed on the first main surface 21 of the silicon substrate 2. The plurality of pores 24 are holes whose depth in the thickness direction D1 of the silicon substrate 2 from the first main surface 21 of the silicon substrate 2 is longer than the opening width of the pore 24 on the first main surface 21 of the silicon substrate 2. Each of the plurality of pores 24 is formed to extend from the first main surface 21 of the silicon substrate 2 along the thickness direction of the silicon substrate 2 and does not reach the second main surface 22. In other words, each of the plurality of pores 24 does not penetrate the silicon substrate 2 in the thickness direction D1 of the silicon substrate 2. That is, each of the plurality of pores 24 is spaced apart from the second main surface 22 of the silicon substrate 2. The opening width of the plurality of pores 24 on the first main surface 21 of the silicon substrate 2 is, for example, 0.1 μm or more and 10 μm or less. Furthermore, the depth of the multiple pores 24 is smaller than the thickness of the silicon substrate 2. The depth of the multiple pores 24 in the thickness direction D1 of the silicon substrate 2 is, for example, 20 μm or more and 300 μm or less, and more preferably 30 μm or more and 100 μm or less. The upper limit of the depth of the multiple pores 24 can be appropriately determined, for example, by the opening width of the multiple pores 24, the formation method of the dope layer 3, dielectric layer 4 and conductive layer 5, etc. The opening width and depth of the pores 24 in the porous portion 23 of the silicon substrate 2 are values ​​obtained from a cross-sectional SEM (Scanning Electron Microscope) image of the capacitor 1.

[0018] The surface 231 of the porous portion 23 includes the inner surface 241 of each of the plurality of pores 24 formed in the first main surface 21 of the silicon substrate 2, and a part of the first main surface 21 of the silicon substrate 2.

[0019] The capacitance of capacitor 1 can be increased by increasing the surface area of ​​the surface 231 of the porous portion 23, as the depth of each of the multiple pores 24 in the porous portion 23 increases. Furthermore, the capacitance of capacitor 1 can be increased by increasing the surface area of ​​the surface 231 of the porous portion 23, as the number of pores 24 in the porous portion 23 increases.

[0020] In the capacitor 1 of this embodiment, the porous portion 23 of the silicon substrate 2 is formed, for example, by performing an anodic oxidation treatment on the silicon wafer that forms the basis of the silicon substrate 2. The plurality of pores 24 of the porous portion 23 are formed by performing an anodic oxidation treatment on the silicon wafer in a region corresponding to the first region A1 of the silicon substrate 2.

[0021] In the capacitor 1 of this embodiment, as shown in Figure 2, the distance L1 between two adjacent pores 24 is non-uniform in the thickness direction D1 of the silicon substrate 2. In the capacitor 1, the surface area of ​​the surface 231 of the porous portion 23 can be increased compared to the case where the distance L1 between two adjacent pores 24 is uniform in the thickness direction D1 of the silicon substrate 2. Note that the distance L1 between two adjacent pores 24 becomes uniform in the thickness direction D1 of the silicon substrate 2 when the multiple pores 24 are formed, for example, by dry etching. Also, in the capacitor 1, the opening width of each of the multiple pores 24 is non-uniform in the thickness direction D1 of the silicon substrate 2.

[0022] In the capacitor 1 of this embodiment, when viewed from a second direction D2 perpendicular to the thickness direction D1 (hereinafter also referred to as the first direction D1) of the silicon substrate 2, the inner surface 241 of one of the two adjacent pores 24 and the inner surface 241 of the other pore 24 are not straight lines, but rather lines with irregularities. The difference in height between the peaks and valleys in the irregularities is smaller than the opening width of the pore 24. The difference in height between the peaks and valleys in the irregularities is a value obtained, for example, from a cross-sectional SEM (Scanning Electron Microscope) image of the capacitor 1. The difference in height between the peaks and valleys in the irregularities can be changed, for example, by the impurity concentration of the silicon wafer that forms the silicon substrate 2, the conditions of the anodizing treatment, etc.

[0023] In the capacitor 1, the impurity concentration of the body region 26 between the doped layer 3 and the second main surface 22 in the silicon substrate 2 is the same as the impurity concentration of the silicon wafer 20. Also, the carrier concentration of the body region 26 in the silicon substrate 2 is the same as the carrier concentration of the silicon wafer 20. When the silicon substrate 2 is formed using the silicon wafer 20, the body region 26 in the silicon substrate 2 contains, for example, boron (B) as an impurity, but is not limited thereto, and may contain indium (In) as an impurity. The impurity concentration of the body region 26 in the silicon substrate 2 is, for example, 1×10 １３ cm －３ or more and 1×10 １７ cm －３ or less, and more preferably 5×10 １３ cm －３ or more and 5×10 １６ cm －３ or less. The impurity concentration of the body region 26 in the silicon substrate 2 is, for example, a value obtained by analysis using SIMS (Secondary Ion Mass Spectroscopy).

[0024] Also, the silicon substrate 2 has a doped layer 3 containing a p-type impurity (for example, boron or indium). The doped layer 3 is formed along the surface 231 of the porous portion 23.

[0025] The doped layer 3 of the silicon substrate 2 is a diffusion layer. The conductivity type of the doped layer 3 is the same as the conductivity type of the body region 26 of the silicon substrate 2. Also, the impurity concentration of the doped layer 3 is higher than the impurity concentration of the body region 26 of the silicon substrate 2. Therefore, when the conductivity type of the body region 26 of the silicon substrate 2 is p-type, the doped layer 3 is a p-type silicon region (p ＋ silicon region) having a higher concentration than the body region 26 of the silicon substrate 2. The type of impurity in the doped layer 3 is, for example, the same as the type of impurity in the body region 26 of the silicon substrate 2. More specifically, when the impurity in the body region 26 is boron, the impurity in the doped layer 3 is boron. The impurity concentration of the doped layer 3 is 1×10 １８ cm －３ or more and 1×10 ２１ cm－３ The following, 5×10 １８ cm －３ or more and 1×10 ２０ cm －３ or less is more preferable. The impurity concentration of the doped layer 3 is a value obtained by analysis by, for example, SIMS.

[0026] Also, the carrier concentration of the doped layer 3 is larger than the carrier concentration of the body region 26. The carrier concentration of the doped layer 3 and the carrier concentration of the body region 26 are values obtained by observing the carrier concentration distribution by, for example, sMIM (Scanning Microwave Impedance Microscope).

[0027] The thickness of the doped layer 3 is, for example, 10 nm or more and 10000 nm or less, and more preferably 50 nm or more and 5000 nm or less. The thickness of the doped layer 3 is a value obtained by observing the cross section of the capacitor 1 by, for example, sMIM (Scanning Microwave Impedance Microscope). The thickness of the doped layer 3 is the thickness of the doped layer 3 in the normal direction at an arbitrary point on the inner surface 241 of the pore 24.

[0028] The doped layer 3 of the silicon substrate 2 is formed over the first region A1 and the second region A2 of the first main surface 21 of the silicon substrate 2. In the first region A1, the doped layer 3 is formed along the surface 231 of the porous portion 23, and in the second region A2, the doped layer 3 is formed along the second region A2.

[0029] (2.2) Dielectric layer As shown in FIGS. 1 to 3, the dielectric layer 4 covers the surface 231 of the porous portion 23. The dielectric layer 4 is in contact with the surface 231 of the porous portion 23. The dielectric layer 4 has a shape along the surface 231 of the porous portion 23 and the second region A2 of the first main surface 21 of the silicon substrate 2. The dielectric layer 4 is interposed between the doped layer 3 and the conductor layer 5 in the thickness direction D1 of the silicon substrate 2, and is also interposed between the doped layer 3 and the conductor layer 5 in a plurality of pores 24 of the porous portion 23. Further, the dielectric layer 4 is also interposed between the first main surface 21 of the silicon substrate 2 and the conductor layer 5 in the thickness direction D1 of the silicon substrate 2.

[0030] The thickness of the dielectric layer 4 is, for example, 10 nm or more and 500 nm or less. The upper limit of the thickness of the dielectric layer 4 is restricted by, for example, the opening width of the pores 24 of the porous portion 23 in one direction along the first main surface 21 of the silicon substrate 2, the thickness in the above one direction of the conductor layer 5 in the pores 24 of the porous portion 23, and the like.

[0031] As shown in FIGS. 3 and 4, the dielectric layer 4 includes a first dielectric portion 41 and a plurality of second dielectric portions 42. The first dielectric portion 41 is in contact with the surface 231 of the porous portion 23 and has a plurality of through holes 410. The second dielectric portions 42 are in contact with the surface 231 of the porous portion 23 and are located inside each of the plurality of through holes 410. The material of the second dielectric portion 42 is silicon oxide. The material of the first dielectric portion 41 includes a dielectric material having a higher dielectric constant than silicon oxide.

[0032] In the present embodiment, the material of the first dielectric portion 41 is hafnium oxide. The material of the first dielectric portion 41 is not limited to hafnium oxide and may be, for example, tantalum oxide, aluminum oxide, or zirconium oxide. The silicon oxide constituting each of the plurality of second dielectric portions 42 is silicon dioxide (SiO ２ ), but it is not essential that it is strictly SiO ２ .

[0033] In the present embodiment, the dielectric constant of the dielectric material of the first dielectric portion 41 is larger than the dielectric constant of the material of the second dielectric portion 42.

[0034] In the present embodiment, the total area of the opening areas of the plurality of through holes 410 is smaller than the area of the main surface of the first dielectric portion 41. When viewed from the lamination direction of the first dielectric portion 41 with respect to the surface 231 of the porous portion 23, as shown in FIG. 4, the opening shape of the through hole 410 is circular. The opening shape of each of the plurality of through holes 410 is not limited to a circular shape. Each of the plurality of through holes 410 of the first dielectric portion 41 is, for example, a pinhole. In the present embodiment, for example, each of the plurality of through holes 410 can be formed as a pinhole during the film formation of the first dielectric portion 41 by appropriately setting the film formation conditions when forming the first dielectric portion 41 by the ALD (Atomic Layer Deposition) method.

[0035] Each of the second dielectric parts 42 is cylindrical, but is not limited to being cylindrical.

[0036] In this embodiment, the dielectric layer 4 has a plurality of second dielectric portions 42 scattered therein, and each side surface of the plurality of second dielectric portions 42 is covered by the first dielectric portion 41.

[0037] (2.3) Conductive Layer As shown in Figures 1 to 3, the conductive layer 5 covers the dielectric layer 4. In a plan view from the thickness direction D1 of the silicon substrate 2, the conductive layer 5 overlaps the first region A1 and the second region A2 of the first main surface 21 of the silicon substrate 2. Therefore, in this embodiment, in a plan view from the thickness direction D1 of the silicon substrate 2, the conductive layer 5 overlaps the doping layer 3.

[0038] The conductive layer 5 is, for example, a conductive polysilicon layer. The impurity concentration of the conductive polysilicon layer is, for example, 1 × 10⁻⁶ １８ cm －３ The above 1 x 10 ２１ cm －３ The following is true: 5 × 10 １８ cm －３ The above 1 x 10 ２０ cm －３ The following is more preferable: The impurities in the conductive polysilicon layer include, for example, one selected from the group consisting of boron, indium, phosphorus, arsenic, and antimony. The conductive layer 5 is not limited to the conductive polysilicon layer, but may be, for example, a metal electrode layer. The material of the metal electrode layer includes, for example, at least one selected from the group consisting of ruthenium (Ru), titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). More specifically, the material of the metal electrode layer is ruthenium, titanium, tantalum, tungsten, aluminum, or an alloy mainly composed of any of these metals.

[0039] The conductive layer 5 has a first portion 51 that overlaps a first region A1 in the thickness direction D1 of the silicon substrate 2, and a second portion 52 that overlaps a second region A2. The first portion 51 of the conductive layer 5 includes columnar portions 512 located inside each of the plurality of pores 24 of the porous portion 23 of the silicon substrate 2, and a portion 511 that connects the upper ends of the plurality of columnar portions 512.

[0040] (2.4) First external connection electrode and second external connection electrode The first external connection electrode 7 is connected to the silicon substrate 2. More specifically, the first external connection electrode 7 is formed on the second region A2 of the first main surface 21 of the silicon substrate 2 and is connected to the first main surface 21 of the silicon substrate 2 through a contact hole 47 formed in the portion of the dielectric layer 4 that is not covered by the conductive layer 5. "The first external connection electrode 7 is connected to the silicon substrate 2" means that the first external connection electrode 7 and the silicon substrate 2 are electrically connected, and more specifically, that the first external connection electrode 7 and the silicon substrate 2 (the doped layer 3) are in ohmic contact.

[0041] In a plan view from the thickness direction D1 of the silicon substrate 2, the outer edge of the first external connection electrode 7 is, for example, square-shaped (see Figure 5). Note that the outer edge of the first external connection electrode 7 is not limited to a square shape, but may be, for example, circular. In a plan view from the thickness direction D1 of the silicon substrate 2, the first external connection electrode 7 overlaps with the second region A2 of the first main surface 21 of the silicon substrate 2, but does not overlap with the first region A1.

[0042] The second external connection electrode 8 is connected to the conductive layer 5. More specifically, the second external connection electrode 8 is connected to the surface of the conductive layer 5 formed on the second region A2 of the first main surface 21 of the silicon substrate 2. "The second external connection electrode 8 is connected to the conductive layer 5" means that the second external connection electrode 8 is electrically connected to the conductive layer 5, and more specifically, that the second external connection electrode 8 and the conductive layer 5 are in ohmic contact.

[0043] In a plan view from the thickness direction D1 of the silicon substrate 2, the outer edge of the second external connection electrode 8 is, for example, square-shaped (see Figure 5). Note that the outer edge of the second external connection electrode 8 is not limited to a square shape, but may be, for example, circular. In a plan view from the thickness direction D1 of the silicon substrate 2, the second external connection electrode 8 overlaps with the second region A2 of the first main surface 21 of the silicon substrate 2, but does not overlap with the first region A1.

[0044] The materials of the first external connection electrode 7 and the second external connection electrode 8 include, for example, aluminum. The materials of the first external connection electrode 7 and the second external connection electrode 8 are not limited to aluminum, but may also include, for example, gold, platinum, ruthenium, etc. The material of the second external connection electrode 8 may be the same as the material of the first external connection electrode 7, or it may be different from the material of the first external connection electrode 7.

[0045] The thickness of the first external connection electrode 7 and the second external connection electrode 8 is, for example, 1 μm or more and 3 μm or less. The thickness of the second external connection electrode 8 may be the same as the thickness of the first external connection electrode 7, or it may be different from the thickness of the first external connection electrode 7.

[0046] (3) Capacitor manufacturing method The manufacturing method of capacitor 1 includes, for example, a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, a seventh step, and an eighth step. The manufacturing method of capacitor 1 will be described below with reference to Figures 6 to 11.

[0047] In the first step, a silicon wafer 20 (see Figure 6), which will serve as the basis for the silicon substrate 2, is prepared. In this embodiment, the silicon wafer 20 is a p-type silicon wafer.

[0048] In the second step, an insulating layer (not shown) with a predetermined pattern is formed on the first main surface 201 of the silicon wafer 20, and then a porous portion 23 is formed on the silicon wafer 20 by anodizing. After that, the insulating layer is removed to obtain the structure shown in Figure 7. When forming the insulating layer with a predetermined pattern, for example, the first step and the second step are performed. In the first step, a silicon oxide layer is formed on the entire surface of the first main surface 201 of the silicon wafer 20, for example by thermal oxidation, and a silicon nitride layer is formed on the silicon oxide layer, for example by the CVD (Chemical Vapor Deposition) method. In the second step, an insulating layer with a predetermined pattern is formed by patterning the laminated structure of the silicon oxide layer and the silicon nitride layer using photolithography and etching techniques. Here, the first main surface 201 of the silicon wafer corresponds to the first main surface 21 of the silicon substrate 2. The insulating layer of a predetermined pattern covers the region on the first main surface 201 of the silicon wafer 20 that corresponds to the second region A2 of the first main surface 21 of the silicon substrate 2, but does not cover the region corresponding to the first region A1 of the first main surface 21 of the silicon substrate 2. When forming the porous portion 23, for example, the silicon wafer 20 is used as the anode and an anodic oxidation treatment is performed on the silicon wafer 20 to form a silicon wafer 20 having a porous portion 23. In the anodic oxidation treatment, a platinum electrode is placed opposite the first main surface 201 of the silicon wafer 20 in an electrolyte, and a current of a predetermined current density is passed between the anode and the cathode for a predetermined time, with the silicon wafer 20 as the anode and the platinum electrode as the cathode, thereby making the silicon wafer 20 porous in the region of the first main surface 201 of the silicon wafer 20 that is not covered by the insulating layer. The electrolyte is, for example, a mixture of hydrofluoric acid and ethanol. Before performing the anodic oxidation treatment, electrodes to be used in the anodic oxidation treatment are formed on the second main surface of the silicon wafer 20. This electrode is removed after the anodizing process. The electrode is, for example, a metal film.

[0049] In the anodic oxidation process in the second step, the shape and depth of the multiple pores 24 can be controlled by changing at least one of the following: the concentration of hydrogen fluoride in the electrolyte, a predetermined current density, and a predetermined time. The concentration of hydrogen fluoride in the electrolyte is preferably, for example, 1 wt% to 80 wt%, and more preferably 20 wt% to 40 wt%. Furthermore, in the manufacturing method of the capacitor 1, the shape of the multiple pores 24 can also be changed by changing the resistivity of the silicon wafer, which is determined by the impurity concentration of the silicon wafer 20 that forms the silicon substrate 2.

[0050] In the third step, as shown in Figure 8, a doped layer 3 consisting of a diffusion layer is formed on the silicon wafer 20. In other words, the third step includes a diffusion step. In the diffusion step, the doped layer 3 is formed by thermally diffusing p-type impurities (for example, boron) into the silicon wafer 20. By performing up to the third step, a silicon wafer 20 having a porous portion 23 and a doped layer 3 is formed.

[0051] In the fourth step, the structure shown in Figure 9 is obtained by forming a first dielectric portion 41 having a plurality of through holes 410 on the surface 231 of the porous portion 23 (the inner surfaces of each of the plurality of pores 24 and a part of the first main surface 201 of the silicon wafer 20). The first dielectric portion 41 is a dielectric film deposited on the surface 231 of the porous portion 23. In the fourth step, the first dielectric portion 41 is formed, for example, by the ALD method. By appropriately setting the film deposition conditions when depositing the first dielectric portion 41 by the ALD method, each of the plurality of through holes 410 can be formed as a pinhole during the deposition of the first dielectric portion 41. For example, by adjusting the supply time in the cycle of supplying a gas species containing the material of the first dielectric portion 41 into the plurality of pores 24 of the porous portion 23, it becomes easier to form pinholes.

[0052] In the fifth step, a chemical conversion treatment is performed to form a plurality of second dielectric parts 42, each made of silicon oxide, as shown in Figure 10. In the chemical conversion treatment, for example, KNO ３In a nitric acid solution to which the additive is added, a platinum electrode is placed opposite the first main surface 201 of the silicon wafer 20, and a predetermined voltage is applied between the anode and the cathode for a predetermined time, with the silicon wafer 20 as the anode and the platinum electrode as the cathode. This oxidizes the portion of the surface 231 of the porous portion 23 that is not covered by the first dielectric portion 41, thereby forming a second dielectric portion 42 so that each of the multiple through holes 410 is filled.

[0053] In the sixth step, as shown in Figure 11, a conductive layer 5 is formed to cover the dielectric layer 4. More specifically, in the sixth step, a conductive material layer that will become the conductive layer 5 is first formed on the dielectric layer 4. In the sixth step, the conductive material layer is formed by, for example, a CVD method, and then, for example, a conductive layer 5 consisting of a part of the conductive material layer is formed by patterning the conductive material layer using photolithography and etching techniques. The conductive layer 5 has a first portion 51 that overlaps with a first region A1 in the thickness direction D1 of the silicon substrate 2, and a second portion 52 that overlaps with a second region A2.

[0054] In the seventh step, the first external connection electrode 7 (see Figure 1) and the second external connection electrode 8 (see Figure 1) are formed. More specifically, in the seventh step, a part of the first main surface 21 of the silicon substrate 2 is exposed by first forming contact holes 47 in the dielectric layer 4. In the seventh step, the contact holes 47 are formed using, for example, photolithography and etching techniques. Subsequently, the first external connection electrode 7 and the second external connection electrode 8 are formed using, for example, a thin-film formation method, photolithography and etching techniques. The thin-film formation method is, for example, vapor deposition, sputtering, or CVD. The seventh step may also include a heat treatment to obtain ohmic contact between the first external connection electrode 7 and the doped layer 3.

[0055] In the method for manufacturing capacitor 1, a silicon wafer (first wafer) is prepared in the first step, and a second wafer containing multiple capacitors 1 can be obtained by performing steps 1 to 7. In the method for manufacturing capacitor 1, multiple capacitors 1 can be obtained by cutting the second wafer with, for example, a dicing saw or a laser dicing device in the eighth step.

[0056] (4) Advantages The capacitor 1 according to the embodiment comprises a silicon substrate 2, a dielectric layer 4, and a conductive layer 5. The silicon substrate 2 includes a porous portion 23 having a plurality of holes 24. The dielectric layer 4 covers the surface 231 of the porous portion 23 in the silicon substrate 2. The conductive layer 5 covers the dielectric layer 4. The dielectric layer 4 includes a first dielectric portion 41 and a plurality of second dielectric portions 42. The first dielectric portion 41 is in contact with the surface 231 of the porous portion 23 and has a plurality of through holes 410. The second dielectric portion 42 is in contact with the surface 231 of the porous portion 23 and is located inside each of the plurality of through holes 410. The material of the second dielectric portion 42 is silicon oxide. The material of the first dielectric portion 41 includes a first dielectric material with a higher dielectric constant than silicon oxide.

[0057] The above configuration makes it possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress. More specifically, the above configuration makes it possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0058] Furthermore, in the capacitor 1 according to the embodiment, the dielectric material of the first dielectric portion 41 includes at least one material selected from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, and zirconium oxide.

[0059] According to the above configuration, the dielectric constant of the dielectric layer 4 can be increased while the dielectric layer 4 can be easily formed by the semiconductor manufacturing process.

[0060] (5) Modified Examples (5.1) Modified Example 1 Hereinafter, capacitor 1 according to Modified Example 1 will be described with reference to Figures 13 and 14.

[0061] (5.1.1) Capacitor Configuration The capacitor 1 according to Modification Example 1 differs from the capacitor 1 according to the embodiment in that the dielectric layer 4 further includes a plurality of diffusion regions 43, as shown in Figure 13. The overall configuration of the capacitor 1 according to Modification Example 1 is the same as the overall configuration of the capacitor 1 according to the embodiment (see Figures 1 and 5), so the illustration and description are omitted.

[0062] The diffusion region 43 is in contact with the surface 231 of the porous portion 23. The diffusion region 43 is interposed between the second dielectric portion 42 and the first dielectric portion 41. The diffusion region 43 contains the constituent elements of the dielectric material of the first dielectric portion 41 and the constituent elements of silicon oxide. More specifically, when the material of the first dielectric portion 41 is hafnium oxide, the diffusion region 43 contains hafnium, silicon, and oxygen.

[0063] (5.1.2) Capacitor Manufacturing Method The method for manufacturing the capacitor 1 according to Modification 1 is substantially the same as the method for manufacturing the capacitor 1 according to the embodiment, wherein a heat treatment step is performed between the fifth step and the sixth step in the method for manufacturing the capacitor 1 according to the embodiment to cause mutual diffusion between the second dielectric part 42 and the first dielectric part 41, thereby forming a diffusion region 43. The heat treatment temperature in the heat treatment step is, for example, 800°C or more and 1000°C or less.

[0064] (5.1.3) Advantages The capacitor 1 according to Modification 1, like the capacitor 1 according to the embodiment, has a dielectric layer 4 that includes a first dielectric portion 41 and a second dielectric portion 42 made of a different material from the first dielectric portion 41, and multiple dielectric portions 42 are scattered in the dielectric layer 4. Therefore, it is possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0065] Furthermore, the capacitor 1 according to Modification 1 further includes a plurality of diffusion regions 43, making it possible to disperse the stress generated in the dielectric layer 4. As shown in Figure 14, the capacitor 1 according to Modification 1 has a stress distribution in which the stress (residual stress in the dielectric layer 4) changes gradually, making it possible to disperse the stress generated in the dielectric layer 4.

[0066] (5.2) Modification 2 Hereinafter, capacitor 1 according to Modification 2 will be described with reference to Figures 15 and 16.

[0067] (5.2.1) Capacitor Configuration The capacitor 1 according to Modification Example 2 differs from the capacitor 1 according to the embodiment in that the first dielectric portion 41 of the dielectric layer 4 has a laminated structure, as shown in Figure 15. The laminated structure of the first dielectric portion 41 is a structure in which a plurality of dielectric material layers 41a, 41b, and 41c are laminated in the lamination direction D3. The lamination direction D3 of the plurality of dielectric material layers 41a, 41b, and 41c is a direction parallel to the normal direction of the surface 231 of the porous portion 23, and varies depending on the position of the surface 231 of the porous portion 23. Note that the overall configuration of the capacitor 1 according to Modification Example 2 is the same as the overall configuration of the capacitor 1 according to the embodiment (see Figures 1 and 5), so the illustration and description are omitted.

[0068] For the sake of explanation, in the following, dielectric material layer 41a, dielectric material layer 41b, and dielectric material layer 41c will also be referred to as the first dielectric material layer 41a, the second dielectric material layer 41b, and the third dielectric material layer 41c, respectively.

[0069] In the modified example 2, the first dielectric material layer 41a, the second dielectric material layer 41b, and the third dielectric material layer 41c are stacked in the order of first dielectric material layer 41a, second dielectric material layer 41b, and third dielectric material layer 41c from the surface 231 of the porous portion 23.

[0070] In the modified example 2, the dielectric material of the first dielectric material layer 41a is hafnium oxide (HfO ２ ) and the dielectric material of the second dielectric material layer 41b is aluminum oxide (Al ２ O ３ ) and the dielectric material of the third dielectric material layer 41c is tantalum oxide (Ta ２ O ５ ) In the modified example 2, the dielectric material of the first dielectric material layer 41a and the dielectric material of the third dielectric material layer 41c may be the same. For example, the dielectric material of the first dielectric material layer 41a may be hafnium oxide, the dielectric material of the second dielectric material layer 41b may be aluminum oxide, and the dielectric material of the third dielectric material layer 41c may be hafnium oxide.

[0071] (5.2.2) Method for Manufacturing a Capacitor The method for manufacturing the capacitor 1 according to Modification 2 is substantially the same as the method for manufacturing the capacitor 1 according to the embodiment. The method for manufacturing the capacitor 1 according to Modification 2 differs from the method for manufacturing the capacitor 1 according to the embodiment in that, in the fourth step of the method for manufacturing the capacitor 1 according to the embodiment, a first dielectric portion 41 having a laminated structure of a first dielectric material layer 41a, a second dielectric material layer 41b, and a third dielectric material layer 41c is formed. The deposition of the first dielectric material layer 41a, the second dielectric material layer 41b, and the third dielectric material layer 41c is, for example, by the ALD method. In each of the plurality of through holes 410 of the first dielectric portion 41, for example, a pinhole in the first dielectric material layer 41a, a pinhole in the second dielectric material layer 41b, and a pinhole in the third dielectric material layer 41c overlap and can be considered as a pinhole in the first dielectric portion 41. By appropriately setting the film deposition conditions when depositing the first dielectric material layer 41a, the second dielectric material layer 41b, and the third dielectric material layer 41c using the ALD method, each of the multiple through holes 410 can be formed as pinholes when the first dielectric portion 41 is deposited.

[0072] (5.2.3) Advantages The capacitor 1 according to Modification 2, like the capacitor 1 according to the embodiment, has a dielectric layer 4 that includes a first dielectric portion 41 and a second dielectric portion 42 made of a different material from the first dielectric portion 41, and a plurality of second dielectric portions 42 are scattered in the dielectric layer 4. Therefore, it is possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0073] Furthermore, in the capacitor 1 according to the modified example 2, the first dielectric portion 41 has a laminated structure in which a plurality of dielectric material layers 41a, 41b, and 41c are stacked in the stacking direction D3. Of the plurality of dielectric material layers 41a, 41b, and 41c, the dielectric materials of two adjacent dielectric material layers in the stacking direction D3 are different from each other.

[0074] According to the above configuration, it is possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0075] Furthermore, as shown in Figure 16, in the capacitor 1 according to Modification 2, stress is distributed in the dielectric layer 4 as indicated by the arrows in the figure, making it possible to reduce the occurrence of cracks. In addition, since the capacitor 1 according to Modification 2 has multiple dielectric material layers 41a, 41b, and 41c stacked on top of each other, the stress in the dielectric layer 4 can be adjusted.

[0076] Furthermore, in the capacitor 1 according to the modified example 2, the dielectric material that is the material of the first dielectric part 41 includes at least two selected from the group consisting of hafnium oxide, tantalum oxide, and aluminum oxide.

[0077] According to the above configuration, the dielectric layer 4 can be easily formed by a semiconductor manufacturing process while increasing the dielectric constant of the dielectric layer 4. In the capacitor 1 according to the modified example 2, the dielectric material which is the material of the first dielectric part 41 may include at least two selected from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, and zirconium oxide.

[0078] (5.3) Modification 3 Hereinafter, capacitor 1 according to Modification 3 will be described with reference to Figure 17.

[0079] (5.3.1) Capacitor Configuration The capacitor 1 according to Modification 3 differs from the capacitor 1 according to Modification 2 in that the dielectric layer 4 further includes a plurality of diffusion regions 43, as shown in Figure 17. The overall configuration of the capacitor 1 according to Modification 3 is the same as the overall configuration of the capacitor 1 according to the embodiment (see Figures 1 and 5), so the illustration and description are omitted.

[0080] The diffusion region 43 is in contact with the surface 231 of the porous portion 23. The diffusion region 43 is interposed between the second dielectric portion 42 and the first dielectric portion 41. The diffusion region 43 contains the constituent elements of the dielectric material of the first dielectric portion 41 and the constituent elements of silicon oxide. More specifically, when the material of the first dielectric material layer 41a is hafnium oxide, the diffusion region 43 contains hafnium, silicon, and oxygen in the region interposed between the second dielectric portion 42 and the first dielectric material layer 41a. When the material of the second dielectric material layer 41b is aluminum oxide, the diffusion region 43 contains aluminum, silicon, and oxygen in the region interposed between the second dielectric portion 42 and the second dielectric material layer 41b. When the material of the third dielectric material layer 41c is tantalum oxide, the diffusion region 43 contains tantalum, silicon, and oxygen in the region interposed between the second dielectric portion 42 and the third dielectric material layer 41c.

[0081] (5.3.2) Capacitor Manufacturing Method The method for manufacturing the capacitor 1 according to Modified Example 3 is substantially the same as the method for manufacturing the capacitor 1 according to Modified Example 2. In the method for manufacturing the capacitor 1 according to Modified Example 3, a heat treatment step is performed between the fifth step and the sixth step in the method for manufacturing the capacitor 1 according to Modified Example 2 to form a plurality of diffusion regions 43. More specifically, the diffusion regions 43 are formed by causing mutual diffusion between the second dielectric portion 42 and the first dielectric portion 41 through the heat treatment step. The heat treatment temperature in the heat treatment step is, for example, 800°C or more and 1000°C or less.

[0082] (5.3.3) Advantages The capacitor 1 according to Modification 3, like the capacitor 1 according to the embodiment, has a dielectric layer 4 that includes a first dielectric portion 41 and a second dielectric portion 42 made of a different material from the first dielectric portion 41, and a plurality of dielectric portions 42 are scattered in the dielectric layer 4. Therefore, it is possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0083] Furthermore, the capacitor 1 according to the modified example 3 further includes a plurality of diffusion regions 43, making it possible to disperse the stress generated in the dielectric layer 4.

[0084] (5.4) Modification 4 Hereinafter, capacitor 1 according to Modification 4 will be described with reference to Figure 18.

[0085] (5.4.1) Capacitor Configuration The capacitor 1 according to Modification 4 differs from the capacitor 1 according to Modification 2 in that the first dielectric portion 41 of the dielectric layer 4 has a laminated structure of two dielectric material layers 41a and 41b, as shown in Figure 18. The overall configuration of the capacitor 1 according to Modification 4 is the same as the overall configuration of the capacitor 1 according to the embodiment (see Figures 1 and 5), so the illustration and description are omitted.

[0086] In the following, for the sake of explanation, dielectric material layer 41a and dielectric material layer 41b will also be referred to as the first dielectric material layer 41a and the second dielectric material layer 41b, respectively.

[0087] In the modified example 4, the first dielectric material layer 41a and the second dielectric material layer 41b are stacked from the surface 231 of the porous portion 23 in the order of the first dielectric material layer 41a and the second dielectric material layer 41b.

[0088] In Modification 4, the dielectric material of the first dielectric material layer 41a is hafnium oxide (HfO ２ ) and the dielectric material of the second dielectric material layer 41b is aluminum oxide (Al ２ O ３ )

[0089] (5.4.2) Capacitor Manufacturing Method The method for manufacturing the capacitor 1 according to Modification 4 is substantially the same as the method for manufacturing the capacitor 1 according to the embodiment. The method for manufacturing the capacitor 1 according to Modification 4 differs from the method for manufacturing the capacitor 1 according to the embodiment in that, in the fourth step of the method for manufacturing the capacitor 1 according to the embodiment, a first dielectric portion 41 having a laminated structure of a first dielectric material layer 41a and a second dielectric material layer 41b is formed. The deposition of the first dielectric material layer 41a and the second dielectric material layer 41b is, for example, by the ALD method. In each of the plurality of through holes 410 of the first dielectric portion 41, for example, a pinhole in the first dielectric material layer 41a and a pinhole in the second dielectric material layer 41b overlap and can be considered as a pinhole in the first dielectric portion 41. By appropriately setting the deposition conditions when depositing the first dielectric material layer 41a and the second dielectric material layer 41b by the ALD method, each of the plurality of through holes 410 can be formed as a pinhole when the first dielectric portion 41 is deposited.

[0090] (5.4.3) Advantages The capacitor 1 according to Modification 4, like the capacitor 1 according to the embodiment, has a dielectric layer 4 that includes a first dielectric portion 41 and a second dielectric portion 42 made of a different material from the first dielectric portion 41, and a plurality of dielectric portions 42 are scattered in the dielectric layer 4. Therefore, it is possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0091] Furthermore, in the capacitor 1 according to the modified example 4, the first dielectric portion 41 has a laminated structure in which two dielectric material layers 41a and 41b are stacked in the stacking direction D3. The two dielectric material layers 41a and 41b are adjacent in the stacking direction D3 and are composed of different dielectric materials.

[0092] According to the above configuration, it is possible to reduce the occurrence of cracks in the dielectric layer 4 caused by thermal stress.

[0093] Furthermore, in the capacitor 1 according to Modification 4, stress is distributed in the dielectric layer 4, making it possible to reduce the occurrence of cracks. Also, in the capacitor 1 according to Modification 4, since two dielectric material layers 41a and 41b are stacked, the stress in the dielectric layer 4 can be adjusted.

[0094] (Other Modifications) The embodiments described are merely one of many embodiments of the present disclosure. The embodiments can be modified in various ways depending on the design, etc., as long as the objectives of the present disclosure are achieved.

[0095] For example, in the dielectric layer 4, it is sufficient for a plurality of second dielectric portions 42 to be scattered, and the through holes 410 in the first dielectric portion 41 do not have to be pinholes. They may be formed during the chemical conversion process when charge is exchanged between the silicon wafer and the solution through the thin portion of the first dielectric portion 41, and the silicon oxide of the second dielectric portion 42 is formed.

[0096] The conductivity type of the body region 26 and the doped layer 3 in the silicon substrate 2 is not limited to p-type, but may also be n-type. When the conductivity type of the body region 26 and the doped layer 3 in the silicon substrate 2 is n-type, the body region 26 and the doped layer 3 contain, for example, phosphorus (P) as an n-type impurity, but are not limited to this, and may also contain arsenic (As) or antimony (Sb) as an impurity. Furthermore, even when the conductivity type of the body region 26 and the doped layer 3 in the silicon substrate 2 is n-type, the impurity concentration of the doped layer 3 is greater than the impurity concentration of the body region 26. Also, the carrier concentration of the doped layer 3 is greater than the carrier concentration of the body region 26.

[0097] When the conductivity type of the doped layer 3 and the body region 26 is n-type, the method for manufacturing the capacitor 1 is substantially the same as the method for manufacturing the capacitor 1 according to the embodiment. However, in the first step, an n-type silicon wafer is prepared instead of a p-type silicon wafer 20. In addition, in order to form the porous portion 23 by anodizing, the holes in the n-type silicon wafer, which will be the basis of the silicon substrate 2, are increased by irradiating it with light.

[0098] Furthermore, the silicon substrate 2 may have a configuration that does not include the doped layer 3.

[0099] Furthermore, the multiple pores 24 in the porous portion 23 of the silicon substrate 2 are not limited to pores formed by anodic oxidation, but may also be formed by, for example, dry etching. When multiple pores 24 in the porous portion 23 are formed by anodic oxidation, the spacing between two adjacent pores 24 can be made non-uniform in the thickness direction of the silicon substrate 2, and the surface area 231 of the porous portion 23 can be increased compared to when multiple pores 24 in the porous portion 23 are formed by dry etching.

[0100] Furthermore, the silicon substrate 2 may have multiple circuit elements other than the capacitor 1 (for example, MOSFETs) formed on it. In other words, the capacitor 1 according to this disclosure can be applied to a semiconductor device including capacitors 1 and 1A, for example, an IC (Integrated Circuit) chip including capacitor 1.

[0101] (Aspects) The following aspects are disclosed herein.

[0102] A capacitor (1) according to the first embodiment comprises a silicon substrate (2), a dielectric layer (4), and a conductive layer (5). The silicon substrate (2) includes a porous portion (23) having a plurality of holes (24). The dielectric layer (4) covers the surface (231) of the porous portion (23) in the silicon substrate (2). The conductive layer (5) covers the dielectric layer (4). The dielectric layer (4) includes a first dielectric portion (41) and a second dielectric portion (42). The first dielectric portion (41) is in contact with the surface (231) of the porous portion (23) and has a plurality of through holes (410). The second dielectric portion (42) is in contact with the surface (231) of the porous portion (23) and is located inside each of the plurality of through holes (410). The material of the second dielectric portion (42) is silicon oxide. The material of the first dielectric portion (41) includes a first dielectric material having a higher dielectric constant than silicon oxide.

[0103] According to this embodiment, it is possible to reduce the occurrence of cracks in the dielectric layer (4) caused by thermal stress.

[0104] In the second embodiment, the capacitor (1) further includes a diffusion region (43) in the dielectric layer (4) as in the first embodiment. The diffusion region (43) is interposed between the second dielectric portion (42) and the first dielectric portion (41). The diffusion region (43) comprises the constituent elements of the first dielectric material of the first dielectric portion (41) and the constituent elements of silicon oxide.

[0105] According to this embodiment, it is possible to disperse the stress generated in the dielectric layer (4).

[0106] In the capacitor (1) according to the third embodiment, in the first embodiment, the first dielectric portion (41) has a laminated structure in which a plurality of dielectric material layers (41a, 41b, 41c; 41a, 41b) are stacked in the stacking direction (D3). Among the plurality of dielectric material layers (41a, 41b, 41c; 41a, 41b), the dielectric materials of two adjacent dielectric material layers in the stacking direction are different from each other.

[0107] According to this embodiment, it is possible to reduce the occurrence of cracks in the dielectric layer (4) caused by thermal stress.

[0108] In the capacitor (1) according to the fourth embodiment, in the first embodiment, the first dielectric material includes at least one material selected from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, and zirconium oxide.

[0109] According to this embodiment, the dielectric constant of the dielectric layer (4) is increased while the dielectric layer (4) is easily formed by the semiconductor manufacturing process.

[0110] 1 Capacitor 2 Silicon substrate 21 First main surface 22 Second main surface 23 Porous portion 231 Surface 24 Hole 241 Inner surface 3 Dope layer 4 Dielectric layer 41 First dielectric portion 41a First dielectric material layer 41b Second dielectric material layer 41c Third dielectric material layer 410 Through hole 42 Second dielectric portion 5 Conductive layer 7 First external connection electrode 8 Second external connection electrode A1 First region A2 Second region D1 Thickness direction D3 Lamination direction

Claims

1. A capacitor comprising: a silicon substrate including a porous portion having a plurality of holes; a dielectric layer covering the surface of the porous portion on the silicon substrate; and a conductive layer covering the dielectric layer, wherein the dielectric layer includes: a first dielectric portion in contact with the surface of the porous portion and having a plurality of through holes; and a second dielectric portion in contact with the surface of the porous portion and located inside each of the plurality of through holes, wherein the material of the second dielectric portion is silicon oxide, and the material of the first dielectric portion includes a first dielectric material having a higher dielectric constant than silicon oxide.

2. The capacitor according to claim 1, wherein the dielectric layer further includes a diffusion region in contact with the surface of the porous portion, the diffusion region is interposed between the second dielectric portion and the first dielectric portion, and comprises the constituent elements of the first dielectric material of the first dielectric portion and the constituent elements of silicon oxide.

3. The capacitor according to claim 1, wherein the first dielectric portion has a laminated structure in which a plurality of dielectric material layers are stacked in the stacking direction, and the dielectric materials of two adjacent dielectric material layers in the stacking direction are different from each other.

4. The capacitor according to claim 1, wherein the first dielectric material comprises at least one material selected from the group consisting of hafnium oxide, tantalum oxide, aluminum oxide, and zirconium oxide.

Images