Readout circuit, hall sensing device and method for operating a readout circuit

Abstract

Embodiments relate to a readout circuit (15) for reading out a Hall element (12) having a first terminal (A), a second terminal (B), a third terminal (C) and a fourth terminal (D). The readout circuit (15) comprises a Hall current source (11) configured to impress a current into the Hall element (15) via the first terminal (A) and the third terminal (C), the first and the third terminal (A, C) being arranged along a first direction. The readout circuit (15) further comprises a compensation block (100) configured to apply a variable compensation voltage to the Hall element (15) via the second terminal (B). Moreover, the readout circuit (15) comprises a comparator (105) configured to determine when a voltage difference between the second (B) and the fourth terminal (D) is zero, the second terminal (B) and the fourth terminal (D) being arranged along a second direction different from the first direction.

Description

[0001] READOUT CIRCUIT , HALL SENSING DEVICE AND METHOD FOR OPERATING

[0002] A READOUT CIRCUIT

[0003] Hall sensors or Hall sensing devices are widely used as contactless sensors , e . g . as position sensors , for example angular position sensors , linear position sensors in the field of automotive , industry and consumer electronics . Further fields of use are current sensors or magnetic field sensors . Generally, concepts are sought to improve Hall sensing devices and a readout circuit for reading out a Hall element .

[0004] It is an obj ect of the present invention to provide an improved readout circuit for a Hal l sens ing device , an improved Hal l sensing device and an improved method for operating the readout circuit .

[0005] SUMMARY

[0006] According to embodiments , the above obj ects are achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0007] Embodiments relate to a readout circuit for reading out a Hall element having a first terminal , a second terminal , a third terminal and a fourth terminal . The readout circuit comprises a Hall current source configured to impress a current into the Hall element via the first terminal and the third terminal , the first and the third terminal being arranged along a first direction . The readout circuit further comprises a compensation block configured to apply a variable compensation voltage to the Hall element via the second terminal , and a comparator configured to determine when a voltage di f ference between the second and the fourth terminal is zero , wherein the second terminal and the fourth terminal are arranged along a second direction di f ferent from the first direction .

[0008] For example , the compensation block may comprise a di f ferential current device comprising a first variable current source at a high level and a second variable current source at a low level configured to be connected to the second terminal and a third variable current source at a high level and a fourth variable current source at a low level configured to be connected to the fourth terminal .

[0009] The readout circuit may further comprise a compensation control device configured to vary a current of the first to fourth variable current sources .

[0010] For example , the compensation block may comprise a first variable current source at a high level and a second variable current source at a low level configured to be connected to the second terminal or to the fourth terminal .

[0011] The readout circuit may further comprise a compensation control device configured to vary a current of the first and second variable current sources .

[0012] According to embodiments , the Hall current source comprises a supply voltage terminal , and the first variable current source and the second variable current source each comprise a variable resistor element and transistor coupled in parallel to the supply voltage terminal , respectively .

[0013] By way of example , the compensation control device may be configured to cease varying the current when the comparator has determined that the voltage di f ference between the second and the fourth terminal is zero . According to embodiments , the compensation block may comprise a first current source at a high level that is configured to be connected to the second terminal or to the fourth terminal , and a first resistor element . The compensation block may further comprise a second current source at a low level that is configured to be connected to the second terminal or to the fourth terminal , and a second resistor element . For example , the first and / or the second current sources may be variable or constant . Further, any of the first and / or the second resistor element may be variable or constant . Any of the first and / or second current sources and the first and / or second resistor elements may be varied so as to compensate the Hall voltage . For example , either a variable current source or a variable resistor element may be used to compensate the Hall voltage .

[0014] According to further embodiments , the compensation block may comprise a variable voltage source .

[0015] For example , the variable voltage source may comprise a volt- age-controlled voltage source .

[0016] The readout circuit may be configured to be operated in di fferent spinning phases , wherein in a first spinning phase a current is impressed into the Hall element between the first terminal and the third terminal and in a second spinning phase the current is impressed into the Hall element between the second terminal and the fourth terminal .

[0017] According to further embodiments , the readout circuit may be operated in further spinning phases . By way of example , in a third spinning phase a current is impressed into the Hall element between the third terminal and the first terminal . Moreover, in a fourth spinning phase the current is impressed into the Hall element between the fourth terminal and the second terminal .

[0018] For example , the compensation block may be configured to generate a binary code corresponding to the compensation current or to the compensation voltage .

[0019] According to embodiments , the compensation block may be configured to generate the binary code in a time which is larger than a spinning phase .

[0020] According to embodiments , a Hall sensing device comprises a Hall element , and a readout circuit as has been explained above .

[0021] A method of operating the readout circuit as described above comprises impressing the compensation current into the Hall element and step wise increasing the compensation current until a sign of an output signal generated by the comparator changes .

[0022] For example , stepwise increasing the compensation current until the sign of the output signal changes may be accomplished in a time which is larger than a spinning phase .

[0023] BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this speci fication . The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles . Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numbers designate corresponding similar parts.

[0025] Fig. 1 is a block diagram of a Hall sensing device comprising a readout circuit according to embodiments.

[0026] Fig. 2 shows an equivalent circuit of the Hall sensing device according to embodiments.

[0027] Figs. 3A to 3D show schematic views of a circuit arrangement.

[0028] Fig. 4A shows examples of signals when performing a measurement .

[0029] Fig. 4B shows examples of signals when performing a measurement according to further embodiments.

[0030] Fig. 5A is a block diagram of a Hall sensing device according to further embodiments.

[0031] Figs. 5B to 5E are schematic views of a circuit arrangement.

[0032] Fig. 6 is a block diagram of a Hall sensing device according to further embodiments.

[0033] Figs. 7A to 7C are block diagrams of a Hall sensing device according to further embodiments, respectively.

[0034] Fig. 8 summarizes a method according to embodiments.

[0035] DETAILED DESCRIPTION In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

[0036] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0037] Fig. 1 shows a block diagram of a Hall sensing device 10 according to embodiments. The Hall sensing device 10 comprises a Hall element 12 and a readout circuit 15 for reading out signals in the Hall element 12. Fig. 1 further shows a magnetic field 16. For example, the magnetic field 16 may be an external magnetic field, and the Hall sensing device 10 is configured to sense the external magnetic field. According to further examples, the magnetic field 16 is generated by an integrated device, e.g. an integrated on-chip coil. In this case, the Hall sensing device 10 may be configured to measure a position, e.g. an angular position of a motor, or a current.

[0038] Generally, when measuring a Hall voltage generated due to the presence of a magnetic field 16, an offset voltage is sensed in addition to the voltage generated due to the Hall-effect. The offset voltage may be due to geometrical errors, piezoresistive effects, inhomogeneous temperatures, etc. A further offset may be due to an offset of an amplifier which may e.g. measure a Hall voltage.

[0039] In order to perform measurements suitable for reducing offset effects, a Hall element usually comprises four terminals, a first terminal A, a second terminal B, a third terminal C, and a fourth terminal D, which are arranged in a rotably symmetric manner. For example, the first and the third terminals A, C may be arranged along a first direction, and the second and the fourth terminals B, D are arranged along a second direction which is perpendicular to the first direction.

[0040] In order to compensate the offset voltage, a Hall current source 11 may impress a current to different terminals during different spinning phases. For example, in a first phase, the current may be applied between the first terminal A and the third terminal C, resulting in a current flow in the first direction. Further, in a second phase, a current may be applied between the second terminal B and the fourth terminal D, resulting in a current flow in the second direction. For example, the Hall element 12 may further comprise a current multiplexer 102 that enables a switching between the first and the second terminals A, B and a further multiplexer 102 that enables a switching between the third terminal C and the fourth terminal D.

[0041] As is clearly to be understood, the Hall element 12 may also be operated in 4-phase spinning or multi-phase spinning. For example, in 4-phase spinning, the first two phases may be as described above. Further, in a third phase, the current is applied between the third terminal C and the first terminal A. Moreover, in a fourth phase, the current is applied between the fourth terminal D and the second terminal B. The readout is then performed in an analogous manner between the terminals that are di f ferent from those to which the current is impressed .

[0042] As is further illustrated in Fig . 1 , the readout circuit 15 comprises a Hall current source 11 which is configured to impress a current into the Hall element 12 , e . g . between the first terminal A and the third terminal C, e . g . during a first spinning phase . For example , a range of a current may be approximately 0 . 5 to 2 mA, e . g . 1 mA. The readout circuit 15 further comprises a compensation block 100 that is configured to inj ect a variable compensation current to the Hall element 12 via the second terminal B, e . g . during the first spinning phase . The readout circuit 15 further comprises a comparator 105 which is configured to determine when a voltage di f ference between the second and the fourth terminal is zero .

[0043] A chopping multiplexer 109 may be arranged to enable switching a sensing output between the first terminal and the second terminal A, B for sensing V2and for changing between the third terminal C and the fourth terminal D for sensing a further voltage output V2. As wil l be explained in more detail below, the chopping multiplexer 109 may also be configured to enable selective input of the compensation voltage .

[0044] The readout circuit 15 may further comprise a common mode control device 108 that is configured to set the bias point of the Hall element 12 in accordance with an input range of the comparator 105 . For example , the common mode control device 108 may be configured to set this point to VDD / 2 or to another voltage in dependence of VDD . According to further embodiments , a common mode control device 108 may also be dispensed with .

[0045] As will be explained in more detail in the following, the compensation block 100 is configured to generate a compensation current . According to embodiments , the compensation current in combination with the Hall resistance ( in a range of approximately 1 to 3 kOhm) of the Hall element 12 generates a compensation voltage that compensates for the Hall voltage generated within the Hall element . The comparator 105 is configured to determine a resulting voltage AV that results from a superposition of the Hall voltage and the compensation voltage . As soon as the resulting voltage AV amounts to zero , it is determined that the compensation current completely compensates for the Hall voltage generated within the Hall element 12 . The compensation current generated at this point corresponds to a measured signal . The condition "AV is equal to zero" may be determined by monitoring a sign of the output of the comparator 105 . By operating the Hall element 12 in di f ferent phases to apply the current provided by the Hall current source 11 to di f ferent pairs of terminals , the Hall voltage may be determined while subtracting the of fset voltage .

[0046] According to embodiments illustrated in Fig . 1 , the compensation block 100 comprises a di f ferential current device which comprises a first current source 111 , a second current source 112 , a third current source 113 and a fourth current source 114 .

[0047] The compensation block 100 is configured to perform a di f ferential compensation . The combination of the first current source 111 and the third current source 113 is matched to the combination of second current source 112 and the fourth current source 114 . For example , a compensation current impressed by the compensation block may be in a range of 1 to 10 pA. Accordingly, the compensation current may be much smaller than the current impressed by the Hall current source 11 .

[0048] Fig . 3A is a schematic illustration of an example of the di fferent current sources of the compensation block 100 being connected to the Hall element 12 during a first phase in which the Hall current source 11 is connected to the first terminal A and a Hall current is caused to flow between the first terminal A and the third terminal C . Fig . 3A speci fically shows the current sources of the compensation block 100 to illustrate the respective compensation currents . During this phase , the first current source 111 of the compensation block 100 impresses a current to the second terminal B, and the fourth current source 114 sinks a current from the fourth terminal D . For the sake of simplicity, it is assumed that the second current source 112 and the third current source 113 are switched of f . However, as is to be clearly understood, according to all configurations referring to Figs . 3A to 3D, all of the first to fourth current sources 111 to 114 may impress / sink a suitable current to the respective terminals . In the configuration of Fig . 3B, a compensation current flows in the second direction and causes , due to the resistance of the Hall element 12 , a compensation voltage for compensating the Hall voltage . A resulting voltage AV corresponding to a superposition of the Hall voltage and the compensation voltage between terminal B and D is measured by the comparator 105 .

[0049] In Fig . 3B, the polarity of the current flow is changed . According to this configuration, similar to Fig . 3A, the Hall current source 11 is connected to the first terminal A and a Hall current is caused to flow from the third terminal C to the first terminal A. Di f fering from the configuration of Fig . 3A, the second current source 112 sinks a current from the second terminal B, and the third current source 113 impresses a current in the fourth terminal D . In the configuration of Fig . 3B, a compensation current flows in the second direction, opposite to the case of case in Fig . 3A, and causes , due to the resi stance of the Hall element 12 , a compensation voltage for compensating the Hal l voltage . A resulting voltage AV between terminal B and D is measured by the comparator 105 .

[0050] Referring to Fig . 3C, during a second phase , a Hall current is impressed by the Hall current source 11 between the second terminal B and the fourth terminal D . In this case , the first current source 111 is connected to the first terminal A and the fourth current source 114 is connected to the third terminal C, resulting in a compensation current / voltage along the first direction . A resulting voltage AV between the first terminal A and the third terminal C is measured by the comparator 105 .

[0051] In Fig . 3D the polarity of the current is changed during a second phase . A Hall current IHflows from the fourth terminal D to the second terminal B . Further, the second current source 112 is connected to the first terminal A and the third current source 113 is connected to the third terminal C, resulting in a compensation current / voltage along the first direction, having a polarity opposite to the configuration of Fig . 3C . A resulting voltage AV between the first terminal A and the third terminal C is measured by the comparator 105 .

[0052] For operating the compensation block 100 implemented as a di fferential or bipolar current device , as is illustrated in Fig . 3A, the first and third current sources 111 , 113 are matched to the second and fourth current sources 112 , 114 . For operating the readout circuit 115 at a high speed, all four current sources 111 to 114 may be operated .

[0053] According to concepts , the compensation block 100 , the comparator 105 and the compensation control device 107 are connected together . The sensor signal is compensated via the compensation block 100 in a way that a zero crossing condition of the comparator 105 is reached . The information about the sensor signal which includes the of fset voltage and the signal voltage is stored in the control code of the compensation control device 107 . For assessing the signal , the code in two sequential phases is subtracted . This results in an of fset compensated value which is proportional to the sensitivity of the Hall sensing device and the resolution of the compensation block 100 . Such a signal may be used in relative sensor concepts where two Hall elements 12 have the same sensi- tivity and resolution of the compensation block 100 . The comparator 105 is used to reach a zero condition . Further, the comparator 105 may be used as filter function . According to further examples , this filter function may alternatively also be included in the compensation control device 107 and / or control unit 121 .

[0054] According to further embodiments , the code of more than 2 sequential phases may subtracted . For example , combining the code of more phases may result in an even smaller remaining of fset .

[0055] The readout circuit 15 further may comprise an automatic gain control circuitry 120 that may control the Hall current source 11 and hence the current through the Hall element 12 . For example , the automatic gain control circuitry 120 may ensure the compliance condition of the Hall element 12 in the whole temperature range . The readout circuit 15 may further comprise a spinning / chopping control block 122 that may generate signals for spinning the current supplied by the Hall current source 11 . Further, the spinning / chopping control block 122 may control chopping at the chopping multiplexer 109 for supporting a sensing function in the respective phases .

[0056] The readout circuit 15 further may comprise a compensation control device 107 . For example , the compensation control device 107 may store information about the sensor signal . The readout circuit 15 may further comprise a control unit 121 which controls communication to other blocks and system components of the device . The readout circuit 15 may further comprise a reference block 123 which may be a general reference block .

[0057] Fig . 2 shows an equivalent circuit of the Hall sensing device 10 comprising the Hall element 12 and a compensation current source provided by the compensation block 100 . As is illustrated in Fig . 2 , the Hall voltage VHwhich is a function of the magnetic field and the impressed current by the Hall current source 11 i s compensated by a voltage-drop acros s RHwhich is created by the bidirectionally inj ected compensation current generated by the compensation block 100 , Icomp - RH corresponds to the resistance of the Hall element 12 . The compensation current ICOmp is created by the compensation block 100 which may comprise a current dig- ital-to-analog converter ( IDAC ) . The code of the IDAC may be directly proportional to the Hall voltage that is compensated .

[0058] Fig . 4A illustrates the principle of operation in greater detail . The AC-code which is created in phase AC corresponds to VH+ Vo f fs et • Further, the BD-code generated in phase BD corresponds to the value of -VH+ VOffSet - By subtracting the BD-code from the AC-code , VHmay be determined .

[0059] For determining the amount and a direction of the current , a comparator 105 is used . Its state may determine an increase or a decrease of the code of the IDAC . For example , the comparator 105 may have hysteresis .

[0060] The upper diagram of Fig . 4A shows Vsig in dependence from time during the di f ferent phases . Phase AC corresponds to the first phase in which the current is impressed between the first terminal A and the third terminal C by the Hall current source 11 . Phase BD corresponds to the second phase in which the Hall current source 11 impresses the current between the second terminal B and the fourth terminal D . As is shown in the upper diagram of Fig . 4A, the compensation current is decreased in a step-wise manner resulting in a step-wise decrease of Vslg. The second diagram of Fig . 4A shows an output 0 of the comparator 105 , sampled at the end of each code , in dependence from time .

[0061] As can be taken from a comparison o f the two upper diagrams of Fig . 4A, at t = ti , the sign of the comparator output changes . Accordingly, during phase AC, the voltage is not further decreased, and a code corresponding to the current corresponds to Vsig=V2. During phase BD, at t = t2 , the sign o f the comparator output changes again and accordingly, the voltage is not further increased . As a result , the BD-code corresponding to Vsig=V2is assessed .

[0062] The third diagram of Fig . 4A shows a resulting code output by the IDAC . The AC-code corresponds to V2and the BD-code corresponds to V2.

[0063] The fourth diagram of Fig . 4A shows the compensation current in dependence from time .

[0064] As is illustrated in Fig . 4A, At2which corresponds to a time for changing the step width when determining V2or V2may be smaller than the duration of the first or second phase . According to embodiments , the determination of the respective codes may be accomplished during a phase .

[0065] According to further embodiments , the determination of the respective IDAC codes may be distributed among multiple phases . This is illustrated in more detail in Fig . 4B . For example , At2may correspond to a part of or may correspond to the complete duration of the phase. For example, within each phase one additional IDAC code may be determined. The code for each spinning phase, e.g. phase AC, may be determined for each phase individually. This may allow to relax the settling time requirements for the comparator 105 while keeping the spinning frequency unchanged thus reducing noise that is proportional to 1 / f, wherein f denotes the frequency. As a result, current consumption of the comparator circuit may be reduced. Fig. 5A shows a Hall sensing device 10 according to further embodiments. The readout circuit 15 of the Hall sensing device 10 shown in Fig. 5A comprises similar components as the readout circuit 15 illustrated in Fig. 1. Differing from embodiments illustrated in Fig. 1, the compensation block 100 comprises a first and a second current source 111, 112 only, while a third and a fourth current source are absent from the compensation block 100.

[0066] Figs. 5B to 5E show circuit examples during different phases and wherein for each of the different phases, the current source has different polarities, respectively. Fig. 5B shows an example in which a current provided by the Hall current source 11 flows between the first terminal A and the third terminal C. Further, the first current source 111 is at a comparatively high level and acts as a current source. During a first phase, the first current source 111 is connected to the second terminal B. Accordingly, the current flows from B to the third terminal C.

[0067] Figs. 5C shows a circuit example when the second current source 112 is at a low level and acts as a current sink. During the second phase, when the current impressed by the Hall current source 11 flows from A to C, the second current source 112 is connected to the second terminal B. Accordingly, a compensation current flows from the first terminal A to the second terminal

[0068] B .

[0069] Fig . 5D shows a case during the third phase in which the current provided by the Hall current source 11 is applied to the second terminal B . During the third phase , the first current source 111 is connected to the first terminal A. Accordingly, the compensation current flows from the first terminal A to the fourth terminal D .

[0070] Fig . 5E shows a case during the fourth phase in which a current supplied by the Hall current source 11 is applied to terminal B , and the first terminal A is connected to the second current source 112 at a low level acting as a current sink . In this case , a compensation current flows from terminal D to the first terminal A.

[0071] Fig . 6 shows a circuit example , when the compensation is based on a supply voltage Vdd . In this case , the compensation block 100 may comprise a bias circuit compri sing two transistors and two resistive elements which are coupled in parallel . As is illustrated in Fig . 6 , the left branch comprising a transi stor and a resistive element implements the first current source 111 , and the second current source 112 is implemented by the righthand current path including a transistor and a variable resistor element 115 , 116 . A terminal of the transistors of the righthand path and the left-hand path is connected to a common node which is connected to the supply voltage , Vdd . Moreover, the multiplexer 102 switching between the first terminal A and the second terminal B of the Hal l element 12 is connected to Vdd . According to embodiments illustrated in Fig . 6 , the Hall current source 11 is implemented by Vdd . Accordingly, the voltage to the Hall element to induce a Hall current is determined by the supply voltage Vdd and the resistance RHof the Hall element . Likewise, the compensation current Icomp is determined by Vdd, the resistance of the variable resistor elements 115 , 116 and the impedance of the associated transistors . Moreover, the multiplexer 102 for switching between the third terminal C and the fourth terminal D is connected to ground ( GND) . In this case , a common mode control device 108 may be dispensed with, since the terminals of the Hall element 12 are connected to the supply voltage Vdd and to ground, respectively . Moreover, the automatic gain control circuitry 120 may as well by dispensed with .

[0072] Due to the speci fic configuration illustrated in Fig . 6 , the complexity of the circuits , in particular of the compensation block 100 may be largely decreased .

[0073] Fig . 7A and 7B are equivalent circuit diagrams of a readout circuit 15 according to further examples in di f ferent switching states . According to embodiments illustrated in Figs . 7A and 7B, the compensation current in combination with the resistance of resistor elements 117 , 118 generates a compensation voltage that compensates for the Hall voltage generated within the Hall element . As is illustrated, the compensation block 100 may comprise a first current source 111 at a high level and a first resistor element 117 . The first current source 111 is configured to be connected to the second terminal B or to the fourth terminal D, e . g . using a switch 119 . The compensation block 100 further comprises a second current source 112 at a low level and a second resistor element 118 . The second current source 112 is configured to be connected to the second terminal B or to the fourth terminal D, e . g . using a switch 119 .

[0074] For example , the first and / or the second current sources 111 , 112 may be variable or constant . Further, any of the first and / or the second resistor elements 117 , 118 may be variable or constant. Any of the first and / or second current sources 111, 112 and of the first and / or second resistor elements 117, 118 may be varied so as to compensate the Hall voltage. For example, either a variable current source or a variable resistor element may be used to compensate the Hall voltage.

[0075] Fig. 7A illustrates a first switching state, wherein the first current source 111 and the second current source 112 are connected to the second terminal B.

[0076] Fig. 7B illustrates a second switching state, wherein the first current source 111 and the second current source 112 are connected to the second terminal D.

[0077] According to embodiments illustrated in Figs. 7A and 7B, depending on a spinning phase, the first current source 111 and the second current source 112 may be alternatively be connected to the first terminal A. Further, depending on a spinning phase, the first current source 111 and the second current source 112 may be connected to the third terminal C.

[0078] According to examples illustrated in Fig. 7C, the compensation block 100 may comprise a variable voltage source, e.g. a volt- age-controlled voltage source 124. The voltage-controlled voltage source 124 may be operable to generate a varying output voltage that is applied to e.g. the second terminal B. Depending on a spinning phase, the varying output voltage may be likewise applied to the first terminal A.

[0079] Fig. 8 illustrates a method according to embodiments. As is shown, a method of operating the readout circuit as has been explained above comprises impressing (S100) the compensation current into the Hall element, and step wise increasing (Slid) the compensation current until a sign of an output signal generated by the comparator changes . For example , stepwise increasing ( S 110 ) the compensation current until the sign of the output signal changes may be accomplished in a time which is larger than a spinning phase . Accordingly, determining the compensation voltage may be distributed among a plurality of spinning phases .

[0080] As has been shown, in comparison to known concepts in which a Hall voltage is sensed using an ampli fier, according to embodiments , the Hall voltage may be sensed using a controlled current source and a comparator . In general , switched current sources may achieve a good performance , in particular, a good INL (" integral nonlinearity" ) and DNL ("di f ferential nonlinearity" ) behaviour i f the operating conditions stay constant . Using thi s method, the operating point is almost the same for di f ferent current spinning phases . As a result , complexity of the readout circuit may be largely reduced . Further, measurement results are directly available in the digital domain .

[0081] While embodiments of the invention have been described above , it is obvious that further embodiments may be implemented . For example , further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above . Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein . LIST OF REFERENCES

[0082] 10 Hall sensing device

[0083] 11 Hall current source

[0084] 12 Hall element

[0085] 15 readout circuit

[0086] 16 magnetic field

[0087] 100 compensation block

[0088] 102 current multiplexer

[0089] 105 comparator

[0090] 107 compensation control device

[0091] 108 common mode control device

[0092] 109 chopping multiplexer

[0093] 111 first current source

[0094] 112 second current source

[0095] 113 third current source

[0096] 114 fourth current source

[0097] 115 first variable resistor element

[0098] 116 second variable resistor element

[0099] 117 first resistor element

[0100] 118 second resistor element

[0101] 119 switch

[0102] 120 automatic gain control circuitry

[0103] 121 control unit

[0104] 122 spinning / chopping control block

[0105] 123 reference block

[0106] 124 voltage-controlled voltage source

[0107] A, B, C, D terminals of Hall element

Claims

CLAIMS1. A readout circuit (15) for reading out a Hall element (12) having a first terminal (A) , a second terminal (B) , a third terminal (C) and a fourth terminal (D) , the readout circuit (15) comprising: a Hall current source (11) configured to impress a current into the Hall element (15) via the first terminal (A) and the third terminal (C) , the first and the third terminal (A, C) being arranged along a first direction; a compensation block (100) configured to apply a variable compensation voltage to the Hall element (15) via the second terminal (B) ; and a comparator (105) configured to determine when a voltage difference between the second (B) and the fourth terminal (D) is zero, the second terminal (B) and the fourth terminal (D) being arranged along a second direction different from the first direction.

2. The readout circuit (15) according to claim 1, wherein the compensation block (100) comprises a differential current device comprising a first variable current source (111) at a high level and a second variable current source (112) at a low level configured to be connected to the second terminal (B) and a third variable current source (113) at a high level and a fourth variable current source (114) at a low level configured to be connected to the fourth terminal (D) .

3. The readout circuit (15) according to claim 2, further comprising a compensation control device (107) configured to vary a current of the first to fourth variable current sources (111, 112, 113, 114) .

4. The readout circuit (15) according to claim 1, wherein the compensation block comprises a first variable current source (111) at a high level and a second variable current source (112) at a low level configured to be connected to the second terminal (B) or to the fourth terminal (D) .

5. The readout circuit (15) according to claim 4, further comprising a compensation control device (107) configured to vary a current of the first and second variable current sources (111, 112) .

6. The readout circuit according to claim 5, wherein theHall current source (11) comprises a supply voltage terminal, and the first variable current source (111) and the second variable current source each comprise a variable resistor element (115, 116) and transistor coupled in parallel to the supply voltage terminal, respectively.

7. The readout circuit (15) according to claim 3, 5 or 6, wherein the compensation control device (107) is configured to cease varying the current when the comparator (105) has determined that the voltage difference between the second and the fourth terminal (B, D) is zero.

8. The readout circuit (15) according to claim 1, wherein the compensation block (100) comprises a first current source (111) at a high level, configured to be connected to the second terminal (B) or to the fourth terminal (D) , and a first resistor element (117) and further comprises a second current source (112) at a low level, configured to be connected to the second terminal (B) or to the fourth terminal (D) , and a second resistor element (118) .

9. The readout circuit (15) according to claim 1, wherein the compensation block (100) comprises a variable voltage source .

10. The readout circuit (15) according to claim 9, wherein the variable voltage source comprises a voltage-controlled voltage source (124) .

11. The readout circuit (15) according to any of the preceding claims, being configured to be operated in different spinning phases, wherein in a first spinning phase a current is impressed into the Hall element (12) between the first terminal and the third terminal (A, C) and in a second spinning phase the current is impressed into the Hall element (12) between the second terminal and the fourth terminal (B, D) .

12. The readout circuit (15) according to claim 11, wherein in a third spinning phase a current is impressed into the Hall element (12) between the third terminal and the first terminal (C,A, ) and in a fourth spinning phase the current is impressed into the Hall element (12) between the fourth terminal and the second terminal (D, B) .

13. The readout circuit (15) according to any of the preceding claims, wherein the compensation block (100) is configured generate a binary code corresponding to the compensation current or to the compensation voltage.

14. The readout circuit (15) according to claim 13, wherein the compensation block (100) is configured to generate the binary code in a time which is larger than a spinning phase.

15. A Hall sensing device (10) comprising: a Hall element (12) ; anda readout circuit (15) according to any of the preceding claims.

16. A method of operating the readout circuit (15) accord- ing to claim 11 or 12, comprising: impressing (S100) the compensation current into theHall element (12) ; and step wise increasing (Slid) the compensation current until a sign of an output signal generated by the comparator (105) changes.

17. The method of claim 16, wherein stepwise increasing the compensation current until the sign of the output signal changes is accomplished in a time which is larger than a spin- ning phase.

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