Glass ceramic substrate for semiconductor package and method for manufacturing same

Abstract

A glass ceramic substrate 1 for a semiconductor package has a crystal phase and a glass phase. When the thermal expansion coefficient of the crystal phase is denoted as α1 [ppm / K] and the thermal expansion coefficient of the glass phase is denoted as α2 [ppm / K], the relation of 2≤α1 / α2≤8 is satisfied.

Description

Glass-ceramic substrate for semiconductor package and method for manufacturing the same

[0001] The present invention relates to a glass-ceramic substrate for a semiconductor package.

[0002] Conventionally, as a substrate for a semiconductor package, an organic substrate made of glass fiber and resin has been widely used. However, in recent years, there has been a problem that it is difficult to meet the demand for finer wiring. Therefore, in order to achieve finer wiring, a glass-ceramic substrate may be used as a substrate for a semiconductor package (see, for example, Patent Document 1).

[0003] International Publication No.: WO2022 / 163588 Japanese Patent Application Laid-Open No. 9-169559

[0004] Masahiro Ashizuka, et al., "Mechanical Properties of Various Silicate Crystals (Part 1)", Journal of the Ceramic Society of Japan, 1989, Vol. 97, No. 5, p. 544-548

[0005] In a substrate for a semiconductor package, a plurality of holes (vias) are formed to electrically connect between wirings. In fact, such holes also have a very small hole diameter and adjacent hole pitch due to the miniaturization of the wiring. Therefore, as a hole drilling method, laser hole drilling that enables microfabrication may be used.

[0006] However, when a glass-ceramic substrate is used as a substrate for a semiconductor package, there is a problem that damage such as cracks is likely to occur around the holes when laser hole drilling is performed. Such a problem becomes particularly prominent when the substrate size of the glass-ceramic substrate is increased. That is, when the substrate size of the glass-ceramic substrate is increased, the number of holes to be formed increases, so the number of laser shots inevitably increases. As a result, strain accumulates, and damage such as cracks is likely to occur around the holes. Here, it goes without saying that a crack refers not to a very small scratch (microcrack) remaining on the surface but to a crack that has progressed from there into the glass-ceramic substrate. The presence of these cracks makes the glass-ceramic substrate more likely to crack.

[0007] An object of the present invention is to provide a glass-ceramics substrate for a semiconductor package and a method for manufacturing the same, which are less likely to be damaged such as cracks even when laser drilling is performed.

[0008] (1) The present invention devised to solve the above problems is a glass-ceramics substrate for a semiconductor package having a crystal phase and a glass phase, where when the thermal expansion coefficient of the crystal phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], a relationship of 2 ≤ α1 / α2 ≤ 8 holds.

[0009] In this way, since the glass-ceramics substrate for a semiconductor package has a crystal phase and a glass phase, the disadvantage of the glass phase, which is likely to be damaged, can be compensated by the crystal phase. And when having a crystal phase and a glass phase in this way, in suppressing damage such as cracks around the hole during laser drilling, based on ordinary knowledge, it is expected that having no difference between the thermal expansion coefficient α1 of the crystal phase and the thermal expansion coefficient α2 of the glass phase (α1 / α2 = 1) will be effective. However, as a result of the intensive research by the present inventor, contrary to the expectation, in suppressing damage such as cracks around the hole during laser drilling, a difference is provided between the thermal expansion coefficient α1 of the crystal phase and the thermal expansion coefficient α2 of the glass phase, and it has been found that setting 2 ≤ α1 / α2 ≤ 8 is effective. That is, if the relationship of 2 ≤ α1 / α2 ≤ 8 holds, damage such as cracks around the hole is less likely to occur even when laser drilling is performed.

[0010] (2) In the configuration of (1) above, it is preferable that the content of the crystal phase is 2 to 50% by weight and the content of the glass phase is 50 to 98% by weight.

[0011] The crystal phase is less likely to be laser-drilled compared to the glass phase. Therefore, in efficiently performing laser drilling, as in the above configuration, it is preferable that the content of the glass phase in the glass-ceramics substrate for a semiconductor package is not less than the content of the crystal phase.

[0012] (3) In the configuration of (1) or (2) above, it is preferable that the glass ceramic substrate for semiconductor packaging has a thermal expansion coefficient α1 of the crystalline phase of 6 to 20 ppm / K and a thermal expansion coefficient α2 of the glass phase of 0.6 to 5 ppm / K.

[0013] (4) In any of the configurations described in (1) to (3) above, it is preferable that the coefficient of thermal expansion of the entire glass ceramic substrate for semiconductor packaging is 2.5 to 15 ppm / K.

[0014] In this way, thermal expansion of the glass-ceramic substrate for semiconductor packaging is suppressed in response to localized heating during laser drilling, making it less likely for cracks or other damage to occur around the holes.

[0015] (5) In any of the configurations (1) to (4) above, it is preferable that there is a pore-forming region in which a plurality of pores with a diameter of 100 μm or less are densely provided, the number of pores being provided at a rate of 1 to 4,000 per 10 mm square within the pore-forming region, and the thickness being 0.1 to 1.0 mm.

[0016] With the glass-ceramic substrate for semiconductor packaging according to the present invention, even within the thickness range described above, holes of the fine diameter described above can be formed crack-free. Furthermore, even when holes are formed at the density per 10 mm square described above, the holes can be formed crack-free. Therefore, it can adequately meet the demand for miniaturization of wiring in, for example, interposers, core substrates, image sensors, etc.

[0017] (6) In any of the configurations (1) to (5) above, the glass ceramic substrate for semiconductor packaging is preferably for use as an interposer.

[0018] (7) In any of the configurations described in (1) to (5) above, the glass ceramic substrate for the semiconductor package is preferably a core substrate.

[0019] (8) In any of the configurations (1) to (5) above, the glass ceramic substrate for semiconductor packaging is preferably for use as a substrate for an image sensor.

[0020] (9) In any of the configurations (1) to (8) above, the glass ceramic substrate for semiconductor packaging has fracture toughness K ＩＣ 1.0 to 2.5 MPa·m １／２ It is preferable that this be the case.

[0021] This method makes it less likely for damage to propagate from microcracks formed around the holes during laser drilling.

[0022] (10) In any of the configurations (1) to (9) above, the glass ceramic substrate for semiconductor packaging preferably has a Young's modulus of 40 to 90 GPa.

[0023] This method makes it less likely for damage to propagate from microcracks formed around the holes during laser drilling.

[0024] (11) In any of the configurations (1) to (3) above, it is preferable that the glass ceramic substrate for semiconductor packaging comprises a layer containing an interlayer insulating material on the substrate.

[0025] (12) The present invention, which was devised to solve the above problems, is a method for manufacturing a glass ceramic substrate for semiconductor packaging, comprising a preparation step of preparing a glass ceramic substrate having a crystalline phase and a glass phase, wherein the relationship 2 ≤ α1 / α2 ≤ 8 is satisfied when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], and a step of applying CO to the glass ceramic substrate ２ The invention is characterized by comprising a hole-drilling process that involves irradiating a laser to form a hole.

[0026] This method makes it less likely for cracks or other damage to occur around the holes in the glass-ceramic substrate for semiconductor packaging during laser drilling.

[0027] According to the present invention, it is possible to provide a glass ceramic substrate for semiconductor packaging that is less susceptible to damage even when drilled with a laser, and a method for manufacturing the same.

[0028] This is a plan view showing a glass-ceramic substrate for a semiconductor package according to this embodiment. This is a cross-sectional view showing an enlarged view of the pore formation region of the glass-ceramic substrate for a semiconductor package shown in Figure 1. This is a cross-sectional view showing a semiconductor package according to this embodiment. This is a flow diagram of the manufacturing method for the glass-ceramic substrate for a semiconductor package according to this embodiment.

[0029] Embodiments of the present invention will be described below with reference to the accompanying drawings.

[0030] <Glass-Ceramic Substrate for Semiconductor Packaging> As shown in Figure 1, the glass-ceramic substrate 1 for semiconductor packaging according to this embodiment is a low-temperature fired glass-ceramic having a glass phase and a crystalline phase. The glass phase has the disadvantage of being prone to breakage, but it has the advantage of being able to reduce voids in the glass-ceramic substrate 1 for semiconductor packaging and contribute to denser wiring. On the other hand, the crystalline phase has the advantage of suppressing breakage of the glass phase.

[0031] In the glass-ceramic substrate 1 for semiconductor packaging, when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], the relationship 2 ≤ α1 / α2 ≤ 8 holds. In this way, a laser (for example, CO) ２ Even when holes are drilled using a laser, compressive stress is applied to the glass phase, making it less likely for cracks or other damage to occur around the holes. α1 / α2 is preferably 2.5 to 7.5, 3.0 to 7.0, 3.5 to 6.5, 4.0 to 6.0, 4.5 to 6.0, 5.0 to 6.0, and particularly preferably 5.5 to 6.0. Unless otherwise specified, the coefficient of thermal expansion refers to measurements taken at 30 to 380°C.

[0032] The lower limit of the thermal expansion coefficient α1 of the crystalline phase is preferably 6 ppm / K or higher, 6.5 ppm / K or higher, 7 ppm / K or higher, and particularly preferably 10 ppm / K or higher. This makes it easier to increase the thermal expansion coefficient of the glass ceramic substrate 1 for semiconductor packages obtained by sintering. In addition, the difference in thermal expansion coefficient with the glass phase becomes larger, making it less likely for damage such as cracks to occur around the holes.

[0033] The upper limit of the thermal expansion coefficient α1 of the crystalline phase is preferably 20 ppm / K or less, 18 ppm / K or less, 16 ppm / K or less, and particularly preferably 15 ppm / K or less. This makes it easier to reduce the thermal expansion coefficient of the glass ceramic substrate 1 for semiconductor packages obtained by sintering.

[0034] The lower limit of the thermal expansion coefficient α2 of the glass phase is preferably 0.6 ppm / K or higher, 0.7 ppm / K or higher, 0.9 ppm / K or higher, 1.1 ppm / K or higher, 1.3 ppm / K or higher, 1.5 ppm / K or higher, 1.7 ppm / K or higher, 1.9 ppm / K or higher, and particularly preferably 2.1 ppm / K or higher. This makes it easier to increase the thermal expansion coefficient of the glass ceramic substrate 1 for semiconductor packages obtained by sintering.

[0035] The upper limit of the thermal expansion coefficient α2 of the glass phase is preferably 5 ppm / K or less, 4.5 ppm / K or less, 4.0 ppm / K or less, 3.5 ppm / K or less, 3.0 ppm / K or less, 2.7 ppm / K or less, and particularly preferably 2.5 ppm / K or less. This makes it easier to lower the thermal expansion coefficient of the glass ceramic substrate 1 for semiconductor packages obtained by sintering. In addition, the difference in thermal expansion coefficient with the crystalline phase becomes larger, making it less likely for damage such as cracks to occur around the holes.

[0036] Here, the thermal expansion coefficient α1 of the crystalline phase is determined as follows. First, the crystalline phase contained in the glass ceramic substrate 1 for semiconductor packaging is identified using an X-ray diffractometer (XRD). Next, the thermal expansion coefficient of the crystalline phase identified by XRD is determined using literature values ​​(for example, values ​​described in Patent Document 2 or Non-Patent Document 1), and this determined value is taken as the thermal expansion coefficient α1. If the glass ceramic substrate 1 for semiconductor packaging contains multiple types of crystalline phases, the thermal expansion coefficient of the crystal with the highest thermal expansion coefficient is taken as α1.

[0037] The coefficient of thermal expansion α2 of the glass phase is determined as follows. First, the glass phase contained in the glass-ceramic substrate 1 for semiconductor packages is confirmed using a transmission electron microscope (TEM). Next, the composition of the glass phase is specified using energy-dispersive X-ray spectroscopy (TEM-EDX) attached to the TEM. Then, based on the composition of the specified glass phase, the coefficient of thermal expansion α2 of the glass phase is determined. Specifically, for example, a glass having the same composition as the specified composition of the glass phase is actually produced, and the coefficient of thermal expansion is measured with a thermal expansion measuring device (TMA method), and the measured value is taken as the coefficient of thermal expansion α2. Alternatively, the coefficient of thermal expansion may be estimated from the composition of the specified glass phase and taken as the coefficient of thermal expansion α2. However, from the viewpoint of obtaining a highly accurate coefficient of thermal expansion α2, it is preferable to produce a glass having the same composition as the specified composition and actually measure the coefficient of thermal expansion.

[0038] Also, the coefficient of thermal expansion α2 of the glass phase can be determined as follows. First, the crystal phase composition and crystallinity are determined by XRD in the glass-ceramic substrate 1 for semiconductor packages. Next, the glass-ceramic substrate 1 for semiconductor packages is melted and solidified to obtain a solid. The overall composition of the glass-ceramic substrate 1 for semiconductor packages is determined from the obtained solid by a method such as fluorescent X-ray analysis. Then, based on the overall composition, crystal phase composition, and crystallinity, the composition of the glass phase is specified (calculated). Then, based on the composition of the specified glass phase, the coefficient of thermal expansion α2 of the glass phase is determined. Specific methods for determining the coefficient of thermal expansion α2 from the composition of the specified glass phase include methods such as actually measuring the coefficient of thermal expansion of a glass having the same composition as the specified composition of the glass phase and methods for estimating the coefficient of thermal expansion from the composition of the specified glass phase, which can be similarly applied.

[0039] The composition of the glass phase is preferably, by weight%, SiO ２ 50 to 80%, B ２ O ３ 15 to 30%, Li ２ O + Na ２ O + K ２ O 0.1 to 2%. Also, by weight ratio, Li ２ O / (Li ２ O + Na ２O+K ２ O) 0.10-0.50, Na ２ O / (Li ２ O + Na ２ O+K ２ O) 0.25-0.65, K ２ O / (Li ２ O + Na ２ O+K ２ O) Preferably 0.05 to 0.35. Here, "Li ２ O + Na ２ O+K ２ "O" is Li ２ O, Na ２ O and K ２ It is the total amount of O. ２ O / (Li ２ O + Na ２ O+K ２ O) is Li ２ The amount of O is Li ２ O, Na ２ O and K ２ This is the value obtained by dividing by the total amount of O. ２ O / (Li ２ O + Na ２ O+K ２ O) is Na ２ The amount of O is Li ２ O, Na ２ O and K ２ This is the value obtained by dividing by the total amount of O. ２ O / (Li ２ O + Na ２ O+K ２ O) is K ２ The amount of O is Li ２ O, Na ２ O and K ２ This is the value obtained by dividing by the total amount of O.

[0040] The crystalline phase may be a phase formed by the crystallization of the glass phase components, or it may be an inorganic filler with components different from glass. Alternatively, the crystalline phase may contain both a phase formed by the crystallization of the glass phase components and an inorganic filler.

[0041] Examples of inorganic fillers include quartz (α-SiO ２ ), alumina (Al ２ O３ ), diopside (MgCaSi ２ O ６ ), anorthite (CaAl ２ Si ２ O ８ ), cordierite (Mg ２ Al ４ Si ５ O １８ ), forsterite (Mg ２ SiO ４ Examples include the following. The thermal expansion coefficients α1 (literature values) of these inorganic fillers are shown in Table 1.

[0042]

[0043] In the glass ceramic substrate 1 for semiconductor packaging, it is preferable that the content of the crystalline phase is 2 to 50% by weight and the content of the glass phase is 50 to 98% by weight.

[0044] The upper limit of the crystalline phase content is more preferably 45% by weight or less, 40% by weight or less, 35% by weight or less, and most preferably 30% by weight or less. In this way, the content of the glass phase is greater than the content of the crystalline phase. The glass phase is easier to process with a laser than the crystalline phase, and if the content of the glass phase is relatively high, crackless holes can be formed even when laser processing is performed with relatively low power energy.

[0045] The lower limit of the glass phase content is more preferably 55% by weight or more, 60% by weight or more, 65% by weight or more, and most preferably 70% by weight or more. In this way, the glass phase content is greater than the crystalline phase content. The glass phase is easier to process with a laser than the crystalline phase, and if the glass phase content is relatively high, crackless holes can be formed even when laser processing is performed with relatively low power energy.

[0046] Here, the content of the crystalline phase and the glass phase is determined by separating the crystalline diffraction lines and amorphous halos into peaks in the diffraction line profile at 10 to 60° using 2θ values ​​obtained by powder X-ray diffraction measurement with CuKα rays. Specifically, if the integrated intensity obtained by separating the broad diffraction lines (amorphous halos) at 10 to 45° from the total scattering curve obtained by subtracting the background from the diffraction line profile is Ia, and the sum of the integrated intensities obtained by separating the peaks of each crystalline diffraction line detected at 10 to 60° is Ic, then the weight %Xc of the crystalline phase and the weight %Xa of the glass phase (amorphous phase) can be calculated from the following equations: Xc = [Ic / (Ic + Ia)] × 100 (%) Xa = 100 - Xc (%)

[0047] The crystal grain size of the inorganic filler in the glass ceramic substrate 1 for semiconductor packaging is preferably 10 μm or less, 8 μm or less, and particularly preferably 5 μm or less. Furthermore, the crystal grain size of the inorganic filler in the sintered body is preferably 0.01 μm or more, and particularly preferably 0.1 μm or more.

[0048] The grain size can be measured, for example, as follows: First, a cross-section is formed from a glass ceramic substrate (sintered body) sample. Next, the sample is heat-treated. This heat treatment is preferably performed by thermal etching in an electric furnace. The heat treatment temperature can be, for example, 900°C or higher and 1600°C or lower. The heat treatment time can be, for example, 1 minute or higher and 60 minutes or lower. Next, the cross-section of the heat-treated sample is observed using a scanning electron microscope (SEM). For example, for any 200 particles in the obtained SEM image, the size of each particle is counted using image analysis software, and the average grain size is determined. This allows the grain size to be determined. In image analysis, the area circle equivalent diameter of the grain is used as the grain size.

[0049] The lower limit of the thermal expansion coefficient α3 for the entire glass ceramic substrate 1 for semiconductor packaging is preferably 2.5 ppm / K or higher, 3.0 ppm / K or higher, 3.5 ppm / K or higher, and particularly preferably 4 ppm / K or higher. The upper limit of the thermal expansion coefficient α3 for the entire glass ceramic substrate 1 for semiconductor packaging is preferably 15 ppm / K or lower, 13 ppm / K or lower, 11 ppm / K or lower, 9 ppm / K or lower, 7 ppm / K or lower, and particularly preferably 6 ppm / K or lower. In this way, thermal expansion of the glass ceramic substrate 1 for semiconductor packaging during laser drilling is suppressed, making it less likely for cracks or other damage to occur around the holes. The thermal expansion coefficient α3 can be measured, for example, by a thermal expansion measuring device (TMA method).

[0050] Fracture toughness K of glass ceramic substrate 1 for semiconductor package ＩＣ The pressure range is 1.0 to 2.5 MPa·m. １／２ This is preferable. This makes it less likely for damage to propagate from microcracks formed around the hole during laser drilling. Fracture toughness K ＩＣ The lower limit is 1.1 MPa·m １／２ It is more preferable that the pressure be greater than or equal to 1.2 MPa·m １／２ The above is even more preferable. Fracture toughness K ＩＣ The upper limit is 2.4 MPa·m １／２ It is more preferable that the pressure be 2.3 MPa·m １／２ The following is even more preferable: K ＩＣ This can be measured by the Indentation Fracture method (IF method) in accordance with JIS R1607. ＩＣ This can be measured, for example, using the SEPB method, or calculated based on the Miller constant.

[0051] The Young's modulus of the glass ceramic substrate 1 for semiconductor packaging is preferably 40 to 90 GPa. This makes it easier to ensure the rigidity of the glass ceramic substrate 1 for semiconductor packaging and makes it difficult for scratches to propagate from microcracks formed around holes during laser drilling. The lower limit of the Young's modulus is preferably 40 GPa or higher, more preferably 45 GPa or higher, and even more preferably 50 GPa or higher. The upper limit of the Young's modulus is preferably 90 GPa or lower, more preferably 85 GPa or lower, and even more preferably 80 GPa. Here, the Young's modulus was measured using a free-resonance type elastic modulus measuring device (JE-RT3 manufactured by Nippon Techno Plus Co., Ltd.). The measurement was performed at room temperature (25°C).

[0052] Furthermore, if the Young's modulus becomes too high, while rigidity increases, the effect of distributing force against impact decreases, making the semiconductor package glass ceramic substrate 1 more susceptible to breakage. Therefore, if impact is applied during the manufacturing process of the semiconductor package glass ceramic substrate 1, there is a risk of the semiconductor package glass ceramic substrate 1 breaking. On the other hand, if the Young's modulus becomes too low, the semiconductor package glass ceramic substrate 1 may bend during movement during the manufacturing process, potentially causing it to come into contact with peripheral equipment such as moving devices. Therefore, from the viewpoint of suppressing such problems, it is preferable that the Young's modulus of the semiconductor package glass ceramic substrate 1 be within the above numerical range.

[0053] The glass ceramic substrate 1 for semiconductor packaging is rectangular in shape, with a vertical dimension L1 and a horizontal dimension L2 of 300 mm x 300 mm or more. From the viewpoint of obtaining multiple core substrates, the substrate size (L1 x L2) of the glass ceramic substrate 1 for semiconductor packaging is preferably 350 mm x 350 mm or more, more preferably 400 mm x 400 mm or more, even more preferably 450 mm x 450 mm or more, and particularly preferably 500 mm x 500 mm or more. However, if the substrate size of the glass ceramic substrate 1 for semiconductor packaging becomes excessively large, the manufacturing of the substrate itself becomes difficult. Therefore, the substrate size (L1 x L2) of the glass ceramic substrate 1 for semiconductor packaging is preferably 700 mm x 700 mm or less, more preferably 650 mm x 650 mm or less, even more preferably 600 mm x 600 mm or less, and particularly preferably 550 mm x 550 mm or less.

[0054] The thickness of the glass ceramic substrate 1 for semiconductor packaging is preferably 0.1 to 1.0 mm. The upper limit of the thickness of the glass ceramic substrate 1 for semiconductor packaging is more preferably 0.8 mm or less, 0.6 mm or less, and most preferably 0.5 mm or less. On the other hand, the lower limit of the thickness of the glass ceramic substrate 1 for semiconductor packaging is more preferably 0.2 mm or more, and most preferably 0.3 mm or more. With such thicknesses, it is easier to ensure the rigidity of the glass ceramic substrate 1 for semiconductor packaging, and therefore it can be suitably used as a core substrate or the like.

[0055] The relative permittivity of the glass ceramic substrate 1 for semiconductor packaging is preferably 1 to 20, 2 to 16, 3 to 12, 4 to 9, 4 to 7, and particularly preferably 4 to 6. The dielectric loss tangent of the glass ceramic substrate 1 for semiconductor packaging is preferably 0.0001 to 0.007, 0.001 to 0.006, and particularly preferably 0.0015 to 0.005. In this way, even if the semiconductor package is used as a high-frequency circuit component, for example, loss of transmission signals and reduction in signal processing speed are less likely to occur. Here, the relative permittivity and dielectric loss tangent refer to values ​​measured at a measurement temperature of 25°C and a frequency of 16 GHz, based on the measurement method for microwave dielectric properties of fine ceramic substrates (JIS R1627).

[0056] As shown in Figure 2, a hole-forming region may be formed in the central portion 1b of the semiconductor package glass ceramic substrate 1, excluding the peripheral portion 1a, where multiple holes H are densely arranged. Note that the holes H are not shown in Figure 1. The hole-forming region may be, for example, a rectangular region in plan view, and multiple such regions may be provided in the central portion 1b of the semiconductor package glass ceramic substrate 1. When multiple hole-forming regions are provided, a band-shaped region without holes H is formed between adjacent hole-forming regions. The holes H are holes that penetrate in the thickness direction of the semiconductor package glass ceramic substrate 1, and are, for example, CO ２ The holes H are formed by laser irradiation. These holes H can be used, for example, as vias to electrically connect wiring.

[0057] The pores H preferably have a diameter D of 100 μm or less, more preferably 90 μm or less, and even more preferably 75 μm or less. The lower limit is not particularly limited, but is 10 μm or more. If the above-mentioned relationship 2 ≤ α1 / α2 ≤ 8 holds true in the semiconductor package substrate, then even if holes of such fine diameters are drilled using a laser, the holes can be formed without cracking. This allows for finer wiring than before when used as a substrate for semiconductor packages.

[0058] Preferably, there are 1 to 4000 holes H per 10 mm square within the hole-forming region. The upper limit of holes H is more preferably 3600 or less, 3200 or less, 2800 or less, 2500 or less, and most preferably 1600 or less. The lower limit of holes H is more preferably 10 or more, 50 or more, 100 or more, 500 or more, and most preferably 1000 or more. If the above-mentioned relationship 2 ≤ α1 / α2 ≤ 8 holds true in the semiconductor package substrate, then even if high-density hole drilling is performed by laser as described above, holes can be formed without cracking. This makes it possible to accommodate finer wiring than before when used as a substrate for semiconductor packages.

[0059] Furthermore, the width W of the peripheral edge 1a of the glass ceramic substrate 1 for semiconductor packaging is preferably 10 mm or less, more preferably 5 mm or less, and even more preferably 3 mm or less. By reducing the width W of the peripheral edge 1a, the area of ​​the central portion 1b from which the core substrate or the like can be collected can be increased.

[0060] <Semiconductor Package> As shown in Figure 3, the semiconductor package 11 according to this embodiment comprises a core substrate 12, a semiconductor element 13, and an interposer 14 disposed between the core substrate 12 and the semiconductor element 13. Although not shown in the figures, the core substrate 12 and the interposer 14 have wiring and holes (vias) that electrically connect the wiring formed therein.

[0061] The core substrate 12 is a single-layer substrate taken from the central portion 1b of the semiconductor package glass ceramic substrate 1. In other words, in this embodiment, multiple core substrates 12 are taken from the central portion 1b of the semiconductor package glass ceramic substrate 1.

[0062] Although not shown in the diagram, it is preferable that the structure consists of interlayer insulating material laminated on the core substrate 12. By forming metal wiring on the interlayer insulating material and laminating multiple layers, a redistribution layer is formed, which enables finer circuit design in semiconductor package substrates.

[0063] Examples of interlayer insulating materials include organic materials containing resin and inorganic materials containing glass. Preferably, the difference in thermal expansion coefficient of the interlayer insulating material from that of the core substrate 12 is within 5.0 ppm / K. With this configuration, warping due to thermal expansion differences is less likely to occur when heat is applied during the semiconductor package manufacturing process.

[0064] The interposer 14 is a relay board for electrically connecting the core substrate 12 and the semiconductor element 13. Note that the semiconductor package 11 does not necessarily have to include the interposer 14. In other words, the semiconductor package 11 may have a configuration in which the semiconductor element 13 is directly placed on the core substrate 12.

[0065] <Method for Manufacturing a Glass Ceramic Substrate for Semiconductor Packaging> As shown in Figure 4, the method for manufacturing the glass ceramic substrate 1 for semiconductor packaging according to this embodiment comprises a substrate molding step S1, a firing step S2, and a hole drilling step S3 in this order. The substrate molding step S1 and the firing step S2 correspond to the preparation steps for preparing the glass ceramic substrate 1 for semiconductor packaging.

[0066] In the substrate molding process S1, first, a slurry, which is a liquid mixed raw material, is prepared by mixing glass powder (which will be the glass phase (or glass phase and crystalline phase) of the glass ceramic substrate 1 for semiconductor packaging), a binder (e.g., acrylic), a solvent, etc. Next, the slurry is molded into a plate shape to obtain a molded body. If the crystalline phase of the glass ceramic substrate 1 for semiconductor packaging contains an inorganic filler, the slurry further contains inorganic filler powder. The types of glass powder and inorganic filler are selected such that the relationship 2 ≤ α1 / α2 ≤ 8 holds in the glass ceramic substrate 1 for semiconductor packaging obtained from the molded body. As a molding method for forming a plate-shaped molded body from the slurry, for example, slip casting, extrusion molding, pressure molding, injection molding, etc., can be used.

[0067] In the firing process S2, the plate-shaped molded body obtained in the substrate molding process S1 is fired to densify the molded body. This yields a glass ceramic substrate 1 for semiconductor packaging having a crystalline phase and a glass phase. The firing temperature is, for example, 700 to 1000°C, and the firing time is, for example, 2 to 15 hours.

[0068] In the hole-drilling process S3, CO2 is injected into the hole-forming region of the central part 1b of the glass ceramic substrate 1 for semiconductor packaging. ２ A laser is used to create multiple holes.

[0069] Furthermore, this manufacturing method may further include a cutting step after the drilling step S3, in which multiple substrates (for example, core substrates, etc.) of a size to be mounted on the semiconductor package 11 are taken from the central portion 1b of the glass ceramic substrate 1 for semiconductor packaging.

[0070] The present invention is not limited to the configuration of the above embodiments, nor is it limited to the effects described above. The present invention can be modified in various ways without departing from the spirit of the invention.

[0071] In the above embodiment, the glass-ceramic substrate 1 for semiconductor packaging was described as being rectangular in shape, but it is not limited to this. For example, the glass-ceramic substrate 1 for semiconductor packaging may be circular in shape or the like.

[0072] In the above embodiment, the case in which the glass ceramic substrate 1 for semiconductor packaging is used as the core substrate 12 was described, but the invention is not limited to this. For example, the glass ceramic substrate 1 for semiconductor packaging may be used as an interposer 14 or a substrate for an image sensor.

[0073] In the above embodiment, the case in which the glass-ceramic substrate 1 for semiconductor packaging is a low-temperature fired glass-ceramic was described, but it may also be crystallized glass.

[0074] The present invention will be described in detail below based on examples, but the present invention is not limited to these examples.

[0075] Table 2 shows the composition of the glass raw materials, fillers, and their physical properties used to fabricate glass ceramic substrates for semiconductor packaging. The thermal expansion coefficients of the glass raw materials and fillers were obtained by measuring the bulk of each material using the TMA method. Samples No. 1 to 5 are examples, and samples No. 6 to 8 are comparative examples.

[0076]

[0077] Table 3 shows the physical properties, firing conditions, and laser processability of the glass ceramic substrate for semiconductor packaging after firing.

[0078] The masses of the glass phase and crystalline phase in the glass-ceramic substrate for semiconductor packaging after firing were determined by powder X-ray diffraction measurements using CuKα rays, and the diffraction line profiles with 2θ values ​​of 10 to 60° were separated into crystalline diffraction lines and amorphous halos.

[0079] The thermal expansion coefficient α1 of the crystalline phase was determined as follows: First, the crystalline phase was identified in a glass-ceramic substrate for semiconductor packaging using XRD, and the literature value for the thermal expansion coefficient of the identified crystalline phase was taken as the thermal expansion coefficient α1.

[0080] The thermal expansion coefficient α2 of the glass phase was determined as follows: First, the crystalline phase composition and degree of crystallinity of the glass-ceramic substrate for semiconductor packaging were determined by XRD. Next, the overall composition of the glass-ceramic substrate for semiconductor packaging was determined from the solidified material obtained by melting and solidifying the substrate by X-ray fluorescence analysis. Subsequently, the composition of the glass phase was identified (calculated) from the overall composition, crystalline phase composition, and degree of crystallinity. Then, glass was fabricated to match the determined glass phase composition, and the thermal expansion coefficient of the obtained glass was measured by TMA, and this value was defined as the thermal expansion coefficient α2.

[0081] The thermal expansion coefficient α3 was determined by measuring the thermal expansion coefficient of the glass-ceramic substrate for semiconductor packaging after firing using the TMA method.

[0082] The relative permittivity and dielectric loss tangent were measured at a temperature of 25°C and a frequency of 16 GHz, based on the measurement method for microwave dielectric properties of fine ceramic substrates (JIS R1627).

[0083] Laser processability was evaluated as follows. First, glass-ceramic substrates for semiconductor packages were prepared after firing, corresponding to each example and each comparative example. The thickness of each glass-ceramic substrate for semiconductor packages was 0.4 mm. Next, CO ２ A single 100 μm diameter hole was formed in the center of each glass-ceramic substrate for semiconductor packages using a laser. The laser irradiation conditions were: wavelength 9.4 μm, pulse width 2 μs, and power density 7 MW / cm². ２ In this evaluation, samples that allowed for crack-free hole formation were marked with "○", while those that resulted in cracks were marked with "×".

[0084]

[0085] Table 4 shows the results for sample No. 2 in Table 3, where the pore diameter was set to 75 μm and the number of pores in a 10 mm × 10 mm area was varied. The laser used was CO ２ Using a laser, with a wavelength of 9.4 μm, a pulse width of 2 μs, and a power density of 7 MW / cm², the measurement was performed. ２ Holes were formed under the following conditions. Examples 2-1 to 2-7 show that when the hole diameter is 100 μm or less and the number of holes per 10 mm square is 4000 or less, crack-free holes can be formed. In contrast, in Example 2-8, where the hole diameter was 100 μm or less but the number of holes was 4356, although the crack occurrence rate was low, cracks occurred in 2% of the holes.

[0086]

[0087] 1. Glass ceramic substrate for semiconductor packaging 11. Semiconductor package 12. Core substrate 13. Semiconductor element 14. Interposer H-hole

Claims

1. A glass ceramic substrate for semiconductor packaging having a crystalline phase and a glass phase, characterized in that when the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], the relationship 2 ≤ α1 / α2 ≤ 8 holds.

2. The glass ceramic substrate for semiconductor packaging according to claim 1, wherein the content of the crystalline phase is 2 to 50% by weight and the content of the glass phase is 50 to 98% by weight.

3. The glass ceramic substrate for semiconductor packaging according to claim 2, wherein the thermal expansion coefficient α1 of the crystalline phase is 6 to 20 ppm / K, and the thermal expansion coefficient α2 of the glass phase is 0.6 to 5 ppm / K.

4. The glass ceramic substrate for semiconductor packaging according to any one of claims 1 to 3, wherein the coefficient of thermal expansion over the entire glass ceramic substrate for semiconductor packaging is 2.5 to 15 ppm / K.

5. A glass ceramic substrate for semiconductor packaging according to any one of claims 1 to 3, having a pore-forming region in which a plurality of pores with a diameter of 100 μm or less are densely arranged, wherein the pores are arranged in a number of 1 to 4,000 per 10 mm square within the pore-forming region, and the thickness is 0.1 to 1.0 mm.

6. A glass-ceramic substrate for semiconductor packaging according to any one of claims 1 to 3, which is for use in an interposer.

7. A glass-ceramic substrate for semiconductor packaging according to any one of claims 1 to 3, which is for use as a core substrate.

8. A glass-ceramic substrate for a semiconductor package according to any one of claims 1 to 3, which is for use as a substrate for an image sensor.

9. Fracture toughness K ＩＣ However, 1.0 to 2.5 MPa·m １／２ A glass-ceramic substrate for semiconductor packaging according to any one of claims 1 to 3.

10. A glass-ceramic substrate for semiconductor packaging according to any one of claims 1 to 3, wherein the Young's modulus is 40 to 90 GPa.

11. A glass-ceramic substrate for semiconductor packaging according to any one of claims 1 to 3, comprising a layer containing an interlayer insulating material on the substrate.

12. Preparation steps for preparing a glass ceramic substrate having a crystalline phase and a glass phase, wherein the thermal expansion coefficient of the crystalline phase is α1 [ppm / K] and the thermal expansion coefficient of the glass phase is α2 [ppm / K], and the relationship 2 ≤ α1 / α2 ≤ 8 holds; and applying CO to the glass ceramic substrate. ２ A method for manufacturing a glass ceramic substrate for semiconductor packaging, characterized by comprising a hole-drilling process that involves irradiating with a laser to form holes.

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