Multilayer ceramic capacitor

Abstract

The present disclosure relates to a multilayer ceramic capacitor (100) which comprises a multilayer body (110) and external electrodes (120, 130). The multilayer body (110) has: an inner layer part (C) in which a plurality of internal ceramic layers (140) and a plurality of internal electrode layers (150) are alternately stacked; an external ceramic layer (X); and a side surface ceramic part (S). The plurality of internal ceramic layers (140), the external ceramic layer (X), and the side surface ceramic part (S) each contain a plurality of grains that are mainly composed of a perovskite compound containing Ba and at least one of Ti and Zr. The inner layer part (C) has a central region (C1), an external ceramic layer vicinity region (C2), and a side surface ceramic part vicinity region (C3). In a particle size distribution of area-equivalent circular diameters of the plurality of grains, D50 of the grains that are contained in the central region (C1), the external ceramic layer vicinity region (C2), and the side surface ceramic part vicinity region (C3) is each 80 nm to 140 nm inclusive, and D99 / D50 is each 1.4 to 2.2 inclusive.

Description

Multilayer ceramic capacitor

[0001] This disclosure relates to multilayer ceramic capacitors.

[0002] With the increasing sophistication of electronic devices, there is a growing demand for higher capacitance in multilayer ceramic capacitors used in these devices. Patent Document 1 discloses a multilayer ceramic capacitor in which reliability and capacitance per unit volume are improved by controlling the number of dielectric crystal grains in the dielectric layer.

[0003] Japanese Patent Publication No. 2023-106279

[0004] The multilayer ceramic capacitor described in Patent Document 1 has a wide particle size distribution of dielectric crystal grains (grains) contained in the dielectric layer, and there is variation in particle size, so there was room for improvement in DC bias characteristics.

[0005] The purpose of this disclosure is to provide a multilayer ceramic capacitor with improved DC bias characteristics.

[0006] The multilayer ceramic capacitor of this disclosure includes a laminate and an external electrode. The laminate has an inner layer portion in which a plurality of internal ceramic layers and a plurality of internal electrode layers are alternately laminated, an external ceramic layer arranged on both sides of the lamination direction of the inner layer portion, and a side ceramic portion arranged on both sides of the width direction perpendicular to the lamination direction of the inner layer portion and the external ceramic layer. The plurality of internal ceramic layers, the external ceramic layer, and the side ceramic portion each contain a plurality of grains mainly composed of a perovskite-type compound containing Ba and at least one of Ti and Zr. The inner layer portion is a cross-section of the laminate, and in a cross-section parallel to the lamination direction and the width direction, it has a central region, a region near the external ceramic layer, and a region near the side ceramic portion. In the particle size distribution of the area circle equivalent diameter of the plurality of grains, when the particle size at which cumulative 50% is based on area is defined as D50 and the particle size at which cumulative 99% is based on area is defined as D99, the D50 of the grains included in the central region, the region near the external ceramic layer, and the region near the side ceramic portion is each between 80 nm and 140 nm. The D99 / D50 values ​​of the grains in the central region, the region near the outer ceramic layer, and the region near the side ceramic portion are, respectively, between 1.4 and 2.2.

[0007] According to this disclosure, it is possible to provide a multilayer ceramic capacitor with improved DC bias characteristics.

[0008] This is a perspective view showing the appearance of a multilayer ceramic capacitor according to an embodiment. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line II-II. This is a cross-sectional view of the multilayer ceramic capacitor shown in Figure 1 along the line III-III. This is a schematic cross-sectional view showing the central region of the multilayer ceramic capacitor according to Embodiment 1. This is a schematic cross-sectional view showing the region near the outer ceramic layer of the multilayer ceramic capacitor according to Embodiment 1. This is a schematic cross-sectional view showing the region near the side ceramic portion of the multilayer ceramic capacitor according to Embodiment 1.

[0009] The multilayer ceramic capacitor according to the embodiment will be described below with reference to the figures. [Multilayer Ceramic Capacitor] Figure 1 is a perspective view showing the external appearance of the multilayer ceramic capacitor according to the embodiment. Figure 2 is a cross-sectional view of the multilayer ceramic capacitor of Figure 1 along the line II-II. Figure 3 is a cross-sectional view of the multilayer ceramic capacitor of Figure 1 along the line III-III.

[0010] As shown in Figures 1 to 3, the multilayer ceramic capacitor 100 according to this embodiment comprises a laminate 110 and external electrodes. The multilayer ceramic capacitor 100 includes a first external electrode 120 and a second external electrode 130 as external electrodes.

[0011] The laminate 110 has a first main surface 111 and a second main surface 112 facing the stacking direction T, a first side surface 113 and a second side surface 114 facing the width direction W perpendicular to the stacking direction T, and a first end surface 115 and a second end surface 116 facing the length direction L perpendicular to the stacking direction T and the width direction W.

[0012] As shown in Figures 2 and 3, the laminate 110 has an inner layer C in which a plurality of inner ceramic layers 140 and a plurality of inner electrode layers 150 are alternately stacked, outer ceramic layers X arranged on both sides of the stacking direction T of the inner layer C, and side ceramic parts S arranged on both sides of the width direction W perpendicular to the stacking direction T of the inner layer C and the outer ceramic layers X. The laminate 110 may further have end face ceramic parts E arranged on both sides of the length direction L of the inner layer C. The laminate 110 can be divided into the inner layer C, two outer ceramic layers X, two side ceramic parts S, and two end face ceramic parts E.

[0013] The inner layer C consists of multiple internal ceramic layers 140 and multiple internal electrode layers 150 stacked alternately. The outer ceramic layer X consists of one or more dielectric layers stacked. The side ceramic portion S consists of one or more dielectric layers stacked.

[0014] The multiple internal ceramic layers 140, the external ceramic layer X, and the side ceramic portion S each contain multiple grains whose main component is a perovskite-type compound containing barium (Ba) and at least one of titanium (Ti) and zirconium (Zr). In this specification, the main component is the component with the largest mass content among the constituent components, and may be, for example, 90% or more by mass, 95% or more by mass, or 99% or more by mass based on the total mass of all constituent components. A grain is a particle surrounded by a grain boundary, and is also called a crystal grain.

[0015] A perovskite-type compound containing Ba and at least one of Ti and Zr has the general formula ABO ３ It can be a perovskite-type compound represented as (A is the A-site component, B is the B-site component, and O is an oxygen atom). ABO ３ Examples of perovskite-type compounds represented by this formula include barium titanate (BaTiO2). ３ ) type perovskite compounds and barium zirconate (BaZrO ３ Examples include perovskite-type compounds of the ) system. ３ Examples of perovskite-type compounds in this system include BaTiO ３ , and BaTiO３ Ba of ２＋ and Ti ４＋ at least one of which is a perovskite-type compound or the like substituted with other ions such as Ca ２＋ and Zr ４＋ etc. The perovskite-type compound such as BaZrO ３ series perovskite-type compounds include, for example, BaZrO ３ , and BaZrO ３ Ba of ２＋ and Zr ４＋ at least one of which is a perovskite-type compound or the like substituted with other ions such as Ca ２＋ and Zr ４＋ etc.

[0016] The molar ratio (A / B) of the A-site component to the B-site component of the perovskite-type compound represented by ABO ３ is preferably 1.004 or more and 1.010 or less. When A / B is within the above range, grain growth during firing can be suppressed, and the generation of coarse particles can be suppressed.

[0017] The particle sizes of a plurality of grains can be measured using a scanning electron microscope (SEM). In this specification, the particle size of one grain refers to the diameter of a circle (hereinafter also referred to as the equivalent area circle diameter) having an area equal to the cross-sectional area of the grain in the SEM observation image of the cross-section parallel to the stacking direction T and the width direction W of the inner layer part C. In this specification, in the particle size distribution of the equivalent area circle diameters of a plurality of grains measured from the SEM observation image of the cross-section parallel to the stacking direction T and the width direction W of the inner layer part C, the particle size at which the cumulative value reaches 50% on an area basis is D50, and the particle size at which the cumulative value reaches 99% on an area basis is D99. The SEM observation image of the above cross-section of the inner layer part C may be, for example, an observation image at 40,000 times magnification by SEM. The cumulative particle size distribution of the particle sizes of a plurality of grains is obtained from the particle sizes of 200 or more grains. Note that it is not necessary for one SEM observation image to contain 200 or more grains, and it is sufficient if the total number of grains included in a plurality of SEM observation images is 200 or more.

[0018] The inner layer C is a cross-section of the laminate 110, and in a cross-section parallel to the lamination direction T and the width direction W, it has a central region C1, a region near the outer ceramic layer C2, and a region near the side ceramic part C3. The central region C1, the region near the outer ceramic layer C2, and the region near the side ceramic part C3 will be described with reference to Figure 3. The central region C1 is a region located near the center in the lamination direction T and the width direction W in a cross-section parallel to the lamination direction T and the width direction W. The central region C1 may be, for example, a region within a 3.0 μm × 3.0 μm square centered on the intersection of a center line that bisects the inner layer C in the lamination direction T and a center line that bisects the inner layer C in the width direction W. The region near the outer ceramic layer C2 is a region located in the center in the width direction W of the inner ceramic layer 140 that is closest to the outer ceramic layer X and the inner ceramic layer 140 that is second closest to the outer ceramic layer X. The central part in the width direction W may be, for example, within a region of 1.5 μm on both sides (total width 3.0 μm) from the center line that bisects the inner layer C in the width direction W. The region C3 near the side ceramic part is a region 3.0 μm inward from the widthwise end of the internal electrode layer 150 (i.e., the boundary between the inner layer C and the side ceramic part S), and is located in the central part in the stacking direction T. The central part in the stacking direction T may be, for example, within a region of 1.5 μm on both sides (total thickness 3.0 μm) from the center line that bisects the inner layer C in the stacking direction T. Although only the region C2 near the outer ceramic layer on the first main surface 111 side is shown in Figure 3, a region C2 near the outer ceramic layer also exists on the second main surface 112 side. The grain size of the grains contained in the region C2 near the outer ceramic layer may be measured from either of the two regions C2 near the outer ceramic layer. Furthermore, although Figure 3 only shows the region C3 near the side ceramic portion on the second side surface 114 side, a region C3 near the side ceramic portion also exists on the first side surface 113 side. The grain size of the grains contained in the region C3 near the side ceramic portion may be measured from either of the two regions C3 near the side ceramic portion.

[0019] In the inner layer portion C, since the sintering behavior in the firing process is different between the central region C1, the vicinity region C2 of the outer ceramic layer, and the vicinity region C3 of the side ceramic portion, the grain sizes of the grains contained in each region may be different. Specifically, the grain size of the grains contained in the vicinity region C2 of the outer ceramic layer or the vicinity region C3 of the side ceramic portion tends to be larger than the grain size of the grains contained in the central region C1. If the grain sizes are different depending on the region of the inner layer portion C, the grain size distribution of the grains contained in the inner layer portion C becomes wider, and it becomes difficult to improve the DC bias characteristics.

[0020] The D50 of the grains contained in the central region C1, the vicinity region C2 of the outer ceramic layer, and the vicinity region C3 of the side ceramic portion is respectively 80 nm or more and 140 nm or less, preferably 90 nm or more and 135 nm or less, and more preferably 100 nm or more and 130 nm or less.

[0021] The D99 / D50 of the grains contained in the central region C1, the vicinity region C2 of the outer ceramic layer, and the vicinity region C3 of the side ceramic portion is respectively 1.4 or more and 2.2 or less, preferably 2.1 or less, and more preferably 2.0 or less.

[0022] The difference between the D50 of the grains contained in the central region C1 and the D50 of the grains contained in the vicinity region C2 of the outer ceramic layer may be 60 nm or less, preferably 30 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less.

[0023] The difference between the D50 of the grains contained in the central region C1 and the D50 of the grains contained in the vicinity region C3 of the side ceramic portion may be 60 nm or less, preferably 30 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less.

[0024] The difference between the D50 of the grains contained in the vicinity region C2 of the outer ceramic layer and the D50 of the grains contained in the vicinity region C3 of the side ceramic portion may be 60 nm or less, preferably 30 nm or less, more preferably 20 nm or less, and still more preferably 10 nm or less.

[0025] The difference between D99 of the grains contained in the central region C1 and D99 of the grains contained in the vicinity region C2 of the external ceramic layer may be 60 nm or less, preferably 50 nm or less, more preferably 40 nm or less, and still more preferably 30 nm or less.

[0026] The difference between D99 of the grains contained in the central region C1 and D99 of the grains contained in the vicinity region C3 of the side ceramic part may be 90 nm or less, preferably 80 nm or less, more preferably 70 nm or less, and still more preferably 60 nm or less.

[0027] The difference between D99 of the grains contained in the vicinity region C2 of the external ceramic layer and D99 of the grains contained in the vicinity region C3 of the side ceramic part may be 50 nm or less, preferably 40 nm or less, more preferably 30 nm or less, and still more preferably 20 nm or less.

[0028] By having D50, D99 and D99 / D50 of the grains contained in the inner layer part C within the above ranges, a multilayer ceramic capacitor with improved DC bias characteristics can be obtained.

[0029] The grain size and grain size distribution of the grains can be within the above ranges, for example, by selecting the grain size and composition of the starting material (for example, BaTiO ３ powder) for manufacturing the internal ceramic layer 140, and adjusting the firing temperature, heating rate, etc. in the firing process of the manufacturing method of the multilayer ceramic capacitor described later.

[0030] The internal ceramic layer 140, the external ceramic layer X and the side ceramic part S can further contain a rare earth element (Re). When the internal ceramic layer 140, the external ceramic layer X and the side ceramic part S further contain a rare earth element, a part of the A-site component of the perovskite-type compound may be substituted by Re.

[0031] Rare earth elements may include at least one selected from the group consisting of scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu).

[0032] The internal ceramic layer 140, the external ceramic layer X, and the side ceramic portion S preferably further contain Dy. The content of Dy in the internal ceramic layer 140 is the amount of BaTiO in the internal ceramic layer 140. ３ The content of Dy in the outer ceramic layer X is preferably 1.5 mol% or more and 1.7 mol% or less per 100 mol%. ３ The content of Dy in the side ceramic portion S is preferably 1.5 mol% to 1.7 mol% relative to 100 mol%. ３ The amount is preferably 1.5 mol% or more and 1.7 mol% or less, relative to 100 mol%.

[0033] The internal ceramic layer 140, the external ceramic layer X, and the side ceramic portion S may further contain at least one element selected from the group consisting of silicon (Si), aluminum (Al), magnesium (Mg), manganese (Mn), nickel (Ni), iron (Fe), copper (Cu), and vanadium (V). By including these elements, the density of the grain can be controlled during the firing process. However, Mg segregates at the edges of the internal electrode layer and forms an oxide layer, which can lead to a decrease in insulation resistance and dielectric breakdown voltage, and may reduce reliability. Therefore, it is preferable not to use Mg when preparing the ceramic slurry described later. The Mg content in the internal ceramic layer 140, the external ceramic layer X, and the side ceramic portion S is preferably 0.05 mol% or less, relative to the total amount of Ti and Zr in the perovskite-type compound (100 mol%).

[0034] The internal ceramic layer 140, the external ceramic layer X, and the side ceramic portion S further preferably contain Si, Al, and Mn as other elements.

[0035] The Si content in the internal ceramic layer 140 is the BaTiO content in the internal ceramic layer 140. ３ The content of Al in the internal ceramic layer 140 is preferably 1.0 mol% or more and 1.4 mol% or less per 100 mol%. ３ The content of Mn in the internal ceramic layer 140 is preferably 0.06 mol% or more and 0.1 mol% or less per 100 mol%. ３ The amount is preferably 0.1 mol% or more and 0.2 mol% or less, relative to 100 mol%.

[0036] The Si content in the outer ceramic layer X is the BaTiO content in the outer ceramic layer X. ３ The content of Al in the outer ceramic layer X is preferably 1.0 mol% to 2.6 mol% relative to 100 mol%. ３ The content of Mn in the outer ceramic layer X is preferably 0.08 mol% or more and 0.27 mol% or less, relative to 100 mol%. ３ The content is preferably 0.2 mol% to 1.0 mol% relative to 100 mol%. Furthermore, the relationship between the Si, Al, and Mn content in the outer ceramic layer X is preferably Si > Mn > Al.

[0037] The Si content in the side ceramic part S is the BaTiO content in the side ceramic part S. ３ The content of Al in the side ceramic portion S is preferably 1.0 mol% to 2.6 mol% relative to 100 mol%. ３ The content of Mn in the side ceramic portion S is preferably 0.08 mol% or more and 0.27 mol% or less per 100 mol%. ３The content is preferably 0.2 mol% to 1.0 mol% relative to 100 mol%. Furthermore, the relationship between the content of Si, Al, and Mn in the side ceramic portion S is preferably Si > Mn > Al.

[0038] When the outer ceramic layer X further contains Si, Al, and Mn, it is preferable that the Si content in the outer ceramic layer X is higher than the Si content in the inner ceramic layer 140, the Al content in the outer ceramic layer X is higher than the Al content in the inner ceramic layer 140, and the Mn content in the outer ceramic layer X is higher than the Mn content in the inner ceramic layer 140.

[0039] When the side ceramic portion S further contains Si, Al, and Mn, it is preferable that the Si content in the side ceramic portion S is higher than the Si content in the internal ceramic layer 140, the Al content in the side ceramic portion S is higher than the Al content in the internal ceramic layer 140, and the Mn content in the side ceramic portion S is higher than the Mn content in the internal ceramic layer 140.

[0040] Because the Si content in the outer ceramic layer X is higher than the Si content in the inner ceramic layer 140, the Al content in the outer ceramic layer X is higher than the Al content in the inner ceramic layer 140, and the Mn content in the outer ceramic layer X is higher than the Mn content in the inner ceramic layer 140, the difference in density of grains contained in the inner ceramic layer 140 and the outer ceramic layer X can be suppressed. As a result, the difference in density of grains contained in the central region C1 and the region C2 near the outer ceramic layer in the inner layer C tends to be suppressed.

[0041] Because the Si content in the side ceramic portion S is higher than the Si content in the internal ceramic layer 140, the Al content in the side ceramic portion S is higher than the Al content in the internal ceramic layer 140, and the Mn content in the side ceramic portion S is higher than the Mn content in the internal ceramic layer 140, the difference in density of the grains contained in the internal ceramic layer 140 and the side ceramic portion S can be suppressed. As a result, the difference in density of the grains contained in the central region C1 and the region C3 near the side ceramic portion in the inner layer C tends to be suppressed.

[0042] The content of rare earth elements and other elements in the internal ceramic layer 140, the external ceramic layer X, and the side ceramic portion S can be determined, for example, from the mixing ratio of the starting materials. Furthermore, the content of rare earth elements and other elements in the internal ceramic layer 140, the external ceramic layer X, and the side ceramic portion S can be quantified, for example, by X-ray fluorescence analysis (XRF), inductively coupled plasma emission spectroscopy (ICP-AES), or energy-dispersive X-ray spectroscopy (EDX). When quantifying the content of rare earth elements and other elements by EDX, for example, it can be measured using an observation image at a magnification of 150,000x using a scanning transmission electron microscope (STEM / EDX).

[0043] The multiple internal ceramic layers 140 may each have a thickness of 0.1 μm or more and 1.0 μm or less, preferably 0.3 μm or more and 0.6 μm or less. The thickness of the internal ceramic layers 140 is measured in an SEM observation image of the cross-section of the laminate 110 in the lamination direction T.

[0044] The thickness of the outer ceramic layer X in the lamination direction T may be 10 μm or more and 100 μm or less, and preferably 12 μm or more and 45 μm or less, taking into account the influence on sinterability such as the amount of heat applied during firing and the amount of particle diffusion.

[0045] The thickness of the side ceramic portion S in the width direction W may be 5 μm to 100 μm, and preferably 8 μm to 25 μm, taking into account the influence on sinterability such as the amount of heat applied during firing and the amount of particle diffusion.

[0046] The thickness of the end face ceramic portion E in the longitudinal direction L may be 5 μm to 100 μm, and preferably 15 μm to 50 μm, taking into account the influence on sinterability such as the amount of heat applied and the amount of diffusion during firing.

[0047] The multiple internal electrode layers 150 include a first internal electrode layer 151 and a second internal electrode layer 152. The first internal electrode layer 151 includes a counter electrode portion that faces the second internal electrode layer 152 via an internal ceramic layer 140, and a lead-out electrode portion that extends from the counter electrode portion to the first end face 115 of the laminate 110. The second internal electrode layer 152 includes a counter electrode portion that faces the first internal electrode layer 151 via an internal ceramic layer 140, and a lead-out electrode portion that extends from the counter electrode portion to the second end face 116 of the laminate 110. The multiple internal electrode layers 150 in the inner layer C include a plurality of pairs of electrode layers consisting of the first internal electrode layer 151 and the second internal electrode layer 152. The total number of the multiple internal electrode layers 150 in the inner layer C may be 100 or more and 1000 or less. The total number of the multiple internal ceramic layers 140 in the inner layer C may be 100 or more and 1000 or less.

[0048] A capacitor is formed when the first internal electrode layer 151 and the second internal electrode layer 152 face each other via the internal ceramic layer 140. The multilayer ceramic capacitor 100 can be described as having multiple capacitors connected in parallel via the first external electrode 120 and the second external electrode 130, which will be described later.

[0049] The thickness of each of the multiple internal electrode layers 150 may be, for example, 0.1 μm or more and 0.5 μm or less, preferably 0.2 μm or more and 0.5 μm or less. The thickness of the internal electrode layers 150 is measured in an SEM observation image of the cross-section of the laminate 110 in the stacking direction T.

[0050] The material constituting the internal electrode layer 150 may be at least one metal selected from the group consisting of Ni, Cu, silver (Ag), gold (Au), and palladium (Pd), or an alloy containing such metal. The internal electrode layer 150 may contain Ni as its main component. The internal electrode layer 150 may further contain tin (Sn).

[0051] The internal electrode layer 150 may further contain dielectric particles referred to as the co-material. The co-material may be the same as or different from the dielectric particles contained in the internal ceramic layer 140. The co-material may further contain Mg.

[0052] The multilayer ceramic capacitor 100 further comprises a first external electrode 120 and a second external electrode 130. The first external electrode 120 is formed on the first end face 115 of the laminate 110 so as to be electrically connected to the first internal electrode layer 151. The first external electrode 120 extends from the first end face 115 to the first main surface 111 and the second main surface 112, and the first side surface 113 and the second side surface 114. The second external electrode 130 is formed on the second end face 116 of the laminate 110 so as to be electrically connected to the second internal electrode layer 152. The second external electrode 130 extends from the second end face 116 to the first main surface 111 and the second main surface 112, and the first side surface 113 and the second side surface 114.

[0053] The first external electrode 120 and the second external electrode 130 each have, for example, a base electrode layer and a plating layer disposed on the base electrode layer. The base electrode layer includes, for example, at least one selected from a sintered body layer, a conductive resin layer, and a metal thin film layer.

[0054] The sintered body layer is formed by baking a paste containing glass powder and metal powder, and includes a glass portion and a metal portion. The glass constituting the glass portion is B ２ O ３ -SiO ２ - Examples include BaO-based glass. The metal constituting the metal part may be at least one selected from Ni, Cu, and Ag, or an alloy containing such metal. Multiple sintered layers may be formed with different components. Furthermore, the sintered layers may be fired simultaneously with the laminate 110 in the manufacturing method described later, or they may be baked on after the laminate 110 has been fired.

[0055] The conductive resin layer comprises conductive particles, such as metal nanoparticles, and a resin portion. The metal constituting the metal nanoparticles may be at least one selected from Ni, Cu, and Ag, or an alloy containing such metal. The resin constituting the resin portion may be an epoxy-based thermosetting resin. The conductive resin layer may be formed from multiple layers of different components.

[0056] The metal thin film layer is a layer with a thickness of 1 μm or less, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal nanoparticles are deposited. The metal constituting the metal thin film layer may be at least one selected from Ni, Cu, Ag, and Au, or an alloy containing such metal. Multiple metal thin film layers may be formed with different components.

[0057] Examples of metals constituting the plating layer include at least one selected from Ni, Cu, Ag, Au, and Sn, or alloys containing such metals. The plating layer may be formed in multiple layers with different components.

[0058] The first external electrode 120 and the second external electrode 130 may each be a plating layer directly provided on the laminate 110 and directly connected to the corresponding internal electrode layer described above.

[0059] [Method for Manufacturing Multilayer Ceramic Capacitors] The multilayer ceramic capacitor 100 of this embodiment is manufactured, for example, as follows. First, a slurry for the internal ceramic layer 140, a slurry for the external ceramic layer X, and a slurry for the side ceramic portion S are prepared. Specifically, these are prepared by mixing a ceramic raw material powder containing a perovskite-type compound as a starting material and additives, a binder, a solvent, etc., in a predetermined mixing ratio.

[0060] The slurry for the internal ceramic layer is, for example, BaTiO ３The mixture may contain, per 100 mol%, Dy in an amount of 1.5 mol% to 1.7 mol%, Mn in an amount of 0.1 mol% to 0.2 mol%, Ni in an amount of 1.3 mol% to 1.7 mol%, Si in an amount of 1.0 mol% to 1.4 mol%, and Al in an amount of 0.06 mol% to 0.1 mol%. These elements can be blended using their respective oxides or carbonates. The molar ratio A / B (e.g., Ba / Ti) of the A-site component to the B-site component of the perovskite-type compound in the internal ceramic layer slurry can be 1.004 to 1.010.

[0061] The slurry for the outer ceramic layer and the slurry for the side ceramic part are, for example, BaTiO ３ The slurry may contain, per 100 mol%, Dy in an amount of 1.5 mol% to 1.7 mol%, Mn in an amount of 0.2 mol% to 1.0 mol%, Ni in an amount of 0.4 mol% to 0.6 mol%, Si in an amount of 1.0 mol% to 2.6 mol%, and Al in an amount of 0.08 mol% to 0.27 mol%. These elements can be blended using their respective oxides or carbonates. Preferably, the relationship between the Si, Al, and Mn content in the slurry for the outer ceramic layer and the slurry for the side ceramic part is Si > Mn > Al. The molar ratio A / B (e.g., Ba / Ti) of the A-site component to the B-site component of the perovskite-type compound in the slurry for the outer ceramic layer and the slurry for the side ceramic part can be 1.004 to 1.010. The slurry for the outer ceramic layer and the slurry for the side ceramic part may have the same composition or different compositions.

[0062] The composition of each ceramic slurry can be appropriately adjusted according to the size of the multilayer ceramic capacitor to be manufactured, as long as it remains within the above composition range.

[0063] Next, the slurry for the internal ceramic layer, the slurry for the external ceramic layer, and the slurry for the side ceramic portion are formed into sheets on a carrier film using a die coater, gravure coater, or microgravure coater, thereby forming the green sheet for the internal ceramic layer, the green sheet for the external ceramic layer, and the green sheet for the side ceramic portion.

[0064] Next, a conductive paste mainly composed of Ni is printed onto a green sheet for the internal ceramic layer using a screen printing method or gravure printing method, etc., to form a conductive pattern that will become the internal electrode.

[0065] Next, a predetermined number of green sheets for the outer ceramic layer are stacked, and then a plurality of green sheets for the inner ceramic layer, each with a conductive pattern formed on top, are stacked sequentially on top of that, and then a predetermined number of green sheets for the outer ceramic layer are stacked on top of that. After that, the mother laminate is formed by pressing and bonding along the stacking direction using a hydrostatic press or a rigid press.

[0066] Next, the mother laminate is divided into a matrix by pressing, dicing, or laser cutting, and separated into multiple laminate chips. The laminate chips may be barrel polished.

[0067] Next, the green sheet for the side ceramic portion is attached to both sides of the laminate chip where the internal electrode layers are exposed, located on both sides in the width direction. In this way, the pre-firing laminate is formed. The green sheet for the side ceramic portion may be a single layer or multiple layers.

[0068] Next, the pre-firing laminate is degreased under predetermined conditions and then heated to a predetermined temperature at a predetermined heating rate to form a laminate. The firing temperature is set appropriately according to the type of starting material and the size of the multilayer ceramic capacitor to be manufactured, but is preferably 1100°C to 1300°C. The heating rate is set appropriately according to the type of starting material and the size of the multilayer ceramic capacitor to be manufactured, but is preferably 15°C / min or higher. When the firing temperature and heating rate are within the above range, a multilayer ceramic capacitor is obtained in which the D50 of the grains included in the central region C1, the region near the outer ceramic layer C2, and the region near the side ceramic part C3 is 80 nm to 140 nm, and the D99 / D50 of the grains included in the central region C1, the region near the outer ceramic layer C2, and the region near the side ceramic part C3 is 1.4 to 2.2, respectively. Heat treatment (annealing) may be performed after firing. The annealing temperature may be, for example, 900°C to 1100°C. The annealing temperature is preferably lower than the highest temperature during the firing process. Annealing is preferably carried out in a weakly reducing atmosphere.

[0069] Next, after a base electrode layer is formed on the surface of the laminate, a plating layer is formed by electroplating to cover the base electrode layer.

[0070] The multilayer ceramic capacitor 100 of this embodiment is manufactured by going through the above series of steps.

[0071] The dimensions of the multilayer ceramic capacitor 100 in this embodiment are not particularly limited, but for example, the dimension in the stacking direction T may be 0.08 mm or more and 0.8 mm or less, the dimension in the width direction W may be 0.08 mm or more and 0.8 mm or less, and the dimension in the length direction L may be 0.18 mm or more and 1.3 mm or less.

[0072] The multilayer ceramic capacitor 100 in this embodiment may be a two-terminal capacitor as shown in Figure 1. Alternatively, the multilayer ceramic capacitor 100 in this embodiment may be a three-terminal capacitor. While the two-terminal capacitor has a configuration in which the first internal electrode layer 151 is exposed on the first end face 115 and the second internal electrode layer 152 is exposed on the second end face 116, the three-terminal capacitor has a configuration in which the first internal electrode layer 151 is exposed on the first end face 115 and the second end face 116, the second internal electrode layer 152 is exposed on the first side surface 113 and the second side surface 114, and furthermore, a third external electrode and a fourth external electrode are provided on the side surface of the laminate 110.

[0073] The present invention will be described in more detail below with reference to examples, but the present invention is not limited thereto.

[0074] <Example 1> (Fabrication of green sheet for internal ceramic layer) BaTiO ３ By mixing this with oxides or carbonates of Dy, Mn, Ni, Si, and Al, a raw material powder for the internal ceramic layer was obtained. ３ The raw materials were blended so that, per 100 mol%, Dy was 1.5 mol% to 1.7 mol%, Mn was 0.1 mol% to 0.2 mol%, Ni was 1.3 mol% to 1.7 mol%, Si was 1.0 mol% to 1.4 mol%, and Al was 0.06 mol% to 0.1 mol%. The molar ratio (A / B) of the A-site component to the B-site component of the obtained raw material powder for the internal ceramic layer was in the range of 1.004 to 1.010. A green sheet for the internal ceramic layer was prepared using the raw material powder for the internal ceramic layer.

[0075] (Fabrication of green sheet for external ceramic layer) BaTiO ３ By mixing this with oxides or carbonates of Dy, Mn, Ni, Si, and Al, a raw material powder for the outer ceramic layer was obtained. ３The raw materials were blended such that, per 100 mol%, Dy was at 1.5 mol% to 1.7 mol%, Mn was at 0.2 mol% to 1.0 mol%, Ni was at 0.4 mol% to 0.6 mol%, Si was at 1.0 mol% to 2.6 mol%, and Al was at 0.08 mol% to 0.27 mol%, with the relationship between the Si, Al, and Mn content being Si > Mn > Al. Furthermore, the Si content in the raw materials powder for the outer ceramic layer was higher than the Si content in the raw materials powder for the inner ceramic layer, the Al content in the raw materials powder for the outer ceramic layer was higher than the Al content in the raw materials powder for the inner ceramic layer, and the Mn content in the raw materials powder for the outer ceramic layer was higher than the Mn content in the raw materials powder for the inner ceramic layer. The molar ratio (A / B) of the A-site component to the B-site component of the obtained raw materials powder for the outer ceramic layer was in the range of 1.004 to 1.010. A green sheet for the outer ceramic layer was fabricated using raw material powder for the outer ceramic layer.

[0076] (Preparation of green sheet for side ceramic section) A green sheet for the side ceramic section was prepared using the same raw material powder for the internal ceramic layer as the raw material powder for the external ceramic layer described above.

[0077] (Manufacturing of Multilayer Ceramic Capacitors) An internal electrode pattern was formed by printing a conductive paste mainly composed of Ni for the internal electrodes onto a green sheet for the internal ceramic layer in a predetermined pattern. Next, a predetermined number of green sheets for the external ceramic layer were stacked, and 300 green sheets for the internal ceramic layer with the internal electrode pattern printed on them were stacked on top of that, and then a predetermined number of green sheets for the external ceramic layer were stacked on top of that. After that, a stacked block was made by pressing in the stacking direction using an isostatic press. The stacked block was cut to a predetermined size, and a stacked chip was cut out. Green sheets for the side ceramic parts were attached to both sides of the stacked chip. At this time, the corners and edges of the stacked chip were rounded by barrel polishing. The stacked chip was sintered to make a stacked body. The sintering temperature was 1200°C, and the heating rate from the start of sintering to reaching the sintering temperature was 15°C / min. A conductive paste mainly composed of Cu for the external electrodes was applied to both ends of the stacked chip and baked to form the baked layer of the external electrodes. A multilayer ceramic capacitor was obtained by applying Ni plating and Sn plating to the surface of the baked layer. The dimensions of the multilayer ceramic capacitor were 0.6 mm in the stacking direction, 0.3 mm in the width direction, and 0.3 mm in the length direction. The thickness of the outer ceramic layer was 18 μm, the thickness of the inner ceramic layer was 0.5 μm, the thickness of the side ceramic portion was 15 μm, and the thickness of the inner electrode layer was 0.37 μm.

[0078] <Examples 2-4> In the same manner as in Example 1, multilayer ceramic capacitors with dimensions of 1.0 mm in the stacking direction, 0.5 mm in the width direction, and 0.5 mm in the length direction were fabricated. The thickness of the outer ceramic layer was 30 μm, the thickness of the inner ceramic layer was 0.51 μm, the thickness of the side ceramic portion was 20 μm, and the thickness of the inner electrode layer was 0.5 μm.

[0079] <Comparative Examples 1-2> Multilayer ceramic capacitors were manufactured in the same manner as in Example 1, except that the composition of at least one of the raw material powders for the outer ceramic layer and the raw material powder for the side ceramic portion was adjusted to be outside the range of the composition described in Example 1. The dimensions of the multilayer ceramic capacitor were 1.0 mm in the stacking direction, 0.5 mm in the width direction, and 0.5 mm in the length direction. The thickness of the outer ceramic layer was 30 μm, the thickness of the inner ceramic layer was 0.51 μm, the thickness of the side ceramic portion was 20 μm, and the thickness of the inner electrode layer was 0.5 μm.

[0080] [Grain Diameter Measurement] The grain diameter of the fabricated multilayer ceramic capacitor was measured according to the following procedure. The cross-section of the multilayer ceramic capacitor was exposed so that the cross-section parallel to the stacking direction and width direction was exposed, and the cross-section was polished up to half its length. SEM observation was performed on the polished cross-section. Observation was performed on the central region, the region near the outer ceramic layer, and the region near the side ceramic part, and SEM observation images were obtained for each region. D50, D99, and D99 / D50 of the grains contained in each region were calculated by image analysis. The results are shown in Table 1.

[0081] [Evaluation of DC Bias Characteristics] The DC bias characteristics of the fabricated multilayer ceramic capacitor were evaluated by measuring the capacitance change rate from the no-load capacitance C0 and the capacitance C6 when a DC voltage of 6V / μm is applied, according to the following formula (1). A capacitance change rate below -40% was judged as NG. Capacitance change rate = (C6 - C0) / C0 × 100 (1)

[0082]

[0083] Figures 4 to 6 are schematic cross-sectional views of the central region, the region near the outer ceramic layer, and the region near the side ceramic portion of the multilayer ceramic capacitor of Example 1. As shown above, the grain size of the multilayer ceramic capacitor of this example was uniform throughout the entire inner layer. In addition to preparing the ceramic slurry so that the Si content in the outer ceramic layer and side ceramic portion was higher than the Si content in the inner ceramic layer, the Al content in the outer ceramic layer and side ceramic portion was higher than the Al content in the inner ceramic layer, and the Mn content in the outer ceramic layer and side ceramic portion was higher than the Mn content in the inner ceramic layer, the difference in grain density between the inner ceramic layer and the outer ceramic layer and side ceramic portion was suppressed by setting appropriate firing temperature and heating rate in the firing process.

[0084] As shown in Table 1, the multilayer ceramic capacitor of this disclosure can exhibit improved DC bias characteristics. This disclosure demonstrates that it is possible to provide a multilayer ceramic capacitor with improved DC bias characteristics.

[0085] In the description of the embodiments described above, the combinable configurations may be combined with each other.

[0086] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than by the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended.

[0087] The above-described exemplary embodiments will be understood by those skilled in the art to be specific examples of the following embodiments: (1) A multilayer ceramic capacitor comprising a laminate and an external electrode, wherein the laminate has an inner layer portion in which a plurality of internal ceramic layers and a plurality of internal electrode layers are alternately laminated, an external ceramic layer disposed on both sides in the lamination direction of the inner layer portion, and a side ceramic portion disposed on both sides in the width direction perpendicular to the lamination direction of the inner layer portion and the external ceramic layer, the plurality of internal ceramic layers, the external ceramic layer and the side ceramic portion each comprises a plurality of grains mainly composed of a perovskite-type compound containing Ba and at least one of Ti and Zr, the inner layer portion has a cross-section of the laminate, in a cross-section parallel to the lamination direction and the width direction, a central region, a region near the external ceramic layer and a region near the side ceramic portion (Item 2) A multilayer ceramic capacitor wherein, in the particle size distribution of the area circle equivalent diameter of the plurality of grains, when the particle size at which cumulative 50% is based on area is defined as D50 and the particle size at which cumulative 99% is based on area is defined as D99, the D50 of the grains included in the central region, the region near the outer ceramic layer, and the region near the side ceramic part is 80 nm or more and 140 nm or less, and the D99 / D50 of the grains included in the central region, the region near the outer ceramic layer, and the region near the side ceramic part is 1.4 or more and 2.2 or less. (Item 2) The multilayer ceramic capacitor according to Item 1, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the outer ceramic layer is 20 nm or less. (Item 3) The multilayer ceramic capacitor according to Item 1 or Item 2, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the side ceramic part is 20 nm or less. (Clause 4) A multilayer ceramic capacitor according to any one of Clauses 1 to 3, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the outer ceramic layer is 10 nm or less.(Clause 5) A multilayer ceramic capacitor according to any one of Clauses 1 to 4, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the side ceramic portion is 10 nm or less. (Clause 6) A multilayer ceramic capacitor according to any one of Clauses 1 to 5, wherein the internal ceramic layer, the external ceramic layer and the side ceramic portion further contain Dy. (Clause 7) A multilayer ceramic capacitor according to any one of Clauses 1 to 6, wherein the internal ceramic layer, the external ceramic layer and the side ceramic portion further contain Si, Al and Mn. (Clause 8) The multilayer ceramic capacitor according to any one of Clauses 1 to 7, wherein the Si content in the outer ceramic layer and the side ceramic portion is higher than the Si content in the inner ceramic layer, the Al content in the outer ceramic layer and the side ceramic portion is higher than the Al content in the inner ceramic layer, and the Mn content in the outer ceramic layer and the side ceramic portion is higher than the Mn content in the inner ceramic layer. (Clause 9) The multilayer ceramic capacitor according to any one of Clauses 1 to 8, wherein the Mg content in the inner ceramic layer, the outer ceramic layer and the side ceramic portion is 0.05 mol% or less with respect to 100 mol% of the total amount of Ti and Zr in the perovskite compound. (Clause 10) The multilayer ceramic capacitor according to any one of Clauses 1 to 9, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the outer ceramic layer is 40 nm or less. (Clause 11) A multilayer ceramic capacitor according to any one of Clauses 1 to 10, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the outer ceramic layer is 30 nm or less. (Clause 12) A multilayer ceramic capacitor according to any one of Clauses 1 to 11, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the side ceramic portion is 70 nm or less.(Clause 13) A multilayer ceramic capacitor according to any one of Clauses 1 to 12, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the side ceramic portion is 60 nm or less. (Clause 14) A multilayer ceramic capacitor according to any one of Clauses 1 to 13, wherein the thickness of each of the plurality of internal ceramic layers is 0.3 μm or more and 0.6 μm or less. (Clause 15) A multilayer ceramic capacitor according to any one of Clauses 1 to 14, wherein the thickness of each of the plurality of internal electrode layers is 0.2 μm or more and 0.5 μm or less, the thickness of the external ceramic layer is 12 μm or more and 45 μm or less, the thickness of the side ceramic portion is 8 μm or more and 25 μm or less, and the thickness of the end face ceramic portion is 15 μm or more and 50 μm or less.

[0088] 100 Multilayer ceramic capacitor, 110 Laminate, 111 First main surface, 112 Second main surface, 113 First side surface, 114 Second side surface, 115 First end surface, 116 Second end surface, 120 First external electrode, 130 Second external electrode, 140 Internal ceramic layer, 150 Internal electrode layer, 151 First internal electrode layer, 152 Second internal electrode layer, C Inner layer portion, C1 Central region, C2 Region near external ceramic layer, C3 Region near side ceramic portion, E End surface ceramic portion, L Length direction, S Side ceramic portion, T Lamination direction, W Width direction, X External ceramic layer.

Claims

1. A multilayer ceramic capacitor comprising a laminate and external electrodes, wherein the laminate has an inner layer portion in which a plurality of internal ceramic layers and a plurality of internal electrode layers are alternately laminated, external ceramic layers arranged on both sides in the lamination direction of the inner layer portion, and side ceramic portions arranged on both sides in the width direction perpendicular to the lamination direction of the inner layer portion and the external ceramic layers, the plurality of internal ceramic layers, the external ceramic layers and the side ceramic portions each contain a plurality of grains mainly composed of a perovskite-type compound containing Ba and at least one of Ti and Zr, and the inner layer portion has a cross-section of the laminate, in a cross-section parallel to the lamination direction and the width direction, a central region, a region near the external ceramic layers and a region near the side ceramic portions, In the particle size distribution of the area circle equivalent diameter of the plurality of grains, when the particle size at which cumulative area accounts for 50% is defined as D50 and the particle size at which cumulative area accounts for 99% is defined as D99, the D50 of the grains included in the central region, the region near the outer ceramic layer, and the region near the side ceramic part is 80 nm or more and 140 nm or less, and the D99 / D50 of the grains included in the central region, the region near the outer ceramic layer, and the region near the side ceramic part is 1.4 or more and 2.2 or less, respectively, in a multilayer ceramic capacitor.

2. The multilayer ceramic capacitor according to claim 1, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the outer ceramic layer is 20 nm or less.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the side ceramic portion is 20 nm or less.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the outer ceramic layer is 10 nm or less.

5. The multilayer ceramic capacitor according to any one of claims 1 to 4, wherein the difference between the D50 of the grains included in the central region and the D50 of the grains included in the region near the side ceramic portion is 10 nm or less.

6. The multilayer ceramic capacitor according to any one of claims 1 to 5, wherein the internal ceramic layer, the external ceramic layer, and the side ceramic portion further include Dy.

7. The multilayer ceramic capacitor according to any one of claims 1 to 6, wherein the internal ceramic layer, the external ceramic layer, and the side ceramic portion further comprise Si, Al, and Mn.

8. The multilayer ceramic capacitor according to any one of claims 1 to 7, wherein the Si content in the outer ceramic layer and the side ceramic portion is higher than the Si content in the inner ceramic layer, the Al content in the outer ceramic layer and the side ceramic portion is higher than the Al content in the inner ceramic layer, and the Mn content in the outer ceramic layer and the side ceramic portion is higher than the Mn content in the inner ceramic layer.

9. The multilayer ceramic capacitor according to any one of claims 1 to 8, wherein the content of Mg in the internal ceramic layer, the external ceramic layer, and the side ceramic portion is 0.05 mol% or less with respect to 100 mol% of the total amount of Ti and Zr in the perovskite compound.

10. The multilayer ceramic capacitor according to any one of claims 1 to 9, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the outer ceramic layer is 40 nm or less.

11. The multilayer ceramic capacitor according to any one of claims 1 to 10, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the outer ceramic layer is 30 nm or less.

12. The multilayer ceramic capacitor according to any one of claims 1 to 11, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the side ceramic portion is 70 nm or less.

13. The multilayer ceramic capacitor according to any one of claims 1 to 12, wherein the difference between the D99 of the grains included in the central region and the D99 of the grains included in the region near the side ceramic portion is 60 nm or less.

14. The multilayer ceramic capacitor according to any one of claims 1 to 13, wherein each of the plurality of internal ceramic layers has a thickness of 0.3 μm or more and 0.6 μm or less.

15. The multilayer ceramic capacitor according to any one of claims 1 to 14, wherein each of the plurality of internal electrode layers has a thickness of 0.2 μm or more and 0.5 μm or less, the thickness of the external ceramic layer is 12 μm or more and 45 μm or less, the thickness of the side ceramic portion is 8 μm or more and 25 μm or less, and the thickness of the end ceramic portion is 15 μm or more and 50 μm or less.

Images