Epitaxial wafer and inspection method, capable of inspecting vertical element

Abstract

This epitaxial wafer includes: a substrate for epitaxial growth in which a seed crystal layer of a single crystal is bonded via an adhesive layer to a support substrate having a structure in which a ceramic core is wrapped with a sealing layer; and a nitride epitaxial film having a vertical device structure formed on the substrate for growth via a buffer layer. A plurality of vertical elements are formed on the epitaxial film, each vertical element is electrically bonded to the seed crystal layer or a current diffusion layer, and an electrode for inspection is further provided on a bottom surface of a recess in which the seed crystal layer or the current diffusion layer is exposed in a part of the epitaxial wafer. Probe inspection is performed between a front-side electrode of each vertical element, and the electrode for inspection.

Description

Epitaxial Wafer and Inspection Method Enabling Inspection of Vertical Elements

[0001] The present invention relates to an epitaxial wafer and an inspection method enabling inspection of vertical elements. More specifically, it relates to an epitaxial wafer and an inspection method enabling inspection of vertical elements such as electronic devices and optical devices formed on a QST (registered trademark of the United States) substrate obtained by bonding a seed crystal layer to a support substrate having a ceramic core, in a wafer state before peeling the vertical elements from the substrate.

[0002] Currently, single-crystal Si substrates are widely used as semiconductor substrates. However, due to their characteristics, they are not always suitable for recent high breakdown voltage and high frequency requirements, and thus, although expensive, substrates of single-crystal SiC and single-crystal GaN have begun to be used. For example, by using semiconductor elements made of silicon carbide (SiC) or nitrides (AlInGaN-based), which are semiconductor materials having a wider bandgap than silicon (Si), to constitute power conversion devices such as inverters and AC / DC converters, reduction of power losses that cannot be achieved with semiconductor elements using silicon has been realized. By using semiconductor elements made of SiC or nitrides, not only are the losses associated with power conversion reduced compared to the conventional case, but also weight reduction, size reduction, and high reliability of the device are promoted.

[0003] Nitrides centered on GaN are excellent in terms of high-frequency characteristics and absolute insulation characteristics compared to SiC, and thus GaN has attracted attention as a next-generation device. As a substrate for growing a GaN epitaxial film, there is a substrate obtained by bonding a seed crystal layer such as Si or SiC to a support substrate having a structure in which a ceramic core having substantially the same thermal expansion coefficient as the crystal to be formed is wrapped with a sealing layer. As such a support substrate having a ceramic core, the QST (registered trademark of the United States) substrate of Qromis is known. In Patent Document 1, as a single-crystal layer on a support substrate having a ceramic core, examples using, in addition to Si and SiC, AlN, AlGaN, Al ２ O ３ etc. are shown.

[0004] Furthermore, when a support substrate with a ceramic core is used, there is a method for fabricating a vertical transistor by separating the support substrate with the ceramic core by ion implantation, as described in Patent Document 2. Also, as described in Patent Document 3, the support substrate with the ceramic core is bonded to an adhesive layer (SiO ２ Another method involves separating the elements by etching the layers to fabricate ultraviolet light-emitting elements. The separated elements can be mounted on a device substrate using a bonding method that utilizes intermolecular bonds, as described in Patent Document 4. By using these techniques to fabricate elements on an epitaxial growth substrate using QST (US registered trademark) substrate and then peeling the elements from the growth substrate, it is possible to fabricate vertical elements having a vertical device structure.

[0005] When fabricating a vertical element having a vertical device structure, the general process is as shown in Figure 1: First, a buffer layer 20 is placed on the epitaxial growth substrate 10, for example, n ＋ A nitride epitaxial film 30 is formed by sequentially epitaxially growing a GaN layer 31, an nGaN layer 32, and a pGaN layer 33 (Figure 1a). Next, multiple vertical elements are fabricated on the wafer using the element fabrication process to form the front side electrodes 40 (Figure 1b). After separating each element (Figure 1c), they are bonded to a temporary support substrate 50 and peeled off from the substrate 10 (Figure 1d). Furthermore, the buffer layer 20 on the back side of each element is removed (Figure 1e) to form the back side electrodes 60 (Figure 1f). Finally, the temporary support substrate 50 is removed, and the elements are mounted on a device mounting substrate 70 to complete the semiconductor device (Figure 1g). The completed semiconductor device is inspected using a probe 3 to check the conductivity between the front side electrodes 40 and the back side electrodes 60, and the acceptable products are selected.

[0006] Japanese Unexamined Patent Publication No. 2022-012558, International Publication No. 2021 / 230148, Japanese Unexamined Patent Publication No. 2022-056492, Japanese Patent No. 5129939

[0007] In this type of process, evaluation of the elements is performed after the semiconductor device is completed, and inspection cannot be carried out during the process. This means that defects in the epitaxial film or defects caused by the element fabrication process cannot be detected, resulting in a high defect rate during inspection at the time of semiconductor device completion and a low yield. In addition, defective products caused by epitaxial growth or the element fabrication process in the early stages of the process also flow through the process, resulting in unnecessary costs.

[0008] Therefore, in view of the above problems, the present invention aims to provide an epitaxial wafer and an inspection method having a structure that allows inspection of vertical elements in the wafer state before they are peeled off the substrate.

[0009] To achieve the above objective, in one aspect of the present invention, an epitaxial wafer capable of inspecting vertical elements comprises an epitaxial growth substrate having a structure in which a ceramic core is encased in a sealing layer, on which a single-crystal seed crystal layer is attached via an adhesive layer, and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically bonded to the seed crystal layer, and an inspection electrode for inspecting the vertical elements in wafer form is further provided at the bottom surface of a recess where the seed crystal layer is exposed in a part of the epitaxial wafer.

[0010] The resistivity of the seed crystal layer is preferably 1 Ωcm or less. Furthermore, the buffer layer is preferably doped with an N-type dopant. In addition, the seed crystal layer is preferably made of either SiC or Si.

[0011] Furthermore, in another embodiment, the epitaxial wafer capable of inspecting vertical elements according to the present invention comprises an epitaxial growth substrate having a structure in which a ceramic core is encased in a sealing layer, on which a single-crystal seed crystal layer is attached via an adhesive layer, and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically bonded to a current diffusion layer provided on the epitaxial wafer, and an inspection electrode for inspecting the vertical elements in wafer form is further provided on the bottom surface of a recess where the current diffusion layer is exposed in a part of the epitaxial wafer.

[0012] The current diffusion layer is preferably low-resistance. The current diffusion layer has an N-type impurity as a dopant, and its carrier density n is n > 5 × 10 １７ cm －３ It is preferable that the current diffusion layer is an AlInGaN layer.

[0013] Preferably, the current diffusion layer consists of a nitride layer containing a two-dimensional electron gas formed between the buffer layer and the nitride epitaxial film.

[0014] In the epitaxial wafer according to the present invention, the vertical device structure is preferably an optical device structure or an electronic device structure.

[0015] In yet another aspect, the present invention provides an inspection method for inspecting vertical elements in an epitaxial wafer on which a plurality of vertical elements are formed, wherein the epitaxial wafer comprises an epitaxial growth substrate having a structure in which a ceramic core is encased in a sealing layer, on which a single crystal seed crystal layer is attached via an adhesive layer, and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically bonded to the seed crystal layer, and an inspection electrode for inspecting the vertical elements in a wafer state is further provided on the bottom surface of a recess where the seed crystal layer is exposed in a part of the epitaxial wafer, and probe inspection is performed between the front electrode of each vertical element and the inspection electrode.

[0016] The resistivity of the seed crystal layer is preferably 1 Ωcm or less. The buffer layer is preferably doped with an N-type dopant.

[0017] Furthermore, in another aspect, the inspection method according to the present invention is an inspection method for inspecting vertical elements in a wafer state of an epitaxial wafer on which a plurality of vertical elements are formed, wherein the epitaxial wafer comprises an epitaxial growth substrate in which a single crystal seed crystal layer is attached via an adhesive layer to a support substrate having a structure in which a ceramic core is encased in a sealing layer, and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically joined to a current diffusion layer provided on the epitaxial wafer, and an inspection electrode for inspecting the vertical elements in a wafer state is further provided on the bottom surface of a recess in which the current diffusion layer is exposed in a part of the epitaxial wafer, and probe inspection is performed between the front electrode of each vertical element and the inspection electrode.

[0018] The current diffusion layer is preferably low-resistance. The current diffusion layer has an N-type impurity as a dopant, and its carrier density n is n > 5 × 10 １７ cm －３It is preferable that the current diffusion layer is an AlInGaN layer.

[0019] Preferably, the current diffusion layer consists of a nitride layer containing a two-dimensional electron gas formed between the buffer layer and the nitride epitaxial film.

[0020] In the inspection method according to the present invention, the vertical device structure is preferably an optical device structure or an electronic device structure.

[0021] As described above, according to the present invention, by providing an inspection electrode on the bottom surface of a recess where a seed crystal layer or current diffusion layer is exposed in a part of the epitaxial wafer, it becomes possible to inspect vertical elements in the wafer state before substrate peeling. This suppresses the decrease in yield during the final inspection after the semiconductor device is completed, and also reduces the number of steps involved in completing defective semiconductor devices, thereby reducing manufacturing costs.

[0022] This is a schematic flowchart illustrating a conventional manufacturing process for producing vertical elements. This is a schematic flowchart illustrating a manufacturing process for vertical elements, including one embodiment of the inspection method according to the present invention. This is a schematic cross-sectional view of the epitaxial wafer of Example 1. This is a schematic cross-sectional view of the epitaxial wafer of Example 2. This is a schematic cross-sectional view of the epitaxial wafer of Example 3. This is a schematic plan view of the epitaxial wafers of Examples 1 to 3, viewed from above the wafer.

[0023] The following describes embodiments of an epitaxial wafer and inspection method capable of inspecting vertical elements according to the present invention with reference to the figures, but the present invention is not limited to these embodiments. In this embodiment, a vertical MOS-FET is shown as an example, but the target semiconductor device is not limited to MOS-FETs, and LEDs, LDs (laser diodes), and Schottky barrier diodes can also be cited.

[0024] First, an example of the manufacturing process of a vertical device, including the steps until manufacturing one embodiment of the epitaxial wafer according to the present invention and the inspection method according to the present invention, is shown in FIG. 2. First, as shown in FIG. 2a, an epitaxial film 30 made of nitride is formed on an epitaxial growth substrate 10 (hereinafter, also simply referred to as "growth substrate") via a buffer layer 20.

[0025] The epitaxial growth substrate 10 preferably includes a support substrate (not shown) having a structure in which a ceramic core (not shown) is wrapped with a sealing layer (not shown), and a single crystal seed crystal layer (not shown) provided via an adhesive layer (not shown).

[0026] The support substrate is a support member for preventing deformation of the epitaxial film 30 and has a structure in which a ceramic core is wrapped with a sealing layer. The core is a layer forming the basis of the support substrate. As the ceramic, for example, polycrystalline AlN, polycrystalline GaN, polycrystalline AlGaN, polycrystalline boron nitride (BN), polycrystalline silicon nitride (Si ３ N ４ ), polycrystalline SiC, Al ２ O ３ , polycrystalline zinc oxide (ZnO), polycrystalline gallium trioxide (Ga ２ O ３ ), or a material containing a mixture thereof, etc. is preferable. The thickness of the core is preferably in the range of, for example, 200 to 1500 μm. The size of the core can be, for example, a diameter of 2 inches to 12 inches. The core is preferably polished on both sides.

[0027] The sealing layer is a layer that covers the periphery of the core to prevent diffusion of impurities. As the sealing layer, for example, silicon oxide (SiO ２ ), Si ３ N ４ , or a mixture thereof, etc. can be used, and Si ３ N ４This is more preferable. The thickness of the sealing layer covering the core is preferably in the range of 50 to 1500 nm. The sealing layer is not limited to one layer, but may consist of multiple layers with different compositions. As a support substrate in which the entire core is enclosed by a sealing layer, for example, Qromis's QST (registered trademark) substrate can be suitably used.

[0028] The adhesive layer is a layer that flattens the irregularities caused by the outer shape of the support substrate. The adhesive layer is also the part that is removed by etching when separating the device from the growth substrate 10 after the device has been formed on the epitaxial film 30. The adhesive layer is made of, for example, SiO ２ Si ３ N ４ Silicon oxynitride (SiON), SiC, Al ２ O ３ It contains one of the following: Si, gallium arsenide (GaAs), and aluminum arsenide (AlAs), and SiO ２ This is preferable.

[0029] The adhesive layer may be applied only to the side of the support substrate where the seed crystal is provided, or it may be applied so as to enclose the entire support substrate, or it may be applied to both sides of the support substrate. The thickness of the adhesive layer can be, for example, 0.5 to 3.0 μm. The arithmetic mean roughness Ra of the surface of the adhesive layer can be 0.02 to 2 nm.

[0030] The seed crystal layer is a base layer on which the epitaxial film 30 grows, and can be made of, for example, Si, SiC, AlN, GaN, AlGaN, or Al ２ O ３ Each of the following single crystals can be used. SiC is particularly preferred. SiC is a material whose lattice constant is closer to that of GaN than to that of Si, and is available in large diameters at a lower cost compared to other crystalline layers such as GaN and AlN that can be used to produce high-quality GaN epitaxial films. Therefore, it can be produced in a simple process without warping or cracking, and has a dislocation density of 1.0 × 10⁻⁶. ６ / cm ２ The following GaN epitaxial films can be formed.

[0031] The crystal structure of the SiC single crystal is not particularly limited, and examples include 6H-SiC, 4H-SiC, and 3C-SiC. For example, 4H-SiC is suitable for electronic devices, while 6H-SiC and 4H-SiC are suitable for visible and ultraviolet light devices. The thickness of the seed crystal layer can be, for example, 0.1 to 1.5 μm. Since the seed crystal layer is ultimately removed, a thick seed crystal layer makes the removal process difficult. Also, a thin seed crystal layer increases the lateral resistance of the growth substrate 10, which is problematic. The size of the seed crystal layer should be smaller than the size of the core of the support substrate 10, for example, a diameter of 2 to 12 inches.

[0032] The seed crystal layer can be provided on the support substrate by, for example, the following method. First, a single crystal seed crystal substrate, which will become the seed crystal layer, is bonded to the support substrate via an adhesive layer. The bonding surface of the seed crystal substrate is pre-implanted with ions. Ion implantation is performed, for example, by implanting hydrogen ions into the bonding surface of the seed crystal substrate at an accelerating voltage of 50 keV to 200 keV. The depth of the ion implanted layer can be changed by adjusting the accelerating voltage. The depth of the ion implanted layer is preferably 0.1 μm to 1.5 μm.

[0033] Next, the seed crystal substrate bonded to the support substrate is separated and peeled off at the depth of the ion implantation layer, allowing the remaining portion to be transferred as a thin film to the support substrate as a seed crystal layer. Then, the transferred seed crystal layer is thinned using methods such as CMP polishing, dry etching, or hydrofluoric acid etching until it reaches a predetermined thickness. Alternatively, to repair the damage to the seed crystal layer caused by ion implantation, heat treatment may be performed at a temperature of 800 to 1000°C in a hydrogen atmosphere. The seed crystal substrate separated and peeled off by thin film transfer can be planarized by polishing, and then ion implanted again on the bonding surface to bond it to another support substrate, allowing it to be repeatedly used for thin film transfer of seed crystal layers.

[0034] An epitaxial film 30 is fabricated on such an epitaxial growth substrate 10, for example, by metal-organic vapor deposition (MOCVD). The buffer layer 20 is a layer that is provided as needed to alleviate mismatches due to differences in lattice constants between the seed crystal layer of the growth substrate 10 and the epitaxial film 30, and to relieve stress on the epitaxial film 30. For example, a multilayer film of AlN, GaN, AlGaN, or AlN / AlGaN is used. Furthermore, in order to reduce the resistance between probes during inspection, which will be described later, it is desirable to dopage the buffer layer 20 with an N-type dopant. Examples of dopant materials include Si, Ge, and C. The dopant concentration is 5 × 10⁻¹⁶. １７ cm －３ The above is preferable. However, if the doping amount is too high, the epitaxial film 30 may not be planarized, so the upper limit of the doping amount should be the value necessary for the epitaxial film 30 to be planarized.

[0035] The epitaxial film 30 is a single-crystal layer on which a semiconductor device is formed. The composition of the epitaxial film 30 may be, for example, a group III nitride such as GaN, InN, or AlN, or a mixed crystal thereof. The composition, structure, and conductivity type of the epitaxial film 30 can be appropriately selected according to the device to be formed, and it may be a multilayer film. For example, in the case of a vertical MOS-FET, the GaN epitaxial film 30 may be n ＋ The layers may be a GaN layer 31, an nGaN layer 32, and a pGaN layer 33. Furthermore, in order to fabricate a high-voltage FET, it is desirable to increase the thickness of the N-type layer (nGaN layer 32), and a thickness of 10 μm or more is desirable to ensure a voltage withstand capability of 1000 V or more.

[0036] Next, as shown in Figure 2b, multiple vertical elements are fabricated on the wafer by the element fabrication process. Specifically, for example, a trench structure having a predetermined pattern is formed on the epitaxial film 30 by photolithography and dry etching, and then a front electrode 40 is formed at a predetermined position to fabricate a vertical element, and the vertical elements are separated by dry etching, n ＋The GaN layer 31 is exposed. Additionally, an inspection electrode 41 is formed on a portion of the wafer at a position closer to the growth substrate 10 than the N-type layer (nGaN layer 32). This allows for the fabrication of the epitaxial wafer 1 according to this embodiment.

[0037] The front electrode 40 consists of a source electrode (not shown) and a gate electrode (not shown), with a gate oxide film (not shown) formed on the substrate side of the gate electrode. The electrode material can be, for example, Ti, Al, Ni, Au, or a laminated structure of two or more of these materials. Other metallic materials may also be used.

[0038] The test electrode 41 is formed in contact with the bottom surface of a recess etched from the surface of the epitaxial film 30 to the nGaN layer 32. As the electrode material for the test electrode 41, for example, Ti, Al, Ni, Au, or a laminated structure of two or more of these materials can be used. Other metallic materials may also be used. When viewed from above the wafer, the test electrode 41 can be arranged as shown in Figure 6, for example. That is, it is arranged in the TEG (test element group) portion 41a or the outer periphery portion 41b of the wafer, which are arranged at regular intervals.

[0039] Note that in Figure 2b, the inspection electrode 41 is n ＋ Although the GaN layer 31 is provided in contact with the bottom surface of the recess where it is exposed, the present invention is not limited to this, and other layers may be provided on the bottom surface of the recess where they are exposed, as long as they are electrically connected to the vertical element. For example, as will be described in detail later, a recess may be provided so that a seed crystal layer (not shown) in the substrate 10 is exposed, and the inspection electrode 41 may be provided on its bottom surface. Also, the buffer layer 20 and n ＋ A nitride such as AlInGaN may be formed between the GaN layer 31 and the other layer.

[0040] As shown in Figure 2c, the epitaxial wafer 1 fabricated in this manner is inspected using a probe 3 between the front electrode 40 (source electrode, gate electrode) on the upper surface of the vertical element and the inspection electrode 41 on the growth substrate 10 side.

[0041] Furthermore, when the inspection electrode 41 is provided in contact with the seed crystal layer, it is preferable to lower the resistivity of the seed crystal layer. This is because lowering the resistivity of the seed crystal layer suppresses the lateral resistance between the inspection electrode 41 and the element, and reduces the resistance between the front electrode 40 and the inspection electrode 41. In addition, a low resistivity of the seed crystal layer is advantageous in reducing the ohmic contact resistance of the inspection electrode 41. The resistivity of the seed crystal layer is preferably, for example, 1 Ωcm or less. More preferably, it is 0.5 Ωcm or less. Note that as shown in Figure 2b, n ＋ When the inspection electrode 41 is placed in contact with the GaN layer 31, the effect of utilizing the lateral conductivity of the seed crystal layer is reduced, so the resistivity of the seed crystal layer may be high.

[0042] By using an epitaxial wafer 1 with such a structure, it becomes possible to inspect the vertical elements in wafer form without peeling them off the growth substrate 10.

[0043] Next, as shown in Figure 2d, the space between the vertical elements is further etched down to the buffer layer 20, for example, by dry etching. At the same time, the inspection electrode 41 is also removed by etching.

[0044] Then, as shown in Figure 2e, after the temporary support substrate 50 is bonded to the upper surface of the vertical element, the growth substrate 10 is peeled off from the vertical element. The growth substrate 10 is peeled off, for example, by immersing it in an HF solution, thereby removing the adhesive layer (SiO₂) of the growth substrate 10. ２ Alternatively, this can be done by dissolving the material and separating it into an upper and lower portion above the adhesive layer.

[0045] Furthermore, as shown in Figure 2f, the buffer layer 20 on the back side of each vertical element is removed. The buffer layer 20 can be etched by dry etching or the like. From this, the n of the vertical element ＋ The GaN layer 31 is exposed.

[0046] Then, as shown in Figure 2g, the exposed n of the vertical element ＋ A back electrode 60 is formed on the GaN layer 31, for example by sputtering. Before forming the back electrode 60, n ＋An ohmic metal such as Al or Ti is formed on the GaN layer 31, and an ohmic electrode is formed by RTA (Rapid Thermal Annealing) treatment in an atmosphere of argon, and then a back electrode 60 is formed on its surface. For example, Au or Ag can be used as the electrode material for the back electrode 60. After the formation of the back electrode 60, N ２ Ya H ２ It is preferable to perform the heat treatment in an atmosphere such as the above.

[0047] Then, as shown in Figure 2h, the temporary support substrate 50 is removed, and each vertical element is mounted on the device mounting substrate 70 to complete the semiconductor device. Note that any defective products found during the wafer inspection described above are not mounted. For the completed semiconductor devices, a final inspection is performed using the probe 3 to check the upper and lower conductivity of the front electrode 40 and the back electrode 60, and the final acceptable products are identified from the IdVd characteristics, IdVg characteristics, and IdVd characteristics and IdVg characteristics in the off state of the semiconductor device.

[0048] The present invention will be described in detail below with reference to examples, but this is not intended to limit the present invention.

[0049] [Example 1] An epitaxial wafer 1A having the structure shown in Figure 3 was fabricated by the following process.

[0050] (Preparation of the support substrate) First, AlN powder and Y as a sintering aid. ２ O ３ After mixing with an organic binder, solvent, etc. to produce a green sheet, it is degreased and N ２ The core was an AlN substrate (AlN polycrystalline ceramic substrate) with a diameter of 8 inches and a thickness of 725 μm, which was sintered at 1900°C under atmospheric conditions and polished on both sides.

[0051] Next, the entire core is covered with a 0.2 μm thick SiON layer using the LPCVD method, and then another LPCVD apparatus is used to coat it with a 0.6 μm thick Si ３ N ４ The entire structure was covered and sealed with layers (total thickness of sealing layer = 0.8 μm), forming the support substrate 11.

[0052] (Lamination of adhesive layers) Si on one side (top surface) of the support substrate ３ N４ For further planarization purposes, a 3 μm thick layer of SiO was laid on top of the layer using plasma CVD (ICP-CVD apparatus). ２ These were stacked. Then, this SiO ２ After firing at 1000°C, the material was polished to a thickness of 1.5 μm and planarized by CMP polishing to create an adhesive layer 12 having an arithmetic mean surface roughness Ra of 0.15 nm.

[0053] (Thin film transfer of seed crystal layer) A single crystal SiC was prepared as the seed crystal substrate to be bonded to the support substrate 1. Here, as the single crystal SiC, for example, an n-type SiC single crystal substrate deflected by 4 degrees to the [11-20] orientation plane in the 4H-SiC(000-1)C plane was used. A low-resistivity SiC single crystal with a resistivity of 0.02 Ωcm was used.

[0054] Hydrogen ions were injected onto the prepared SiC single crystal substrate at a depth of 0.5 μm with a dose of 6 × 10⁻¹⁶ at 95 keV. １７ cm －２ Ion implantation was performed under these conditions. Then, the ion-implanted surface of the C-plane of the SiC single crystal was bonded to the adhesive layer 12 surface of the support substrate 11 that had been prepared earlier. Subsequently, the seed crystal substrate was peeled and separated at the peeling position (the position where the ions were implanted at a depth of 0.5 μm), thereby transferring a portion of the SiC single crystal substrate as a seed crystal layer 13 to the support substrate 11 as a thin film. Then, this transferred seed crystal layer 13 was thinned by CMP polishing and hydrofluoric acid etching until its thickness reached 0.38 μm. Furthermore, the damaged portion of the seed crystal layer 13 caused by ion implantation was restored by heat treatment at 1000°C in a hydrogen atmosphere.

[0055] (GaN Epitaxial Growth) Next, an epitaxial film 30 having a device structure was fabricated on the epitaxial growth substrate 10 prepared in this manner using a MOCVD apparatus as follows. First, a Si-doped buffer layer 20 was grown on the seed crystal layer 13 of the growth substrate 10. The film thickness was approximately 25 nm. The doping amount was 1 × 10⁻⁶. １８ cm －３ That's what I decided.

[0056] Next, as the first layer of the epitaxial film 30, a Si concentration of 1 × 10⁻¹⁰ is used. １８ cm －３ n ＋GaN was grown. ＋ The GaN film thickness was set to 1 μm. Next, the Si concentration was 3 × 10⁻⁶. １６ cm －３ N-type GaN was grown to a thickness of 5 μm. Subsequently, Mg-doped GaN (Mg concentration 5 × 10⁻¹⁶) was grown. １８ cm －３ (film thickness 0.2 μm) and Si-doped GaN (Si concentration 2 × 10⁻¹⁶) １８ cm －３ A film thickness of 0.2 μm was grown. As a result, starting from the buffer layer 20 side, n ＋ GaN layer 31, nGaN layer 32, pGaN layer 33, n ＋ An epitaxial film 30 having a structure for vertical devices in which GaN layers 34 are stacked was fabricated.

[0057] (Device Fabrication) Next, the epitaxial wafer for this vertical device was processed using the following device manufacturing process to fabricate multiple vertical devices having vertical power devices (MOS-FETs). First, a mask with a predetermined pattern shape was formed on the outermost surface of the wafer by photolithography, a trench structure was formed by drying, and a gate insulating film (SiO2) was applied to the trench portion. ２ ) 42 was formed. In addition, a mask with a predetermined pattern shape was formed by photography, and the surface n ＋ A pattern was formed by etching a portion of the GaN layer 34. Furthermore, a mask with a predetermined pattern shape was formed using photography, and the front electrode 40 (source electrode S and gate electrode G) was created. Al and Ti were used as the electrode materials.

[0058] Simultaneously, an inspection electrode 41 was formed on a portion of the wafer on the growth substrate 10 side as follows. First, a mask with a predetermined pattern shape was formed by photography, and dry etching was performed until the seed crystal layer 13 made of SiC was exposed to create a recess 43a for forming the inspection electrode 41. This recess 43a for forming the inspection electrode 41 had a recessed shape relative to the epitaxial film 30 and the buffer layer 20, and the inspection electrode 41 was formed in contact with the seed crystal layer 13 exposed on the bottom surface of the recess 43a. Subsequently, an ohmic contact was formed by heat treatment in an inert gas atmosphere such as argon.

[0059] In the process described above, an epitaxial wafer 1A equipped with an inspection electrode 41 was fabricated, as shown in Figure 3. By forming the inspection electrode 41 in contact with the low-resistance SiC seed crystal layer 13, the seed crystal layer 13 functions as a current diffusion layer, and probe testing between the front electrode 40 and the inspection electrode 41 becomes possible by utilizing the lateral conductivity of SiC, as shown by the arrow in the figure.

[0060] (Inspection in wafer state) For the vertical elements described above, probe inspection was performed using a probe 3 between the front electrode 40 (source electrode S, gate electrode G) at the top of each vertical element and the inspection electrode 41 on the growth substrate 10 side, which is located away from the vertical element. The I-V characteristics of the vertical elements were inspected, and approved and rejected products were identified from the IdVd characteristics, IdVg characteristics, and IdVd and IdVg characteristics in the off state.

[0061] (Inter-element separation, substrate peeling) After the above inspection, the seed crystal layer 13 between the vertical elements was etched by dry etching, exposing the adhesive layer 12. A temporary support substrate (not shown) was bonded to the upper surface of the vertical element and immersed in HF solution. This caused the SiO of the adhesive layer 12 to be exposed. ２ It melted and separated into a part above the adhesive layer 12 and a part below it.

[0062] (Buffer layer removal, back electrode formation) The buffer layer 20 on the back of the portion having the separated device structure is dry-etched, n ＋ The GaN layer 31 was exposed. Then, n ＋ An ohmic metal such as Al or Ti is formed on the GaN layer 31, and an ohmic electrode is formed by RTA (Rapid Thermal Annealing) treatment in an atmosphere such as argon. Then, a back electrode such as Au or Ag is formed on its surface by sputtering. ２ Ya H ２ The heat treatment was performed in an atmosphere such as the one described above.

[0063] (Mounting onto device mounting board, final inspection) Next, each vertical element was mounted onto the device mounting board to complete the semiconductor device. During device mounting, no defective products that had been inspected in the wafer state were mounted. The completed semiconductor device underwent a final inspection with top and bottom conductivity, and the final acceptable products were identified from the IdVd characteristics, IdVg characteristics, and IdVd characteristics and IdVg characteristics in the off state of the semiconductor device.

[0064] [Example 2] An epitaxial wafer 1B having the structure shown in Figure 4 was fabricated in the following steps. In the device fabrication step of Example 1, n ＋ Dry etching is performed until the GaN layer 31 is exposed to create a recess 43b for forming an inspection electrode, and n ＋ An epitaxial wafer 1B was fabricated in the same manner as in Example 1, except that an inspection electrode 41 was formed in contact with the GaN layer 31. Then, after inspection in the wafer state in the same manner as in Example 1, mounting onto a device mounting substrate and final inspection were performed.

[0065] In Example 2, n ＋ The GaN layer 31 acts as a current diffusion layer, and as shown by the arrow in Figure 4, n ＋ The lateral conductivity of the GaN layer 31 was utilized for testing with the probe 3. The testing procedures in the wafer state were the same as in Example 1, and each test could be performed. The layer for forming the testing electrode was the first layer of such an epitaxial film 30. ＋ The film is not limited to the GaN layer 31, but is any nitride film that functions as a current diffusion layer. For example, a low-resistance AlInGaN layer may be provided as the current diffusion layer.

[0066] [Example 3] An epitaxial wafer 1C having the structure shown in Figure 5 was fabricated by the following process. In the GaN epitaxial growth process of Example 1, after growing the buffer layer 20, an undoped GaN layer 36 was grown to a thickness of 1 μm, and then an undoped AlGaN layer 35 (20% Al, film thickness 20 nm) was grown, and then n ＋ The point where the GaN layer 31 was grown, and in the device fabrication process, n ＋Dry etching is performed until the GaN layer 31, AlGaN layer 35, and un-GaN layer 36 are exposed to create a recess 43c for forming an inspection electrode, and n ＋ An epitaxial wafer 1C was fabricated in the same manner as in Example 1, except that an inspection electrode 41 was formed so as to be in contact with the GaN layer 31, the AlGaN layer 35, and the un-GaN layer 36 simultaneously. Then, after inspection in the wafer state in the same manner as in Example 1, mounting onto a device mounting substrate and final inspection were performed.

[0067] In this structure, the stacked structure of the un-GaN layer 36 and the AlGaN layer 35 generates a two-dimensional electron gas (2DEG) 7 at the interface between the un-GaN layer 36 and the AlGaN layer 35 due to spontaneous polarization in the AlGaN layer 35. Therefore, by utilizing electrons that are highly concentrated and have high mobility, lateral current diffusion is facilitated as shown by the arrows in the figure. Note that the buffer layer 20 and n ＋ The layer formed between the GaN layer 31 and the un-GaN layer 36 is not limited to the AlGaN layer 35, but is not particularly limited as long as it is a nitride film that generates a two-dimensional electron gas 7 at the interface with the un-GaN layer 36. Examples of such nitride films include AlInGaN and BInGaN. In other words, in Example 3, the nitride layer containing the two-dimensional electron gas 7 can be said to be the current diffusion layer.

[0068] The test electrode 41 is n ＋ The GaN layer 31, AlGaN layer 35, and un-GaN layer 36 are formed to be in contact simultaneously, that is, the inspection electrode 41 and the two-dimensional electron gas are in direct contact, which facilitates current diffusion from the inspection electrode 41 to the two-dimensional electron gas. Furthermore, current diffusion in the vertical direction of the AlGaN layer 35 is possible by utilizing the tunnel effect because the AlGaN layer 35 is extremely thin.

[0069] In this manner, the lateral conductivity of the two-dimensional electron gas 7 generated by the stacked structure of the un-GaN layer 36 and the AlGaN layer 35 was utilized for inspection using the probe 3. The inspection items in the wafer state were the same as those in Example 1, and each inspection could be performed.

[0070] [Example 4] An epitaxial wafer was fabricated in the same manner as in Example 1, except that the resistivity of the SiC seed crystal layer 13 was set to approximately 1 Ωcm in the thin film transfer process of the seed crystal layer of Example 1, and the wafer was inspected. As a result, although the resistance between probes was higher in the wafer inspection, it was confirmed that each characteristic could be inspected in the same manner as in Example 1.

[0071] [Example 5] An epitaxial wafer was fabricated in the same manner as in Example 1, except that the seed crystal layer 13 was made of Si(111) in the thin film transfer process of the seed crystal layer of Example 1, and the wafer was inspected. The resistivity of the seed crystal layer 13 was set to approximately 0.02 Ωcm. As a result, it was confirmed that each characteristic could be inspected in the wafer state, similar to Example 1.

[0072] [Example 6] An epitaxial wafer was fabricated in the same manner as in Example 1, except that the thickness of the buffer layer 20 was set to 100 nm in the GaN epitaxial growth process of Example 1, and inspection was performed in the wafer state. As a result, although the resistance between probes was higher in the wafer state inspection, it was confirmed that each characteristic inspection could be performed in the same manner as in Example 1.

[0073] [Example 7] In the GaN epitaxial growth process of Example 1, n ＋ The Si concentration in the GaN layer 31 is 1 × 10⁻⁶ １８ cm －３ Except for the points mentioned above, an epitaxial wafer was fabricated in the same manner as in Example 1, and inspection was performed in the wafer state. As a result, it was confirmed that each characteristic could be inspected in the wafer state, just as in Example 1.

[0074] [Example 8] An epitaxial wafer was fabricated in the same manner as in Example 2, except that the seed crystal layer 13 to be thin-film transferred was made of semi-insulating SiC in the thin-film transfer process of the seed crystal layer in Example 2, and the wafer was inspected. The resistivity of the seed crystal layer 13 was approximately 1 × 10⁻⁶. ８ The value was set to Ωcm. As a result, it was confirmed that each characteristic could be tested in the wafer state, similar to Example 2.

[0075] [Example 9] In the thin film transfer process of the seed crystal layer of Example 3, an epitaxial wafer was fabricated in the same manner as in Example 3, except that the seed crystal layer 13 to be thin film transferred was made of semi-insulating SiC, and inspection in the wafer state was performed. The resistivity of the seed crystal layer 13 was about 1×10 ８ Ω·cm. As a result, it was confirmed that each characteristic inspection could be performed by inspection in the wafer state, similar to Example 3.

[0076] [Comparative Example 1] In the thin film transfer process of the seed crystal layer of Example 1, an epitaxial wafer was fabricated in the same manner as in Example 1, except that the resistivity of the seed crystal layer 13 made of SiC to be thin film transferred was set to about 10 Ω·cm, and inspection in the wafer state was performed. As a result, the resistance between the probes was high, and each characteristic inspection could not be performed by inspection in the wafer state. This is because in Comparative Example 1, the resistivity of the seed crystal layer was very high and it did not function as a current diffusion layer.

[0077] [Comparative Example 2] In the GaN epitaxial growth process of Example 1, an epitaxial wafer was fabricated in the same manner as in Example 1, except that the film thickness of the buffer layer 20 was set to 100 nm and an undoped structure without Si doping was used, and inspection in the wafer state was performed. As a result, the resistance between the probes was high, and each characteristic inspection could not be performed by inspection in the wafer state.

[0078] [Comparative Example 3] In the GaN epitaxial growth process of Example 2, an epitaxial wafer was fabricated in the same manner as in Example 2, except that the Si concentration of the n ＋ GaN layer 31 was set to 2×10 １７ cm －３ . As a result, the resistance between the probes was high, and each characteristic inspection could not be performed by inspection in the wafer state.

[0079] 1 Epitaxial wafer 3 Probe 10 Substrate for epitaxial growth 11 Support substrate 12 Adhesive layer 13 Seed crystal layer 20 Buffer layer 30 Epitaxial film 31 n ＋ GaN layer 32 nGaN layer 33 pGaN layer 34 n ＋GaN layer 35 AlGaN layer 36 un-GaN layer 40 Front electrode (source electrode S, gate electrode G) 41 Test electrode 42 Gate oxide film 43a-43c Recess

Claims

1. An epitaxial wafer comprising: an epitaxial growth substrate having a structure in which a ceramic core is encased in a sealing layer, to which a single-crystal seed crystal layer is attached via an adhesive layer; and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically bonded to the seed crystal layer which is a current diffusion layer, and an inspection electrode for inspecting the vertical elements in wafer form is further provided on the bottom surface of a recess in which the seed crystal layer is exposed in a part of the epitaxial wafer.

2. The epitaxial wafer according to claim 1, wherein the resistivity of the seed crystal layer is 1 Ωcm or less.

3. The epitaxial wafer according to claim 1, wherein the buffer layer is doped with an N-type dopant.

4. The epitaxial wafer according to claim 1, wherein the seed crystal layer is made of either SiC or Si.

5. An epitaxial wafer comprising: an epitaxial growth substrate having a structure in which a ceramic core is encased in a sealing layer, to which a single-crystal seed crystal layer is attached via an adhesive layer; and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically bonded to a current diffusion layer provided on the epitaxial wafer, and an inspection electrode for inspecting the vertical elements in wafer form is further provided on the bottom surface of a recess where the current diffusion layer is exposed in a part of the epitaxial wafer.

6. The current diffusion layer has an N-type impurity as a dopant, and its carrier density n is n > 5 × 10 １７ cm －３ The epitaxial wafer according to claim 5.

7. The epitaxial wafer according to claim 6, wherein the current diffusion layer is an AlInGaN layer.

8. The epitaxial wafer according to claim 5, wherein the current diffusion layer comprises a nitride layer containing a two-dimensional electron gas formed between the buffer layer and the nitride epitaxial film.

9. The epitaxial wafer according to any one of claims 1 to 8, wherein the vertical device structure is an optical device structure or an electronic device structure.

10. An inspection method for inspecting vertical elements in a wafer state of an epitaxial wafer on which a plurality of vertical elements are formed, comprising: an epitaxial growth substrate having a single crystal seed crystal layer attached via an adhesive layer to a support substrate having a structure in which a ceramic core is encased in a sealing layer; and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, and each vertical element is electrically joined to the seed crystal layer which is a current diffusion layer; and an inspection electrode for inspecting the vertical elements in a wafer state is further provided on the bottom surface of a recess in which the seed crystal layer is exposed in a part of the epitaxial wafer; and a probe inspection is performed between the front electrode of each vertical element and the inspection electrode.

11. The inspection method according to claim 10, wherein the resistivity of the seed crystal layer is 1 Ωcm or less.

12. The inspection method according to claim 10, wherein the buffer layer is doped with an N-type dopant.

13. An inspection method for inspecting vertical elements in a wafer state of an epitaxial wafer on which a plurality of vertical elements are formed, comprising: an epitaxial growth substrate having a single crystal seed crystal layer attached via an adhesive layer to a support substrate having a structure in which a ceramic core is encased in a sealing layer; and a nitride epitaxial film having a vertical device structure formed on the epitaxial growth substrate via a buffer layer, wherein a plurality of vertical elements are formed on the nitride epitaxial film, each vertical element is electrically bonded to a current diffusion layer provided on the epitaxial wafer; an inspection electrode for inspecting the vertical elements in a wafer state is further provided on the bottom surface of a recess where the current diffusion layer is exposed in a part of the epitaxial wafer; and a probe inspection is performed between the front electrode of each vertical element and the inspection electrode.

14. The current diffusion layer has an N-type impurity as a dopant, and its carrier density n is n > 5 × 10 １７ cm －３ The inspection method according to claim 13.

15. The method for inspecting a semiconductor device according to claim 13, wherein the current diffusion layer is an AlInGaN layer.

16. The inspection method according to claim 13, wherein the current diffusion layer is a nitride layer containing a two-dimensional electron gas formed between the buffer layer and the nitride epitaxial film.

17. The inspection method according to any one of claims 10 to 16, wherein the vertical device structure is an optical device structure or an electronic device structure.

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