Electronic device for performing data input / output operations and non-transitory computer-readable storage medium

Abstract

This electronic device may comprise: at least one processor including a processing circuit; and a memory which stores instructions and includes one or more storage devices. The one or more storage devices may include a storage device including a cache memory. The instructions may cause the electronic device to: identify a power state of the electronic device; and transmit, from the at least one processor to the storage device, a command to disable the cache memory, on the basis of the power state satisfying a reference condition.

Description

Electronic device performing data input / output operations and non-transient computer-readable storage medium

[0001] The following descriptions relate to electronic devices that perform data input / output operations and non-transient computer-readable storage media.

[0002] Cache memory can be used to improve the data transfer speed between a processor and memory. For example, an electronic device can improve the data transfer speed by storing data provided from the processor in the memory through the cache memory.

[0003] The information described above may be provided as related art for the purpose of aiding understanding of the present disclosure. No claim or determination is made as to whether any of the foregoing may be applied as prior art related to the present disclosure.

[0004] An electronic device is provided. The electronic device may include at least one processor comprising a processing circuit; and a memory comprising one or more storage devices for storing instructions. The one or more storage devices may include a storage device comprising a cache memory. When the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to identify the power state of the electronic device. When the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to transmit a command from the at least one processor to the storage device to disable the cache memory based on the power state satisfying a reference condition.

[0005] An electronic device is provided. The electronic device may include at least one processor comprising a processing circuit; and a memory comprising one or more storage devices for storing instructions. The one or more storage devices may include a storage device comprising a cache memory. When the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to identify a power state of the electronic device. When the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to transmit data and an instruction associated with the data from the at least one processor to the storage device based on the power state satisfying a reference condition. The instruction may be used to store the data in the storage device by bypassing the cache memory.

[0006] A non-transient computer-readable storage medium is provided. The non-transient computer-readable storage medium may store one or more programs. The one or more programs may include instructions that cause the electronic device to identify the power state of the electronic device when executed by the electronic device having at least one processor and a storage device including a cache memory. The one or more programs may include instructions that cause the electronic device to transmit a command to disable the cache memory from the at least one processor to the storage device based on the power state satisfying a reference condition when executed by the electronic device.

[0007] A non-transient computer-readable storage medium is provided. The non-transient computer-readable storage medium may store one or more programs. The one or more programs may include instructions that cause the electronic device to identify the power state of the electronic device when executed by the electronic device having at least one processor and a storage device including a cache memory. The one or more programs may include instructions that cause the electronic device to transmit data and a command associated with said data from the at least one processor to the storage device based on the power state satisfying a reference condition when executed by the electronic device. The command may be used to store said data in the storage device by bypassing the cache memory.

[0008] Figure 1 is a schematic view of an exemplary electronic device.

[0009] Figure 2 illustrates an example of a data input / output environment of an electronic device.

[0010] Figure 3 illustrates an example of a hierarchical structure regarding a storage device.

[0011] FIG. 4 is a flowchart illustrating an example of a method of storing data in a storage device based on the power state of an electronic device.

[0012] Figure 5 is an example illustrating the operation of storing data in a storage device through a cache memory.

[0013] Figure 6 is an example illustrating an operation to bypass cache memory based on a command to disable cache memory.

[0014] FIG. 7 is a flowchart illustrating another example of an operation method for storing data in a storage device based on the power state of an electronic device.

[0015] Figure 8 is an example illustrating the operation of storing data in a storage device based on commands associated with the data.

[0016] FIG. 9 is a flowchart illustrating an example of an operation method for selectively bypassing cache memory based on commands associated with data.

[0017] FIG. 10 is a block diagram of an electronic device in a network environment according to various embodiments.

[0018] Figure 1 is a schematic view of an exemplary electronic device.

[0019] Referring to FIG. 1, the electronic device (101) may include at least one processor (110), memory (120), power management integrated circuitry (PMIC) (130), and battery (140). The electronic device (101) may include at least a part of the electronic device (1001) of FIG. 10 or correspond to at least a part of the electronic device (1001) of FIG. 10.

[0020] At least one processor (110) may include a processing circuit. At least one processor (110) may include a single processor or multiple processors. At least one processor (110) may control the memory (120) and / or one or more components (e.g., PMIC (130)) of the electronic device (101). For example, at least one processor (110) may include at least a part of the processor (1020) of FIG. 10 or correspond to at least a part of the processor (1020) of FIG. 10.

[0021] Memory (120) may store one or more programs configured to be executed individually and / or collectively by at least one processor (110). The one or more programs may include instructions. The instructions may cause an electronic device (101) to perform operations described with reference to FIGS. 2 through 9. Memory (120) may include one or more storage devices. For example, the one or more storage devices may include storage devices including cache memory and non-volatile memory. At least some of the one or more programs may be available to manage, control, and / or execute file system and storage device drivers described below. For example, memory (120) may include at least a portion of the memory (1030) of FIG. 10 or correspond to at least a portion of the memory (1030) of FIG. 10.

[0022] The PMIC (130) can manage power supplied to the electronic device (101). For example, the PMIC (130) can distribute power to at least one component of the electronic device (101) based on power supplied from the battery (140) and / or an external power source (not shown). For example, the PMIC (130) can detect the voltage, current, resistance and / or temperature of the battery (140). The detected voltage of the battery (140),

[0023] Information regarding current, resistance and / or temperature can be transmitted to at least one processor (110). As another example, a PMIC (130) can identify a voltage from the external power source. Information regarding the identified voltage can be transmitted to at least one processor (110). For example, the PMIC (130) can be implemented as at least part of the power management module (1088) of FIG. 10.

[0024] The battery (140) can supply power to at least one component of the electronic device (101) through the PMIC (130). For example, the battery (140) may be described as a rechargeable battery that supplies power to at least one processor (110) and memory (120). However, it is not limited thereto. For example, the battery (140) may include a non-rechargeable cell. For example, the battery (140) may include at least a part of the battery (1089) of FIG. 10 or correspond to at least a part of the battery (1089) of FIG. 10.

[0025] Figure 2 illustrates an example of a data input / output environment of an electronic device.

[0026] Referring to FIG. 2, the data input / output environment (200) may include at least one processor (110) and a storage device (210).

[0027] At least one processor (110) can perform data input / output operations of the electronic device (101) by performing operations of storing data in the storage device (210) and reading data stored in the storage device (210). At least one processor (110) can transmit commands regarding the data input / output operations to the storage device (210). For example, at least one processor (110) may be configured to function as a host device (or host) in relation to the storage device (210).

[0028] The storage device (210) may include a cache memory (211) and a non-volatile memory (212). The cache memory (211) may be described as a volatile memory that loses stored data when the power supplied to the cache memory (211) is cut off. By example, the cache memory (211) may include static random access memory (SRAM). The non-volatile memory (212) may retain stored data regardless of (or independently of) the power supplied to the non-volatile memory (212). By example, the non-volatile memory (212) may include NAND flash. By example, the storage device (210) may be described as a single chip including the cache memory (211) and the non-volatile memory (212). For example, the storage device (210) may be described as a solid state drive (SSD), universal flash storage (UFS), or embedded multimedia card (eMMC). However, it is not limited thereto. The present disclosure may be applied to an electronic device comprising a non-volatile memory and a cache memory associated with said non-volatile memory. The storage device (210) may include at least a portion of the memory (120) or correspond to at least a portion of the memory (120).

[0029] Figure 3 illustrates an example of a hierarchical structure regarding a storage device.

[0030] Referring to FIG. 3, a hierarchical structure (300) relating to a storage device (210) may include a file system (301), a storage device driver (302), and a storage device (210). The storage device (210) may include a cache memory (211) and a non-volatile memory (212).

[0031] A file system (301) may be described as software for managing data stored in a storage device (210) in file units. For example, the file may include data and metadata associated with the data. For example, the metadata may include information regarding the file system (301) and / or attributes of the file. For example, the metadata may include information regarding a file system superblock, a checkpoint, a block, and / or file allocation. Information regarding the file system superblock may include information regarding the type, size, and / or number of available blocks of the file system (301). Information regarding the checkpoint may include information regarding the time at which a change to the file occurs, identified based on the file system (301). Information regarding the block may include information regarding the size of the block and / or the address of the block, which is a unit for physically storing data in the file system (301). The information regarding the file allocation above may include information regarding the type to which the file is allocated to the block. For example, the metadata may include information regarding the inode of the file and / or the inode of the directory associated with the file. The information regarding the inode of the file may include information regarding the type of the file, the size of the file, and / or the storage location of the data contained in the file. The directory may be described as a file for managing the file or other directories. The information regarding the inode of the directory may include information regarding the type of the directory, the size of the directory, and / or the storage location of the data contained in the directory.For example, a file system (301) can be described as software stored in memory (120) (e.g., storage device (210)) that is executed by at least one processor (110).

[0032] The storage device driver (302) can control data input / output operations regarding the cache memory (211) and non-volatile memory (212) based on commands received from the file system (301). For example, the storage device driver (302) can be described as software stored in memory (120) (e.g., storage device (210)) that is executed by at least one processor (110).

[0033] For example, the electronic device (101) can increase the data input / output speed of the storage device (210) by using a file system (301) and a storage device driver (302) to store data provided by at least one processor (110) in a non-volatile memory (212) through a cache memory (211).

[0034] For example, the electronic device (101) can increase the reliability of data stored in the storage device (210) by using a file system (301) and a storage device driver (302) to bypass the cache memory (211) based on the power state of the electronic device (101) and storing data provided by at least one processor (110) in a non-volatile memory (212).

[0035] A method of operation for storing data in a storage device based on the power state of an electronic device is described with reference to FIG. 4.

[0036] FIG. 4 is a flowchart illustrating an example of a method of storing data in a storage device based on the power state of an electronic device.

[0037] Referring to FIG. 4, in operation 401, at least one processor (110) can identify a power state of an electronic device (101). The power state can be described as a state regarding the process in which power from a battery (140) is supplied to the electronic components of the electronic device (101) through a PMIC (130). For example, the power state of the electronic device (101) may include a state related to the power off of the electronic device (101) and a state related to the power of the battery (140) of the electronic device (101).

[0038] For example, the power state may include a state regarding a power-off sequence executed by at least one processor (110). The power-off sequence may be performed to stop or terminate the supply of power from the battery (140) to the electronic components of the electronic device (101) via the PMIC (130). As an example without limitation, at least one processor (110) may terminate an application running using an operating system (OS) and cut off the power supplied to the electronic components of the electronic device (101) using the PMIC (130) while the power-off sequence is being performed. For example, the operating system may be described as software stored in memory (120) that is executed by at least one processor (110). For example, at least one processor (110) can identify the power state of the electronic device (101) by detecting (or identifying) (or recognizing) the power-off sequence of the electronic device (101) that has started or will start. For example, at least one processor (110) can identify the power state of the electronic device (101) by identifying (or determining) (or detecting) (or recognizing) the power-off sequence of the electronic device (101) that has started or will start. The method of operation for detecting the power-off sequence may be described in various ways according to the embodiment. For example, at least one processor (110) can identify an update of at least one software application of the electronic device (101) that has been performed or will be performed. At least one processor (110) can detect the power-off sequence of the electronic device (101) that will start based on the update of the at least one software application.In another example, at least one processor (110) can identify user input for turning off the electronic device (101). At least one processor (110) can detect the power-off sequence of the electronic device (101) that has been started or is to be started, based on the user input.

[0039] In another example, the power state may include a state regarding the state of charge (SoC) of the battery (140). For example, the SoC may represent a percentage according to the charge state of the battery (140). In an example without limitation, at least one processor (110) may identify the SoC of the battery (140) based on information regarding the voltage, current, resistance, and / or temperature of the battery (140) detected by the PMIC (130). The method of operation for identifying the SoC may be described in various ways according to the embodiment. For example, at least one processor (110) may identify the SoC of the battery (140) using a voltage measurement method using the voltage of the battery (140), a current integration method using the current of the battery (140), an impedance measurement method using the resistance change of the battery (140), and / or an extended Kalman filter method using the voltage, current, and temperature of the battery (140). For example, at least one processor (110) can identify the power state of the electronic device (101) by identifying the SoC of the battery (140) that supplies power to the storage device (210). However, it is not limited thereto. For example, at least one processor (110) can identify the power state of the electronic device (101) by identifying the voltage from an external power source of the electronic device (101).

[0040] As described above, at least one processor (110) can identify the power state of the electronic device (101) by performing the operation of detecting the power-off sequence of the electronic device (101), the operation of identifying the SoC of the battery (140), and / or the operation of identifying the voltage from the external power source.

[0041] In operation 402, at least one processor (110) can identify whether the power state of the electronic device (101) satisfies a reference condition.

[0042] For example, at least one processor (110) can identify the power state satisfying the reference condition based on detecting the power-off sequence.

[0043] In another example, at least one processor (110) can identify the power state of the electronic device (101) satisfying the reference condition based on the SoC of the battery (140) which is lower than a threshold value. The threshold value may be set in various ways according to the embodiment. However, it is not limited thereto. For example, at least one processor (110) can identify the power state of the electronic device (101) satisfying the reference condition based on the voltage identified from the external power source which is lower than a threshold voltage. The threshold voltage may be set in various ways according to the embodiment.

[0044] In operation 403, at least one processor (110) can control the storage device (210) to store data in the non-volatile memory (212) of the storage device (210) via the cache memory (211) based on the power state that does not satisfy the reference condition. The data may be provided from at least one processor (110). The data may be stored in the non-volatile memory (212) of the storage device (210) via the cache memory (211) while the power state of the electronic device (101) does not satisfy the reference condition.

[0045] The operation 403 of storing data in the non-volatile memory (212) of the storage device (210) through the cache memory (211) is described with reference to FIG. 5.

[0046] Figure 5 is an example illustrating the operation of storing data in a storage device through a cache memory.

[0047] Referring to FIG. 5, a storage device (210) is shown that stores data in a non-volatile memory (212) through a cache memory (211).

[0048] Data may be provided from at least one processor (110). Data may be stored in the non-volatile memory (212) of the storage device (210) via the cache memory (211) while the power state of the electronic device (101) does not satisfy the reference condition.

[0049] For example, while the power state of the electronic device (101) does not satisfy the reference condition, the electronic device (101) can increase the data input / output speed of the storage device (210) by storing data in the non-volatile memory (212) of the storage device (210) through the cache memory (211). For example, the electronic device (101) can increase the data input / output speed of the storage device (210) by temporarily storing pieces of data to be stored in the storage device (210) in the cache memory (211), and then concurrently storing the pieces of data stored in the cache memory (211) in the non-volatile memory (212). For example, the electronic device (101) can increase the data input / output speed of the storage device (210) by storing data in the cache memory (211) before storing data in the storage device (210) and then sending a response to at least one processor (110) indicating that the storage of data is completed.

[0050] Referring again to FIG. 4, in operation 404, at least one processor (110) may transmit a command to a storage device (210) to disable (deactivate) the cache memory (211) based on the power state satisfying the reference condition. For example, the command to disable the cache memory (211) may be for not using the cache memory (211). For example, the command to disable the cache memory (211) may be for controlling the storage device (210) to store data provided from at least one processor (110) in the non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211).

[0051] In operation 405, the storage device (210) can store data provided by at least one processor (110) in non-volatile memory (212) by bypassing the cache memory (211) based on receiving the command to disable the cache memory (211).

[0052] For example, the storage device (210) may store the data provided by at least one processor (110) in non-volatile memory (212) by bypassing the cache memory (211) according to the command to disable the cache memory (211) based on the power-off sequence being detected by at least one processor (110). For example, the data transmitted to the storage device (210) after the cache memory (211) is disabled may be described as all data that is not stored in non-volatile memory (212) when the cache memory (211) is disabled. For example, the data may include data stored in files identified by the file system (301) as well as metadata stored in the files associated with said data. For example, at least some of the metadata stored in the files may be described as metadata associated with the booting of the electronic device (101) and / or metadata associated with the operation of the file system (301). For example, at least one processor (110) can identify at least a portion of the metadata and data associated with the metadata when the cache memory (211) is disabled. For example, the metadata and the data associated with the metadata may be cached in a cache memory associated with at least one processor (110) by at least one processor (110) when the cache memory (211) is disabled. At least one processor (110) can transmit at least a portion of the cached metadata to the storage device (210) after transmitting the command to disable the cache memory (211) based on the detection of the power-off sequence.For example, at least one processor (110) can perform an unmount operation to detach a file system (301) mounted on a storage device (210) from the storage device (210) by transmitting the data provided by at least one processor (110), which includes at least a portion of the cached metadata, to the storage device (210) based on the detection of the power-off sequence.

[0053] In another example, the storage device (210) may store the data provided by at least one processor (110) in the non-volatile memory (212) by bypassing the cache memory (211) according to the command to disable the cache memory (211), based on identifying the SoC of the battery (140) that is lower than the threshold value by at least one processor (110). For example, the data transmitted to the storage device (210) after the cache memory (211) is disabled may be described as all data that is not stored in the non-volatile memory (212) when the cache memory (211) is disabled. For example, after the at least one processor (110) transmits the command to disable the cache memory (211) to the storage device (210), the processor may transmit a command to enable (activate) the cache memory (211) to the storage device (210). For example, a command to enable the cache memory (211) may be for controlling the storage device (210) to store data provided by at least one processor (110) in the non-volatile memory (212) through the cache memory (211) by using the cache memory (211). For example, the storage device (210) may store data provided by at least one processor (110) in the non-volatile memory (212) by bypassing the cache memory (211) during the interval from the time of receiving the command to disable the cache memory (211) to the time of receiving the command to enable the cache memory (211).

[0054] The operation 404 of transmitting a command to disable the cache memory (211) and the operation 405 of bypassing the cache memory (211) and storing data in the non-volatile memory (212) of the storage device (210) are described with reference to FIG. 6.

[0055] Figure 6 is an example illustrating an operation to bypass cache memory based on a command to disable cache memory.

[0056] Referring to FIG. 6, a storage device (210) is shown that stores data in non-volatile memory (212) by bypassing the cache memory (211) based on a command to disable the cache memory (211).

[0057] A command is a command to disable the cache memory (211). The command may be provided from at least one processor (110). The command may be transmitted from at least one processor (110) to a storage device (210) when the power state of the electronic device (101) satisfies the reference condition. The storage device (210) may disable the cache memory (211) based on receiving the command. The storage device (210) may store data in the non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211) based on disabling the cache memory (211).

[0058] For example, while the power state of the electronic device (101) satisfies the reference condition, the electronic device (101) can increase the reliability of the data stored in the storage device (210) by bypassing the cache memory (211) and storing the data in the non-volatile memory (212) of the storage device (210).

[0059] FIG. 7 is a flowchart illustrating another example of an operation method for storing data in a storage device based on the power state of an electronic device.

[0060] Referring to FIG. 7, in operation 701, at least one processor (110) can identify the power state of the electronic device (101). The power state can be described as a state regarding the process in which power from the battery (140) is supplied to the electronic components of the electronic device (101) through the PMIC (130). For example, the power state of the electronic device (101) may include a state related to the power off of the electronic device (101) and a state related to the power of the battery (140) of the electronic device (101).

[0061] For example, the power state may include a state regarding a power-off sequence executed by at least one processor (110). The power-off sequence may be performed to stop or terminate the supply of power from the battery (140) to the electronic components of the electronic device (101) via the PMIC (130). As an example without limitation, at least one processor (110) may terminate an application running using an operating system (OS) and cut off the power supplied to the electronic components of the electronic device (101) using the PMIC (130) while the power-off sequence is being performed. For example, the operating system may be described as software stored in memory (120).

[0062] For example, at least one processor (110) can identify the power state of the electronic device (101) by detecting (or identifying) (or recognizing) the power-off sequence of the electronic device (101) that has been started or is to be started. The method of operation for detecting the power-off sequence may be described in various ways according to the embodiment. For example, at least one processor (110) can identify an update of at least one software application of the electronic device (101) that has been performed or is to be performed. At least one processor (110) can detect the power-off sequence of the electronic device (101) that is to be started based on the update of the at least one software application. As another example, at least one processor (110) can identify a user input for turning off the electronic device (101). At least one processor (110) can detect the power-off sequence of the electronic device (101) that has been started or is to be started based on the user input.

[0063] In another example, the power state may include a state regarding the state of charge (SoC) of the battery (140). For example, the SoC may represent a percentage according to the charge state of the battery (140). In an example without limitation, at least one processor (110) may identify the SoC of the battery (140) based on information regarding the voltage, current, resistance, and / or temperature of the battery (140) detected by the PMIC (130). The method of operation for identifying the SoC may be described in various ways according to the embodiment. For example, at least one processor (110) may identify the SoC of the battery (140) using a voltage measurement method using the voltage of the battery (140), a current integration method using the current of the battery (140), an impedance measurement method using the resistance change of the battery (140), and / or an extended Kalman filter method using the voltage, current, and temperature of the battery (140). For example, at least one processor (110) can identify the power state of the electronic device (101) by identifying the SoC of the battery (140) that supplies power to the storage device (210). However, it is not limited thereto. For example, at least one processor (110) can identify the power state of the electronic device (101) by identifying the voltage from an external power source of the electronic device (101).

[0064] As described above, at least one processor (110) can identify the power state of the electronic device (101) by performing the operation of detecting the power-off sequence of the electronic device (101), the operation of identifying the SoC of the battery (140), and / or the operation of identifying the voltage from the external power source.

[0065] In operation 702, at least one processor (110) can identify whether the power state of the electronic device (101) satisfies a reference condition.

[0066] For example, at least one processor (110) can identify the power state satisfying the reference condition based on detecting the power-off sequence.

[0067] In another example, at least one processor (110) can identify the power state of the electronic device (101) satisfying the reference condition based on the SoC of the battery (140) which is lower than a threshold value. The threshold value may be set in various ways according to the embodiment. However, it is not limited thereto. For example, at least one processor (110) can identify the power state of the electronic device satisfying the reference condition based on the voltage identified from the external power source which is lower than a threshold voltage. The threshold voltage may be set in various ways according to the embodiment.

[0068] In operation 703, at least one processor (110) can control the storage device (210) to store data in the non-volatile memory (212) of the storage device (210) via the cache memory (211) based on the power state that does not satisfy the reference condition. The data may be provided from at least one processor (110). The data may be stored in the non-volatile memory (212) of the storage device (210) via the cache memory (211) while the power state of the electronic device (101) does not satisfy the reference condition.

[0069] In operation 704, at least one processor (110) can identify whether data to be transferred to a storage device (210) satisfies the condition for bypassing the cache memory (211) based on the power state satisfying the reference condition. For example, the data satisfying the condition for bypassing may be associated with the booting of the electronic device (101). For example, the data satisfying the condition for bypassing may include at least a portion of metadata stored in files identified according to the file system (301). The metadata may be in a state where it is cached in the cache memory associated with at least one processor (110) by at least one processor (110).

[0070] For example, data satisfying the conditions for the above bypass may include metadata associated with the booting of the electronic device (101). For example, the metadata may include information regarding the file system (301) and / or the attributes of the file. For example, the metadata may include information regarding the file system superblock, checkpoint, block, and / or file allocation. The information regarding the file system superblock may include information regarding the type, size, and / or number of available blocks of the file system (301). The information regarding the checkpoint may include information regarding the time at which a change to the file occurs, identified based on the file system (301). The information regarding the block may include information regarding the size of the block, which is a unit for physically storing data in the file system (301), and / or the address of the block. The information regarding the file allocation may include information regarding the type of the file allocated to the block.

[0071] According to an embodiment, at least one processor (110) can increase the reliability of data stored in a storage device (210) by setting the metadata satisfying the condition for bypassing information regarding the inode of the file and / or the inode of the directory associated with the file. The information regarding the inode of the file may include information regarding the type of the file, the size of the file, and / or the storage location of the data contained in the file. The directory may be described as a file for managing the file or other directories. The information regarding the inode of the directory may include information regarding the type of the directory, the size of the directory, and / or the storage location of the data contained in the directory. For example, a file system (301) may be described as software stored in memory (120) (e.g., storage device (210)) which is executed by at least one processor (110).

[0072] For example, data that does not satisfy the above conditions for bypassing may be described as data that is not associated with the booting of the electronic device (101) and is not metadata. However, it is not necessarily limited thereto. For example, the data that does not satisfy the above conditions for bypassing may include at least some metadata. For example, at least one processor (110) may set the metadata that satisfies the above conditions for bypassing in various ways. For example, at least one processor (110) may set the metadata using a file (e.g., sysfs node) for dynamic configuration changes of an operating system (e.g., linux).

[0073] For example, at least one processor (110) may apply default settings at the time of compilation or loading of a module regarding the file system (301) and set an indication (e.g., a setting value) for a file of a defined type. For example, at least one processor (110) may identify whether the metadata satisfies the condition for bypassing based on the indication associated with the metadata. For example, the indication associated with the metadata may have a value indicating the type of metadata to bypass the cache memory (211).

[0074] For example, at least one processor (110) may identify a first part of the metadata as the data to be transmitted based on the indication associated with the metadata while the power state satisfies the reference condition. At least one processor (110) may transmit the first part of the metadata and a command associated with the first part of the metadata (e.g., a command to bypass a cache memory, to be described later) to a storage device (210) while the power state satisfies the reference condition. The first part of the metadata may be stored in a non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211). For example, at least one processor (110) may transmit the second part of the metadata to the storage device (210) by refraining from transmitting the command associated with the second part of the metadata while the power state satisfies the reference condition. The second part of the above metadata can be stored in the non-volatile memory (212) of the storage device (210) through the cache memory (211).

[0075] For example, the value of the above indication may be stored in two or more files (file ( / sys / fs / f2fs / fua_write / global) and file ( / sys / fs / f2fs / fua_write / node)). For example, if the value stored in file ( / sys / fs / f2fs / fua_write / global) corresponds to '1', the command may be applied to the file system superblock, checkpoint, block, and file allocation. For example, the value of the default setting for the two or more files may correspond to '0', indicating that the command is not applied. For example, if the value stored in file ( / sys / fs / f2fs / fua_write / node) corresponds to '1', the command may be applied to the inode of the file and the inode of the directory associated with the file. For example, if the above value stored in the file ( / sys / fs / f2fs / fua_write / node) corresponds to '2', the above command can be applied to the inode of the directory associated with the said file. For example, the value of the above default setting regarding the said files may correspond to '0', indicating that the above command is not applied.

[0076] As another example, the value of the above indication may be set through a format (e.g., 0:2, 1:0, 1:1, or 1:2) defined in a file ( / sys / fs / f2fs / fua_write / options).

[0077] In operation 705, at least one processor (110) may transmit the data and the command associated with the data to the storage device (210) based on the data being transmitted satisfying the condition for bypassing. The command may be used to store the data in the non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211). At least one processor (110) may transmit the data satisfying the condition for bypassing to the storage device (210) as associated with transmitting the command to the storage device (210). For example, at least one processor (110) may cause the storage device (210) to bypass the cache memory (211) and store the data satisfying the condition based on the command in the non-volatile memory (212). For example, the above command can be described as a force unit access (FUA) command (e.g., force unit access write) for bypassing the cache memory (211) included in the storage device (210).

[0078] For example, the data satisfying the above conditions for bypassing may be associated with the booting of the electronic device (101). For example, at least one processor (110) may set data associated with the booting of the electronic device (101), including at least a portion of data regarding the booting process of the electronic device (101) and / or at least a portion of data regarding an application for booting the electronic device (101). The method of operation by at least one processor (110) for setting the data associated with booting may be described in various ways according to the embodiments. As an example without limitation, at least one processor (110) may apply an identification number defined for the data associated with booting to set the data associated with booting. For example, at least one processor (110) may designate services and applications affecting the booting of the electronic device (101) as a defined process group (e.g., boot_group) and apply the identification number to the defined process group. For example, data in a file stored in the process group to which the identification number is applied may bypass the cache memory (211) based on the command. For example, the defined process group may be changed while the electronic device (101) is performing an operation based on a file (e.g., sysfs node) for dynamic configuration changes of the operating system (e.g., linux).

[0079] At least one processor (110) may transmit the command to the storage device (210) for all data within a file stored in the defined process group as described above. According to an embodiment, at least one processor (110) may transmit the command to the storage device (210) only for data within a file having a reference type (e.g., reference extension) among the files stored in the defined process group.

[0080] For example, at least one processor (110) can identify files associated with booting the electronic device (101) according to a file system (301). Data stored in the files identified according to the file system (301) may be cached by at least one processor (110) in a cache memory associated with at least one processor (110). At least one processor (110) can identify data stored in at least one file of a reference type among the files as the data associated with booting while the power state satisfies the reference condition. For example, the reference type may be described as a reference file extension such as a file extension (.xml), a file extension (.db), and a file extension (.key). For example, the reference type may be changed while the electronic device (101) performs an operation based on a file (e.g., sysfs node) for dynamic configuration changes of an operating system (e.g., linux). For example, the above reference type may be set based on a format (e.g., xml:db:key:...) defined in a file (sys / fs / f2fs / fua_write / file_extensions). For example, data contained in a file (abc.xml), a file (ddd.xml), and a file (data.db) may bypass the cache memory (211) based on the above command. As another example, at least one processor (110) may process the above command by using a system call (e.g., an ioctl system call) on the file when the application saves a file having a file extension (.xml) and a file extension (.db). At least one processor (110) may transmit the data stored in the at least one file and the above command associated with the data to the storage device (210).

[0081] For example, the data associated with the above command may include at least a portion of metadata stored in files identified according to the file system (301). The metadata may be cached in a cache memory associated with at least one processor (110) by at least one processor (110).

[0082] In operation 706, the storage device (210) can store data provided by at least one processor (110) in non-volatile memory (212) by bypassing the cache memory (211) based on receiving the command associated with the data satisfying the condition for bypassing the cache memory (211).

[0083] In operation 707, at least one processor (110) may refrain from transmitting the command associated with the data to be transmitted to the storage device (210) while the power state satisfies the reference condition, based on the fact that the data to be transmitted does not satisfy the condition for bypassing.

[0084] In operation 708, at least one processor (110) can control the storage device (210) to store data that does not satisfy the conditions for bypassing in the non-volatile memory (212) of the storage device (210) via the cache memory (211). The data may be provided from at least one processor (110). The data may be stored in the non-volatile memory (212) of the storage device (210) via the cache memory (211).

[0085] FIG. 7 illustrates that in operation 704, operations 705 and 706 are performed, or operations 707 and 708 are performed, depending on whether the data to be transmitted satisfies the condition for bypassing, but this is merely illustrative. Operations 704, 707, and 708 may be omitted or skipped. For example, at least one processor (110) may perform operations 705 and 706 based on the power state of the electronic device (101) satisfying the reference condition.

[0086] The operations 704, 705, 706, 707, and 708 of storing the data in a storage device (210) based on the above command associated with the data are described with reference to FIG. 8.

[0087] Figure 8 is an example illustrating the operation of storing data in a storage device based on commands associated with the data.

[0088] Referring to FIG. 8, a storage device (210) for storing first data (data 1) and second data (data 2) is illustrated. A command associated with the first data (data 1) can be described as a command used to store the first data (data 1) in the non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211). The command may be provided by at least one processor (110). The command may be transmitted from at least one processor (110) to the storage device (210) when the first data (data 1) satisfies the conditions for bypass. The first data (data 1) may be data associated with the command that satisfies the conditions for bypass. The second data (data 2) is data not associated with a command and may be data that does not satisfy the above conditions for bypass.

[0089] At least one processor (110) can transmit a command associated with the first data (data 1) to a storage device (210). The storage device (210) can store the first data (data 1) in a non-volatile memory (212) by bypassing a cache memory (211) based on receiving a command associated with the first data (data 1) while the power state of the electronic device (101) satisfies the reference condition. For example, the electronic device (101) can increase the reliability of the data stored in the storage device (210) by bypassing the cache memory (211) and storing the first data (data 1) in the non-volatile memory (212) of the storage device (210).

[0090] For example, the electronic device (101) can reliably reboot the electronic device (101) even if the state of the power applied to the electronic device (101) is unstable, by bypassing the cache memory (211) and storing the data associated with booting directly in the non-volatile memory (212).

[0091] For example, the electronic device (101) can reliably store metadata regarding the file system (301) even if the state of the power applied to the electronic device (101) is unstable, by bypassing the cache memory (211) and storing the data containing at least part of the metadata directly in the non-volatile memory (212).

[0092] At least one processor (110) may refrain from transmitting a command associated with the second data (data 2) to the storage device (210). The storage device (210) may store the second data (data 2) in the non-volatile memory (212) via the cache memory (211) while the power state of the electronic device (101) satisfies the reference condition. For example, the electronic device (101) may increase the data input / output speed of the storage device (210) by storing the second data (data 2) in the non-volatile memory (212) of the storage device (210) via the cache memory (211).

[0093] In one embodiment, the operation of storing the first data (data 1) shown in FIG. 8 in the non-volatile memory (212) by bypassing the cache memory (211) and the operation of storing the second data (data 2) in the non-volatile memory (212) through the cache memory (211) can be performed regardless of the power state of the electronic device (101). For example, the electronic device (101) can selectively perform the operation of bypassing the cache memory (211) depending on whether the data to be transmitted to the storage device (210) satisfies the condition for bypassing, while the cache memory (211) is in an activated (enabled) state, regardless of the power state of the electronic device (101). A method of selectively bypassing the cache memory (211) regardless of the power state is described with reference to FIG. 9.

[0094] FIG. 9 is a flowchart illustrating an example of an operation method for selectively bypassing cache memory based on commands associated with data.

[0095] Referring to FIG. 9, in operation 901, at least one processor (110) can identify data to be transmitted to a storage device (210).

[0096] In operation 902, at least one processor (110) can identify whether the data to be transferred to the storage device (210) satisfies the conditions for bypassing the cache memory (211). For example, the data satisfying the conditions for bypassing may be associated with the booting of the electronic device (101). For example, the data satisfying the conditions for bypassing may include at least a portion of metadata stored in files identified according to the file system (301). The metadata may be in a state where it is cached in the cache memory associated with at least one processor (110) by at least one processor (110).

[0097] For example, data satisfying the conditions for the above bypass may include metadata associated with the booting of the electronic device (101). For example, the metadata may include information regarding the file system (301) and / or the attributes of the file. For example, the metadata may include information regarding the file system superblock, checkpoint, block, and / or file allocation. The information regarding the file system superblock may include information regarding the type, size, and / or number of available blocks of the file system (301). The information regarding the checkpoint may include information regarding the time at which a change to the file occurs, identified based on the file system (301). The information regarding the block may include information regarding the size of the block, which is a unit for physically storing data in the file system (301), and / or the address of the block. The information regarding the file allocation may include information regarding the type of the file allocated to the block.

[0098] According to an embodiment, at least one processor (110) can increase the reliability of data stored in a storage device (210) by setting the metadata satisfying the condition for bypassing information regarding the inode of the file and / or the inode of the directory associated with the file. The information regarding the inode of the file may include information regarding the type of the file, the size of the file, and / or the storage location of the data contained in the file. The directory may be described as a file for managing the file or other directories. The information regarding the inode of the directory may include information regarding the type of the directory, the size of the directory, and / or the storage location of the data contained in the directory. For example, a file system (301) may be described as software stored in memory (120) (e.g., storage device (210)) which is executed by at least one processor (110).

[0099] For example, data that does not satisfy the above conditions for bypassing may be described as data that is not associated with the booting of the electronic device (101) and is not metadata. However, it is not necessarily limited thereto. For example, the data that does not satisfy the above conditions for bypassing may include at least some metadata. For example, at least one processor (110) may set the metadata that satisfies the above conditions for bypassing in various ways. For example, at least one processor (110) may set the metadata using a file (e.g., sysfs node) for dynamic configuration changes of an operating system (e.g., linux).

[0100] For example, at least one processor (110) may apply default settings at the time of compilation or loading of a module regarding the file system (301) and set an indication (e.g., a setting value) for a file of a defined type. For example, at least one processor (110) may identify whether the metadata satisfies the condition for bypassing based on the indication associated with the metadata. For example, the indication associated with the metadata may have a value indicating the type of metadata to bypass the cache memory (211).

[0101] For example, at least one processor (110) may identify a first part of the metadata as the data to be transmitted based on the indication associated with the metadata. At least one processor (110) may transmit the first part of the metadata and a command associated with the first part of the metadata (e.g., a command to bypass the cache memory, to be described later) to the storage device (210). The first part of the metadata may be stored in the non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211). For example, at least one processor (110) may transmit the second part of the metadata to the storage device (210) by refraining from transmitting the command associated with the second part of the metadata. The second part of the metadata may be stored in the non-volatile memory (212) of the storage device (210) via the cache memory (211).

[0102] For example, the value of the above indication may be stored in two or more files (file ( / sys / fs / f2fs / fua_write / global) and file ( / sys / fs / f2fs / fua_write / node)). For example, if the value stored in file ( / sys / fs / f2fs / fua_write / global) corresponds to '1', the command may be applied to the file system superblock, checkpoint, block, and file allocation. For example, the value of the default setting for the two or more files may correspond to '0', indicating that the command is not applied. For example, if the value stored in file ( / sys / fs / f2fs / fua_write / node) corresponds to '1', the command may be applied to the inode of the file and the inode of the directory associated with the file. For example, if the above value stored in the file ( / sys / fs / f2fs / fua_write / node) corresponds to '2', the above command can be applied to the inode of the directory associated with the said file. For example, the value of the above default setting regarding the said files may correspond to '0', indicating that the above command is not applied.

[0103] As another example, the value of the above indication may be set through a format (e.g., 0:2, 1:0, 1:1, or 1:2) defined in a file ( / sys / fs / f2fs / fua_write / options).

[0104] In operation 903, at least one processor (110) may transmit the data and the command associated with the data to the storage device (210) based on the fact that the data to be transmitted satisfies the condition for bypassing. The command may be used to store the data in the non-volatile memory (212) of the storage device (210) by bypassing the cache memory (211). At least one processor (110) may transmit the data satisfying the condition for bypassing to the storage device (210) as associated with transmitting the command to the storage device (210). For example, at least one processor (110) may cause the storage device (210) to store the data satisfying the condition based on the command in the non-volatile memory (212) by bypassing the cache memory (211). For example, the above command can be described as a force unit access (FUA) command (e.g., force unit access write) for bypassing the cache memory (211) included in the storage device (210).

[0105] For example, the data satisfying the above conditions for bypassing may be associated with the booting of the electronic device (101). For example, at least one processor (110) may set data associated with the booting of the electronic device (101), including at least a portion of data regarding the booting process of the electronic device (101) and / or at least a portion of data regarding an application for booting the electronic device (101). The method of operation by at least one processor (110) for setting the data associated with booting may be described in various ways according to the embodiments. As an example without limitation, at least one processor (110) may apply an identification number defined for the data associated with booting to set the data associated with booting. For example, at least one processor (110) may designate services and applications affecting the booting of the electronic device (101) as a defined process group (e.g., boot_group) and apply the identification number to the defined process group. For example, data in a file stored in the process group to which the identification number is applied may bypass the cache memory (211) based on the command. For example, the defined process group may be changed while the electronic device (101) is performing an operation based on a file (e.g., sysfs node) for dynamic configuration changes of the operating system (e.g., linux).

[0106] At least one processor (110) may transmit the command to the storage device (210) for all data within a file stored in the defined process group as described above. According to an embodiment, at least one processor (110) may transmit the command to the storage device (210) only for data within a file having a reference type (e.g., reference extension) among the files stored in the defined process group.

[0107] For example, at least one processor (110) can identify files associated with booting the electronic device (101) according to a file system (301). Data stored in the files identified according to the file system (301) may be cached by at least one processor (110) in a cache memory associated with at least one processor (110). At least one processor (110) can identify data stored in at least one file of a reference type among the files as the data associated with booting. For example, the reference type may be described as a reference file extension such as a file extension (.xml), a file extension (.db), and a file extension (.key). For example, the reference type may be changed while the electronic device (101) is performing an operation based on a file (e.g., sysfs node) for dynamic configuration changes of an operating system (e.g., linux). For example, the above reference type may be set based on a format (e.g., xml:db:key:...) defined in a file (sys / fs / f2fs / fua_write / file_extensions). For example, data contained in a file (abc.xml), a file (ddd.xml), and a file (data.db) may bypass the cache memory (211) based on the above command. As another example, at least one processor (110) may process the above command by using a system call (e.g., an ioctl system call) on the file when the application saves a file having a file extension (.xml) and a file extension (.db). At least one processor (110) may transmit the data stored in the at least one file and the above command associated with the data to the storage device (210).

[0108] For example, the data associated with the above command may include at least a portion of metadata stored in files identified according to the file system (301). The metadata may be cached in a cache memory associated with at least one processor (110) by at least one processor (110).

[0109] In operation 904, the storage device (210) can store data provided by at least one processor (110) in non-volatile memory (212) by bypassing the cache memory (211) based on receiving the command associated with the data satisfying the condition for bypassing the cache memory (211).

[0110] In operation 905, at least one processor (110) may refrain from transmitting the command associated with the data to be transmitted to the storage device (210) based on the fact that the data to be transmitted does not satisfy the condition for bypassing.

[0111] In operation 906, at least one processor (110) can control the storage device (210) to store data that does not satisfy the conditions for bypassing in the non-volatile memory (212) of the storage device (210) via the cache memory (211). The data may be provided from at least one processor (110). The data may be stored in the non-volatile memory (212) of the storage device (210) via the cache memory (211).

[0112] The electronic device (101) may correspond to the electronic device (1001) described with reference to FIG. 10 below.

[0113] FIG. 10 is a block diagram of an electronic device in a network environment according to various embodiments.

[0114] Referring to FIG. 10, in a network environment (1000), an electronic device (1001) may communicate with an electronic device (1002) through a first network (1098) (e.g., a short-range wireless communication network) or with at least one of an electronic device (1004) or a server (1008) through a second network (1099) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (1001) may communicate with the electronic device (1004) through a server (1008). According to one embodiment, the electronic device (1001) may include a processor (1020), memory (1030), input module (1050), sound output module (1055), display module (1060), audio module (1070), sensor module (1076), interface (1077), connection terminal (1078), haptic module (1079), camera module (1080), power management module (1088), battery (1089), communication module (1090), subscriber identification module (1096), or antenna module (1097). In some embodiments, at least one of these components (e.g., connection terminal (1078)) may be omitted from the electronic device (1001), or one or more other components may be added. In some embodiments, some of these components (e.g., sensor module (1076), camera module (1080), or antenna module (1097)) may be integrated into a single component (e.g., display module (1060)).

[0115] The processor (1020) can, for example, execute software (e.g., program (1040)) to control at least one other component (e.g., hardware or software component) of the electronic device (1001) connected to the processor (1020) and can perform various data processing or operations. According to one embodiment, as at least part of the data processing or operations, the processor (1020) can store commands or data received from other components (e.g., sensor module (1076) or communication module (1090)) in volatile memory (1032), process the commands or data stored in volatile memory (1032), and store the resulting data in non-volatile memory (1034). According to one embodiment, the processor (1020) may include a main processor (1021) (e.g., a central processing unit or an application processor) or an auxiliary processor (1023) that can operate independently or together with it (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, if the electronic device (1001) includes a main processor (1021) and an auxiliary processor (1023), the auxiliary processor (1023) may be configured to use less power than the main processor (1021) or to be specialized for a designated function. The auxiliary processor (1023) may be implemented separately from the main processor (1021) or as part thereof.

[0116] The auxiliary processor (1023) may control at least some of the functions or states associated with at least one component of the electronic device (1001) (e.g., display module (1060), sensor module (1076), or communication module (1090)) on behalf of the main processor (1021) while the main processor (1021) is in an inactive (e.g., sleep) state, or together with the main processor (1021) while the main processor (1021) is in an active (e.g., application execution) state. According to one embodiment, the auxiliary processor (1023) (e.g., image signal processor or communication processor) may be implemented as part of another functionally related component (e.g., camera module (1080) or communication module (1090)). According to one embodiment, the auxiliary processor (1023) (e.g., neural network processing unit) may include a hardware structure specialized for processing an artificial intelligence model. The artificial intelligence model may be generated through machine learning. Such learning may be performed, for example, on the electronic device (1001) itself where the artificial intelligence model is executed, or through a separate server (e.g., server (1008)). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model may include a plurality of artificial neural network layers.An artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to the hardware structure, the artificial intelligence model may include a software structure, either additionally or substantially.

[0117] The memory (1030) can store various data used by at least one component of the electronic device (1001) (e.g., processor (1020) or sensor module (1076)). The data may include, for example, input data or output data for software (e.g., program (1040)) and related commands. The memory (1030) may include volatile memory (1032) or non-volatile memory (1034).

[0118] The program (1040) may be stored as software in memory (1030) and may include, for example, an operating system (1042), middleware (1044), or an application (1046).

[0119] The input module (1050) can receive commands or data to be used for a component of the electronic device (1001) (e.g., processor (1020)) from outside the electronic device (1001) (e.g., user). The input module (1050) may include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0120] The sound output module (1055) can output a sound signal to the outside of the electronic device (1001). The sound output module (1055) may include, for example, a speaker or a receiver. The speaker may be used for general purposes, such as multimedia playback or recording playback. The receiver may be used to receive incoming calls. According to one embodiment, the receiver may be implemented separately from the speaker or as part thereof.

[0121] The display module (1060) can visually provide information to an external (e.g., user) of the electronic device (1001). The display module (1060) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling said device. According to one embodiment, the display module (1060) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of the force generated by said touch.

[0122] The audio module (1070) can convert sound into an electrical signal or, conversely, convert an electrical signal into sound. According to one embodiment, the audio module (1070) can acquire sound through an input module (1050) or output sound through an audio output module (1055) or an external electronic device (e.g., electronic device (1002)) (e.g., speaker or headphones) connected directly or wirelessly to the electronic device (1001).

[0123] The sensor module (1076) can detect the operating state of the electronic device (1001) (e.g., power or temperature) or the external environmental state (e.g., user state) and generate an electrical signal or data value corresponding to the detected state. According to one embodiment, the sensor module (1076) may include, for example, a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0124] The interface (1077) may support one or more specified protocols that can be used for the electronic device (1001) to be connected directly or wirelessly to an external electronic device (e.g., electronic device (1002)). According to one embodiment, the interface (1077) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0125] The connection terminal (1078) may include a connector through which the electronic device (1001) can be physically connected to an external electronic device (e.g., electronic device (1002)). According to one embodiment, the connection terminal (1078) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0126] The haptic module (1079) can convert an electrical signal into a mechanical stimulus (e.g., vibration or movement) or an electrical stimulus that can be perceived by the user through tactile or kinesthetic senses. According to one embodiment, the haptic module (1079) may include, for example, a motor, a piezoelectric element, or an electric stimulation device.

[0127] The camera module (1080) can capture still images and video. According to one embodiment, the camera module (1080) may include one or more lenses, image sensors, image signal processors, or flashes.

[0128] The power management module (1088) can manage power supplied to the electronic device (1001). According to one embodiment, the power management module (1088) can be implemented, for example, as at least part of a power management integrated circuitry (PMIC).

[0129] The battery (1089) can supply power to at least one component of the electronic device (1001). According to one embodiment, the battery (1089) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0130] The communication module (1090) can support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between an electronic device (1001) and an external electronic device (e.g., electronic device (1002), electronic device (1004), or server (1008)), and the performance of communication through the established communication channel. The communication module (1090) may include one or more communication processors that operate independently of the processor (1020) (e.g., application processor) and support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (1090) may include a wireless communication module (1092) (e.g., cellular communication module, short-range wireless communication module, or GNSS (global navigation satellite system) communication module) or a wired communication module (1094) (e.g., LAN (local area network) communication module, or power line communication module). The corresponding communication module among these communication modules can communicate with an external electronic device (1004) through a first network (1098) (e.g., a short-range communication network such as Bluetooth, WiFi (wireless fidelity) direct, or IrDA (infrared data association)) or a second network (1099) (e.g., a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules may be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (1092) can identify or authenticate the electronic device (1001) within a communication network such as the first network (1098) or the second network (1099) using subscriber information (e.g., International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module (1096).

[0131] The wireless communication module (1092) can support 5G networks and next-generation communication technologies following 4G networks, for example, new radio access technology. NR access technology can support high-speed transmission of high-capacity data (enhanced mobile broadband (eMBB)), minimization of terminal power and connection of multiple terminals (massive machine type communications (mMTC)), or high reliability and low latency (ultra-reliable and low-latency communications (URLLC)). The wireless communication module (1092) can support a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate, for example. The wireless communication module (1092) can support various technologies for securing performance in the high-frequency band, such as beamforming, massive MIMO (multiple-input and multiple-output), full-dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large-scale antenna. The wireless communication module (1092) can support various requirements specified in the electronic device (1001), external electronic device (e.g., electronic device (1004)), or network system (e.g., second network (1099)). According to one embodiment, the wireless communication module (1092) may support a Peak data rate (e.g., 20 Gbps or more) for eMBB realization, loss coverage (e.g., 164 dB or less) for mMTC realization, or U-plane latency (e.g., downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less) for URLLC realization.

[0132] An antenna module (1097) can transmit a signal or power to or from an external source (e.g., an external electronic device). According to one embodiment, the antenna module (1097) may include an antenna comprising a radiator made of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (1097) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as a first network (1098) or a second network (1099), may be selected from the plurality of antennas, for example, by a communication module (1090). A signal or power may be transmitted or received between the communication module (1090) and an external electronic device through the selected at least one antenna. According to some embodiments, in addition to the radiator, other components (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as part of the antenna module (1097).

[0133] According to various embodiments, the antenna module (1097) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent to a first surface (e.g., bottom surface) of the printed circuit board and capable of supporting a specified high frequency band (e.g., mmWave band), and a plurality of antennas (e.g., array antennas) disposed on or adjacent to a second surface (e.g., top surface or side surface) of the printed circuit board and capable of transmitting or receiving a signal of the specified high frequency band.

[0134] At least some of the above components can be connected to each other via a communication method between peripheral devices (e.g., bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)) and exchange signals (e.g., commands or data) with each other.

[0135] According to one embodiment, commands or data may be transmitted or received between an electronic device (1001) and an external electronic device (1004) through a server (1008) connected to a second network (1099). Each of the external electronic devices (1002, or 1004) may be the same or a different type of device as the electronic device (1001). According to one embodiment, all or part of the operations performed on the electronic device (1001) may be performed on one or more of the external electronic devices (1002, 1004, or 1008). For example, if the electronic device (1001) needs to perform a function or service automatically or in response to a request from a user or another device, the electronic device (1001) may request one or more external electronic devices to perform at least part of the function or service instead of performing the function or service itself or additionally. One or more external electronic devices that receive the above request may execute at least part of the requested function or service, or additional function or service related to the request, and transmit the result of the execution to the electronic device (1001). The electronic device (1001) may provide the result as is or additionally processed as at least part of the response to the request. For this purpose, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device (1001) may provide ultra-low latency services using, for example, distributed computing or mobile edge computing. In one embodiment, the external electronic device (1004) may include an Internet of Things (IoT) device. The server (1008) may be an intelligent server using machine learning and / or neural networks.According to one embodiment, an external electronic device (1004) or server (1008) may be included within the second network (1099). The electronic device (1001) may be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0136] The technical problems to be solved in this disclosure are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art to which this disclosure belongs.

[0137] As described above, an electronic device (e.g., electronic device (101)) may include at least one processor (e.g., at least one processor (110)) comprising a processing circuit; and a memory (e.g., memory (120)) that stores instructions and includes one or more storage devices. The one or more storage devices may include a storage device (e.g., storage device (210)) that includes a cache memory (e.g., cache memory (211)). When the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to transmit a command from the at least one processor to the storage device to disable the cache memory based on the power state that satisfies a reference condition.

[0138] For example, the command to disable the cache memory may be configured to control the storage device to store data provided from the at least one processor in the storage device by bypassing the cache memory. For example, when the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to control the storage device to store data provided from the at least one processor in the storage device through the cache memory, based on the power state that does not satisfy the reference condition.

[0139] For example, when the above instructions are executed individually or collectively by the at least one processor: if the power state does not satisfy the reference condition, the electronic device may be caused to store data provided from the at least one processor in the storage device through the cache memory.

[0140] For example, when the above instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to detect a power-off sequence of the electronic device that has started or is to be started. The power-off sequence may be performed to stop or terminate the supply of power to the electronic components of the electronic device. When the above instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to identify the power state as satisfying the reference condition based on the detection.

[0141] For example, when the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to identify metadata stored in files identified according to a file system (e.g., file system (301)). The metadata may be cached by the at least one processor. When the instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to transmit at least a portion of the metadata as data from the at least one processor to the storage device, after transmitting the command from the at least one processor to the storage device based on the power state satisfying the reference condition.

[0142] For example, the above instructions may cause the electronic device to: identify an update of at least one software application of the electronic device that has been performed or is to be performed when executed individually or collectively by the at least one processor; and detect the power-off sequence of the electronic device to be started based on the update of the at least one software application.

[0143] For example, when the above instructions are executed individually or collectively by the at least one processor: to identify a user input to turn off the electronic device; and to cause the electronic device to detect the power-off sequence of the electronic device that has been started or is to be started based on the user input.

[0144] For example, the electronic device may further include a rechargeable battery (e.g., battery (140)) that supplies power to the storage device. When the instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to identify the state of charge (SoC) of the rechargeable battery; and identify the power state of the electronic device as satisfying the reference condition based on the SoC being lower than a threshold value.

[0145] For example, when the above instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to identify a voltage from an external power source; and identify the power state of the electronic device as satisfying the reference condition based on the voltage that is lower than a threshold voltage.

[0146] As described above, an electronic device (e.g., electronic device (101)) may include at least one processor (e.g., at least one processor (110)) comprising a processing circuit; and a memory (e.g., memory (120)) that stores instructions and includes one or more storage devices. The one or more storage devices may include a storage device (e.g., storage device (210)) that includes a cache memory (e.g., cache memory (211)). The instructions may cause the electronic device to transmit data and a command associated with said data from the at least one processor to said storage device, based on the power state that satisfies a reference condition, when executed individually or collectively by the at least one processor: identifying the power state of said electronic device; and based on said power state that satisfies a reference condition. The command may be used to store said data in said storage device by bypassing the cache memory.

[0147] For example, the data may be a first data comprising at least a portion of metadata stored within files identified according to a file system (e.g., file system (301)). The metadata may be cached by the at least one processor. The instructions may cause the electronic device to transmit second data from the at least one processor to the storage device and refrain from transmitting the command associated with the second data when executed individually or collectively by the at least one processor: while the power state satisfies the reference condition. The second data may be stored in the storage device through the cache memory.

[0148] For example, when the above instructions are executed individually or collectively by the at least one processor, the electronic device may be caused to identify metadata stored within files identified according to a file system. The metadata may be cached by the at least one processor. When the above instructions are executed individually or collectively by the at least one processor, while the power state satisfies the reference condition, the electronic device may be caused to identify a first part of the metadata as the data to be transmitted based on an indication associated with the metadata, transmit the first part of the metadata and the command associated with the first part of the metadata from the at least one processor to the storage device, and transmit the second part of the metadata from the at least one processor to the storage device by refraining from transmitting the command associated with the second part of the metadata. The first part of the metadata may be stored in the storage device by bypassing the cache memory. The second part of the above metadata can be stored in the storage device through the cache memory.

[0149] For example, the above data may be associated with the booting of the electronic device.

[0150] For example, when the above instructions are executed individually or collectively by the at least one processor, the electronic device may be configured to identify files identified according to a file system. Data stored in the files may be cached by the at least one processor. When the above instructions are executed individually or collectively by the at least one processor, while the power state satisfies the reference condition, the electronic device may be configured to identify at least one file of a reference type among the files and to transmit the data stored in the at least one file and the command associated with the data.

[0151] For example, data provided from the at least one processor may be stored in the storage device via the cache memory while the power state does not satisfy the reference condition.

[0152] For example, when the above instructions are executed individually or collectively by the at least one processor: the electronic device may be caused to control the storage device to store data provided from the at least one processor through the cache memory in the storage device based on the power state that does not satisfy the reference condition.

[0153] For example, when the above instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to detect a power-off sequence of the electronic device that has started or is to be started. The power-off sequence may be performed to stop or terminate the supply of power to the electronic components of the electronic device. When the above instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to identify the power state as satisfying the reference condition based on the detection.

[0154] For example, the electronic device may further include a rechargeable battery (e.g., battery (140)) that supplies power to the storage device. When the instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to identify the state of charge (SoC) of the rechargeable battery; and identify the power state of the electronic device as satisfying the reference condition based on the SoC being lower than a threshold value.

[0155] For example, when the above instructions are executed individually or collectively by the at least one processor, they may cause the electronic device to identify a voltage from an external power source; and identify the power state of the electronic device as satisfying the reference condition based on the voltage that is lower than a threshold voltage.

[0156] A non-transient computer-readable storage medium as described above may store one or more programs. The one or more programs may include instructions that cause the electronic device (e.g., electronic device (101)) to identify the power state of the electronic device when executed by the electronic device having a storage device (e.g., storage device (210)) comprising at least one processor (e.g., at least one processor (110)) and a cache memory (e.g., cache memory (211)). The one or more programs may include instructions that cause the electronic device to transmit a command to disable the cache memory from the at least one processor to the storage device based on the power state satisfying a reference condition when executed by the electronic device.

[0157] For example, the command to disable the cache memory may be configured to control the storage device to store data provided from the at least one processor by bypassing the cache memory.

[0158] For example, the above one or more programs may include instructions that cause the electronic device to store data provided from the at least one processor in the storage device through the cache memory when executed by the electronic device: if the power state does not satisfy the reference condition.

[0159] For example, the above one or more programs may include instructions that, when executed by the electronic device: detect a power-off sequence of the electronic device that has been started or is to be started, said power-off sequence is performed to cease or terminate the supply of power to the electronic components of the electronic device; and, based on said detection, cause the electronic device to identify the power state as satisfying said reference condition.

[0160] For example, the above one or more programs may include instructions that, when executed by the electronic device: identify metadata stored in files identified according to a file system, said metadata is cached by said at least one processor; and, based on said power state satisfying said reference condition, cause said electronic device to transmit at least a portion of said metadata as said data from said at least one processor to said storage device after transmitting said command from said at least one processor to said storage device.

[0161] For example, the above one or more programs may include instructions that cause the electronic device to: identify the state of charge (SoC) of a rechargeable battery included in the electronic device when executed by the electronic device; and identify the power state of the electronic device as satisfying the reference condition based on the SoC being lower than a threshold value.

[0162] A non-transient computer-readable storage medium as described above may store one or more programs. The one or more programs may include instructions that cause the electronic device to identify the power state of the electronic device when executed by the electronic device (e.g., electronic device (101)) having a storage device (e.g., storage device (210)) comprising at least one processor (e.g., at least one processor (110)) and a cache memory (e.g., cache memory (211)). The one or more programs may include instructions that cause the electronic device to transmit data and a command associated with said data from the at least one processor to the storage device based on the power state satisfying a reference condition when executed by the electronic device. The command may be used to store said data in the storage device by bypassing the cache memory.

[0163] The effects obtainable from the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present disclosure belongs.

[0164] The electronic device according to the various embodiments disclosed in this document may be of various forms. The electronic device may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a consumer electronics device. The electronic device according to the embodiments of this document is not limited to the devices described above.

[0165] The various embodiments of this document and the terms used therein are not intended to limit the technical features described in this document to specific embodiments, and should be understood to include various modifications, equivalents, or substitutions of said embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of said items unless the relevant context clearly indicates otherwise. In this document, phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B or C," "at least one of A, B and C," and "at least one of A, B, or C" may each include any one of the items listed together in the corresponding phrase, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used simply to distinguish said components from other said components and do not limit said components in any other aspect (e.g., importance or order). Where any (e.g., 1st) component is referred to as "coupled" or "connected" to another (e.g., 2nd) component, with or without the terms "functionally" or "communicationly," it means that said any component may be connected to said other component directly (e.g., via a wire), wirelessly, or through a third component.

[0166] The term “module” as used in the various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit, for example. A module may be a component formed integrally, or a minimum unit of said component or a part thereof that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0167] Various embodiments of the present document may be implemented as software (e.g., program (1040)) comprising one or more instructions stored in a storage medium (e.g., internal memory (1036) or external memory (1038)) readable by a machine (e.g., electronic device (1001)). For example, a processor (e.g., processor (1020)) of the machine (e.g., electronic device (1001)) may call at least one of the one or more instructions stored from the storage medium and execute it. This enables the machine to be operated to perform at least one function according to the at least one called instruction. The one or more instructions may include code generated by a compiler or code that can be executed by an interpreter. The storage medium readable by the machine may be provided in the form of a non-transitory storage medium. Here, 'non-temporary' simply means that the storage medium is a tangible device and does not contain a signal (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily.

[0168] According to one embodiment, the method according to the various embodiments disclosed herein may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily created on a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0169] According to various embodiments, each component (e.g., module or program) of the components described above may include a singular or multiple entities, and some of the multiple entities may be separated and placed in other components. According to various embodiments, one or more of the components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Generally or additionally, multiple components (e.g., module or program) may be integrated into a single component. In this case, the integrated component may perform one or more functions of each of the multiple components in the same or similar manner as those performed by the corresponding component among the multiple components prior to integration. According to various embodiments, operations performed by the module, program, or other components may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

Claims

1. In an electronic device, At least one processor including a processing circuit; and Memory that stores instructions and includes one or more storage devices, The above one or more storage devices include a storage device including a cache memory, and When the above instructions are executed individually or collectively by the at least one processor: Identifying the power status of the above electronic device; and Based on the power state satisfying the reference condition, to transmit a command to disable the cache memory from the at least one processor to the storage device, The above electronic device, causing, Electronic device.

2. In claim 1, the command to disable the cache memory is configured to control the storage device to store data provided from the at least one processor by bypassing the cache memory, Electronic device.

3. In claim 1, when the instructions are executed individually or collectively by at least one processor: If the above power state does not satisfy the above reference condition, the data provided from the at least one processor is stored in the storage device through the cache memory. The above electronic device, causing, Electronic device.

4. In claim 1, when the instructions are executed individually or collectively by the at least one processor: Detecting a power-off sequence of the electronic device that has started or is to be started, and the power-off sequence is performed to stop or terminate the supply of power to the electronic components of the electronic device; and Based on the above detection, to identify the power state as satisfying the above standard condition, The above electronic device, causing, Electronic device.

5. In claim 4, when the instructions are executed individually or collectively by the at least one processor: Identifying metadata stored within files identified according to a file system, wherein the metadata is cached by the at least one processor; and Based on the power state satisfying the above standard condition, after transmitting the command from the at least one processor to the storage device, at least a portion of the metadata is transmitted as data from the at least one processor to the storage device. The above electronic device, causing, Electronic device.

6. In claim 4, when the instructions are executed individually or collectively by at least one processor: Identifying at least one software application update of the electronic device that has been performed or will be performed; and To detect the power-off sequence of the electronic device to be started based on the update of the at least one software application, The above electronic device, causing, Electronic device.

7. In claim 4, when the instructions are executed individually or collectively by at least one processor: Identifying user input for turning off the above electronic device; and To detect the power-off sequence of the electronic device that has started or will start based on the above user input, The above electronic device, causing, Electronic device.

8. In claim 1, the electronic device further comprises a rechargeable battery that supplies power to the storage device, and When the above instructions are executed individually or collectively by the at least one processor: Identify the state of charge (SoC) of the above-mentioned rechargeable battery; and To identify the power state of the electronic device as satisfying the reference condition based on the above SoC which is lower than the threshold value, The above electronic device, causing, Electronic device.

9. In claim 1, when the instructions are executed individually or collectively by at least one processor: Identifying voltage from an external power source; and To identify the power state of the electronic device as satisfying the reference condition based on the above voltage which is lower than the threshold voltage, The above electronic device, causing, Electronic device.

10. In a non-transient computer-readable storage medium storing one or more programs, said one or more programs when executed by an electronic device having a storage device comprising at least one processor and a cache memory: Identifying the power status of the above electronic device; and Based on the power state satisfying the reference condition, to transmit a command to disable the cache memory from the at least one processor to the storage device, Instructions including those that cause the above electronic device Non-transient computer-readable storage media.

11. In claim 10, the command to disable the cache memory is configured to control the storage device to store data provided from the at least one processor by bypassing the cache memory, Non-transient computer-readable storage media.

12. In claim 10, the one or more programs, when executed by the electronic device: If the above power state does not satisfy the above reference condition, the data provided from the at least one processor is stored in the storage device through the cache memory. Instructions including those that cause the above electronic device Non-transient computer-readable storage media.

13. In claim 10, the one or more programs, when executed by the electronic device: Detecting a power-off sequence of the electronic device that has started or is to be started, and the power-off sequence is performed to stop or terminate the supply of power to the electronic components of the electronic device; and Based on the above detection, to identify the power state as satisfying the above standard condition, Instructions including those that cause the above electronic device Non-transient computer-readable storage media.

14. In claim 13, the one or more programs, when executed by the electronic device: Identifying metadata stored within files identified according to a file system, wherein the metadata is cached by the at least one processor; and Based on the power state satisfying the above standard condition, after transmitting the command from the at least one processor to the storage device, at least a portion of the metadata is transmitted as data from the at least one processor to the storage device. Instructions including those that cause the above electronic device Non-transient computer-readable storage media.

15. In claim 10, the one or more programs, when executed by the electronic device: Identifying the state of charge (SoC) of a rechargeable battery included in the electronic device; and To identify the power state of the electronic device as satisfying the reference condition based on the above SoC which is lower than the threshold value, Instructions including those that cause the above electronic device Non-transient computer-readable storage media.

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