Array substrate, display panel and display panel mother substrate
By setting intermediate redundant gate test pads in the array substrate and the display panel motherboard, the problem of low mask utilization efficiency in the production of large-size TV panels is solved, achieving high production efficiency and cost reduction.
WO2026113076A1PCT designated stage Publication Date: 2026-06-04TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-04
Smart Images
Figure CN2024140345_04062026_PF_FP_ABST
Abstract
The present application relates to an array substrate, a display panel and a display panel mother substrate. When a gate test pad is provided around an outer bonding region, an intermediate redundant gate test pad is additionally provided around an intermediate bonding region. Patterns around the intermediate bonding region and patterns around the outer bonding region tend to be the same. The patterns around the outer bonding region and the patterns around the intermediate bonding region may be prepared by means of stitching masks, thereby reducing the number of mask exposures during the fabrication of the array substrate and the display panel.
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