Method for manufacturing semiconductor package

Abstract

This method for manufacturing a semiconductor package comprises: preparing a circuit member including a semiconductor substrate and a plurality of terminal electrodes; disposing a curable resin film on a terminal electrode side of the circuit member; disposing a pressing member having a flat surface on the opposite side of the curable resin film to the circuit member in an orientation such that the flat surface is positioned on the curable resin film side; and heating the curable resin film while pressing the circuit member and the curable resin film so that the pressing member is pressed against the curable resin film, thereby attaching the curable resin film to the circuit member so as to cover the plurality of terminal electrodes and enter between adjacent terminal electrodes.

Description

Method for manufacturing a semiconductor package

[0001] The present disclosure relates to a method for manufacturing a semiconductor package.

[0002] In recent years, with the rapid increase in functionality of electronic devices represented by AI / HPC, etc., the size and density of semiconductor packages have been rapidly increasing. Regarding the structure of semiconductor packages, not only the density of surface mounting has increased, but also the technology of inorganic (silicon) interposers or organic interposers (Bridge die / RDL), and the implementation process has become more complex and diverse with the use of 2.xD implementation and 3D implementation technology (HBM / Chiplet) using TSV, etc. For example, Resonac Co., Ltd. is mainly based on the "Packaging Solution Center" and is developing the technology of the next-generation semiconductor packaging process from the perspective of customers (semiconductor manufacturers) by combining implementation processes and materials.

[0003] As a technology in the field of semiconductor packages, Patent Document 1 discloses a method for manufacturing a semiconductor device in which a semiconductor die is mounted face-up on a carrier and sealed, a wiring layer is formed on the sealing layer, and another semiconductor die is further mounted on the wiring layer. Patent Document 2 discloses a method for manufacturing another semiconductor device.

[0004] U.S. Patent Application Publication No. 2021 / 0098421 Specification, U.S. Patent Application Publication No. 2022 / 0093526 Specification

[0005] The present disclosure relates to stably disposing a circuit member having a semiconductor substrate and terminal electrodes on a base material in the manufacture of a semiconductor package.

[0006] This disclosure includes: [1] preparing a circuit member including a semiconductor substrate having a first surface and a second surface on the back thereof, and a plurality of terminal electrodes provided on the first surface of the semiconductor substrate; arranging a curable resin film on the terminal electrode side of the circuit member; arranging a pressing member having a flat surface on the side of the curable resin film opposite to the circuit member, with the flat surface facing the curable resin film; heating the curable resin film while applying pressure to the circuit member so that the pressing member presses against the curable resin film, thereby attaching the curable resin film to the circuit member so that it covers the plurality of terminal electrodes and fits between adjacent terminal electrodes; curing the curable resin film to form a cured resin layer, which is the cured curable resin film, on the circuit member; and holding the circuit member and the cured resin layer with a holding member adsorbed to the cured resin layer. A method for manufacturing a semiconductor package, comprising: placing the circuit member and the cured resin layer, held by the holding member, on a substrate; and then separating the holding member from the cured resin layer. [2] The method according to [1], further comprising separating the circuit member together with the cured resin layer, wherein the separated circuit member and the cured resin layer are held by the holding member and placed on the substrate. [3] The method according to [1] or [2], further comprising forming a sealing layer on the substrate that seals the circuit member placed on the substrate. [4] The method according to [3], further comprising removing a portion of the sealing layer and the cured resin layer from the side opposite to the substrate, thereby exposing the tips of a plurality of terminal electrodes. [5] The method according to [3] or [4], further comprising mounting a plurality of semiconductor components having semiconductor dies on the terminal electrode side of the circuit member after the sealing layer has been formed, wherein two or more of the semiconductor components are electrically connected to each other via the circuit member.[6] The method according to [5], wherein the circuit member is arranged on the substrate in a orientation such that the terminal electrodes are located on the opposite side of the substrate, and the method further includes forming a wiring layer on the terminal electrode side of the circuit member after the sealing layer has been formed, the wiring layer including wiring electrically connected to the terminal electrodes, and a plurality of semiconductor components are mounted on the wiring layer on the opposite side of the circuit member. [7] The method according to [5], wherein the substrate has a temporary fixing layer, and the circuit member is arranged on the temporary fixing layer in a orientation such that the terminal electrodes are located on the substrate side, and the method further includes separating the substrate, the sealing layer and the circuit member after the sealing layer has been formed, and forming a wiring layer on the terminal electrode side of the circuit member including wiring electrically connected to the terminal electrodes, and a plurality of semiconductor components are mounted on the opposite side of the wiring layer to the circuit member. [8] The method according to [5], wherein the substrate comprises a temporary fixing layer and a wiring layer provided on the temporary fixing layer, the wiring layer including wiring, the circuit member is arranged on the wiring layer such that the terminal electrode is oriented toward the substrate side and the terminal electrode is electrically connected to the wiring of the wiring layer, the method further comprises separating the substrate and the wiring layer after the sealing layer has been formed, and after the substrate and the wiring layer have been separated, a plurality of semiconductor components are mounted on the wiring layer opposite to the circuit member. [9] The method according to any one of [1] to [8], wherein the tensile modulus of the cured resin layer at 25°C is 10 MPa or more.

[0007] In the manufacturing of semiconductor packages, circuit components having a semiconductor substrate and terminal electrodes can be stably placed on the substrate.

[0008] Figures 1(a) and 1(b) are cross-sectional views showing an example of a method for manufacturing a semiconductor package. Figures 2(a) and 2(b) are cross-sectional views showing an example of a method for manufacturing a semiconductor package. Figures 3(a) and 3(b) are cross-sectional views showing an example of a method for manufacturing a semiconductor package. Figures 4(a) and 4(b) are cross-sectional views showing an example of a method for manufacturing a semiconductor package. Figure 5 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 6 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 7 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 8 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 9 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 11 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 12 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 13 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package. Figure 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor package.

[0009] The present invention is not limited to the following examples. In the following description, the same or corresponding parts are denoted by the same reference numerals, and redundant descriptions may be omitted. Unless otherwise specified, positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. The dimensional ratios in the drawings are not limited to those shown.

[0010] In this specification, the term "layer" includes not only structures that are formed over the entire surface when observed in a plan view, but also structures that are formed in only a part of the surface. In this specification, the term "process" includes not only independent processes, but also processes in which the intended function of that process is achieved, even if it cannot be clearly distinguished from other processes.

[0011] In this specification, numerical ranges indicated using "~" represent a range that includes the numbers before and after "~" as the minimum and maximum values, respectively. In numerical ranges described in stages in this specification, the upper or lower limit of one stage of the numerical range may be replaced with the upper or lower limit of another stage of the numerical range. In numerical ranges described in this specification, the upper or lower limit of that numerical range may be replaced with the values ​​shown in the examples.

[0012] Figures 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, and 14 are cross-sectional views illustrating an example of a method for manufacturing a semiconductor package. The method shown in Figures 1 to 14 is an example of a method for manufacturing the semiconductor package 200 illustrated in Figure 14. The semiconductor package 200 comprises a package substrate 60 and a encapsulation structure 150 mounted on the package substrate 60. The encapsulation structure 150 includes a plurality of semiconductor components 51, 52, a circuit member 10 arranged to partially overlap the semiconductor components 51, 52 in the thickness direction of the encapsulation structure 150, a wiring layer 41 (hereinafter sometimes referred to as the "first wiring layer") provided between the circuit member 10 and the semiconductor components 51, 52, and a wiring layer 42 (hereinafter sometimes referred to as the "second wiring layer") provided on the side of the circuit member 10 opposite to the semiconductor components 51, 52. The circuit member 10 has a semiconductor substrate 11 and a plurality of terminal electrodes 12, and functions as a bridge die including a circuit that relays a plurality of semiconductor components 51, 52.

[0013] The method shown in Figures 1 to 14 includes preparing a circuit member 10 (Figure 1(a)) having a semiconductor substrate 11 and terminal electrodes 12; placing a curable resin film 20 (Figure 1(b)) on the terminal electrode 12 side of the circuit member 10; placing a pressurizing member 80 (Figure 2(a)) on the side S20 of the curable resin film 20 opposite to the circuit member 10; heating the curable resin film 20 while pressurizing the circuit member 10 and the curable resin film 20, thereby attaching the curable resin film 20 to the circuit member 10; curing the curable resin film 20 to form a curable resin layer 20C (Figure 3(a)) on the circuit member 10; holding the circuit member 10 and the curable resin layer 20C with a holding member 90 (Figure 4(a)); and placing the circuit member 10 and the curable resin layer 20C held by the holding member 90 on a base material 1 (Figure 5).

[0014] The semiconductor substrate 11 of the circuit member 10 shown in Figure 1(a) may be a semiconductor wafer (e.g., a silicon wafer) having a first surface S11 and a second surface S12 on the back side of the first surface, and including portions corresponding to a plurality of semiconductor dies. The first surface S11 and the second surface S12 of the semiconductor substrate 11 may be circular or rectangular. The semiconductor substrate 11 to which the curable resin film is attached may also be a semiconductor die formed by framing a semiconductor wafer.

[0015] A plurality of terminal electrodes 12 are provided on the first surface S11 of the semiconductor substrate 11. The terminal electrodes 12 are usually connected to wiring formed within the semiconductor substrate 11. The terminal electrodes 12 may be, for example, metal pillars such as copper pillars or metal bumps. The maximum width or diameter of the terminal electrodes 12 may be, for example, 10 μm or more and 50 μm or less. The terminal pitch (distance between terminal electrodes 12) may be, for example, 5 μm or more and 20 μm or less. The height of the terminal electrodes 12 from the first surface S11 may be, for example, 20 μm or more and 50 μm or less. The terminal pitch between terminal electrodes 12 means the shortest distance between the outer surfaces of adjacent terminal electrodes 12. The plurality of terminal electrodes 12 may include conductive vias that penetrate the semiconductor substrate 11.

[0016] In the example shown in Figure 1(a), the multiple terminal electrodes 12 are unevenly distributed in a portion of the first surface S11. In other words, the first surface S11 includes a first region where the multiple terminal electrodes 12 are provided, and a second region where the terminal electrodes 12 are not provided, or where the terminal electrodes 12 are provided at a lower density than in the first region. When the first surface S11 includes multiple regions with different densities of terminal electrodes 12, large steps tend to be easily formed on the surface of the cured resin layer 20C formed on the first surface S11. However, according to the method of this disclosure, even in such cases, a cured resin layer 20C having a surface with small steps can be easily formed.

[0017] As shown in Figure 1(b), the curable resin film 20 is positioned on the terminal electrode 12 side of the circuit member 10, facing the first surface S11. The curable resin film 20 may be placed on the circuit member 10 under conditions where the pressure it receives is below atmospheric pressure (for example, 0.101 MPa or less). The temperature of the curable resin film 20 when it is positioned on the terminal electrode 12 side of the circuit member 10 may be room temperature (for example, 10°C to 40°C). Before heating and pressurizing using the pressurizing member 80, a gap may remain between the semiconductor substrate 11 and the curable resin film 20, particularly between adjacent terminal electrodes 12. The thickness of the curable resin film 20 can be the same as the thickness of the curable resin layer 20C. The curable resin film 20 may be a thermosetting resin film. The curable resin film 20 may be a normal adhesive film used as a die attach film (DAF). Details of examples of the curable resin film 20 will be described later.

[0018] Next, as shown in Figure 2(a), a pressurizing member 80 having a flat surface S80 is positioned on the surface S20 of the curable resin film 20 opposite to the circuit member 10, such that the flat surface S80 is located on the curable resin film 20 side. In this example of the disclosure, the flat surface S80 may be in contact with the surface S20 of the curable resin film 20, or the entire surface S20 of the curable resin film 20 may be in contact with the flat surface S80 of the pressurizing member 80. A protective film (separator) may be interposed between the pressurizing member 80 and the surface S20 of the curable resin film 20. The flat surface S80 is a surface that does not contain large steps and can be flat enough to be suitable for normal hot pressing. The maximum step (maximum height difference) on the flat surface S80 may be, for example, 7 μm or less. The pressurizing member 80 may include a metal molded body (e.g., a metal plate) having a flat surface S80.

[0019] After the pressurizing member 80 is positioned, the circuit member 10 and the curable resin film 20 are heated while the pressurizing member 80 is pressed against the curable resin film 20. The circuit member 10 and the curable resin film 20 may also be pressed by a pressurizing means other than the pressurizing member 80, or the pressurizing member 80 itself may be pressed against the circuit member 10 and the curable resin film 20, or the pressurizing member 80 may be pressed by its own weight, etc. Through this heating and pressurizing, as shown in Figure 2(b), the curable resin film 20 is attached to the circuit member 10 so as to cover the multiple terminal electrodes 12 and fit between adjacent terminal electrodes 12. As a result, any gaps remaining between the semiconductor substrate 11 and the curable resin film 20 may be filled. However, a small gap may remain between the curable resin film 20 attached to the circuit member 10 and the circuit member 10. During this heating and pressurizing, the curing reaction of the curable resin film 20 does not have to proceed substantially, but may proceed partially. In other words, prior to the subsequent curing process, the curable resin film 20 may be uncured or semi-cured (stage B).

[0020] The circuit member 10 and the curable resin film 20 can be heated by heat exchange with a heat source while the circuit member 10 and the curable resin film 20 are under pressure. The heat source can be, for example, a heated medium. The medium may be a gas or a liquid. The heat source may be an electric heater (e.g., a heating plate). The temperature of the heat source may be constant or change during heating. The temperature of the heat source may be gradually increased by repeatedly maintaining a constant temperature and then increasing the temperature. The maximum temperature of the heat source may be the temperature at which the curable resin film melts or flows. The maximum temperature of the heat source may be 50°C or more and 200°C or less, or 80°C or more and 200°C or less.

[0021] While the circuit member 10 and the curable resin film 20 are being heated under pressure, and / or before that, the laminate of the circuit member 10 and the curable resin film 20 may be placed under reduced pressure.

[0022] Next, as shown in Figure 3(a), a curable resin layer 20C, which is a cured curable resin film, is formed on the circuit member 10 by curing the curable resin film 20 attached to the circuit member 10. The curable resin layer 20C only needs to be cured to a degree that does not pose practical problems in terms of heat resistance, etc., and does not necessarily need to be completely cured. "Completely cured" means, for example, that no heat generation due to the curing reaction is substantially observed in differential scanning calorimetry. The curable resin layer 20C covers a plurality of terminal electrodes 12 and is embedded between adjacent terminal electrodes 12. In the example of Figure 3(a), the curable resin layer 20C embeds the entire terminal electrode 12. If a protective film (separator) is interposed between the pressurizing member 80 and the surface S20 of the curable resin film 20, the protective film may be peeled off from the curable resin film 20 or the curable resin layer 20C before or after the curing of the curable resin film 20.

[0023] The thickness of the cured resin layer 20C at the time it is held by the holding member 90 is usually greater than the height of the terminal electrode 12. The thickness of the cured resin layer 20C at the time it is held by the holding member 90 may be, for example, 200 μm or less, or 20 μm or more.

[0024] The tensile modulus of the cured resin layer 20C, or the cured product of the curable resin film 20, at 25°C may be, for example, 10 MPa or more, or 1.0 GPa or more. A high modulus of elasticity of the cured resin layer 20C may be advantageous in suppressing bending and cracking of the semiconductor substrate 11, and in facilitating easy polishing of the cured resin layer 20C.

[0025] The coefficient of linear expansion of the cured resin layer 20C or the cured product of the curable resin film 20 below the glass transition temperature may be, for example, 10 ppm / K or more and 200 ppm / K or less. The thermal conductivity of the cured resin layer 20C or the cured product of the curable resin film 20 may be 0.3 W / m·K or more, or 0.5 W / m·K or more.

[0026] The adhesive strength between the cured resin layer 20C and the first surface S11 of the semiconductor substrate 11 may be 1 MPa or more, or 3 MPa or more.

[0027] In the example shown in Figure 3(a), an adhesive layer 28 is provided on the second surface S12 of the semiconductor substrate 11. The adhesive layer 28 can be a thermosetting layer formed from a thermosetting resin composition. The adhesive layer 28 may be a layer formed from the same thermosetting resin composition as the curable resin film 20. At this stage, the adhesive layer 28 does not need to be cured, and may be cured by the thermal history it receives in any subsequent process. The adhesive layer 28 may not be provided at all. The difference between the coefficient of linear expansion of the cured adhesive layer 28 and the cured resin layer 20C may be within 150 ppm / K. A small difference in the coefficients of linear expansion of the two can contribute, for example, to suppressing fluctuations in the position or parallelism of the circuit member 10, and to suppressing warping of the circuit member 10. The adhesive layer 28 may have a light transmittance of 10% or more and 100% or less.

[0028] The adhesive layer 28 is provided, for example, by laminating a conventional NCF (non-conductive film) or by applying an NCP (non-conductive paste). The thermosetting resin composition constituting the adhesive layer 28 includes a thermosetting resin which is a compound having reactive groups that form a crosslinked structure by self-polymerization and / or reaction with a curing agent. The thermosetting resin may be, for example, epoxy resin, bismaleimide resin, triazine resin, polyimide resin, polyamide resin, cyanoacrylate resin, phenol resin, unsaturated polyester resin, melamine resin, urea resin, polyurethane resin, polyisocyanate resin, furan resin, resorcinol resin, xylene resin, benzoguanamine resin, diallyl phthalate resin, silicone resin, polyvinyl butyral resin, siloxane-modified epoxy resin, siloxane-modified polyamideimide resin, acrylate resin, or a combination of two or more selected from these. The resin composition constituting the adhesive layer 28 may also contain other components such as a curing agent (e.g., an imidazole-based curing agent), a curing accelerator, a flux compound, and an inorganic filler.

[0029] The surface S20C of the cured resin layer 20C opposite to the circuit member 10 may form a step that reflects the irregularities of the circuit member 10, including the terminal electrode 12. However, by using a method that includes pressurization with a pressurizing member 80, the formation of a large step on the surface S20C of the cured resin layer 20C can be suppressed.

[0030] As shown in Figure 3(b), the semiconductor substrate 11 may be cut together with the cured resin layer 20C along the cutting line D. This separates the semiconductor substrate 11 together with the cured resin layer 20C into individual pieces. The separated semiconductor substrate 11 can be a semiconductor die. The method for cutting the semiconductor substrate 11 and the cured resin layer 20C can be a conventional dicing method. For dicing, the circuit member 10 may be held on a dicing tape attached to the semiconductor substrate 11 or the adhesive layer 28. Before cutting the semiconductor substrate 11, the semiconductor substrate 11 may be thinned by grinding. The thickness of the separated semiconductor substrate 11 may be, for example, 100 μm or less, or 50 μm or less.

[0031] As shown in Figure 4(a), the cured resin layer 20C on the diced semiconductor substrate 11 is adsorbed onto the holding member 90. The entire surface S20C of the cured resin layer 20C opposite to the circuit member 10 may be adsorbed onto the holding member 90. The holding member 90 adsorbs the cured resin layer 20C, for example, by vacuum adsorption. The holding member 90 may also function as a heating element that can heat the cured resin layer 20C and the circuit member 10. The holding member 90 may be, for example, a collet. The circuit member 10 and the cured resin layer 20C held by the holding member 90 are picked up as shown in Figure 4(b). If a dicing tape is used for dicing the semiconductor substrate 11, the circuit member 10 and the cured resin layer 20C are picked up so that the circuit member 10 or the adhesive layer 28 peels off from the dicing tape.

[0032] If the cured resin layer 20C is not provided, the pickup member must hold the outer periphery of the circuit member 10 while avoiding the exposed terminal electrodes 12, which may lead to bending or damage of the semiconductor substrate 11. By holding the circuit member 10 with a holding member 90 adsorbed to the surface S20C of the cured resin layer 20C, bending or damage of the semiconductor substrate 11 can be suppressed. The adsorption of the cured resin layer 20C to the holding member 90 is also advantageous in terms of efficient heat conduction from the holding member 90 to the circuit member 10. In addition, a small step difference on the surface S20C of the cured resin layer 20C opposite to the circuit member 10 can contribute to even more stable holding by the holding member 90. If the step difference on the surface S20C is large, for example, the circuit member 10 and the cured resin layer 20C may fall off the holding member 90.

[0033] As shown in Figure 5, the picked-up circuit member 10 and cured resin layer 20C are aligned by the movement of the holding member 90 and then placed on the substrate 1. In one example of this disclosure, the circuit member 10 is placed on the substrate 1 with the terminal electrodes 12 facing away from the substrate 1, in other words, face-up. The substrate 1 has a temporary fixing member 100 and a wiring layer 42 (second wiring layer) provided on the temporary fixing member 100. The circuit member 10 and cured resin layer 20C are placed in predetermined positions on the wiring layer 42. Thereafter, as shown in Figure 6, the holding member 90 is separated from the cured resin layer 20C. If the circuit member 10 has conductive vias penetrating the semiconductor substrate 11, these conductive vias may be connected to wiring in the wiring layer 42. In the examples of Figures 5 and 6, an adhesive layer 28 is interposed between the circuit member 10 and the substrate 1 (wiring layer 42). The circuit member 10 and cured resin layer 20C may be pressed against the substrate 1 by the holding member 90. In that case, a small step difference on the surface S20C of the cured resin layer 20C opposite to the circuit member 10 can contribute to improving the uniformity of the pressure received by the circuit member 10. If the circuit member 10 is subjected to uneven pressure, for example, the semiconductor substrate 11 may be damaged.

[0034] The temporary fixing member 100 comprises a carrier substrate 101 and a temporary fixing layer 102 provided on the carrier substrate 101. A wiring layer 42 is provided on the temporary fixing layer 102. The temporary fixing layer 102 is a layer that temporarily fixes semiconductor components and the like and can be peeled off by heat or the like, and can be appropriately selected from those that are normally available to those skilled in the art for similar purposes. The wiring layer 42 comprises an insulating layer 47 and wiring 45c provided within the insulating layer 47. The wiring 45c of the wiring layer 42 is exposed on the side of the wiring layer 42 opposite to the temporary fixing member 100. The base material 1 further comprises wiring 27 provided on the exposed wiring 45c of the wiring layer 42. The wiring layer 42 can be formed by a normal method used for forming a rewiring layer.

[0035] The base material 1 does not necessarily have to have a wiring layer 42. In that case, the circuit member 10 and the cured resin layer 20C may be placed on the temporary fixing layer 102. After the sealing layer 25 etc. is formed, the temporary fixing layer 102 and the circuit member 10 may be separated, and the wiring layer 42 may be formed on the circuit member 10 and the sealing layer 25.

[0036] In one example of this disclosure, as shown in Figure 7, a sealing layer 25 is formed on the substrate 1 to seal the circuit member 10 placed on the substrate 1. In the example of Figure 7, the sealing layer 25 is formed on the wiring layer 42 of the substrate 1 so as to surround the circuit member 10 and the cured resin layer 20C. The sealing layer 25 may have a maximum thickness greater than the combined thickness of the circuit member 10 and the cured resin layer 20C, and may cover the entire circuit member 10 and the cured resin layer 20C. The sealing layer 25 also seals the wiring 27.

[0037] The encapsulation layer 25 can be formed using an encapsulant commonly used in the manufacture of semiconductor packages. The encapsulant for forming the encapsulation layer 25 is typically a thermosetting resin composition, and the encapsulation layer 25 can be a cured product of the encapsulant. The encapsulant (thermosetting resin composition) for forming the encapsulation layer 25 may include, for example, an epoxy resin and a curing agent. The encapsulant and the encapsulation layer 25 formed therefrom may contain an inorganic filler (e.g., a filler). The average particle size of the inorganic filler contained in the encapsulant and the encapsulation layer 25 may be, for example, 50 μm or less, 25 μm or less, 10 μm or less, or 0.01 μm or less. When the encapsulant (encapsulation layer 25) and the curable resin film 20 (cured resin layer 20C) contain an inorganic filler, the average particle size of the inorganic filler contained in the encapsulant (encapsulation layer 25) may be greater than the average particle size of the inorganic filler contained in the curable resin film 20 (cured resin layer 20C). Since the sealing material for forming the sealing layer 25 does not need to fill the space between the terminal electrodes 22, the sealing layer 25 can be easily formed properly even if the sealing material contains large-particle inorganic fillers. The inclusion of large-particle inorganic fillers in the sealing material and the sealing layer 25 is advantageous in terms of ease of polishing the sealing layer 25 and reduction of warping of the semiconductor package. The difference between the linear expansion coefficient of the sealing layer 25 and the linear expansion coefficient of the cured resin layer 20C may be 150 ppm / K or less.

[0038] After the sealing layer 25 is formed, as shown in Figure 8, a portion of the sealing layer 25 and the cured resin layer 20C may be removed from the side opposite to the substrate 1, thereby exposing the tips of the multiple terminal electrodes 12. A substantially flat connection surface S21 including the cured resin layer 20C and the sealing layer 25 may be formed. The method for removing a portion of the sealing layer 25 and the cured resin layer 20C can be a conventional method such as chemical mechanical polishing (CMP). The tips of the wiring 27 within the sealing layer 25 may be exposed, and the wiring 27 may penetrate the sealing layer 25. At this point, the cured resin layer 20C may have a thickness approximately equal to the height of the terminal electrodes 12.

[0039] Subsequently, as shown in Figure 9, a wiring layer 41 (first wiring layer) may be formed on the terminal electrode 12 side of the circuit member 10. The wiring layer 41 includes an insulating layer 47 and wirings 45a and 45b provided within the insulating layer 47. Wiring 45a is electrically connected to the terminal electrode 12. Wiring 45b may be electrically connected to wiring 45c via wiring 27 that penetrates the sealing layer 25. Wirings 45a and 45b within the wiring layer 41 are exposed on the side of the wiring layer 41 opposite to the circuit member 10. The wiring layer 41 is not limited to wirings 45a and 45b, but may also include wiring for rewiring semiconductor components mounted on the wiring layer 41. The wiring layer 41 can also be formed by a conventional method used for forming a rewiring layer.

[0040] After the sealing layer 25 and the wiring layer 41 are formed, a plurality of semiconductor components 51 and 52 may be mounted on the terminal electrode 12 side of the circuit member 10, in other words, on the side of the wiring layer 41 opposite to the circuit member 10, as shown in Figure 10. Each of the plurality of semiconductor components 51 and 52 has a semiconductor die 50 and a plurality of terminal electrodes 55a and 55b provided on the outer surface of the semiconductor die 50. The terminal electrode 55a is electrically connected to the terminal electrode 12 of the circuit member 10 via wiring 45a in the wiring layer 41. In this way, the two semiconductor components 51 and 52 are mounted on the wiring layer 41 so that they are electrically connected to each other via the circuit member 10. That is, the circuit member 10 functions as a bridge die. The terminal electrode 55b is connected to wiring 45b in the wiring layer 41. The terminal electrode 55b may also be electrically connected to wiring 45c in the wiring layer 42 via wiring 45b and wiring 27. For mounting the semiconductor components 51 and 52, the wiring including the terminal electrodes 55a and 55b of the semiconductor components 51 and 52 may be subjected to a reflow process by heating.

[0041] The semiconductor components 51 and 52 can be various types of chips, including integrated circuits. The semiconductor components 51 and 52 may be, for example, a system-on-a-chip (SoC), a logic chip, memory (such as an HBM), a CMOS sensor, or a combination of two or more of these.

[0042] After the semiconductor components 51 and 52 are mounted, a sealing layer 57 may be formed to enclose the semiconductor components 51 and 52, as shown in Figure 11. After forming a sealing layer 57 that completely encloses the semiconductor components 51 and 52, a portion of the sealing layer 57 may be removed from the side opposite to the circuit member 10, as shown in Figure 12. The sealing layer 57 may be removed so that the semiconductor dies 50 of the semiconductor components 51 and 52 are exposed. The sealing layer 57 can be removed by conventional methods such as chemical mechanical polishing (CMP). The sealing layer 57 can be formed using the same sealing material as the sealing material that forms the sealing layer 25.

[0043] Separate the temporary fixing member 100 and the wiring layer 42, and as shown in FIG. 13, bumps 71 connected to the exposed wiring 45c of the wiring layer 42 may be provided on the surface of the wiring layer 42 opposite to the circuit member 10. At this point, a sealing structure 150 including a plurality of semiconductor components 51, 52, a wiring layer 41 (first wiring layer), a circuit member 10, a wiring layer 42 (second wiring layer), and bumps 71 is formed.

[0044] Then, by mounting the sealing structure 150 on the package substrate 60 as shown in FIG. 14, a semiconductor package 200 is obtained. The semiconductor package 200 may be provided on the surface of the package substrate 60 opposite to the sealing structure 150 and may have bumps 72 connected to an external device (for example, a motherboard). The semiconductor package 200 may have an adhesive layer 65 interposed between the sealing structure 150 and the package substrate 60.

[0045] The structure of the semiconductor package and its manufacturing process are not limited to the above examples and can be changed as appropriate.

[0046] For example, the base material may have a temporary fixing member having a carrier substrate and a temporary fixing layer, and on the temporary fixing layer, the circuit member may be arranged with the terminal electrodes positioned toward the base material side. In that case, after a sealing layer for sealing the circuit member is formed, the base material may be separated from the sealing layer and the circuit member. After the base material is separated from the sealing layer and the circuit member, a first wiring layer including wiring electrically connected to the terminal electrodes may be formed on the terminal electrode side of the circuit member, and a plurality of semiconductor components may be mounted on the side of the first wiring layer opposite to the circuit member.

[0047] Alternatively, the base material may have a temporary fixing material layer and a first wiring layer provided on the temporary fixing layer and including wiring, and on the first wiring layer, the circuit member may be arranged with the terminal electrodes positioned toward the base material side and the terminal electrodes electrically connected to the wiring of the first wiring layer. In that case, after the sealing layer is formed, the base material and the first wiring layer may be separated. After the base material and the first wiring layer are separated, a plurality of semiconductor components may be mounted on the side of the first wiring layer opposite to the circuit member.

[0048] In the method for manufacturing a semiconductor package exemplified above with a curable resin film, examples of the curable resin film applicable for forming a cured resin layer on the terminal electrode side of a circuit member will be described in detail below.

[0049] The curable resin film may be thermosetting. In that case, a cured resin layer is formed by thermosetting the curable resin film. The curable resin film may contain a thermosetting resin which is a compound having a reactive group that forms a crosslinked structure by self-polymerization and / or reaction with a curing agent. The thermosetting resin may contain, for example, at least one selected from the group consisting of epoxy resins, bismaleimide resins, triazine resins, and phenolic resins. The content of the thermosetting resin may be 1 part by mass or more and 30 parts by mass or less with respect to 100 parts by mass of the mass of the curable resin film. The curable resin film may contain a curing agent that reacts with the thermosetting resin.

[0050] The curable resin film may further contain one or more other components selected from a curing accelerator that promotes the reaction between the thermosetting resin and the curing agent, a high molecular weight resin component, a coupling agent (for example, a silane coupling agent), and an inorganic filler.

[0051] The weight average molecular weight (standard polystyrene conversion value by GPC method) of the high molecular weight resin component may be 100,000 or more and may be 3,000,000 or less. The high molecular weight resin component may contain, for example, at least one resin selected from the group consisting of acrylic rubber, polyimide, and phenoxy resin. The high molecular weight resin component may have a reactive group such as an epoxy group. The content of the high molecular weight resin component may be 30 parts by mass or more and 80 parts by mass or less with respect to 100 parts by mass of the mass of the curable resin film.

[0052] The inorganic filler may be a filler containing one or more inorganic materials selected from, for example, glass, silica, alumina, titanium oxide, carbon black, mica, and boron nitride. The inorganic filler may be a filler containing silica, alumina, titanium oxide, or boron nitride, or may be a filler containing silica, alumina, or boron nitride.

[0053] The average particle diameter of the inorganic filler may be, for example, 20 μm or less, or 10 μm or less. The maximum particle diameter of the inorganic filler may be, for example, 30 μm or less. The average particle diameter of the inorganic filler may be 5 μm or less, and the maximum particle diameter of the inorganic filler may be 20 μm or less. Smaller average and maximum particle diameters of the inorganic filler may be advantageous in terms of filling between terminal electrodes and suppressing warping. The average particle diameter and / or maximum particle diameter of the inorganic filler may be 0.001 μm or more.

[0054] The average and maximum particle diameters of the inorganic filler can be, for example, the average and maximum particle sizes of the particle images of the inorganic filler observed with a scanning electron microscope (SEM). The particle size of the particle image may be, for example, the diameter of a circle having the same area as the area of ​​the particle image. The number of particles whose particle size is determined in order to find the average and maximum particle diameters may be, for example, about 20. When observing a cross-section of a cured product formed from a curable resin film, the proportion of particles with a particle size of 3 μm or less may be 80% or more of the total number of particles.

[0055] The aspect ratio of the inorganic filler may be between 50 and 85 from the viewpoint of improving thermal conductivity. Here, the aspect ratio is, for example, the average of the major axis / minor axis ratio, which is the ratio of the major axis to the minor axis in any 20 particles.

[0056] The inorganic filler content may be 10% by mass or more and 95% by mass, based on the mass of the curable resin film. The inorganic filler content may be 20% by mass or more, 30% by mass or more, or 40% by mass or more, or 45% by mass or more and 95% by mass or less, based on the mass of the curable resin film.

[0057] The concentration of ionic impurities in the curable resin film and the curable resin layer formed therefrom may be, for example, 5 ppm or less, 3 ppm or less, 1 ppm or less, 0.5 ppm or less, or 0.3 ppm or less. A low concentration of ionic impurities can contribute to suppressing migration between terminal electrodes. The ionic impurities here may be one or more selected from, for example, sodium (Na), potassium (K), and chlorine (Cl).

[0058] The present invention is not limited to the following embodiments.

[0059] Examples 1 and 2 A silicon wafer, a test circuit member having numerous bumps (terminal electrodes) provided on the silicon wafer, a curable resin film, and an aluminum plate (pressure member) having a flat surface (step difference of approximately 7 μm or less) were prepared. The bumps were provided in a portion of the surface of the silicon wafer. The curable resin film was placed on the bump side of the circuit member (silicon wafer). Next, the aluminum plate was placed on the curable resin film so that its flat surface was in contact with the entire surface of the curable resin film. The laminate consisting of the circuit member, curable resin film, and aluminum plate was heated from the aluminum plate side with a heat source (heated air) at 120°C, and pressurized at a pressure of 0.5 MPa for a pressurizing time of 120 seconds or 240 seconds, thereby pressing the aluminum plate against the curable resin film. Due to this heating and pressurizing, the curable resin film was attached to the circuit member so that it covered the bumps and penetrated between the bumps. A curable resin layer was formed by heat curing the curable resin film attached to the circuit member.

[0060] Comparative Examples 1 and 2: In these examples, the aluminum plate was not placed on the curable resin film. Instead, a laminate consisting only of the circuit member and the curable resin film was pressed against the curable resin film using a balloon containing heated air. The laminate was then heated to 70°C or 120°C and pressurized for 120 seconds, thereby attaching the curable resin film to the circuit member. A cured resin layer was formed by heat-curing the curable resin film attached to the circuit member.

[0061] The step height on the surface of the evaluated cured resin layer was measured using a laser microscope. Here, the step height is the maximum height difference on the side of the cured resin layer opposite to the circuit member. Table 1 shows the conditions for each level and the measurement results of the step height. It was confirmed that a cured resin layer with a small step height is formed by attaching the curable resin film to the circuit member using an aluminum plate (pressure member).

[0062]

[0063] 1...Base material, 10...Circuit component, 11...Semiconductor substrate, 12...Terminal electrode, 20...Curable resin film, 20C...Curable resin layer, 25...Sealing layer, 27...Wiring, 28...Adhesive layer, 41, 42...Wiring layer, 45a, 45b, 45c...Wiring, 47...Insulating layer, 50...Semiconductor die, 51, 52...Semiconductor component, 55a, 55b...Terminal electrode, 57...Sealing layer, 60...Package substrate, 65...Conditioning Adhesive layer, 71, 72... bumps, 80... pressurizing member, S80... flat surface, 90... holding member, 100... temporary fixing member, 101... carrier substrate, 102... temporary fixing layer, 150... sealing structure, 200... semiconductor package, S11... first surface, S12... second surface, S20... surface of the curable resin film opposite to the circuit member, S20C... surface of the curable resin layer opposite to the circuit member, D... cutting line.

Claims

1. Prepare a circuit member including a semiconductor substrate having a first surface and a second surface on its reverse side, and a plurality of terminal electrodes provided on the first surface of the semiconductor substrate; place a curable resin film on the terminal electrode side of the circuit member; place a pressing member having a flat surface on the side of the curable resin film opposite to the circuit member, with the flat surface facing the curable resin film; heat the curable resin film while applying pressure to the circuit member so that the pressing member presses against the curable resin film, thereby attaching the curable resin film to the circuit member so that it covers the plurality of terminal electrodes and fits between adjacent terminal electrodes; cure the curable resin film to form a cured resin layer, which is the cured curable resin film, on the circuit member; and hold the circuit member and the cured resin layer with a holding member adsorbed to the cured resin layer. A method for manufacturing a semiconductor package, comprising: arranging the circuit member and the cured resin layer, which are held by the holding member, on a substrate; and then separating the holding member from the cured resin layer.

2. The method according to claim 1, further comprising separating the circuit member together with the cured resin layer, wherein the separated circuit member and the cured resin layer are held by the holding member and arranged on the substrate.

3. The method according to claim 1, further comprising forming a sealing layer on the substrate that seals the circuit member disposed on the substrate.

4. The method according to claim 3, further comprising removing a portion of the sealing layer and the cured resin layer from the side opposite to the substrate, thereby exposing the tips of a plurality of terminal electrodes.

5. The method according to claim 3 or 4, further comprising mounting a plurality of semiconductor components having semiconductor dies on the terminal electrode side of the circuit member after the sealing layer has been formed, wherein two or more of the semiconductor components are electrically connected to each other via the circuit member.

6. The method according to claim 5, wherein the circuit member is arranged on the substrate in a orientation such that the terminal electrodes are located on the opposite side from the substrate, and the method further includes forming a wiring layer on the terminal electrode side of the circuit member after the sealing layer has been formed, the wiring layer including wiring electrically connected to the terminal electrodes, and a plurality of semiconductor components are mounted on the side of the wiring layer opposite to the circuit member.

7. The method according to claim 5, wherein the substrate has a temporary fixing layer, the circuit member is arranged on the temporary fixing layer with the terminal electrodes facing the substrate side, and the method further comprises: separating the substrate, the sealing layer and the circuit member after the sealing layer has been formed; and forming a wiring layer on the terminal electrode side of the circuit member, including wiring electrically connected to the terminal electrodes, after the substrate, the sealing layer and the circuit member have been separated, and a plurality of semiconductor components are mounted on the side of the wiring layer opposite to the circuit member.

8. The method according to claim 5, wherein the substrate comprises a temporary fixing layer and a wiring layer provided on the temporary fixing layer, the wiring layer including wiring, the circuit member is arranged on the wiring layer such that the terminal electrode is oriented toward the substrate side and the terminal electrode is electrically connected to the wiring of the wiring layer, the method further comprises separating the substrate and the wiring layer after the sealing layer has been formed, and after the substrate and the wiring layer have been separated, a plurality of semiconductor components are mounted on the wiring layer opposite to the circuit member.

9. The method according to claim 1, wherein the tensile modulus of the cured resin layer at 25°C is 10 MPa or more.

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