Display substrate, display panel, and display apparatus

Abstract

A display substrate, a display panel, and a display apparatus. The display substrate comprises: a base substrate (1); a first thin film transistor (2), comprising a first active layer (201), a first gate (G1), a first source electrode (S1), and a first drain electrode (D1); a first transparent electrode (3); a plurality of first vias (401) and a plurality of second vias (402); the first source electrode (S1) is in contact with the first active layer (201) by means of the first vias (401), and the first drain electrode (D1) is in contact with the first active layer (201) by means of the second vias (402); a light-shielding layer (5) comprising a plurality of light-shielding patterns (501); orthographic projections of the light-shielding patterns (501) on the base substrate (1) do not overlap with orthographic projections of bottom surfaces or top surfaces of the first vias (401) and the second vias (402) on the base substrate (1); on a side where orthographic projections of the first vias (401) and the second vias (402) on the base substrate (1) face an orthographic projection of the first gate (G1) on the base substrate (1), the orthographic projections of the light-shielding patterns (501) on the base substrate (1) overlap with an orthographic projection of the first active layer (201) on the base substrate (1).

Description

Display substrate, display panel and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to display substrates, display panels, and display devices. Background Technology

[0002] With the rapid development of display products, user demands are constantly increasing. Low Temperature Poly-Silicon (LTPS) technology is one of the more mature display technologies. In LTPS display products, a light-shielding layer is required to block the first active layer of the first thin-film transistor. However, in related technologies, there is a problem that some pixel electrodes are connected to the light-shielding layer, affecting display uniformity. Summary of the Invention

[0003] This disclosure provides a display substrate, which includes:

[0004] Substrate, including the display area;

[0005] A plurality of first thin-film transistors are located in the display area; the first thin-film transistors include: a first active layer, a first gate located on the side of the first active layer away from the substrate, and a first source and a first drain located on the side of the first gate away from the first active layer;

[0006] Multiple first transparent electrodes are located on the side of the first source and first drain that are away from the substrate; the first transparent electrodes are electrically connected to the first drain.

[0007] Multiple vias, including multiple first vias and multiple second vias; the first source electrode contacts the first active layer through the first vias, and the first drain electrode contacts the first active layer through the second vias;

[0008] A light-shielding layer is located between the substrate and the first active layer. The light-shielding layer includes a plurality of light-shielding patterns located in the display area. The orthographic projection of the light-shielding pattern on the substrate does not overlap with the orthographic projection of the first via and the second via on the substrate. On the side where the orthographic projection of the bottom or top surface of the first via and the second via on the substrate faces the orthographic projection of the first gate on the substrate, the orthographic projection of the light-shielding pattern on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

[0009] In some embodiments, the substrate further includes: a peripheral region surrounding the display area; the display substrate further includes:

[0010] Multiple first signal lines are located in the peripheral area on one side of the display area in a first direction; each of the multiple first signal lines includes a first trace and / or a second trace; the first trace is disposed on the same layer as the light-shielding pattern, and the second trace is disposed on the same layer as the first gate; both the first trace and the second trace include a first portion, and the angle between the extension direction of the first portion and the first direction is greater than 0° and less than 90°; among the multiple first signal lines, some of the first traces are arranged along a second direction, and some of the second traces are arranged along a second direction, and the second direction intersects the first direction and the extension direction of the first portion; the orthographic projection of the first portion of the first trace on the substrate overlaps with the orthographic projection of the first portion of the second trace on the substrate, and the area between the orthographic projections of the first portions of any two adjacent second traces on the substrate overlaps with the orthographic projection of the edge of the first portion of the first trace on the substrate.

[0011] In some embodiments, the first portion has a first edge that extends in the same direction as the display area and is close to the side of the display area;

[0012] In the orthographic projection of the substrate, there are overlapping first and second traces, and the first edge of the second trace is closer to the display area in the orthographic projection of the substrate than the first edge of the first trace in the orthographic projection of the substrate.

[0013] In some embodiments, the first trace and the second trace further include a first connection portion disposed on the same layer as the first portion and electrically connected thereto; the pattern of the first connection portion in the orthographic projection onto the substrate includes a rounded corner area.

[0014] The first signal line further includes a second connection portion located on a different layer from the first trace and the second trace; the first connection portion and the second connection portion are electrically connected.

[0015] In some embodiments, each first signal line includes a first trace and a second trace;

[0016] The first trace and the second trace in the first signal line do not overlap in their orthographic projections onto the substrate.

[0017] The first connection portion of the first trace and the first connection portion of the second trace are electrically connected through the second connection portion.

[0018] In some embodiments, the plurality of first signal lines are divided into a plurality of signal line groups arranged along a second direction;

[0019] The two first traces that are closest to each other in two adjacent signal line groups also include: a second portion located on one side of the first portion in the first direction and electrically connected to the first portion; the second portion includes at least a portion extending along the first direction;

[0020] In two adjacent signal line groups, the distance between the second portions of the two closest first traces in the second direction is greater than or equal to 290 micrometers.

[0021] In some embodiments, the display substrate further includes:

[0022] Multiple first dummy traces are disposed on the same layer as the light-shielding pattern; multiple first dummy traces extend along a first direction; the orthographic projection of the first dummy traces on the substrate is located in the region between the orthographic projections of the two closest first traces in two adjacent signal line groups on the substrate.

[0023] Multiple second dummy traces are set on the same layer as the light-shielding pattern; the second dummy traces are located on the side of the first traces away from the display area, and the second dummy traces include at least a portion extending in the same direction as the first portion; some second dummy traces are located on the side of the second portion away from the adjacent signal line group in the second direction, and the distance between some second dummy traces and the second portion is not exactly the same.

[0024] In some embodiments, the display substrate further includes:

[0025] Multiple third traces are located in the peripheral area; the multiple third traces are located on different layers from the first trace and the second trace; some of the multiple third traces include: a third part whose extension direction intersects with the extension direction of the first part; the area where the orthographic projection of the third part of the multiple third traces on the substrate overlaps with the orthographic projection of the second trace on the substrate is a first sub-region.

[0026] At least one pin group; the orthographic projection of the at least one pin group onto the substrate is located on the side of the orthographic projection of the plurality of first signal lines onto the substrate away from the display area; the pin group includes a plurality of bonding pins; the first signal lines are electrically connected to the bonding pins;

[0027] At least one electrostatic discharge structure; the electrostatic discharge structure includes: at least one fourth trace and at least one electrostatic discharge terminal; the fourth trace is disposed on the same layer as the second trace, and the electrostatic discharge terminal is disposed on a different layer from the fourth trace; the fourth trace includes: a fourth portion and a fifth portion electrically connected in sequence; the orthographic projection of the fourth portion onto the substrate is located on the side of the first sub-region facing the orthographic projection of the pin group onto the substrate in a first direction; the orthographic projection of the fifth portion onto the substrate is located on the side of the pin group in a second direction, and the end of the fifth portion away from the fourth portion is electrically connected to the electrostatic discharge terminal.

[0028] In some embodiments, the pin group includes a plurality of bonded pins arranged in a plurality of bonded pin rows along a first direction;

[0029] The electrostatic discharge structure includes m fourth traces. The fourth part of each of the m fourth traces is electrically connected to the m bonding pins closest to the fifth part in the bonding pin row closest to the display area; m is a positive integer.

[0030] In some embodiments, the display substrate further includes: a plurality of third dummy traces disposed on the same layer as the second traces; the third dummy traces are located on the side of a portion of the plurality of second traces away from the display area; and a portion of the third dummy traces extend to the side of the first sub-region away from the display area.

[0031] The end of the fourth part away from the fifth part is electrically connected to the third dummy trace extending to the side of the first sub-region away from the display area.

[0032] In some embodiments, the plurality of bonding pins in the pin group includes: a plurality of first bonding pins, and a plurality of second bonding pins located on the side of the plurality of first bonding pins away from the display area in a first direction;

[0033] The fourth wiring also includes: a sixth part and a seventh part; one end of the sixth part is electrically connected to the fourth part, the other end of the sixth part is electrically connected to the seventh part, the end of the seventh part away from the sixth part is electrically connected to the electrostatic discharge terminal, and the fifth part and the seventh part are electrically connected to different electrostatic discharge terminals;

[0034] The sixth part overlaps in the region between the orthographic projection of the substrate and the first bonding pins adjacent to each other in the second direction in the orthographic projection of the substrate in the pin group;

[0035] The seventh part is located in the region between the projections of the plurality of first bonding pins and the plurality of second bonding pins onto the substrate.

[0036] In some embodiments, the electrostatic discharge terminal is disposed on the same layer as the first active layer.

[0037] In some embodiments, the display substrate includes at least one pin group; the display substrate further includes:

[0038] Multiple data lines extend along the first direction and are arranged along the second direction;

[0039] A multiplexing circuit is located in the peripheral area. The multiplexing circuit includes: multiple multiplexing units and multiple multiplexing control lines. The multiple multiplexing control lines include: a first multiplexing control line and a second multiplexing control line. The first multiplexing control line and the second multiplexing control line are electrically connected to different bonding pins in the pin group. Each of the multiple multiplexing units includes: multiple multiplexing switches. The control terminals of some of the multiple multiplexing switches in the multiple multiplexing unit are electrically connected to the first multiplexing control line, and the control terminals of the remaining multiple multiplexing switches in the multiple multiplexing unit are electrically connected to the second multiplexing control line. In each multiplexing unit, the output terminals of the multiple multiplexing switches are electrically connected to different data lines, the input terminals of the multiple multiplexing switches electrically connected to the same multiplexing control line are electrically connected to different first signal lines, and the input terminals of some of the multiple multiplexing switches electrically connected to different multiplexing control lines are electrically connected to the same first signal line.

[0040] In some embodiments, the display substrate includes: a plurality of pin groups arranged along a second direction; the plurality of bonding pins in the pin groups include: a plurality of first bonding pins and a plurality of second bonding pins;

[0041] The plurality of first bonded pins include: a plurality of first cascaded pins, and a plurality of first non-cascaded pins located on the side of the plurality of first cascaded pins away from the adjacent pin group in a second direction, wherein the first signal line is electrically connected to the first non-cascaded pins;

[0042] Multiple second-bonded pins include: control pins that are electrically connected to the first multiplexer control line and the second multiplexer control line, respectively;

[0043] The multiplexing control line includes: an eighth portion electrically connected to a control pin and extending generally along a first direction, and a ninth portion electrically connected to the eighth portion and extending in a direction intersecting the eighth portion; the orthographic projection of the eighth portion onto the substrate is located on the side of the orthographic projection of the control pin onto the substrate facing the display area, and the orthographic projection of the eighth portion onto the substrate is located in the region between the orthographic projections of a plurality of first cascaded pins and a plurality of first non-cascaded pins onto the substrate; the orthographic projection of the ninth portion onto the substrate is located on the side of the orthographic projection of a plurality of first bonding pins onto the substrate facing the display area.

[0044] The display substrate also includes:

[0045] Multiple pin group cascade lines are located in the peripheral area; multiple first cascade pins of two adjacent pin groups are electrically connected through at least a portion of the multiple pin group cascade lines; in a first direction, the orthographic projection of the pin group cascade lines on the substrate is located on the side of the first cascade pins away from the display area, and in a second direction, the orthographic projection of the pin group cascade lines on the substrate is located on the side of the eighth portion of the orthographic projection on the substrate facing the orthographic projection of the multiple first cascade pins on the substrate.

[0046] In some embodiments, each multiplexing control line is electrically connected to n multiplexing switches in the multiplexing unit; n is an integer greater than 1.

[0047] The multiplexing circuit also includes: n first sub-control lines electrically connected to the ninth part of the multiplexing control line, and the n first sub-control lines are electrically connected one-to-one with the n multiplexing switches in the multiplexing unit;

[0048] The first sub-control line is projected onto the substrate on the side of the pin group cascade line that is projected onto the substrate towards the display area.

[0049] In some embodiments, the two ends of a portion of the first sub-control line are electrically connected to two adjacent pin groups respectively via multiplexing control signal lines.

[0050] In some embodiments, the orthographic projection of the first sub-control line onto the substrate is located on the side of the first portion of the plurality of first signal lines that is away from the display area in the orthographic projection of the substrate.

[0051] The orthographic projection of multiple multiplexing units onto the substrate is located on the side of the first portion of multiple first signal lines that is projected onto the substrate toward the display area.

[0052] The multiplexing circuit also includes: multiple second sub-control lines and multiple connection traces; the first sub-control lines and the second sub-control lines are electrically connected one-to-one through the connection traces;

[0053] The n second sub-control lines, which are electrically connected to a multiplexing control line, are electrically connected one-to-one with the n multiplexing switches in the multiplexing unit;

[0054] The second sub-control line is projected onto the substrate between the first portion of the multiple first signal lines and the multiple multiplexing units.

[0055] In some embodiments, the display substrate includes a plurality of first dummy traces; the plurality of first dummy traces are divided into a plurality of first dummy trace groups;

[0056] The orthographic projection of multiple connection traces on the substrate lies between the orthographic projections of the two first dummy trace groups on the substrate.

[0057] In some embodiments, the light-shielding layer includes: a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer stacked together;

[0058] The film layer containing the first gate is the first conductive layer; the first conductive layer includes: a fourth sub-conductive layer, a fifth sub-conductive layer, and a sixth sub-conductive layer stacked together;

[0059] The film layer containing the first source and the first drain is the second conductive layer; the second conductive layer includes: a seventh sub-conductive layer, an eighth sub-conductive layer, and a ninth sub-conductive layer stacked together.

[0060] The ratio of the thickness of the fourth sub-conductive layer to the thickness of the fifth sub-conductive layer is greater than or equal to 16% and less than or equal to 25%, and the ratio of the thickness of the sixth sub-conductive layer to the thickness of the fifth sub-conductive layer is greater than or equal to 25% and less than or equal to 34%.

[0061] The materials of the first sub-conductive layer, the third sub-conductive layer, the fourth sub-conductive layer, and the sixth sub-conductive layer are molybdenum;

[0062] The materials for the seventh and ninth sub-conductive layers are titanium.

[0063] The materials for the second, fifth, and eighth sub-conductive layers are aluminum.

[0064] In some embodiments, the light-shielding pattern corresponds one-to-one with the first active layer;

[0065] The first active layer includes a first sub-active layer, a second sub-active layer, a third sub-active layer, a fourth sub-active layer, and a fifth sub-active layer connected in sequence;

[0066] In the first direction, the second sub-active layer and the fourth sub-active layer are located on one side of the third sub-active layer, the first sub-active layer is located on the side of the second sub-active layer away from the third sub-active layer, and the fifth sub-active layer is located on the side of the fourth sub-active layer away from the third sub-active layer.

[0067] The first via's orthographic projection onto the substrate falls within the orthographic projection of the first sub-active layer onto the substrate, and the second via's orthographic projection onto the substrate falls within the orthographic projection of the fifth sub-active layer onto the substrate.

[0068] The orthographic projection of each light-shielding pattern on the substrate does not overlap with the orthographic projection of the third sub-active layer on the substrate. The orthographic projection of each light-shielding pattern on the substrate covers the orthographic projection of the second sub-active layer, the fourth sub-active layer, and the area between the second and fourth sub-active layers on the substrate.

[0069] This disclosure provides a display panel, which includes:

[0070] The display substrate provided in the embodiments of this disclosure;

[0071] Opposing substrate, positioned opposite to the display substrate;

[0072] The liquid crystal layer is located between the display substrate and the opposing substrate.

[0073] This disclosure provides a display device, which includes a display panel provided in this disclosure. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 is a schematic diagram of the structure of a display substrate provided in an embodiment of this disclosure;

[0076] Figure 2 is a schematic diagram of a cross-sectional structure along FF' in Figure 1 provided by an embodiment of this disclosure;

[0077] Figure 3 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0078] Figure 4 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0079] Figure 5 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0080] Figure 6 is a schematic diagram of the structure of another display substrate provided in an embodiment of this disclosure;

[0081] Figure 7 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0082] Figure 8 is a schematic diagram of a display substrate provided by related technologies;

[0083] Figure 9 is a schematic diagram of the structure of another display substrate provided in an embodiment of this disclosure;

[0084] Figure 10 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0085] Figure 11 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0086] Figure 12 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0087] Figure 13 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0088] Figure 14 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0089] Figure 15 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0090] Figure 16 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0091] Figure 17 is a schematic diagram of the structure of another display substrate provided in an embodiment of this disclosure;

[0092] Figure 18 is a schematic diagram of another display substrate provided in an embodiment of this disclosure;

[0093] Figure 19 is a schematic diagram of another display substrate provided by related technologies;

[0094] Figure 20 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0095] Figure 21 is a schematic diagram of the structure of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0096] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0097] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0098] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0099] In related technologies, the source and drain of a thin-film transistor (TFT) need to contact the active layer through vias penetrating the insulating layer. For liquid crystal display (LCD) products, light emitted from the backlight module can affect the leakage current of the TFT. Therefore, a light-shielding section is needed to block the active layer to reduce light-induced leakage current. Furthermore, to block as much of the active layer as possible, the light-shielding section needs to block the area of ​​the via where the drain contacts the active layer. However, during the via etching process, if some areas of the active layer are etched through, it can lead to electrical connection between the light-shielding section and the drain and pixel electrodes. This results in either a connection or a non-connection between the light-shielding section and the pixel electrodes, causing different capacitances between the gate and drain, ultimately leading to inconsistent deflection voltages of the liquid crystal molecules and uneven display.

[0100] This disclosure provides a display substrate, as shown in Figures 1 and 2, the display substrate comprising:

[0101] Substrate 1 includes display area AA;

[0102] Multiple first thin-film transistors 2 are located in the display area AA; the first thin-film transistor 2 includes: a first active layer 201, a first gate G1 located on the side of the first active layer 201 away from the substrate 1, and a first source S1 and a first drain D1 located on the side of the first gate G1 away from the first active layer 201.

[0103] Multiple first transparent electrodes 3 are located on the side of the first source electrode S1 and the first drain electrode D1 that is away from the substrate 1; the first transparent electrodes 3 are electrically connected to the first drain electrode D1;

[0104] Multiple vias 4, including multiple first vias 401 and multiple second vias 402; the first source S1 contacts the first active layer 201 through the first via 401, and the first drain D1 contacts the first active layer 201 through the second via 402.

[0105] A light-shielding layer 5 is located between the substrate 1 and the first active layer 201. The light-shielding layer 5 includes a plurality of light-shielding patterns 501 located in the display area AA. The orthographic projection of the light-shielding pattern 501 on the substrate 1 does not overlap with the orthographic projection of the bottom or top surface of the first via 401 and the second via 402 on the substrate 1. On the side where the orthographic projection of the first via 401 and the second via 402 on the substrate 1 faces the orthographic projection of the first gate G1 on the substrate 1, the orthographic projection of the light-shielding pattern 501 on the substrate 1 overlaps with the orthographic projection of the first active layer 201 on the substrate 1.

[0106] It should be noted that the orthographic projection of the light-shielding pattern on the substrate and the orthographic projection of the bottom or top surface of the first via and the second via on the substrate do not overlap, meaning that the orthographic projection of the light-shielding pattern on the substrate does not overlap with the orthographic projection of the bottom surface of the first via and the bottom surface of the second via on the substrate, and or, the orthographic projection of the light-shielding pattern on the substrate does not overlap with the orthographic projection of the top surface of the first via and the top surface of the second via on the substrate.

[0107] The display substrate provided in this embodiment has a light-shielding pattern whose orthogonal projection on the substrate does not overlap with the orthogonal projection of the bottom or top surface of the first via and the second via on the substrate. This avoids the via penetrating the active layer, causing the source and drain electrodes to be electrically connected to the light-shielding pattern. Consequently, it avoids the first transparent electrode being electrically connected to the light-shielding pattern, and avoids uneven display caused by areas on the display substrate where the first transparent electrode is electrically connected to the light-shielding pattern and areas where the first transparent electrode is not electrically connected to the light-shielding pattern.

[0108] It should be noted that Figure 2 is a cross-sectional view along FF' in Figure 1.

[0109] In some embodiments, as shown in FIG3, the distance h1 between the edge of the light-shielding pattern 501 projected onto the substrate 1 and the edge of the first via 401 and the second via 402 projected onto the substrate 1 is greater than or equal to 1.3 micrometers.

[0110] It should be noted that the patterning process of the light-shielding layer, vias, and thin-film transistors may contain errors that cause positional fluctuations in each layer. Furthermore, alignment deviations may exist in the patterning processes of different layers. In other words, these process fluctuations will affect the positions of the light-shielding pattern, the first via, and the second via. Considering these process fluctuations, the distance between the edge of the light-shielding pattern's projection onto the substrate and the edges of the first and second vias' projections onto the substrate is greater than or equal to 1.3.

[0111] The display substrate provided in this embodiment takes into account process fluctuations. The distance between the edge of the light-shielding pattern in the orthographic projection of the substrate and the edge of the first via and the second via in the orthographic projection of the substrate is greater than or equal to 1.3. This can ensure that the orthographic projection of the light-shielding pattern in the substrate does not overlap with the orthographic projection of the first via and the second via in the substrate, thereby avoiding the situation where the light-shielding pattern is electrically connected to the first transparent electrode due to process fluctuations.

[0112] In some embodiments, as shown in FIG2, the light-shielding pattern 501 corresponds one-to-one with the first active layer 201. Specifically, the orthogonal projection of the light-shielding pattern onto the substrate covers the channel region other than the first via and the second via. As shown in FIG2, the orthogonal projection of the light-shielding pattern 501 onto the substrate and the orthogonal projection of the first gate G1 onto the substrate have an overlapping area, and the orthogonal projection of the first gate G1 onto the substrate falls within the orthogonal projection of the light-shielding pattern 501 onto the substrate.

[0113] In some embodiments, as shown in FIG3, the first active layer 201 includes a first sub-active layer 2011, a second sub-active layer 2012, a third sub-active layer 2013, a fourth sub-active layer 2014, and a fifth sub-active layer 2015 connected in sequence; in the first direction Y, the second sub-active layer 2012 and the fourth sub-active layer 2014 are located on one side of the third sub-active layer 2013, the first sub-active layer 2011 is located on the side of the second sub-active layer 2012 away from the third sub-active layer 2013, and the fifth sub-active layer 2015 is located on the side of the fourth sub-active layer 2014 away from the third sub-active layer 2013; that is, the shape of the first active layer 2011 in the orthographic projection of the substrate is U-shaped;

[0114] The first via 401, when projected onto the substrate 1, falls within the projection of the first sub-active layer 2011 onto the substrate 1; the second via 402, when projected onto the substrate 1, falls within the projection of the fifth sub-active layer 2015 onto the substrate 1.

[0115] The orthographic projection of each light-shielding pattern 501 onto the substrate 1 does not overlap with the orthographic projection of the third sub-active layer 2013 onto the substrate 1. The orthographic projection of each light-shielding pattern 501 onto the substrate 1 covers the orthographic projection of the second sub-active layer 2012, the fourth sub-active layer 2014, and the area between the second sub-active layer 2012 and the fourth sub-active layer 2014 onto the substrate 1.

[0116] It should be noted that, in order to make it easier to see the orthographic projection relationship between the first active layer 201 and the light-shielding pattern 501 on the substrate 1, Figure 3 does not show other film layers besides the first active layer 201, the light-shielding pattern 501, and the substrate 1.

[0117] The display substrate provided in this embodiment has a light-shielding pattern integrally connected to shield the U-shaped active layer in the area other than the first via and the second via. This allows for maximum shielding of the first thin-film transistor channel region while avoiding electrical connection between the light-shielding layer and the pixel electrode, thereby further reducing the light leakage current of the first thin-film transistor.

[0118] In some embodiments, as shown in FIG3, the width of the first sub-active layer 2011 in the second direction X is greater than the width of the second sub-active layer 2012 in the second direction X, and the width of the fifth sub-active layer 201 in the second direction X is greater than the width of the fourth sub-active layer 2014 in the second direction X.

[0119] In some embodiments, as shown in FIG3, the orthogonal projection of the light-shielding pattern 501 onto the substrate 1 covers the orthogonal projections of the second sub-active layer 2012 and / or the fourth sub-active layer 2014 onto the substrate 1. Specifically, the coverage area of ​​the orthogonal projection of the light-shielding pattern 501 onto the substrate 1 can be determined based on the length of the second sub-active layer 2012 in the first direction Y, the length of the fourth sub-active layer 2014 in the first direction Y, and the extent of the channel region. In FIG3, the orthogonal projection of the light-shielding pattern 501 onto the substrate 1 covers the orthogonal projection of the fourth sub-active layer 2014 onto the substrate 1, and the orthogonal projection of the light-shielding pattern 501 onto the substrate 1 covers a portion of the orthogonal projection area of ​​the second sub-active layer 2012 onto the substrate 1.

[0120] In some embodiments, as shown in FIG3, the length of the second sub-active layer 2012 in the first direction Y is greater than the length of the fourth sub-active layer 2014 in the first direction Y.

[0121] In specific implementations, the orthographic projection coverage area of ​​the light-shielding pattern 501 on the substrate 1 can be determined based on the length of the second sub-active layer 2012 in the first direction Y, the length of the fourth sub-active layer 2014 in the first direction Y, and the extent of the channel region. In some embodiments, as shown in FIG3, the orthographic projection of the light-shielding pattern 501 on the substrate 1 may also overlap with the orthographic projections of the first sub-active layer 2011 and / or the fifth sub-active layer 2015 on the substrate 1. That is, the orthographic projection of the light-shielding pattern 501 on the substrate 1 covers the orthographic projections of the first sub-active layer 2011 near the second sub-active layer 2012 and / or the fifth sub-active layer 2015 near the fourth sub-active layer 2014 on the substrate 1. In Figure 3, examples are given where the orthographic projection of the light-shielding pattern 501 on the substrate 1 does not overlap with the orthographic projection of the first sub-active layer 2011 on the substrate 1, and the orthographic projection of the light-shielding pattern 501 on the substrate 1 overlaps with the orthographic projection of the fifth sub-active layer 2015 on the substrate 1.

[0122] In some embodiments, as shown in FIG2, the film layer on which the first gate G1 is located is the first conductive layer 24, and the film layer on which the first source S1 and the first drain D1 are located is the second conductive layer 25.

[0123] The light-shielding layer 5 is in direct contact with the substrate 1;

[0124] The display substrate also includes:

[0125] The first insulating layer 6 is located between the light-shielding pattern 501 and the first active layer 201;

[0126] The second insulating layer 30 is located between the first active layer 201 and the first conductive layer 24;

[0127] The third insulating layer 31 is located between the first conductive layer 24 and the second conductive layer 25.

[0128] The second transparent electrode 33 is located on the side of the second conductive layer 25 that is away from the substrate 1; the first transparent electrode 3 is located on the side of the second transparent electrode 33 that is away from the substrate 1.

[0129] The fourth insulating layer 34 is located between the second conductive layer 25 and the second transparent electrode 33;

[0130] The fifth insulating layer 35 is located between the second transparent electrode 33 and the first transparent electrode 3;

[0131] The first via 401 and the second via 402 are both vias 4 that penetrate the third insulating layer 31 and the second insulating layer 30; at the first via 401 and the second via 402, the first active layer 201 is a conductor region 2011, and the region outside the conductor region 2011 is a semiconductor region 2012.

[0132] The plurality of vias 4 also include: a plurality of third vias 403 penetrating the fourth insulating layer 34 and a plurality of fourth vias 404 penetrating the fifth insulating layer 35.

[0133] In some embodiments, as shown in FIG1, a plurality of first thin-film transistors 2 are arranged in an array along a first direction Y and a second direction X; the first direction Y intersects with the second direction X, and FIG1 illustrates the example where the first direction Y is perpendicular to the second direction X.

[0134] The second conductive layer 25 also includes multiple data lines 20; the data lines 20 are integrally connected to the first source S1; that is, the area where the data lines 20 contact the first active layer 201 serves as the first source S1; the multiple data lines 20 extend approximately along the first direction Y and are arranged along the second direction X.

[0135] The first conductive layer 24 also includes multiple scan lines 36; the scan lines 36 are integrally connected with the first gate G1; the multiple scan lines 36 are arranged along the first direction Y and generally extend along the second direction X.

[0136] It should be noted that "multiple data lines extending approximately along the first direction Y" means that the multiple data lines can extend in a straight line or a zigzag line along the first direction Y. "Multiple scan lines extending approximately along the second direction X" means that the multiple scan lines can extend in a straight line or a zigzag line along the second direction X. The intersection of multiple scan lines and multiple data lines divides the area of ​​a sub-pixel.

[0137] In some embodiments, the first transparent electrode is a pixel electrode, and the second transparent electrode is a common electrode.

[0138] In some embodiments, the first transparent electrode may be located between the second transparent electrode and the second conductive layer.

[0139] In some embodiments, as shown in FIG1, the second transparent electrode 33, i.e. the common electrode, is disposed over the entire surface.

[0140] In some embodiments, the second transparent electrode is reused as a touch electrode. That is, the display substrate is used in a touch display product. As shown in FIG1, the second transparent electrode 33 includes a plurality of openings 3301. The plurality of openings are used to divide the second transparent electrode into regions of a plurality of touch electrodes. As shown in FIG1, the second conductive layer 25 also includes a plurality of common electrode lines 37. The common electrode lines 37 are reused as touch traces.

[0141] In some embodiments, the materials of the first transparent electrode and the second transparent electrode include indium tin oxide.

[0142] In some embodiments, as shown in FIG4, the substrate 1 further includes: a peripheral region NA surrounding the display area AA; the peripheral region NA includes: a first peripheral region NA1 and a second peripheral region NA2 located on both sides of the display area AA in the first direction Y, and a third peripheral region NA3 and a fourth peripheral region NA4 located on both sides of the display area AA in the second direction X.

[0143] The first peripheral region NA1 includes at least one bonding region 41, and the bonding region 41 includes a plurality of bonding pins 16; when the display substrate is applied to the display panel, the display panel also needs to be bonded to the driver chip, and the driver chip is bonded to the plurality of bonding pins 16 in the bonding region 41 of the display substrate.

[0144] The first peripheral area NA1 also includes a fan-out area 43 located between the display area AA and the binding area 41 in the first direction Y.

[0145] In some embodiments, as shown in FIG4, the peripheral region NA includes a plurality of signal lines 44; among the plurality of signal lines 44, at least a portion of the signal lines 44 are located in the fan-out region 43 in the orthographic projection of the substrate 1; the signal lines 44 are electrically connected to the bonding pins 16.

[0146] It should be noted that Figure 4 only shows signal line 44 electrically connected to data line 20. In specific implementations, multiple signal lines also include signal lines electrically connected to scan lines, signal lines electrically connected to common electrodes, etc. Thus, the driver chip can transmit signals through bonding pins, signal lines located in the peripheral area, and various traces in the display area. Among the multiple signal lines, the signal lines whose orthogonal projection on the substrate passes through the fan-out area are fan-out lines. Signal lines electrically connected to both scan lines and bonding pins, and signal lines electrically connected to both data lines and bonding pins are all fan-out lines. When the common electrode is multiplexed as a touch electrode, and the common electrode line is multiplexed as a touch signal line, the signal lines electrically connected to both the touch signal line and bonding pins are also fan-out lines.

[0147] In some embodiments, as shown in FIG5, the multiple signal lines 44 include a light-shielding layer trace 502 located in the light-shielding layer 5, a first conductive layer trace 2401 located in the first conductive layer 24, and a second conductive layer trace 2501 located in the second conductive layer 25. That is, the display substrate provided in this embodiment has three layers of wiring in the peripheral area. Compared with the two layers of wiring in the peripheral area in related technologies, it can further save wiring space, which is beneficial to reduce the size of the peripheral area and makes it easier to achieve narrow bezel display.

[0148] It should be noted that the signal line 44 shown in Figure 5 includes three conductive layers. However, not every signal line in the surrounding area is necessarily a three-layer wiring. Each signal line includes at least one of the following: a light-shielding layer trace, a first conductive layer trace, and a second conductive layer trace.

[0149] In some embodiments, as shown in FIG6, the light-shielding layer 5 includes: a first sub-conductive layer 5-1, a second sub-conductive layer 5-2, and a third sub-conductive layer 5-3 stacked together;

[0150] The first conductive layer 24 includes: a fourth sub-conductive layer 24-1, a fifth sub-conductive layer 24-2, and a sixth sub-conductive layer 24-3 stacked together;

[0151] The second conductive layer 25 includes a seventh sub-conductive layer 25-1, an eighth sub-conductive layer 25-2, and a ninth sub-conductive layer 25-3 stacked together.

[0152] In some embodiments, the thickness of the second sub-conductive layer is greater than the thickness of the first sub-conductive layer and the thickness of the third sub-conductive layer;

[0153] The thickness of the fifth sub-conductive layer is greater than the thickness of the fourth sub-conductive layer and the thickness of the sixth sub-conductive layer;

[0154] The thickness of the eighth sub-conductive layer is greater than the thickness of the seventh sub-conductive layer and the thickness of the ninth sub-conductive layer.

[0155] In some embodiments, the materials of the first sub-conductive layer, the third sub-conductive layer, the fourth sub-conductive layer, and the sixth sub-conductive layer are molybdenum;

[0156] The materials for the seventh and ninth sub-conductive layers are titanium.

[0157] The materials for the second, fifth, and eighth sub-conductive layers are aluminum.

[0158] The display substrate provided in this embodiment includes three sub-conductive layers: a light-shielding layer, a first conductive layer, and a second conductive layer. The intermediate sub-conductive layers of the light-shielding layer, the first conductive layer, and the second conductive layer are all aluminum conductive layers. Since aluminum has low resistance, the resistance of the light-shielding layer, the first conductive layer, and the second conductive layer can be reduced. Furthermore, other sub-conductive layers are disposed above and below the aluminum conductive layers of the light-shielding layer, the first conductive layer, and the second conductive layer to prevent warping of the aluminum conductive layers.

[0159] In some embodiments, as shown in FIG6, the plurality of vias 4 further include: a plurality of fifth vias 405 and a plurality of sixth vias 406; the fifth vias 405 penetrate the third insulating layer 31, the second insulating layer 30 and the first insulating layer 6, and the sixth vias 406 penetrate the third insulating layer 31.

[0160] In the peripheral area (not shown), the trace 2501 located in the second conductive layer 25 is electrically connected to the trace 502 located in the light-shielding layer 5 through the fifth via 405, and the trace 2501 located in the second conductive layer 25 is electrically connected to the trace 2401 located in the first conductive layer 24 through the sixth via 406.

[0161] It should be noted that the first, second, fifth, and sixth vias are all formed through a patterning process after the third insulating layer is coated. This means that three types of vias need to be formed simultaneously: contact holes for the light-shielding layer, contact holes for the active layer, and contact holes for the first conductive layer, all requiring good overlap. However, the sixth via (contact hole in the first conductive layer) is relatively shallow, while the fifth via (contact hole in the light-shielding layer) is relatively deep. This difference in film thickness leads to significant etching differences at each via location. There is a risk of over-etching the top molybdenum conductive layer of the first conductive layer, exposing the aluminum conductive layer and allowing acid corrosion of the aluminum metal in subsequent processes, thus affecting the yield of the first conductive layer.

[0162] In some embodiments, the thickness of the first conductive layer is greater than or equal to 4300 angstroms and less than or equal to 4800 angstroms.

[0163] In some embodiments, the ratio of the thickness of the fourth sub-conductive layer to the thickness of the fifth sub-conductive layer is greater than or equal to 16% and less than or equal to 25%, and the ratio of the thickness of the sixth sub-conductive layer to the thickness of the fifth sub-conductive layer is greater than or equal to 25% and less than or equal to 34%.

[0164] The display substrate provided in this embodiment has a thicker sixth sub-conductive layer, which can reduce the risk of over-etching of the sixth sub-conductive layer at the top of the first conductive layer, prevent the fifth sub-conductive layer from being exposed and corroded, and improve the yield of the first conductive layer.

[0165] In some embodiments, when the thickness of the fifth sub-conductive layer is 3000 angstroms, for example, the thickness of the fourth sub-conductive layer is greater than or equal to 500 angstroms and less than or equal to 800 angstroms, and the thickness of the sixth sub-conductive layer is greater than or equal to 800 angstroms and less than or equal to 1000 angstroms. In some embodiments, the thickness of the fourth sub-conductive layer is 500 angstroms, and the thickness of the sixth sub-conductive layer is 1000 angstroms.

[0166] It should be noted that due to the increased thickness of the sixth sub-conductive layer, the etching time of the third insulating layer needs to be increased to ensure a good overlap between the second conductive layer and the first conductive layer and the light-shielding layer. In related technologies, the thickness of the molybdenum metal at the top of the first conductive layer is 800 angstroms, and the etching time of the third insulating layer is approximately 135 ± 90 seconds (s). When the thickness of the sixth sub-conductive layer increases to 1000 angstroms, the etching time of the third insulating layer increases, for example, to 165 ± 80 seconds. The etching of the third insulating layer typically requires the use of two etchants: the first etchant is used first, followed by the second. The second etchant is insensitive to etching the sixth sub-conductive layer, thus preventing over-etching of the sixth sub-conductive layer. For example, the first etchant is carbon tetrafluoride, and the second etchant is pentafluoroethane. To ensure that the topmost molybdenum layer of the first conductive layer is not over-etched, the etching time of the first etchant (carbon tetrafluoride) is maximized while the etching time of the second etchant (pentafluoroethane) is minimized. The etching time ratio of the first etchant to the second etchant is approximately 2:1 to 3:1. This ensures good adhesion between the second conductive layer and the first conductive layer and the light-shielding layer, while preventing the sixth sub-conductive layer from being over-etched.

[0167] In some embodiments, the active layer is made of polycrystalline silicon.

[0168] In some embodiments, the material of the first insulating layer includes silicon oxide.

[0169] In some embodiments, as shown in FIG6, the light-shielding layer 5 has a first surface 38, a second surface 39 parallel to the plane of the substrate 1, and a first side surface 40 connecting the first surface 38 and the second surface 39; the second surface 39 is located on the side of the first surface 38 away from the substrate 1.

[0170] The first side 40 of the light-shielding layer 5 has a slope angle a1, that is, the angle between the first side 40 and the first surface 38 is less than 90°.

[0171] In some embodiments, as shown in FIG6, the first insulating layer 6 includes a first sub-insulating layer 601, a second sub-insulating layer 602, and a third sub-insulating layer 603 sequentially stacked on the side of the light-shielding pattern 501 away from the substrate 1; the density of the second sub-insulating layer 602 is greater than the density of the first sub-insulating layer 601 and the density of the third sub-insulating layer 603.

[0172] It should be noted that in related technologies, during photolithography or oxidation, defects in the first insulating layer, i.e., the silicon oxide film, can cause localized pinholes, resulting in discontinuities in the oxide layer and a pinhole effect. When a three-layer sub-conductive layer is used as the light-shielding layer, the thickness of the light-shielding layer increases compared to a single-layer conductive layer. If the slope angle of the light-shielding layer is too large, the silicon oxide film covering the sides of the light-shielding layer may be thinner, increasing the likelihood of pinholes. Subsequent etching processes may result in etching solution seeping into the light-shielding layer through the pinholes, corroding the light-shielding layer and causing defects in the light-shielding layer pattern.

[0173] The display substrate provided in this disclosure, by covering a less dense first sub-insulating layer with a denser second sub-insulating layer, can alleviate or even avoid the pinhole effect in the first insulating layer, thereby preventing the etching solution from corroding the light-shielding layer and improving the fabrication yield of the light-shielding layer. Film density affects adhesion. Since the density of the first sub-insulating layer is lower than that of the second sub-insulating layer, the problem of peeling and breakage of the first insulating layer, which would occur if the entire first insulating layer were a high-density film layer, can be avoided. This allows for the setting of a denser second sub-insulating layer, avoiding the pinhole effect, while ensuring adhesion between the first insulating layer and the light-shielding layer. Furthermore, the placement of a less dense third sub-insulating layer above the second sub-insulating layer avoids affecting the crystallization effect of the active layer.

[0174] In some embodiments, the first sub-insulating layer, the second sub-insulating layer, and the third sub-insulating layer are all made of the same material. The density of the first, second, and third sub-insulating layers can be varied by adjusting their deposition rates. A slower deposition rate results in more uniform material diffusion and a higher density of the formed film; that is, the deposition rate of the second sub-insulating layer is lower than that of the first and third sub-insulating layers.

[0175] In some embodiments, the coating rate of the second sub-insulating layer is greater than or equal to 13 A / s and less than or equal to 19 A / s, and the coating rates of the first and third sub-insulating layers are greater than or equal to 64 A / s and less than or equal to 70 A / s.

[0176] In some embodiments, the density of the first sub-insulating layer is equal to the density of the third sub-insulating layer. That is, the deposition rate of the first sub-insulating layer is equal to the deposition rate of the third sub-insulating layer.

[0177] In some embodiments, the deposition rate of the second sub-insulating layer is 15 A / s, and the deposition rates of the first and third sub-insulating layers are 65 A / s.

[0178] In some embodiments, the thickness of the second sub-insulating layer is greater than or equal to the thickness of the first sub-insulating layer, and the thickness of the second sub-insulating layer is greater than the thickness of the third sub-insulating layer.

[0179] In some embodiments, the thickness of the first insulating layer, i.e., the total thickness of the first sub-insulating layer, the second sub-insulating layer, and the third sub-insulating layer, is greater than or equal to 3720 angstroms and less than or equal to 4280 angstroms.

[0180] In related technologies, the thickness of a single uniform density first insulating layer is about 3300 angstroms. However, in the display substrate provided in this disclosure, the thickness of the first insulating layer is greater than or equal to 3720 angstroms and less than or equal to 4280 angstroms. This means that while increasing the density of the first insulating layer, the thickness of the first insulating layer is also increased, further avoiding the problem that the first insulating layer film covering the first side of the light-shielding layer is too thin and the probability of pinhole effect increases.

[0181] In some embodiments, the thickness of the first sub-insulating layer is greater than or equal to 1400 angstroms and less than or equal to 1500 angstroms, the thickness of the second sub-insulating layer is greater than or equal to 1420 angstroms and less than or equal to 1580 angstroms, and the thickness of the third sub-insulating layer is greater than or equal to 900 angstroms and less than or equal to 1100 angstroms.

[0182] In some embodiments, the total thickness of the first sub-insulating layer, the second sub-insulating layer, and the third sub-insulating layer is 4000 angstroms; the thickness of the first sub-insulating layer and the second sub-insulating layer is 1500 angstroms, and the thickness of the third sub-insulating layer is 1000 angstroms.

[0183] In some embodiments, as shown in FIG6, the slope angle α1 of the light-shielding layer 5 is greater than 0° and less than or equal to 40°.

[0184] In related technologies, the slope angle of the light-shielding layer is typically close to 50°. The display substrate provided in this disclosure has a slope angle α1 of the light-shielding layer greater than 0° and less than or equal to 40°, which is equivalent to reducing the slope angle α1 of the light-shielding layer. This avoids the problem of a thinner first insulating layer covering the first side of the light-shielding layer, increasing the probability of pinhole effects. It further prevents etching solution from seeping into the light-shielding layer through small holes and corroding it, leading to pattern loss in the light-shielding layer, thus improving the yield rate of the light-shielding layer.

[0185] In some embodiments, the slope angle α1 of the light-shielding layer is, for example, 38°.

[0186] In some embodiments, as shown in Figures 4 and 7, the display substrate further includes:

[0187] Multiple first signal lines 7 are located in the peripheral area NA on one side of the display area AA in the first direction Y; each of the multiple first signal lines 7 includes a first trace 701 and / or a second trace 702; the first trace 701 is disposed on the same layer as the light-shielding pattern 501, that is, the light-shielding layer 5 includes the first trace 701, and the second trace 702 is disposed on the same layer as the first gate G1; both the first trace 701 and the second trace 702 include a first portion 8, and the angle between the extension direction of the first portion 8 and the first direction Y is greater than 0° and less than 90°; multiple first... In signal line 7, a portion of the first trace 701 is arranged along the second direction X, and a portion of the second trace 702 is arranged along the second direction X. The second direction X intersects the first direction Y and the extension direction of the first portion 8. The orthographic projection of the first portion 8 of the first trace 701 onto the substrate 1 overlaps with the orthographic projection of the first portion 8 of the second trace 702 onto the substrate 1, and the area between the orthographic projections of the first portions 8 of any two adjacent second traces 702 onto the substrate 1 overlaps with the orthographic projection of the first portion 8 of the first trace 701 onto the substrate 1.

[0188] It should be noted that the patterning process for the second traces in areas where there is a light-shielding layer beneath the first portion of two adjacent second traces has higher resolution, which is more conducive to exposure. In related technologies, as shown in Figure 8, in a certain region (E3 in the figure), the area between the orthographic projections of two adjacent second traces 702 on the substrate 1 does not overlap with the orthographic projection of the first trace 701 on the substrate 1. That is, there is no pattern of the light-shielding layer 5 beneath the area between the two adjacent second traces E3 in region E3. The patterning process for the second traces in areas where there is no light-shielding layer beneath the area between two adjacent second traces has lower resolution, which can easily lead to insufficient exposure, adhesion between adjacent second traces, and short circuits.

[0189] The display substrate provided in this embodiment has an area between the orthographic projection of the first portion of any two adjacent second traces onto the substrate, which overlaps with the orthographic projection of the first portion of the first trace onto the substrate. That is, there is a light-shielding layer below the area between the first portions of any two adjacent second traces, which is the pattern of the first portion of the first trace. This can improve the uniformity of the resolution of the patterning process of the second traces, avoid the problem of adhesion and short circuit between adjacent second traces, and improve the manufacturing yield of the display substrate.

[0190] Furthermore, in some embodiments, as shown in FIG7, the region between the first portions 8 of any two adjacent second traces 702 in the orthographic projection of the substrate 1 overlaps with the edge of the first portion 8 of the first trace 701 in the orthographic projection of the substrate 1.

[0191] It should be noted that Figure 7 is an enlarged schematic diagram of the E2 region in Figure 4. That is, as shown in Figure 4, the multiple signal lines 44 include multiple first signal lines 7; the first trace 701 in the first signal line 7 is the light-shielding layer trace 502, and the second trace in the first signal line 7 is the first conductive layer trace 2401.

[0192] In some embodiments, as shown in FIG7, the first portion 8 has a first edge 801 that extends in the same direction as the display area AA and is close to the side of the display area AA.

[0193] In the region near the display area (E7), in the orthographic projection of the substrate 1, there are overlapping first traces 701 and second traces 702. The first edge 801 of the second trace 702 is closer to the display area AA in the orthographic projection of the substrate 1 than the first edge 801 of the first trace 701. The first edge 801 of the first trace 701 is located between the first portions 8 of the two adjacent second traces 702 in the orthographic projection of the substrate 1.

[0194] In the display substrate provided in this embodiment, in the region near the display area (i.e., the first fan-out region 4301 described below) of the dashed line E7, the first edge of the second trace is closer to the display area than the first edge of the first trace. That is, the upper edge of the second trace is located above the upper edge of the first trace. This ensures that the region between the orthographic projections of the first portions of any two adjacent second traces on the substrate overlaps with the orthographic projections of the first portions of the first traces on the substrate.

[0195] In the area far from the display area (i.e., the second fan-out area 4302 described later) of the dashed line E7, alternatively, the area between the orthographic projection of the first part of any two adjacent second traces on the substrate 1 overlaps with the orthographic projection of the edge of the first part of the first trace on the substrate 1. This can improve the uniformity of the patterning process resolution of the second traces, avoid the problem of adjacent two second traces sticking together or short-circuiting, and improve the yield of the display substrate.

[0196] In some embodiments, in a first trace and a second trace that overlap in the orthographic projection of the substrate, the distance between the first edge of the first trace in the orthographic projection of the substrate and the first edge of the second trace in the orthographic projection of the substrate is approximately 0.8 micrometers. This ensures that, considering process variations, the region between the first portions of any two adjacent second traces in the orthographic projection of the substrate overlaps with the first portion of the first trace in the orthographic projection of the substrate.

[0197] In some embodiments, as shown in FIG4, a plurality of first signal lines 7 constitute at least one signal line group 10; the display substrate further includes:

[0198] At least one pin group 15; the orthographic projection of at least one pin group 15 onto the substrate 1 is located on the side of the substrate 1 away from the display area AA where the orthographic projection of multiple first signal lines 7 is onto the substrate 1. For example, the pin group 15 corresponds one-to-one with the bonding area 41, and the orthographic projection of one pin group 15 onto the substrate 1 is located in one bonding area 41; the pin group 15 includes multiple bonding pins 16; the first signal lines 7 are electrically connected to the bonding pins 16; for example, the signal line group 10 corresponds one-to-one with the pin group 15, and multiple first signal lines 7 in one signal line group 10 are electrically connected to some of the bonding pins 16 in one pin group 15.

[0199] It should be noted that Figure 4 is an example of a display substrate including one signal line group 10 and one pin group 15. When the display substrate includes multiple signal line groups 10 and multiple pin groups 15, the multiple signal line groups 10 are arranged along the second direction X, and the multiple pin groups 15 are arranged along the second direction X.

[0200] In some embodiments, as shown in FIG4, the end of the first signal line 7 away from the bonding pin 16 is electrically connected to the data line 20. Multiple data lines 20 are arranged along a second direction X, as shown in FIG9. A portion of the multiple first signal lines 7 are also arranged along the second direction X, with the first traces 701 and second traces 702 alternating in the arrangement of the multiple first signal lines 7 along the second direction X. That is, the multiple first signal lines 7 include regions where the first traces 701 and second traces 702 are alternately arranged (regions E4, E5, and E6 in FIG9) and regions where the first traces 701 and second traces 702 overlap in their orthographic projections onto the substrate 1.

[0201] In some embodiments, as shown in FIG9, one end of the first signal line 7 is electrically connected to the data line 20, and the other end of the first signal line 7 extends to the bonding area 41 and is electrically connected to the bonding pin 16. At both ends of the first signal line 7, a plurality of first signal lines 7 are arranged along the second direction X.

[0202] In some embodiments, as shown in Figures 7 and 9, the first trace 701 and the second trace 702 further include a first connecting portion 9 disposed on the same layer as and electrically connected to the first portion 8. That is, the first connecting portion 9 of the first trace 701 is disposed on the same layer as the first portion 8 of the first trace 701, and the first connecting portion 9 of the second trace 702 is disposed on the same layer as the first portion 8 of the second trace 702.

[0203] In some embodiments, as shown in FIG7 and FIG9, the first connecting portion 9 is located at least on one side of the first portion 8 in the first direction Y when projected onto the substrate 1.

[0204] At one end of the plurality of first portions 8, the plurality of first connecting portions 9 are arranged along the second direction X in the orthographic projection of the substrate 1, and the first connecting portions 9 of the first trace 701 and the first connecting portions 9 of the second trace 702 are arranged alternately in the orthographic projection of the substrate 1.

[0205] In some embodiments, as shown in Figures 7 and 9, the width of the first connecting portion 9 in the second direction X is greater than the line width of the first portion 8, that is, the width of the first portion 8 in the direction perpendicular to its extension.

[0206] In some embodiments, as shown in Figures 7 and 9, the first trace 701 and the second trace 702 further include a second portion 13 disposed on the same layer as the first portion 8 and the first connecting portion 9; in the first direction Y, the second portion 13 is electrically connected to the first portion 8 on at least one side. That is, one or both ends of the first portion 8 are electrically connected to the second portion 13.

[0207] In some embodiments, as shown in Figures 7 and 9, the first part 8 and the first connecting part 9 are electrically connected through the second part 13.

[0208] In some embodiments, as shown in FIG7, the first signal line 7 further includes a second connection portion 703 located on a different layer from the first trace 701 and the second trace 702; the first connection portion 9 is electrically connected to the second connection portion 703. Specifically, the second connection portion 703 is electrically connected to the first connection portion 9 of the first trace 701 through a fifth via 405, and the second connection portion 703 is electrically connected to the first connection portion 9 of the second trace 702 through a sixth via 406. FIG5 is, for example, a cross-sectional view along II' in FIG7.

[0209] In some embodiments, as shown in FIG7 and FIG9, each first signal line 7 includes a first trace 701 and a second trace 702.

[0210] The first trace 701 and the second trace 702 in the first signal line 7 do not overlap in their orthographic projections on the substrate 1.

[0211] The first connecting portion 9 of the first trace 701 and the first connecting portion 9 of the second trace 702 are electrically connected via the second connecting portion 703 (not shown in FIG9).

[0212] The display substrate provided in this embodiment features a three-layer wiring for the first signal line. Within the same first signal line, the first trace and the second trace are electrically connected via jumpers from a second connection portion, which is more conducive to saving wiring space. It also avoids the accumulation of static electricity due to excessively long trace lengths.

[0213] In some embodiments, the second connection portion is disposed on the same layer as the source and drain. That is, as shown in Figures 5 and 7, the second connection portion 703 is located in the second conductive layer 25.

[0214] In some embodiments, as shown in FIG7 and FIG9, the fan-out area 43 includes a first fan-out area 4301 and a second fan-out area 4302 located on the side of the first fan-out area 4301 away from the display area AA in the first direction Y.

[0215] In the first signal line 7, the orthographic projection of one of the first trace 701 and the second trace 702 on the substrate 1 is located in the first fan-out region 4301, and the orthographic projection of the other of the first trace 701 and the second trace 702 on the substrate 1 is located in the second fan-out region 4302.

[0216] In the first sector 4301, multiple first traces 701 are arranged along the second direction X, and multiple second traces 702 are arranged along the second direction X.

[0217] In the second sector 4302, multiple first traces 701 are arranged along the second direction X, and multiple second traces 702 are arranged along the second direction X.

[0218] In some embodiments, as shown in FIG9, in the region E6 of the jumper between the first trace 701 and the second trace 702, the first trace 701 and the second trace 702 in the first fan-out region 4301 are alternately arranged in the orthographic projection of the first trace 701 and the second trace 702 on the substrate 1 along the second direction X; in the second fan-out region 4302, the first trace 701 and the second trace 702 in the orthographic projection of the first trace 701 and the second trace 702 on the substrate 1 are alternately arranged in the second direction X.

[0219] In some embodiments, as shown in Figures 7 and 9, the orthographic projection of the first connecting portion 9 onto the substrate 1 is rectangular. That is, the orthographic projection pattern of the first connecting portion 9 onto the substrate 1 has a right-angled region.

[0220] Alternatively, in some embodiments, the first connection portion does not include right-angled areas in the orthographic projection pattern of the substrate. Specifically, the first connection portion is connected between edges extending perpendicularly in the orthographic projection pattern of the substrate by arc segments or straight segments intersecting the perpendicular edges. This can reduce the risk of tip discharge at the first connection portion.

[0221] In some embodiments, the orthographic projection pattern of the first connecting portion onto the substrate is an octagon.

[0222] Alternatively, in some embodiments, as shown in FIG10, the pattern of the first connecting portion 9 projected onto the substrate 1 includes rounded corner areas. That is, in the pattern of the first connecting portion 9 projected onto the substrate 1, the edges extending perpendicularly (e.g., the two line segments labeled 45 and 46 in the figure) are connected by arc segments 47, thereby avoiding sharp corners in the first connecting portion 9, reducing the risk of tip discharge of the first connecting portion, and preventing discharge damage to adjacent traces. For example, in FIG10, the orthogonal projection of the first connecting portion 9 onto the substrate 1 is a rounded rectangle.

[0223] In some embodiments, the orthographic projection of the second connecting portion onto the substrate is rectangular. That is, the orthographic projection pattern of the second connecting portion onto the substrate has a right-angled region.

[0224] Alternatively, in some embodiments, the second connection portion in the orthographic projection pattern of the substrate does not include right-angled areas. Specifically, the edges of the second connection portion extending perpendicularly in the orthographic projection pattern of the substrate are connected by arc segments or straight segments intersecting all the perpendicular edges. This can reduce the risk of tip discharge of the second connection portion. In some embodiments, the orthographic projection pattern of the second connection portion in the substrate is octagonal. Alternatively, in some embodiments, the orthographic projection pattern of the second connection portion in the substrate is a rounded rectangle.

[0225] In some embodiments, FIG4 illustrates an example of a display substrate including a pin group 15. Alternatively, in some embodiments, as shown in FIG11, the display substrate includes a plurality of pin groups 15 arranged along a second direction X, and correspondingly, a plurality of first signal lines 7 are divided into a plurality of signal line groups 10 arranged along the second direction X. For example, two adjacent pin groups 15 are arranged substantially symmetrically, and two adjacent signal line groups 10 are arranged substantially symmetrically.

[0226] Due to limited wiring space, the area between two adjacent signal line groups, i.e., region E8 in Figure 11, has relatively small wiring space. The use of a three-layer sub-conductive layer stack in the light-shielding layer results in low resistance. However, when the trace length in the surrounding area of ​​the light-shielding layer is too long, static electricity can easily accumulate. In related technologies, the distance between the first traces of the light-shielding layer of two adjacent signal line groups is too close, typically about 115 micrometers. Static electricity is easily released at this close distance, causing damage to the light-shielding layer traces. In severe cases, this can lead to trace breaks, preventing signal transmission and affecting the yield of the light-shielding layer traces, which in turn affects the yield of the display substrate.

[0227] In some embodiments, as shown in FIG12, the two first traces 701 that are closest to each other in two adjacent signal line groups 10 further include a second portion 13 located on one side of the first portion 8 in the first direction Y and electrically connected to the first portion 8, the second portion 13 including at least a portion extending along the first direction Y;

[0228] In two adjacent signal line groups 10, the distance h2 between the second portions 13 of the two closest first traces 701 in the second direction X is greater than or equal to 290 micrometers.

[0229] In the display substrate provided in this embodiment, the distance h2 between the second portions of the light-shielding layer that are closest to each other in two adjacent signal line groups is greater than or equal to 290 micrometers in the second direction. This is equivalent to increasing the distance between the light-shielding layer traces, thereby preventing static electricity from being released at locations where the traces are close together and damaging the light-shielding layer traces, improving the manufacturing yield of the light-shielding layer, and thus improving the manufacturing yield of the display substrate.

[0230] It should be noted that Figure 11 is a simplified schematic diagram of the NA signal line group and bonding pin in the peripheral area. Figure 12 is a detailed structural schematic diagram of the E8 area in Figure 11. In Figure 12, the two first traces 701, labeled 701-1 and 701-2, are the two closest first traces 701 in two adjacent signal line groups 10, respectively. The two closest first traces 701 in two adjacent signal line groups 10 are the rightmost first trace 701 in the left signal line group 10 and the leftmost first trace 701 in the right signal line group 10, respectively. The second parts 13, labeled 13-1 and 13-2, are the closest second parts 13 in two adjacent signal line groups 10, respectively. The second parts 13, labeled 13-1 and 13-2, are both electrically connected to the end of the first part 8 that is away from the bonding pin 16 in the extension direction.

[0231] In some embodiments, as shown in FIG12, the plurality of signal lines 44 further includes a plurality of second signal lines 50. A portion of the second signal line 50 is located between two adjacent first signal lines 7; one end of the second signal line 50 is electrically connected to a common electrode line (not shown), and the other end of the second signal line 50 is electrically connected to a bonding pin (not shown). The second signal line 50 also extends through the fan-out region 43 to the bonding region (not shown), i.e., the second signal line 50 is also a fan-out line. The second signal line 50 includes at least a second conductive layer trace 2501.

[0232] In some embodiments, in order to make full use of the wiring space, as shown in FIG12, the second part 13, denoted by reference numerals 13-1 and 13-2, is located on the side of the first part 8 away from the display area AA; the two first traces 701, denoted by reference numerals 701-1 and 701-2, also include second conductive layer traces 2501. The second parts 13, denoted by reference numerals 13-1 and 13-2, are all electrically connected to the second conductive layer traces 2501. The second conductive layer traces 2501, which are electrically connected to the second parts 13, denoted by reference numerals 13-1 and 13-2, respectively, each include a plurality of second connecting portions 703. The corresponding first traces 701 also include first connecting portions 9 that are electrically connected to the second connecting portions 703 one by one. In two adjacent signal line groups 10, the two closest first traces 701, namely the two first traces 701-1 and 701-2 in the attached drawings, have their orthographic projections on the substrate 1 overlapping with the orthographic projections of the second signal line 50 on the substrate 1. Therefore, there is an overlapping area between the orthographic projections of the first trace 701 on the substrate 1 and the orthographic projections of the second signal line 50 on the substrate 1. The first trace 701 also includes a light-shielding layer trace 502, which connects the two first connection portions 9.

[0233] In some embodiments, as shown in FIG11, at least in the first peripheral region NA1, the display substrate further includes a plurality of dummy traces 48.

[0234] In some embodiments, as shown in FIG12, the display substrate further includes:

[0235] Multiple first dummy traces 11 are disposed on the same layer as the light-shielding pattern (not shown); that is, multiple dummy traces 48 include: multiple first dummy traces 11 located in the light-shielding layer 5; multiple first dummy traces 11 extend along the first direction Y;

[0236] The orthographic projection of the first dummy trace 11 onto the substrate 1 is located in the region between the orthographic projections of the two closest first traces 701 onto the substrate 1 in two adjacent signal line groups 10.

[0237] The display substrate provided in this embodiment provides multiple first dummy traces in the area between the orthographic projections of the two closest first traces in two adjacent signal line groups onto the substrate, thereby further preventing static electricity from being released at the two closest first traces and damaging the first traces.

[0238] In some embodiments, as shown in FIG12, the display substrate further includes:

[0239] Multiple second dummy traces 12 are disposed on the same layer as the light-shielding pattern (not shown); that is, the multiple dummy traces 48 also include: multiple second dummy traces 12 located in the light-shielding layer 5; the second dummy traces 12 are located on the side of the portion of the first trace 701 away from the display area AA, and the second dummy traces 12 include at least a portion extending in the same direction as the first portion 8.

[0240] It should be noted that, since the fan-out area includes a large number of signal lines, reducing the size of the fan-out area increases the difficulty of patterning the signal lines. Typically, signal lines are made of metal and require processes such as photoresist coating, exposure, development, and etching to form the fan-out line pattern. For any of the light-shielding conductive layers, the first conductive layer, and the second conductive layer, if there is a large blank area on one side of the signal line, this area, without photoresist coverage, is prone to accumulating a large amount of etching solution. A high concentration of etching solution can cause the traces near the blank area to be etched through, affecting signal transmission. The signal line group has large blank areas on both sides of the second direction X. In this embodiment, the second dummy trace is a dummy trace set in the blank area on one side of multiple first traces in the light-shielding layer, avoiding damage to the first traces near the blank area. If the first signal line includes a first trace and a second trace, in a signal line group, multiple second dummy traces are provided on the side of the first trace and the last trace of the multiple first traces in the first fan-out area that are far from the display area, and multiple second dummy traces are provided on the side of the first trace and the last trace of the multiple first traces in the second fan-out area that are far from the display area.

[0241] It should be noted that if one end of the second dummy trace on one side of the second part is at the same distance from the second part, that is, if the end of the second dummy trace on one side of the second part is on a straight line extending along the first direction Y, the risk of tip discharge is more likely to occur.

[0242] In some embodiments, as shown in FIG12, a portion of the second dummy trace 12 is located on the side of the second portion 13 away from the adjacent signal line group 10 in the second direction X, and the distance between the portion of the second dummy trace 12 and the second portion 13 is not exactly the same. That is, the end of the portion of the second dummy trace 12 near the second portion 13 is not on a straight line extending along the first direction Y. This reduces the risk of tip discharge of the second dummy trace on one side of the second portion, avoids damage to the light-shielding layer traces, and improves the yield of the display substrate.

[0243] In some embodiments, as shown in FIG12, among the multiple second dummy traces 12 on one side of the second portion 13, the distance h4 between the second dummy trace 12 closest to the display area (not shown) and the second portion 13 is smaller than the distance h5 between the other second dummy traces 12 and the second portion 13.

[0244] In some embodiments, as shown in FIG12, among the multiple second dummy traces 12 on one side of the second portion 13, the distance h5 between the remaining second dummy traces 12, except for the second dummy trace 12 closest to the display area (not shown), and the second portion 13 is approximately 50 micrometers.

[0245] In some embodiments, as shown in Figures 13-15, the display substrate further includes:

[0246] Multiple third traces 14 are located in the peripheral region NA; the multiple third traces 14 are located on different layers from the first trace (not shown) and the second trace 702; some of the multiple third traces 14 include a third portion 1401 whose extension direction intersects the extension direction of the first portion 8; the area where the orthographic projection of the third portion 1401 of the multiple third traces 14 on the substrate 1 overlaps with the orthographic projection of the second trace 702 on the substrate 1 is the first sub-region E1.

[0247] In some embodiments, the third trace is disposed on the same layer as the source and drain. That is, the second conductive layer 25 includes the third trace, as shown in Figures 13 to 15, where the third trace 14 is the second conductive layer trace 2501.

[0248] In some embodiments, in the third peripheral region and / or the fourth peripheral region, the display substrate further includes a gate driving circuit electrically connected to the plurality of scan lines; the plurality of signal lines further include a third signal line electrically connected to the gate driving circuit; for example, the third signal line includes a third trace.

[0249] It should be noted that in the first sub-region E1, the third part of the third trace and the second trace overlap in the orthographic projection on the substrate. The second trace, i.e. the first conductive layer trace, is prone to static electricity discharge. Since the distance between this region and the bonding pin is small, and the second trace is electrically connected to the bonding pin, static electricity is easily conducted to the bonding pin, and the bonding pin is easily damaged by electrostatic discharge.

[0250] In some embodiments, as shown in Figures 13-15, the display substrate further includes:

[0251] At least one electrostatic discharge structure 17; the electrostatic discharge structure 17 includes: at least one fourth trace 1701 and at least one electrostatic discharge terminal 1702; the fourth trace 1701 is disposed on the same layer as the second trace 702, and the electrostatic discharge terminal 1702 is located on a different layer from the fourth trace 1701; the fourth trace 1701 includes: a fourth portion 17011 and a fifth portion 17012 connected in sequence; the orthographic projection of the fourth portion 17011 on the substrate 1 is located on the side of the first sub-region E1 facing the orthographic projection of the pin group 15 on the substrate 1 in the first direction Y; the orthographic projection of the fifth portion 17012 on the substrate 1 is located on the side of the pin group 15 in the second direction X, and the end of the fifth portion 17012 away from the fourth portion 17011 is electrically connected to the electrostatic discharge terminal 1702.

[0252] The display substrate provided in this embodiment further includes an electrostatic discharge structure. The electrostatic discharge structure includes a fourth trace disposed on the same layer as the second trace. The fourth trace includes a fourth portion located on the side of the first sub-region facing the orthogonal projection of the pin group onto the substrate. The fourth trace also includes a fifth portion located on the side of the pin group in the second direction X. This allows the electrostatic discharge accumulated on the second trace in the first sub-region E1 to be conducted to the electrostatic discharge terminal through the fourth and fifth portions. Since there is a large area without a metal pattern on one side of the pin group in the second direction X, the electrostatic discharge will not affect the bonding pins after passing through the fifth portion. Furthermore, since the electrostatic discharge terminal is located on a different layer from the second and fourth traces, electrostatic discharge at the bonding pins can be avoided.

[0253] It should be noted that for each signal line group, an electrostatic discharge structure needs to be set on the side where the first sub-region E1 exists.

[0254] In some embodiments, as shown in FIG13, the pin group 15 includes a plurality of bonding pins 16 divided into a plurality of bonding pin rows 18 arranged along a first direction Y.

[0255] The electrostatic discharge structure 17 includes m fourth traces 1701. The fourth portion 17011 of the m fourth traces 1701 is electrically connected to the m bonding pins 16 closest to the fifth portion 17012 in the bonding pin row 18 closest to the display area AA, respectively; m is a positive integer. That is, in the display substrate provided by this embodiment, the electrostatic discharge structure is electrically connected to the bonding pins, so even if static electricity is conducted to the bonding pins, it can be discharged to the electrostatic discharge terminal through the fourth traces.

[0256] In some embodiments, m = 4. Of course, in actual implementation, the value of m can be set according to actual needs. For example, tests can be conducted in advance to determine the number of bonding pins that are easily damaged by electrostatic discharge, which can then be used as the value of m.

[0257] In some embodiments, as shown in FIG14, the display substrate further includes: a plurality of third dummy traces 19 disposed on the same layer as the second trace 702; the third dummy traces 19 are located on the side of a portion of the plurality of second traces 702 away from the display area AA; a portion of the third dummy traces 19 extend to the side of the first sub-region E1 away from the display area AA;

[0258] The end of Part 4 17011 away from Part 5 17012 is electrically connected to the third dummy trace 19 extending to the side of the first sub-region E1 away from the display area AA.

[0259] It should be noted that the third dummy trace is a dummy trace located in a blank area on one side of multiple second traces in the first conductive layer, to avoid damage to the second traces near the blank area. Typically, the third dummy trace is relatively long and easily accumulates static electricity. In the display substrate provided in this embodiment, the fourth part of the static discharge structure and the third dummy trace allow static electricity accumulated in the third dummy trace to be discharged to the static discharge terminal via the fourth trace, in addition to the static electricity in the first region E1 being released through the static discharge structure.

[0260] In some embodiments, as shown in Figures 13 and 14, the electrostatic discharge structure includes one electrostatic discharge terminal. That is, the third dummy trace 19 in Figure 14 is far from the fourth part 17011 and does not need to be electrically connected to the electrostatic discharge terminal. Alternatively, in some embodiments, the electrostatic discharge structure may include two electrostatic discharge terminals, that is, both ends of the fourth trace are electrically connected to the electrostatic discharge terminal.

[0261] In some embodiments, as shown in FIG15, the plurality of bonding pins 16 in the pin group 15 include: a plurality of first bonding pins 1601, and a plurality of second bonding pins 1602 located on the side of the plurality of first bonding pins 1601 away from the display area AA in the first direction Y;

[0262] The fourth trace 1701 also includes: a sixth part 17013 and a seventh part 17014; one end of the sixth part 17013 is electrically connected to the fourth part 17011, the other end of the sixth part 17013 is electrically connected to the seventh part 17014, the end of the seventh part 17014 away from the sixth part 17013 is electrically connected to the electrostatic discharge terminal 1702, and the fifth part 17012 and the seventh part 17014 are electrically connected to different electrostatic discharge terminals 1702;

[0263] The sixth part 17013 has an overlap between the orthographic projection of the substrate 1 and the area between the first bonding pin 1601 adjacent in the second direction X in the pin group 15 and the orthographic projection of the substrate 1.

[0264] The seventh part 17014 is projected onto the substrate 1 in the region between the projections of the plurality of first bonding pins 1601 and the plurality of second bonding pins 1602 onto the substrate 1.

[0265] The display substrate provided in this embodiment has both ends of the fourth trace electrically connected to an electrostatic discharge terminal, which is equivalent to increasing the electrostatic discharge location and allowing further electrostatic discharge at the bonding pins. Furthermore, the end of the fourth trace away from the fifth portion extends to the area between the orthographic projections of the plurality of first bonding pins and the plurality of second bonding pins in the pin group onto the substrate. This area also contains a large area without metal patterns, so electrostatic discharge at this location will not affect the bonding pins.

[0266] In some embodiments, the bonding pin includes: a first sub-pin located on a first conductive layer, a second sub-pin located on a second conductive layer, and a third sub-pin disposed on the same layer as the first transparent electrode. The first sub-pin is electrically connected to the second sub-pin, and the second sub-pin is electrically connected to the third sub-pin.

[0267] In some embodiments, the electrostatic discharge terminal is disposed on the same layer as the first active layer. When the first active layer includes polysilicon, the electrostatic discharge terminal also includes polysilicon. In this way, the resistance of the electrostatic discharge terminal is greater than the resistance of the light-shielding layer, the second conductive layer, the first transparent electrode, and the second transparent electrode, and the electrostatic discharge terminal and the sub-pins of the bonding pins are located on different layers, which is more conducive to reducing the risk of static electricity release at the bonding pins. Of course, in specific implementations, the electrostatic discharge terminal can also be located on other conductive layers.

[0268] In some embodiments, the fourth trace is electrically connected to the electrostatic discharge terminal through a via penetrating the second insulating layer.

[0269] In some embodiments, as shown in Figures 16 and 17, the display substrate further includes:

[0270] A multiplexing circuit 21 is located in the peripheral area NA. The multiplexing circuit 21 includes: multiple multiplexing units 2101 and multiple multiplexing control lines 2102. The multiple multiplexing control lines 2102 include: a first multiplexing control line 2102-1 and a second multiplexing control line 2102-2. The first multiplexing control line 2102-1 and the second multiplexing control line 2102-2 are electrically connected to different bonding pins 16 in the pin group 15. Each multiplexing unit 2101 includes: multiple multiplexing switches 21011. The multiplexing unit 2101 controls the multiple multiplexing switches 21011. Terminal 54 is electrically connected to the first multiplexing control line 2102-1. The control terminals 54 of the remaining multiplexing switches 21011 in the multiplexing unit 2101 are electrically connected to the second multiplexing control line 2102-2. In each multiplexing unit 2101, the output terminals 55 of the multiple multiplexing switches 21011 are electrically connected to different data lines 20, and the input terminals 53 of the multiple multiplexing switches 21011 electrically connected to the same multiplexing control line 2102 are electrically connected to different first signal lines 7. The input terminals 53 of the multiple multiplexing switches 21011 partially connected to different multiplexing control lines 2102 are electrically connected to the same first signal line 7.

[0271] The display substrate provided in this embodiment has multiple data lines electrically connected to multiple first signal lines via a multiplexing circuit. The input terminals of multiple multiplexing switches, some of which are electrically connected to different multiplexing control lines, are electrically connected to the same first signal line. This means the number of first signal lines is less than the number of data lines, thereby reducing the number of signal lines in the peripheral area, saving wiring space, and facilitating the implementation of a narrow bezel. Furthermore, since the control terminals of some multiplexing switches in a multiplexing unit are electrically connected to the same multiplexing control line, compared to the prior art where all multiplexing switches in a multiplexing unit are electrically connected to different multiplexing control lines, the number of multiplexing control lines can be reduced, further saving wiring space.

[0272] In some embodiments, the multiplexer is a second transistor. That is, the multiplexer includes a second active layer, a second gate, a second source, and a second drain; the second active layer is disposed on the same layer as the first active layer, the second gate is disposed on the same layer as the first gate, and the second source and second drain are disposed on the same layer as the first source and first drain. The second gate is electrically connected to the multiplexer control line, the second source is electrically connected to the first signal line, and the second drain is electrically connected to the data line.

[0273] In some embodiments, as shown in Figures 16, 17, and 18, each multiplexing unit 2101 includes: two multiplexing subunits 2101-1; one multiplexing subunit 2101-1 includes a plurality of multiplexing switches 20111; the plurality of multiplexing switches 20111 in one multiplexing subunit 2101-1 are electrically connected to the same multiplexing control line 2102 circuit.

[0274] Multiple multiplexer switches 20111 in a multiplexer subunit 2101-1 are electrically connected to different first signal lines 7.

[0275] In some embodiments, as shown in FIG16, the two multiplexing subunits 2101-1 are a first multiplexing subunit 2101-101 and a second multiplexing subunit 2101-102, respectively; the second gates of the plurality of multiplexing switches 20111 in the first multiplexing subunit 2101-101 are electrically connected to the first multiplexing control line 21021, and the second gates of the plurality of multiplexing switches 20111 in the second multiplexing subunit 2101-102 are electrically connected to the second multiplexing control line 21022.

[0276] In some embodiments, as shown in FIG16, the multiplexing subunit 2101-1 includes two multiplexing switches 20111, namely a first multiplexing switch T1 and a second multiplexing switch T2. The two multiplexing switches 20111 are electrically connected to different first signal lines 7. The first multiplexing switch T1 is electrically connected to the first signal line 7 (reference numeral 7-4), and the second multiplexing switch T2 is electrically connected to the first signal line 7 (reference numeral 7-3). Furthermore, the first multiplexing switches T1 of both multiplexing subunits 2101-1 are electrically connected to the first signal line 7 (reference numeral 7-4), and the second multiplexing switches T2 of both multiplexing subunits 2101-1 are electrically connected to the first signal line 7 (reference numeral 7-3).

[0277] In some embodiments, as shown in FIG18, the plurality of bonding pins 16 in the pin group 15 include: a plurality of first bonding pins 1601 and a plurality of second bonding pins 1602;

[0278] The plurality of first bonded pins 1601 include: a plurality of first cascaded pins 16011, and a plurality of first non-cascaded pins 16012 located on the side of the plurality of first cascaded pins 16011 away from the adjacent pin group 15 in the second direction X, and the first signal line 7 is electrically connected to the first non-cascaded pins 16012.

[0279] The plurality of second bonding pins 1602 include: control pins 16021 that are electrically connected to the first multiplexer control line 2102-1 and the second multiplexer control line 2102-2 respectively;

[0280] The multiplexing control line 2102 includes: an eighth portion 21021 electrically connected to the control pin 16021 and extending generally along a first direction Y, and a ninth portion 21022 electrically connected to the eighth portion 21021 and extending in a direction intersecting the eighth portion 21021; the orthographic projection of the eighth portion 21021 on the substrate 1 is located on the side of the orthographic projection of the control pin 16021 on the substrate 1 facing the display area AA, and the orthographic projection of the eighth portion 21021 on the substrate 1 is located in the region between the orthographic projections of the plurality of first cascaded pins 16011 and the plurality of first non-cascaded pins 16012 on the substrate 1; the orthographic projection of the ninth portion 21022 on the substrate 1 is located on the side of the orthographic projection of the plurality of first bonding pins 1601 on the substrate 1 facing the display area AA.

[0281] The display substrate also includes:

[0282] Multiple pin group cascade lines 22 are located in the peripheral area NA; multiple first cascade pins 16011 of two adjacent pin groups 15 are electrically connected through at least a portion of the pin group cascade lines 22; in the first direction Y, the orthographic projection of the pin group cascade lines 22 on the substrate 1 is located on the side of the first cascade pins 16011 away from the display area AA, and the orthographic projection of the pin group cascade lines 22 on the substrate 1 in the second direction X is located on the side of the orthographic projection of the eighth portion 21021 on the substrate 1 toward the orthographic projection of the multiple first cascade pins 16011 on the substrate 1.

[0283] It should be noted that, as shown in Figure 19, the related technology includes four multiplexer control lines 2102. These four multiplexer control lines 2102 need to be routed around the side of the pin group 15, while the pin group cascade line 22 needs to extend inside the pin group 15 through the second bonding pin 1602 to the area below the pin group 15. The pin group cascade line 22 occupies a large space in both the first direction Y and the second direction X, which is not conducive to achieving a narrow bezel. However, the display substrate provided in this embodiment, as shown in Figure 18, reduces the number of multiplexer control lines 2102. There is sufficient wiring space for the multiplexer control lines 2102 at the connection point with the control pin 16021, between the bonding pins 16 inside the pin group 15, and on the side of the pin group 15 facing the display area (not shown). This eliminates the need for the multiplexer control lines 2102 to be routed around the side of the pin group 15, i.e., the side of the first cascade pin 16011. In this way, the pin group cascade line 22 can be directly routed in the area between the first cascade pins 16011 of the two pin groups 15, avoiding the pin group cascade line 22 from the side of the pin group 15 away from the display area, and saving routing space in both the first direction Y and the second direction X.

[0284] In some embodiments, as shown in FIG18, the display substrate further includes at least one driving pin group 60 located on the side of the pin group 15 away from the display area (not shown) in a first direction Y, the driving pin group 60 including a plurality of third bonding pins 6001. The third bonding pins 60 are electrically connected to the second bonding pins 1602.

[0285] In practice, the drive pin group is bonded to the flexible circuit board.

[0286] The display substrate provided in this embodiment does not require the pin group cascade line to be wound between the pin group and the driving pin group, thereby reducing the distance between the pin group and the driving pin group and facilitating the realization of a narrow bezel.

[0287] In some embodiments, as shown in FIG16, each multiplexing control line 2102 is electrically connected to n multiplexing switches 20111 in multiplexing unit 2101; n is an integer greater than 1.

[0288] In some embodiments, as shown in Figures 17 and 18, the multiplexing circuit 21 further includes: n first sub-control lines 2103 electrically connected to the ninth portion 21022 of the multiplexing control line 2102, and the n first sub-control lines 2103 are electrically connected to the n multiplexing switches 20111 in the multiplexing unit 2101 in a one-to-one correspondence.

[0289] The orthographic projection of the first sub-control line 2103 onto the substrate 1 is located on the side of the pin group cascade line 22 onto the substrate 1 facing the display area (not shown).

[0290] In some embodiments, n = 2.

[0291] In some embodiments, as shown in FIG18, the two ends of a portion of the first sub-control line 2103 are electrically connected to two adjacent pin groups 15 respectively via multiplexer control signal lines.

[0292] In some embodiments, as shown in FIG12, FIG17 and FIG18, the orthographic projection of the first sub-control line 2103 on the substrate 1 is located on the side of the first portion 8 of the plurality of first signal lines 7 on the substrate 1 away from the display area (not shown).

[0293] The orthographic projection of multiple multiplexing units 2101 onto the substrate 1 is located on the side of the orthographic projection of the first portion 8 of multiple first signal lines 7 onto the substrate 1 facing the display area (not shown).

[0294] The multiplexing circuit 21 also includes: multiple second sub-control lines 2104 and multiple connecting lines 2105; and is electrically connected to the first sub-control line 2103 and the second sub-control line 2104 one-to-one through the connecting lines 2105.

[0295] The n second sub-control lines 2104, which are electrically connected to a multiplexing control line 2102, are electrically connected one-to-one with the n multiplexing switches 21011 in the multiplexing unit 2101.

[0296] The orthographic projection of the second sub-control line 2104 onto the substrate 1 lies between the orthographic projection of the first portion 8 of the plurality of first signal lines 7 onto the substrate 1 and the orthographic projection of the plurality of multiplexing units 2101 onto the substrate 1.

[0297] The display panel provided in this embodiment uses a multi-channel selection control line that is electrically connected to the multi-channel selection unit via a first sub-control line, a connecting trace, and a second sub-control line. This avoids the accumulation of static electricity due to excessive length of the multi-channel selection control line in the second direction X. Furthermore, each multi-channel selection control line is electrically connected to n second sub-control lines, and these n second sub-control lines are electrically connected one-to-one to the n multi-channel selection switches in the multi-channel selection unit, reducing the wiring complexity of the electrical connection between the multi-channel selection unit and the second sub-control lines.

[0298] In some embodiments, as shown in FIG12, the multiple first dummy traces 11 are divided into multiple first dummy trace groups 23;

[0299] The orthographic projection of multiple connecting traces 2105 onto the substrate 1 is located between the orthographic projections of the two first dummy trace groups 23 onto the substrate 1.

[0300] Based on the same inventive concept, this disclosure also provides a display panel, as shown in FIG20, the display panel including:

[0301] The display substrate 25 provided in the embodiments of this disclosure;

[0302] The opposing substrate 26 is disposed opposite to the display substrate 25;

[0303] The liquid crystal layer 27 is located between the display substrate 25 and the opposing substrate 26.

[0304] In some embodiments, the opposing substrate also includes a substrate substrate. For ease of distinction, the substrate substrate of the opposing substrate is referred to as the second substrate substrate. The opposing substrate also includes a black matrix located on the side of the second substrate substrate facing the liquid crystal layer and a plurality of color resists. The black matrix includes a plurality of opening regions, and the color resists are located at least in the opening regions. The plurality of color resists include, for example, a plurality of red color resists, a plurality of blue color resists, and a plurality of green color resists.

[0305] In some embodiments, the display panel further includes: a first alignment layer located between the display substrate and the liquid crystal layer, and a second alignment layer located between the opposing substrate and the liquid crystal layer.

[0306] Based on the same inventive concept, this disclosure also provides a display device, as shown in FIG21, which includes a display panel 28 provided in this disclosure embodiment.

[0307] In some embodiments, as shown in FIG21, the display device may further include a backlight module 29 located on the light-incident side of the display panel 28.

[0308] In some embodiments, the backlight module may be a direct-lit backlight module, or it may be an edge-lit backlight module.

[0309] In practical implementation, a side-lit backlight module may include LED strips, stacked reflective sheets, light guide plates, diffusers, prism assemblies, etc., with the LED strips located on one side of the thickness direction of the light guide plate. A direct-lit backlight module may include a matrix light source, a reflective sheet, diffuser plate, and brightness enhancement film stacked on the light-emitting side of the matrix light source, with the reflective sheet including openings directly opposite the positions of the LEDs in the matrix light source. The LEDs in the LED strips and the LEDs in the matrix light source can be light-emitting diodes (LEDs), such as miniature LEDs (Mini LEDs, Micro LEDs, etc.). Submillimeter-scale or even micrometer-scale miniature LEDs, like organic light-emitting diodes (OLEDs), are self-emissive devices. Like OLEDs, they possess a series of advantages such as high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they have advantages over organic LEDs, such as lower power consumption, greater resistance to high and low temperatures, and longer lifespan. Furthermore, when micro LEDs are used as backlights, more precise dynamic backlighting effects can be achieved. This not only effectively improves screen brightness and contrast but also solves the glare problem caused by traditional dynamic backlighting between bright and dark areas of the screen, thus optimizing the visual experience.

[0310] In some embodiments, the light-incident side of the display panel is one side of the display substrate, that is, the backlight module and the display substrate are disposed opposite to each other, and the opposing substrate is located on the side of the display substrate away from the backlight module.

[0311] The display device provided in this disclosure includes any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure. Implementation of this display device can refer to the embodiments of the display panel described above; repeated details will not be repeated.

[0312] In summary, the display substrate, display panel, and display device provided in this disclosure embodiment have a light-shielding pattern projected onto the substrate in a way that does not overlap with the projected bottom or top surfaces of the first and second vias onto the substrate. This avoids the vias penetrating the active layer, causing the source and drain electrodes to be electrically connected to the light-shielding pattern. Consequently, it avoids the first transparent electrode being electrically connected to the light-shielding pattern, and avoids uneven display caused by areas on the display substrate where the first transparent electrode is electrically connected to the light-shielding pattern or areas where the first transparent electrode is not electrically connected to the light-shielding pattern.

[0313] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0314] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A display substrate, wherein, The display substrate includes: Substrate, including the display area; A plurality of first thin-film transistors are located in the display area; the first thin-film transistors include: a first active layer, a first gate located on the side of the first active layer opposite to the substrate, and a first source and a first drain located on the side of the first gate opposite to the first active layer; Multiple first transparent electrodes are located on the side of the first source and first drain that are away from the substrate; the first transparent electrodes are electrically connected to the first drain. Multiple vias, including multiple first vias and multiple second vias; the first source electrode contacts the first active layer through the first vias, and the first drain electrode contacts the first active layer through the second vias; A light-shielding layer is located between the substrate and the first active layer; the light-shielding layer includes a plurality of light-shielding patterns located in the display area; the orthographic projection of the light-shielding patterns on the substrate does not overlap with the orthographic projection of the bottom or top surface of the first via and the second via on the substrate; on the side where the orthographic projection of the first via and the second via on the substrate faces the orthographic projection of the first gate on the substrate, the orthographic projection of the light-shielding patterns on the substrate overlaps with the orthographic projection of the first active layer on the substrate.

2. The display substrate according to claim 1, wherein, The substrate further includes: a peripheral region surrounding the display area; the display substrate further includes: Multiple first signal lines are located in the peripheral area on one side of the display area in a first direction; each of the multiple first signal lines includes a first trace and / or a second trace; the first trace is disposed on the same layer as the light-shielding pattern, and the second trace is disposed on the same layer as the first gate; both the first trace and the second trace include a first portion, the angle between the extension direction of the first portion and the first direction is greater than 0° and less than 90°; among the multiple first signal lines, some of the first traces are arranged along a second direction, and some of the second traces are arranged along a second direction, the second direction intersects the first direction and the extension direction of the first portion; the orthographic projection of the first portion of the first trace on the substrate overlaps with the orthographic projection of the first portion of the second trace on the substrate, and the area between the orthographic projections of the first portions of any two adjacent second traces on the substrate overlaps with the edge of the first portion of the first trace on the substrate.

3. The display substrate according to claim 2, wherein, The first portion has a first edge that extends in the same direction as the display area and is close to the side of the display area. In the orthographic projection of the substrate having overlapping first and second traces, the first edge of the second trace is closer to the display area in the orthographic projection of the substrate than the first edge of the first trace in the orthographic projection of the substrate.

4. The display substrate according to claim 2 or 3, wherein, The first trace and the second trace further include a first connection portion disposed on the same layer as the first portion and electrically connected thereto; the pattern of the first connection portion in the orthographic projection on the substrate includes a rounded corner area; The first signal line further includes a second connection portion located on a different layer from the first trace and the second trace; the first connection portion is electrically connected to the second connection portion.

5. The display substrate according to claim 4, wherein, Each of the first signal lines includes the first trace and the second trace; The first trace and the second trace in the first signal line do not overlap in their orthographic projections on the substrate. The first connection portion of the first trace and the first connection portion of the second trace are electrically connected through the second connection portion.

6. The display substrate according to any one of claims 2 to 5, wherein, The plurality of first signal lines are divided into a plurality of signal line groups arranged along the second direction; The two first traces that are closest to each other in two adjacent signal line groups further include: a second portion located on one side of the first portion in the first direction and electrically connected to the first portion; the second portion includes at least a portion extending along the first direction; In two adjacent signal line groups, the distance between the second portions of the two closest first traces in the second direction is greater than or equal to 290 micrometers.

7. The display substrate according to claim 6, wherein, The display substrate further includes: Multiple first dummy traces are disposed on the same layer as the light-shielding pattern; the multiple first dummy traces extend along the first direction; the orthographic projection of the first dummy trace on the substrate is located in the region between the orthographic projections of the two closest first traces in two adjacent signal line groups on the substrate. Multiple second dummy traces are disposed on the same layer as the light-shielding pattern; the second dummy traces are located on the side of the first trace away from the display area, and the second dummy traces include at least a portion extending in the same direction as the first portion; some of the second dummy traces are located on the side of the second portion away from the adjacent signal line group in the second direction, and the distance between some of the second dummy traces and the second portion is not exactly the same.

8. The display substrate according to any one of claims 2 to 7, wherein, The display substrate further includes: Multiple third traces are located in the peripheral area; the multiple third traces are located on different layers from the first trace and the second trace; a portion of the multiple third traces includes a third portion whose extension direction intersects with the extension direction of the first portion; the area where the orthographic projection of the third portion of the multiple third traces on the substrate overlaps with the orthographic projection of a portion of the second traces on the substrate is a first sub-region; At least one pin group; the orthographic projection of the at least one pin group onto the substrate is located on the side of the orthographic projection of the plurality of first signal lines onto the substrate away from the display area; the pin group includes a plurality of bonding pins; the first signal lines are electrically connected to the bonding pins; At least one electrostatic discharge structure; the electrostatic discharge structure includes: at least one fourth trace and at least one electrostatic discharge terminal; the fourth trace is disposed on the same layer as the second trace, and the electrostatic discharge terminal is located on a different layer from the fourth trace; the fourth trace includes: a fourth portion and a fifth portion electrically connected in sequence; the fourth portion, in the orthographic projection of the substrate, is located on the side of the first sub-region facing the orthographic projection of the pin group on the substrate in the first direction; the fifth portion, in the orthographic projection of the substrate, is located on the side of the pin group in the second direction, and the end of the fifth portion away from the fourth portion is electrically connected to the electrostatic discharge terminal.

9. The display substrate according to claim 8, wherein, The pin group includes a plurality of bonding pins arranged in a plurality of bonding pin rows along the first direction; The electrostatic discharge structure includes m fourth traces, and the fourth part of the m fourth traces is electrically connected one-to-one with the m binding pins closest to the fifth part in the binding pin row closest to the display area; m is a positive integer.

10. The display substrate according to claim 8, wherein, The display substrate further includes: multiple third dummy traces disposed on the same layer as the second traces; the third dummy traces are located on the side of some of the multiple second traces away from the display area; some of the third dummy traces extend to the side of the first sub-region away from the display area; The end of the fourth portion away from the fifth portion is electrically connected to the third dummy trace extending to the side of the first sub-region away from the display area.

11. The display substrate according to claim 8, wherein, The plurality of bonding pins in the pin group include: a plurality of first bonding pins, and a plurality of second bonding pins located on the side of the plurality of first bonding pins away from the display area in the first direction; The fourth wiring also includes a sixth part and a seventh part; one end of the sixth part is electrically connected to the fourth part, the other end of the sixth part is electrically connected to the seventh part, the end of the seventh part away from the sixth part is electrically connected to the electrostatic discharge terminal, and the fifth part is electrically connected to the seventh part but not to the electrostatic discharge terminal; The sixth portion overlaps with the region between the orthographic projection of the substrate and the orthographic projection of the first bonding pin in the second direction in the pin group on the substrate. The seventh portion is projected onto the substrate in the region between the projections of the plurality of first bonding pins and the plurality of second bonding pins onto the substrate.

12. The display substrate according to any one of claims 8 to 11, wherein, The electrostatic discharge terminal is disposed in the same layer as the first active layer.

13. The display substrate according to any one of claims 2 to 12, wherein, The display substrate includes at least one pin group; the display substrate further includes: Multiple data lines extend along the first direction and are arranged along the second direction; A multiplexing circuit is located in the peripheral area; the multiplexing circuit includes: multiple multiplexing units and multiple multiplexing control lines; the multiple multiplexing control lines include: a first multiplexing control line and a second multiplexing control line; the first multiplexing control line and the second multiplexing control line are electrically connected to different bonding pins in the pin group; each of the multiple multiplexing units includes: multiple multiplexing switches; the control terminals of some of the multiple multiplexing switches included in the multiple multiplexing unit are connected to the first multiplexing control line. The multiplexing control line is electrically connected, and the control terminals of the remaining multiplexing switches in the multiplexing unit are electrically connected to the second multiplexing control line; in each multiplexing unit, the output terminals of the multiple multiplexing switches are electrically connected to different data lines, the input terminals of the multiple multiplexing switches electrically connected to the same multiplexing control line are electrically connected to different first signal lines, and the input terminals of some multiple multiplexing switches electrically connected to different multiplexing control lines are electrically connected to the same first signal line.

14. The display substrate according to claim 13, wherein, The display substrate includes: a plurality of pin groups arranged along the second direction; the plurality of bonding pins in the pin groups include: a plurality of first bonding pins and a plurality of second bonding pins; The plurality of first bonded pins include: a plurality of first cascaded pins, and a plurality of first non-cascaded pins located on the side of the plurality of first cascaded pins away from the adjacent pin group in the second direction, wherein the first signal line is electrically connected to the first non-cascaded pins; The plurality of second bonding pins include: control pins that are electrically connected to the first multiplexer control line and the second multiplexer control line, respectively; The multiplexing control line includes: an eighth portion electrically connected to the control pin and extending generally along the first direction, and a ninth portion electrically connected to the eighth portion and extending in a direction intersecting the eighth portion; the orthographic projection of the eighth portion on the substrate is located on the side of the orthographic projection of the control pin on the substrate facing the display area, and the orthographic projection of the eighth portion on the substrate is located in the region between the orthographic projections of the plurality of first cascaded pins and the plurality of first non-cascaded pins on the substrate; the orthographic projection of the ninth portion on the substrate is located on the side of the orthographic projection of the plurality of first bonding pins on the substrate facing the display area. The display substrate further includes: Multiple pin group cascade lines are located in the peripheral area; the plurality of first cascaded pins of two adjacent pin groups are electrically connected through at least a portion of the multiple pin group cascade lines; in the first direction, the orthographic projection of the pin group cascade line on the substrate is located on the side of the first cascaded pin away from the display area, and the orthographic projection of the pin group cascade line on the substrate is located in the second direction on the side of the orthographic projection of the eighth portion on the substrate facing the orthographic projection of the plurality of first cascaded pins on the substrate.

15. The display substrate according to claim 14, wherein, Each of the multiplexing control lines is electrically connected to the n multiplexing switches in the multiplexing unit; n is an integer greater than 1; The multiplexing circuit further includes: n first sub-control lines electrically connected to the ninth part of the multiplexing control line, wherein the n first sub-control lines are electrically connected one-to-one with the n multiplexing switches in the multiplexing unit; The orthographic projection of the first sub-control line onto the substrate is located on the side of the orthographic projection of the pin group cascade line onto the substrate facing the display area.

16. The display substrate according to claim 15, wherein, Both ends of the first sub-control line are electrically connected to the two adjacent pin groups via the multiplexer control signal line.

17. The display substrate according to claim 15 or 16, wherein, The orthographic projection of the first sub-control line onto the substrate is located on the side of the orthographic projection of the first portion of the plurality of first signal lines onto the substrate away from the display area; The orthographic projection of the plurality of multiplexing units on the substrate is located on the side of the orthographic projection of the plurality of first signal lines on the substrate facing the display area. The multiplexing circuit further includes: multiple second sub-control lines and multiple connecting traces; the first sub-control lines and the second sub-control lines are electrically connected one-to-one through the connecting traces; The n second sub-control lines, which are electrically connected to one of the multiplexing control lines, are electrically connected one-to-one with the n multiplexing switches in the multiplexing unit; The second sub-control line is projected onto the substrate in a projection between the first portion of the plurality of first signal lines in a projection onto the substrate and the plurality of multiplexing units in a projection onto the substrate.

18. The display substrate according to claim 17, wherein, The display substrate includes multiple first dummy traces; the multiple first dummy traces are divided into multiple first dummy trace groups; The multiple connection traces are projected onto the substrate between the two first dummy trace groups and their projected onto the substrate.

19. The display substrate according to any one of claims 1 to 18, wherein, The light-shielding layer includes: a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer stacked together; The film layer containing the first gate is a first conductive layer; the first conductive layer includes: a fourth sub-conductive layer, a fifth sub-conductive layer, and a sixth sub-conductive layer stacked together. The film layer containing the first source and the first drain is a second conductive layer; the second conductive layer includes a seventh sub-conductive layer, an eighth sub-conductive layer, and a ninth sub-conductive layer stacked together. The ratio of the thickness of the fourth sub-conductive layer to the thickness of the fifth sub-conductive layer is greater than or equal to 16% and less than or equal to 25%, and the ratio of the thickness of the sixth sub-conductive layer to the thickness of the fifth sub-conductive layer is greater than or equal to 25% and less than or equal to 34%. The first sub-conductive layer, the third sub-conductive layer, the fourth sub-conductive layer, and the sixth sub-conductive layer are made of molybdenum. The materials of the seventh sub-conductive layer and the ninth sub-conductive layer are titanium; The second sub-conductive layer, the fifth sub-conductive layer, and the eighth sub-conductive layer are made of aluminum.

20. The display substrate according to any one of claims 1 to 19, wherein, The light-shielding pattern corresponds one-to-one with the first active layer; The first active layer includes a first sub-active layer, a second sub-active layer, a third sub-active layer, a fourth sub-active layer, and a fifth sub-active layer connected in sequence; In a first direction, the second sub-active layer and the fourth sub-active layer are located on one side of the third sub-active layer, the first sub-active layer is located on the side of the second sub-active layer away from the third sub-active layer, and the fifth sub-active layer is located on the side of the fourth sub-active layer away from the third sub-active layer. The first via's orthographic projection onto the substrate falls within the orthographic projection of the first sub-active layer onto the substrate, and the second via's orthographic projection onto the substrate falls within the orthographic projection of the fifth sub-active layer onto the substrate. The orthographic projection of each of the light-shielding patterns on the substrate does not overlap with the orthographic projection of the third sub-active layer on the substrate. The orthographic projection of each of the light-shielding patterns on the substrate covers the orthographic projection of the second sub-active layer, the fourth sub-active layer, and the area between the second sub-active layer and the fourth sub-active layer on the substrate.

21. A display panel, wherein, The display panel includes: The display substrate according to any one of claims 1 to 20; The opposing substrate is disposed opposite to the display substrate; A liquid crystal layer is located between the display substrate and the opposing substrate.

22. A display device, wherein, The display device includes the display panel according to claim 21.

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