Array substrate and display panel

Abstract

Provided in the present application are an array substrate and a display panel. The array substrate comprises a pixel region and a bonding region located on one side of the pixel region, wherein the pixel region is provided with a plurality of sub-pixels, and at least one sub-pixel comprises a silicon semiconductor transistor and an oxide transistor; and the bonding region is provided with a plurality of bonding terminals and signal traces connected to the bonding terminals, and the signal traces in the bonding region are formed by using conductive layers where gates of the silicon semiconductor transistors and gates of the oxide semiconductor transistors are located.

Description

Array substrate and display panel Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for the resolution, power consumption, and image quality of display products. To meet these requirements, Low Temperature Polycrystalline Oxide (LTPO) technology is often used to fabricate the pixel driving circuits in the driving backplane of display products. LTPO technology combines the high mobility of Low Temperature Poly Silicon (LTPS) with the low leakage current of oxide semiconductors such as Indium Gallium Zinc Oxide (IGZO), offering advantages such as high resolution, high response speed, high brightness, high aperture ratio, low power consumption, and support for refresh rates from 1Hz to 120Hz.

[0003] However, the driving backplane using low-temperature polycrystalline oxide technology requires the fabrication of two types of thin-film transistor (TFT) devices, resulting in numerous film layers and a large number of masks. This leads to complex processes, low fabrication efficiency, and high manufacturing costs. To reduce the number of masks, the number of film layers in the driving backplane can be appropriately reduced, for example, by removing the bottom gate of the oxide transistor. However, removing the bottom gate of the oxide transistor results in limited wiring space in the bonding area. Invention Overview

[0004] This application provides an array substrate and a display panel to alleviate the technical problem of limited wiring space in existing bonding areas.

[0005] The technical solution provided in this application is as follows:

[0006] In a first aspect, embodiments of this application provide an array substrate, which includes a pixel region and a bonding region located on one side of the pixel region. The pixel region is provided with a plurality of sub-pixels, and at least one of the sub-pixels includes a silicon semiconductor transistor and an oxide transistor. The bonding region is provided with a plurality of bonding terminals and signal traces connected to the bonding terminals.

[0007] The signal traces connected to a portion of the bonding terminals are located in the first conductive layer where the gate of the silicon semiconductor transistor is located, and the signal traces connected to the other portion of the bonding terminals are located in the second conductive layer where the gate of the oxide transistor is located. The active portion of the oxide transistor is located between the first conductive layer and the second conductive layer.

[0008] Secondly, embodiments of this application also provide a display panel, which includes an array substrate. The array substrate includes a pixel region and a bonding region located on one side of the pixel region. The pixel region is provided with a plurality of sub-pixels. At least one of the sub-pixels includes a silicon semiconductor transistor and an oxide transistor. The bonding region is provided with a plurality of bonding terminals and signal traces connected to the bonding terminals.

[0009] The signal traces connected to a portion of the bonding terminals are located in the first conductive layer where the gate of the silicon semiconductor transistor is located, and the signal traces connected to the other portion of the bonding terminals are located in the second conductive layer where the gate of the oxide transistor is located. The active portion of the oxide transistor is located between the first conductive layer and the second conductive layer. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments or prior art, the drawings used in the description of the embodiments or prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of this application.

[0012] Figure 2 is a schematic diagram of a portion of the film structure of the array backplane provided in an embodiment of this application.

[0013] Figure 3 is a schematic diagram of a portion of the film structure in the bonding area on the array backplane provided in an embodiment of this application.

[0014] Figure 4 is a schematic diagram of one arrangement of the binding terminals in the binding area of ​​Figure 1.

[0015] Figure 5 is a schematic diagram of a signal line arrangement provided in an embodiment of this application.

[0016] Figure 6 is an enlarged schematic diagram of point M in Figure 5.

[0017] Figure 7 is a circuit diagram of a sub-pixel provided in an embodiment of this application. Embodiments of the present invention

[0018] The following descriptions of the embodiments are based on the accompanying illustrations, illustrating specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of this application, and not for limiting this application. In the figures, structurally similar units are denoted by the same reference numerals. In the figures, the thickness of some layers and regions is exaggerated for clarity and ease of description. That is, the dimensions and thicknesses of each component shown in the figures are arbitrarily shown, but this application is not limited thereto.

[0019] Please refer to Figures 1 to 3. Figure 1 is a schematic diagram of a planar structure of an array substrate provided in an embodiment of this application. Figure 2 is a schematic diagram of a partial film layer structure of an array backplane provided in an embodiment of this application. Figure 3 is a schematic diagram of a partial film layer structure of a bonding area on an array backplane provided in an embodiment of this application. The array substrate 100 includes a pixel region AA and a bonding region BA located on one side of the pixel region AA. A plurality of sub-pixels SP are disposed in the pixel region AA, and the plurality of sub-pixels SP can be arranged in an array. At least one of the sub-pixels SP includes a silicon semiconductor transistor 1 and an oxide transistor 2. The bonding region BA is provided with a plurality of bonding terminals 3 and signal traces connected to the bonding terminals 3 (first signal trace 32 / second signal trace 52 as shown in Figure 3). Each signal trace is connected to one bonding terminal 3, and each bonding terminal 3 is connected to one signal trace. The signal traces connected to a portion of the bonding terminals 3 are located in the first conductive layer 30 where the gate 31 of the silicon semiconductor transistor 1 is located, and the signal traces connected to another portion of the bonding terminals 3 are located in the second conductive layer 50 where the gate 51 of the oxide transistor 2 is located. The active portion 41 of the oxide transistor 2 is located between the first conductive layer 30 and the second conductive layer 50.

[0020] Thus, by using the conductive layer containing the gate 31 of silicon semiconductor transistor 1 and the gate 51 of oxide transistor 2 to form the signal trace of the bonding region BA, it is easy to compress the wiring space and improve the problem of limited wiring space in the bonding region. This allows the bottom gate of the oxide transistor to be removed, reducing the number of photomasks and lowering costs, without affecting the wiring space in the bonding region.

[0021] Specifically, referring to Figure 1, the array substrate 100 includes a pixel area AA and a non-pixel area NA located on one side of the pixel area AA. The pixel area AA contains multiple sub-pixels SP arranged in an array. For example, the multiple sub-pixels SP are arranged sequentially in a first direction X and in a second direction Y. The first direction X and the second direction Y are different, and the angle between the first direction X and the second direction Y is greater than 0 degrees and less than or equal to 90 degrees. For example, the first direction X is perpendicular to the second direction Y, that is, the first direction X is the row direction and the second direction Y is the column direction. The non-pixel area NA includes a fan-out area SA located near the pixel area AA and a bonding area BA located on the side of the fan-out area SA away from the pixel area AA. The fan-out area SA is used to fan out various signal traces within the pixel area AA. The bonding area BA is used to provide bonding terminals 3 to bond electronic components such as integrated circuits (ICs) and flexible printed circuits (FPCs), connecting the integrated circuits, flexible printed circuits, and other electronic components to the signal lines within the pixel area AA.

[0022] Referring to Figures 2 and 3, each sub-pixel SP includes a silicon semiconductor transistor 1, an oxide transistor 2, and a storage capacitor C1. One plate of the storage capacitor C1 and the gate 31 of the silicon semiconductor transistor 1 are both located on a first conductive layer 30. The other plate of the storage capacitor C1 and the active portion 41 of the oxide transistor 2 are both located on a first semiconductor layer 40. The gate 51 of the oxide transistor 2 is located on a second conductive layer 50. The bonding terminal 3, the source 64, and the drain 63 of the oxide transistor 2 are all located on a third conductive layer 60. The signal traces 32 / 52 are located on one of the first conductive layer 30 and the second conductive layer 50. The first semiconductor layer 40 is located between the first conductive layer 30 and the second conductive layer 50, and the third conductive layer 60 is located on the side of the second conductive layer 50 away from the first semiconductor layer 40.

[0023] Specifically, the array substrate 100 includes a substrate 10 and a second semiconductor layer 20, a first conductive layer 30, a first semiconductor layer 40, and a second conductive layer 50 sequentially disposed on the substrate 10. The second semiconductor layer 20 is disposed on one side of the substrate 10 and includes the active portion 21 of a silicon semiconductor transistor 1. The first conductive layer 30 is disposed on the side of the second semiconductor layer 20 away from the substrate 10 and includes the gate 31 of the silicon semiconductor transistor 1, with the gate 31 corresponding to the active portion 21 of the silicon semiconductor transistor 1. The first semiconductor layer 40 is disposed on the side of the first conductive layer 30 away from the substrate 10 and includes the first electrode 42 of a storage capacitor C1 and the active portion 41 of an oxide transistor 2, with the first electrode 42 of the storage capacitor C1 corresponding to the gate 31 of the silicon semiconductor transistor 1. The second conductive layer 50 is disposed on the side of the first semiconductor layer 40 away from the substrate 10. The second conductive layer 50 includes the gate 51 of the oxide transistor 2, and the gate 51 of the oxide transistor 2 is disposed correspondingly to the active portion 41 of the oxide transistor 2. In this way, by making the first electrode 42 of the storage capacitor C1 and the active portion 41 of the oxide transistor 2 co-layered, the conductive layer between the first semiconductor layer 40 and the first conductive layer 30 can be removed, thereby simplifying the film layers of the array substrate 100, simplifying the fabrication process, improving fabrication efficiency, and reducing manufacturing costs.

[0024] The array substrate 100 further includes a third conductive layer 60 and a fourth conductive layer 80. The third conductive layer 60 is disposed on the side of the second conductive layer 50 away from the substrate 10. The third conductive layer 60 includes a source 61 and a drain 62 of the silicon semiconductor transistor 1, a source 64 and a drain 63 of the oxide transistor 2, and a bonding terminal 3. The fourth conductive layer 80 is located on the side of the third conductive layer 60 away from the substrate 10. The material of the fourth conductive layer 80 is the same as that of the third conductive layer 60. The fourth conductive layer 80 forms a transition electrode 81, which is connected to the drain 62 of the silicon semiconductor transistor 1.

[0025] The array substrate 100 further includes a light-shielding layer 70 disposed between the substrate 10 and the second semiconductor layer 20. The light-shielding layer 70 includes a first light-shielding portion 71 and a second light-shielding portion 72. The first light-shielding portion 71 is disposed corresponding to the active portion 21 of the silicon semiconductor transistor 1, and the second light-shielding portion 72 is disposed corresponding to the active portion 41 of the oxide transistor 2. The first light-shielding portion 71 is located on the side of the active portion 21 of the silicon semiconductor transistor 1 away from the gate 31 of the silicon semiconductor transistor 1, and the second light-shielding portion 72 is located on the side of the active portion 41 of the oxide transistor 2 away from the gate 51 of the oxide transistor 2. The second light-shielding portion 72 is connected to the gate 51 of the oxide transistor 2. Naturally, the array substrate 100 also includes an insulating layer located between the various conductive layers and the semiconductor layers.

[0026] Specifically, referring to FIG2, a light-shielding layer 70 is disposed on one side of the substrate 10, and a first buffer layer 11 and a second buffer layer 12 are disposed between the light-shielding layer 70 and the second semiconductor layer 20. The first buffer layer 11 covers the light-shielding layer 70 and the substrate 10, and the second buffer layer 12 covers the first buffer layer 11. Optionally, the substrate 10 can be an inorganic material substrate or an organic material substrate. For example, in one embodiment of this application, the material of the substrate 10 can be a glass material such as soda-lime glass, quartz glass, or sapphire glass, or a metal material such as stainless steel, aluminum, or nickel. In another embodiment of this application, the substrate 10 can also be a flexible substrate, for example, the material of the substrate 10 can be polyimide (PI). The substrate 10 can also be a composite of multilayer materials. The first buffer layer 11 and the second buffer layer 12 can be inorganic thin films, such as SiNx, SiOx, or a composite layer thereof. The material of the light-shielding layer 70 includes a metallic material with light-shielding properties.

[0027] The second semiconductor layer 20 is disposed on the second buffer layer 12. The material of the second semiconductor layer 20 includes semiconductor materials such as polysilicon. The active portion 21 of the silicon semiconductor transistor 1 formed by the second semiconductor layer 20 includes a first channel portion 211 and a first source contact portion 212 and a first drain contact portion 213 located on opposite sides of the first channel portion 211. A first light-shielding portion 71 is disposed at least corresponding to the first channel portion 211 to shield the first channel portion 211 from light.

[0028] A first insulating layer 13 is disposed between the second semiconductor layer 20 and the first conductive layer 30. The material of the first insulating layer 13 includes inorganic materials such as SiNx and SiOx. The material of the first conductive layer 30 includes a metallic material with conductive properties, such as molybdenum. The gate 31 formed by the first conductive layer 30 is disposed correspondingly to the first channel portion 211.

[0029] A second insulating layer 14 is disposed between the first conductive layer 30 and the first semiconductor layer 40. The material of the second insulating layer 14 includes inorganic materials such as SiNx and SiOx. The material of the first semiconductor layer 40 includes metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO). The first semiconductor layer 40 forms the active portion 41 of the oxide transistor 2 and the first electrode 42 of the storage capacitor C1. The active portion 41 of the oxide transistor 2 includes a second channel portion 411 and a second source contact portion 412 and a second drain contact portion 413 located on opposite sides of the second channel portion 411. A second light-shielding portion 72 is disposed at least corresponding to the second channel portion 411 to shield the second channel portion 411 from light. The first electrode 42 of the storage capacitor C1 is disposed corresponding to the gate 31 of the silicon semiconductor transistor 1 to form the storage capacitor C1. Of course, in some embodiments, the second light-shielding portion 72 may also be electrically connected to the gate 51 of the oxide transistor 2 to serve as the bottom gate of the oxide transistor 2.

[0030] A third insulating layer 15 is disposed between the first semiconductor layer 40 and the second conductive layer 50. The material of the third insulating layer 15 includes inorganic materials such as SiNx and SiOx. The material of the second conductive layer 50 includes metallic materials with conductive properties, such as molybdenum and titanium. That is, the second conductive layer 50 can be formed by two metal layers, a titanium layer and a molybdenum layer. The molybdenum layer is located on the side of the titanium layer away from the substrate 10. The titanium layer is used to block hydrogen from the upper layer to avoid affecting the active part 41.

[0031] A fourth insulating layer 16 is disposed between the second conductive layer 50 and the third conductive layer 60. The material of the fourth insulating layer 16 includes inorganic materials such as SiNx and SiOx. An opening 161 is formed on the fourth insulating layer 16. The material of the third conductive layer 60 includes conductive metals such as titanium, aluminum, and copper. The third conductive layer 60 forms the source 61 and drain 62 of the silicon semiconductor transistor 1, and the source 64 and drain 63 of the oxide transistor 2. The source 61 of the silicon semiconductor transistor 1 is connected to the first source contact 212, the drain 62 of the silicon semiconductor transistor 1 is connected to the first drain contact 213, the source 64 of the oxide transistor 2 is connected to the second source contact 412, and the drain 63 of the oxide transistor 2 is connected to the second drain contact 413.

[0032] The array substrate 100 also includes a sixth conductive layer 90, which is located on the side of the fourth conductive layer 80 away from the substrate 10. A first planarization layer 17 is disposed between the third conductive layer 60 and the fourth conductive layer 80. The first planarization layer 17 is made of an organic material and fills the opening 161.

[0033] A second planarization layer 18 is disposed between the fourth conductive layer 80 and the sixth conductive layer 90. The material of the second planarization layer 18 includes an organic material. The material of the sixth conductive layer 90 includes a transparent conductive material such as indium tin oxide. A first electrode 91 is formed on the sixth conductive layer 90, and the first electrode 91 is connected to the transition electrode 81.

[0034] The array substrate 100 further includes a third planarization layer 19 and a barrier 92. The material of the third planarization layer 19 includes an organic material. The third planarization layer 19 covers the sixth conductive layer 90 and the second planarization layer 18, and the third planarization layer 19 has an opening 191 at the position corresponding to the first electrode 91, the opening 191 exposing a portion of the first electrode 91. The barrier 92 is disposed on the third planarization layer 19 and located around the opening 191.

[0035] In one embodiment, continuing to refer to FIG3, the bonding terminal 3 includes a first terminal portion 65 and a second terminal portion 82. The first terminal portion 65 is located on the third conductive layer 60, and the second terminal portion 82 is located on the fourth conductive layer 80. The fourth conductive layer 80 is located on the side of the third conductive layer 60 away from the second conductive layer 50. The first terminal portion 65 overlaps with the signal trace 32, and the second terminal portion 82 covers the first terminal portion 65. In the thickness direction of the array substrate 100, the orthographic projection of the second terminal portion 82 on the substrate 10 of the array substrate 100 covers the orthographic projection of the first terminal portion 65 on the substrate 10 of the array substrate 100.

[0036] Of the two adjacent bonding terminals 3, the signal trace 32 connected to one of the bonding terminals 3 is located in one of the first conductive layer 30 and the second conductive layer 50, and the signal trace 32 connected to the other bonding terminal 3 is located in the other of the first conductive layer 30 and the second conductive layer 50.

[0037] Specifically, referring to Figures 3 to 6, Figure 4 is a schematic diagram of the arrangement of bonding terminals in the bonding area of ​​Figure 1, Figure 5 is a schematic diagram of the arrangement of signal lines provided in the embodiment of this application, and Figure 6 is an enlarged schematic diagram of point M in Figure 5. Referring to Figures 3 and 4, the bonding terminal 3 includes a plurality of first bonding terminals 3-1 arranged at intervals in the first direction, and the signal trace includes a first signal trace 32 connected to the first bonding terminal 3-1. Referring to Figure 3, taking two adjacent first bonding terminals 3-1 as an example, the two first bonding terminals 3-1 are a first type of first bonding terminal 3-11 and a second type of first bonding terminal 3-12. The first signal trace 32 connected to the first type of first bonding terminal 3-11 is a first type of first signal trace 32-1, and the first signal trace 32 connected to the second type of first bonding terminal 3-12 is a second type of first signal trace 32-2. The first type of first signal trace 32-1 is located in the first conductive layer 30, and the second type of first signal trace 32-2 is located in the second conductive layer 50. The fourth insulating layer 16 has a first via 162 at the position corresponding to the first signal trace 32-1 of the first type. The portion of the first bonding terminal 3-11 of the first type located inside the first via 162 is connected to the first signal trace 32-1 of the first type exposed by the first via 162. The fourth insulating layer 16 has a second via 163 at the position corresponding to the first signal trace 32-2 of the second type. The portion of the first bonding terminal 3-12 of the second type located inside the second via 163 is connected to the first signal trace 32-2 of the second type exposed by the second via 163.

[0038] In one embodiment, continuing to refer to Figures 3 and 4, the signal line further includes a second signal trace 52 located between two adjacent first signal traces 32, wherein the adjacent first signal traces 32 and the second signal trace 52 are located on different layers. Optionally, the bonding terminal 3 further includes a second bonding terminal 3-2 located away from the pixel area from the first bonding terminal 3-1, and the second bonding terminal 3-2 is connected to the second signal trace 52.

[0039] Optionally, referring to Figure 3, there are a plurality of second signal traces 52 between two adjacent first signal traces 32. Two adjacent second signal traces 52 are located on different layers; for example, one of two adjacent second signal traces 52 is located on a first conductive layer, and the other is located on a second conductive layer. Furthermore, the second signal trace 52 that is closer to the first signal trace 32 is located on a different layer than the corresponding first signal trace 32; that is, adjacent first signal traces 32 and second signal traces 52 are located on different layers.

[0040] Specifically, among the plurality of second signal traces 52, those located in the first conductive layer 30 are classified as first-type second signal traces 52-1, and those located in the second conductive layer 50 are classified as second-type second signal traces 52-2. The first-type second signal traces 52-1 and second-type second signal traces 52-2 are arranged alternately, with some second-type second signal traces 52-2 located between adjacent first-type second signal traces 52-1 and first-type first signal traces 32-1, and some first-type second signal traces 52-1 located between adjacent second-type second signal traces 52-2 and second-type first signal traces 32-2.

[0041] Referring to Figures 5 and 6, the signal trace 32 includes a trace portion 321 and a bonding portion 322 connected to the trace portion 321. The bonding terminal 3 overlaps with the corresponding bonding portion 322. In the first direction X, the width of the bonding portion 322 is greater than the width of the trace portion 321. The first direction X is perpendicular to the arrangement direction of the pixel area AA and the bonding area BA. The second direction Y is the arrangement direction of the pixel area AA and the bonding area BA. In the thickness direction of the array substrate 100, the orthographic projection of the bonding terminal 3 on the substrate 10 of the array substrate 100 overlaps the orthographic projection of the corresponding bonding portion 322 on the substrate 10 of the array substrate 100.

[0042] Referring to Figure 7, which is a circuit diagram of a sub-pixel provided in an embodiment of this application, taking each sub-pixel SP as an example including 8 transistors and 2 capacitors, the 8 transistors are driving transistor T1, switching transistor T2, compensation transistor T3, first initialization transistor T4, first light-emitting control transistor T5, second light-emitting control transistor T6, second initialization transistor T7, and third initialization transistor T8. The 2 capacitors are the first capacitor Cst and the second capacitor Cboost.

[0043] Specifically, the gate of the switching transistor T2 is connected to the first scan signal line Pscan, and the first electrode of the switching transistor T2 is connected to the data line DATA.

[0044] The first electrode of the driving transistor T1 and the second electrode of the switching transistor T2 are connected to the first node A.

[0045] The gate of the compensation transistor T3 is connected to the second scan signal line Nscan1, the first electrode of the compensation transistor T3 is connected to the gate of the driving transistor T1 at the second node Q, and the second electrode of the compensation transistor T3 is connected to the second electrode of the driving transistor T1.

[0046] The gate of the first initialization transistor T4 is connected to the third scan signal line Nscan2, the first electrode of the first initialization transistor T4 is connected to the first initialization signal line VI-G, and the second electrode of the first initialization transistor T4 is connected to the gate of the driving transistor T1 at the second node Q.

[0047] The gate of the first light-emitting control transistor T5 is connected to the light-emitting control signal line EM, the first electrode of the first light-emitting control transistor T5 is connected to the high-potential power supply line VDD, and the second electrode of the first light-emitting control transistor T5 is connected to the first electrode of the driving transistor T1 at the first node A.

[0048] The gate of the second light-emitting control transistor T6 is connected to the light-emitting control signal line EM, and the first electrode of the second light-emitting control transistor T6 is connected to the second electrode of the driving transistor T1 at the third node B.

[0049] The gate of the second initialization transistor T7 is connected to the fourth scan signal line Pscan2, the first electrode of the second initialization transistor T7 is connected to the second initialization signal line VI-ANO, and the second electrode of the second initialization transistor T7 is connected to the second electrode of the second light-emitting control transistor T6 at the fourth node C.

[0050] The gate of the third initialization transistor T8 is connected to the fourth scan signal line Pscan2, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line VI3, and the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T1 at the first node A.

[0051] One plate of the first capacitor Cst is connected to the high-potential power line VDD, and the other plate of the first capacitor Cst is connected to the gate of the driving transistor T1 at the second node Q.

[0052] One plate of the second capacitor Cboost is connected to the first scan signal line Pscan, and the other plate of the second capacitor Cboost is connected to the second electrode of the first initialization transistor T4.

[0053] The silicon semiconductor transistor 1 includes a switching transistor T2, a driving transistor T1, a first light-emitting control transistor T5, a second light-emitting control transistor T6, a second initialization transistor T7, and a third initialization transistor T8; the oxide transistor 2 includes a compensation transistor T3 and a first initialization transistor T4; the first capacitor Cst is a storage capacitor C1, and the second capacitor Cboost is a boost capacitor.

[0054] Optionally, the first plate 42 of the storage capacitor C1 is configured to correspond to the gate of the driving transistor T1.

[0055] It should be noted that in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source. The first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM can be connected to different gate driving circuits respectively. Specifically, five sets of gate driving circuits can be used to output signals to the first scan signal line Pscan, the second scan signal line Nscan1, the third scan signal line Nscan2, the fourth scan signal line Pscan2, and the light emission control signal line EM respectively. Among them, the gate driving circuit connected to the first scan signal line Pscan can be double-sided driving, and the other gate driving circuits are single-sided driving.

[0056] Based on the same inventive concept, this application also provides a display panel, which includes a light-emitting device and an array substrate 100 of one of the foregoing embodiments. The light-emitting device is disposed on the array substrate 100, and the array substrate 100 is used to drive the light-emitting device to emit light.

[0057] As can be seen from the above embodiments:

[0058] This application provides an array substrate and a display panel. The array substrate includes a pixel region and a bonding region located on one side of the pixel region. The pixel region is provided with a plurality of sub-pixels, at least one of the sub-pixels including a silicon semiconductor transistor and an oxide transistor. The bonding region is provided with a plurality of bonding terminals and signal traces connected to the bonding terminals. The signal traces connected to some of the bonding terminals are located in a first conductive layer where the gate of the silicon semiconductor transistor is located, and the signal traces connected to other of the bonding terminals are located in a second conductive layer where the gate of the oxide transistor is located. The active portion of the oxide transistor is located between the first conductive layer and the second conductive layer. Thus, by using the conductive layers where the gates of the silicon semiconductor transistors and the gates of the oxide transistors are located to form the signal traces of the bonding region, it is convenient to compress the wiring space and improve the problem of limited wiring space in the bonding region. This allows the bottom gate of the oxide transistor to be removed, reducing the number of photomasks and lowering costs, without affecting the wiring space of the bonding region.

[0059] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0060] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An array substrate, comprising a pixel region and a bonding region located on one side of the pixel region, wherein a plurality of sub-pixels are disposed in the pixel region, at least one of the sub-pixels comprising a silicon semiconductor transistor and an oxide transistor, and the bonding region is provided with a plurality of bonding terminals and signal traces connected to the bonding terminals; wherein The signal traces connected to a portion of the bonding terminals are located in the first conductive layer where the gate of the silicon semiconductor transistor is located, and the signal traces connected to another portion of the bonding terminals are located in the second conductive layer where the gate of the oxide transistor is located. The active portion of the oxide transistor is located between the first conductive layer and the second conductive layer.

2. The array substrate according to claim 1, wherein, Each of the sub-pixels also includes a storage capacitor, one plate of which is located in the first conductive layer, and the other plate of which, along with the active portion of the oxide transistor, is located in the first semiconductor layer. The bonding terminal, along with the source and drain of the oxide transistor, is located in the third conductive layer, which is located on the side of the second conductive layer away from the first semiconductor layer.

3. The array substrate according to claim 2, wherein, Of the two adjacent bonding terminals, the signal trace connected to one of the bonding terminals is located in one of the first conductive layer and the second conductive layer, and the signal trace connected to the other bonding terminal is located in the other of the first conductive layer and the second conductive layer.

4. The array substrate according to claim 3, wherein, The signal trace includes a trace portion and a bonding portion connected to the trace portion. The bonding terminal overlaps with the corresponding bonding portion. In a first direction, the width of the bonding portion is greater than the width of the trace portion. The first direction is perpendicular to the arrangement direction of the pixel area and the bonding area.

5. The array substrate according to claim 4, wherein, In the thickness direction of the array substrate, the orthographic projection of the bonding terminal on the substrate of the array substrate overlaps the orthographic projection of the corresponding bonding portion on the substrate of the array substrate.

6. The array substrate of claim 4, wherein, The bonding terminals include a plurality of first bonding terminals spaced apart in the first direction, and the signal traces include first signal traces connected to the first bonding terminals and second signal traces located between two adjacent first signal traces, wherein the adjacent first signal traces and second signal traces are located on different layers.

7. The array substrate according to claim 6, wherein, The bonding terminal also includes a second bonding terminal located away from the pixel area from the first bonding terminal, and the second bonding terminal is connected to the second signal trace.

8. The array substrate of claim 6, wherein, There are multiple second signal traces between two adjacent first signal traces, and two adjacent second signal traces are located on different layers.

9. The array substrate of claim 1, wherein, The array substrate further includes: A light-shielding layer, the light-shielding layer including a first light-shielding portion disposed corresponding to the active portion of the silicon semiconductor transistor, and a second light-shielding portion disposed corresponding to the active portion of the oxide transistor; The first light-shielding portion is located on the side of the active portion of the silicon semiconductor transistor away from the gate of the silicon semiconductor transistor, and the second light-shielding portion is located on the side of the active portion of the oxide transistor away from the gate of the oxide transistor, and the second light-shielding portion is connected to the gate of the oxide transistor.

10. The array substrate according to any one of claims 2 to 9, wherein, The bonding terminal includes a first terminal portion and a second terminal portion. The first terminal portion is located on the third conductive layer, and the second terminal portion is located on the fourth conductive layer. The fourth conductive layer is located on the side of the third conductive layer away from the second conductive layer. The first terminal portion overlaps with the signal trace, and the second terminal portion covers the first terminal portion.

11. A display panel comprising an array substrate, the array substrate comprising a pixel region and a bonding region located on one side of the pixel region, the pixel region being provided with a plurality of sub-pixels, at least one of the sub-pixels comprising a silicon semiconductor transistor and an oxide transistor, the bonding region being provided with a plurality of bonding terminals and signal traces connected to the bonding terminals; wherein The signal traces connected to a portion of the bonding terminals are located in the first conductive layer where the gate of the silicon semiconductor transistor is located, and the signal traces connected to another portion of the bonding terminals are located in the second conductive layer where the gate of the oxide transistor is located. The active portion of the oxide transistor is located between the first conductive layer and the second conductive layer.

12. The display panel of claim 11, wherein, Each of the sub-pixels also includes a storage capacitor, one plate of which is located in the first conductive layer, and the other plate of which, along with the active portion of the oxide transistor, is located in the first semiconductor layer. The bonding terminal, along with the source and drain of the oxide transistor, is located in the third conductive layer, which is located on the side of the second conductive layer away from the first semiconductor layer.

13. The display panel of claim 12, wherein, Of the two adjacent bonding terminals, the signal trace connected to one of the bonding terminals is located in one of the first conductive layer and the second conductive layer, and the signal trace connected to the other bonding terminal is located in the other of the first conductive layer and the second conductive layer.

14. The display panel of claim 13, wherein, The signal trace includes a trace portion and a bonding portion connected to the trace portion. The bonding terminal overlaps with the corresponding bonding portion. In a first direction, the width of the bonding portion is greater than the width of the trace portion. The first direction is perpendicular to the arrangement direction of the pixel area and the bonding area.

15. The display panel of claim 14, wherein, In the thickness direction of the array substrate, the orthographic projection of the bonding terminal on the substrate of the array substrate overlaps the orthographic projection of the corresponding bonding portion on the substrate of the array substrate.

16. The display panel of claim 14, wherein, The bonding terminals include a plurality of first bonding terminals spaced apart in the first direction, and the signal traces include first signal traces connected to the first bonding terminals and second signal traces located between two adjacent first signal traces, wherein the adjacent first signal traces and second signal traces are located on different layers.

17. The display panel of claim 16, wherein, The bonding terminal also includes a second bonding terminal located away from the pixel area from the first bonding terminal, and the second bonding terminal is connected to the second signal trace.

18. The display panel of claim 16, wherein, There are multiple second signal traces between two adjacent first signal traces, and two adjacent second signal traces are located on different layers.

19. The display panel of claim 11, wherein, The array substrate further includes: A light-shielding layer, the light-shielding layer including a first light-shielding portion disposed corresponding to the active portion of the silicon semiconductor transistor, and a second light-shielding portion disposed corresponding to the active portion of the oxide transistor; The first light-shielding portion is located on the side of the active portion of the silicon semiconductor transistor away from the gate of the silicon semiconductor transistor, and the second light-shielding portion is located on the side of the active portion of the oxide transistor away from the gate of the oxide transistor, and the second light-shielding portion is connected to the gate of the oxide transistor.

20. The display panel of any one of claims 12-19, wherein, The bonding terminal includes a first terminal portion and a second terminal portion. The first terminal portion is located on the third conductive layer, and the second terminal portion is located on the fourth conductive layer. The fourth conductive layer is located on the side of the third conductive layer away from the second conductive layer. The first terminal portion overlaps with the signal trace, and the second terminal portion covers the first terminal portion.

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