Imaging element and imaging device

Abstract

This imaging element comprises: a plurality of pixels arranged in a matrix; a plurality of first vertical signal lines that is provided corresponding to the columns of the plurality of pixels and that extends in the column direction; a pixel chip on which the plurality of pixels and the plurality of first vertical signal lines are arranged; one or more column circuit groups (40) including a plurality of column circuits (41) arranged along the row direction; a plurality of power supply lines (50) that is electrically connected to the plurality of column circuits (41) and that extends in the column direction; a logic chip (120) on which the one or more column circuit groups (40) and the plurality of power supply lines (50) are arranged and which is laminated with the pixel chip; and a plurality of first pads (11) that is electrically connected to the plurality of column circuits (41) via the plurality of power supply lines (50) and that is arranged along the row direction. A pitch (P1) at which the plurality of first pads (11) are arranged side by side is an integral multiple of a pitch (P2) at which the column circuits (41) are arranged side by side.

Description

Image pickup device and imaging apparatus

[0001] The present disclosure relates to an image pickup device and an imaging apparatus.

[0002] Conventionally, an image pickup device for picking up an image has been known.

[0003] For example, Patent Document 1 discloses a solid-state imaging device having a stacked structure of a pixel chip and a logic chip.

[0004] Japanese Patent Application Laid-Open No. 2015-138862

[0005] There is a demand for reducing the design man-hours while suppressing variations in noise in signals output from a plurality of pixels in an image pickup device. In particular, when stacking a plurality of chips as in the image pickup device disclosed in Patent Document 1, the design man-hours tend to increase due to the design of wirings arranged on each chip.

[0006] The present disclosure provides an image pickup device and the like that can reduce the design man-hours while suppressing variations in noise in signals output from a plurality of pixels.

[0007] An image pickup device according to an aspect of the present disclosure includes a plurality of pixels arranged in a matrix in a plan view, a plurality of first vertical signal lines through which signals output from the plurality of pixels are transmitted, the plurality of first vertical signal lines being provided corresponding to columns of the plurality of pixels and extending in a column direction of the plurality of pixels, a pixel chip in which the plurality of pixels and the plurality of first vertical signal lines are arranged, a plurality of column circuits provided corresponding to columns of the plurality of pixels and into which signals output from the plurality of pixels are input, the plurality of column circuits including one or more column circuit groups arranged along a row direction of the plurality of pixels, a plurality of power supply lines electrically connected to the plurality of column circuits and extending in the column direction, a logic chip in which the one or more column circuit groups and the plurality of power supply lines are arranged and which is stacked with the pixel chip, and a plurality of first pads electrically connected to the plurality of column circuits through the plurality of power supply lines and arranged along the row direction, the plurality of first pads being arranged in a pitch that is an integer multiple of a pitch in which the plurality of column circuits are arranged in the plan view.

[0008] An imaging device according to one aspect of this disclosure comprises the above-mentioned image sensor.

[0009] According to this disclosure, it is possible to reduce design man-hours while suppressing noise variations in signals output from multiple pixels in an image sensor or the like.

[0010] Figure 1 is a perspective view showing an example of an image sensor according to Embodiment 1. Figure 2 is a schematic plan view showing an example of a planar layout in the pixel chip of the image sensor according to Embodiment 1. Figure 3 is a schematic plan view showing an example of a planar layout in the logic chip of the image sensor according to Embodiment 1. Figure 4 is another schematic plan view showing an example of a planar layout in the logic chip of the image sensor according to Embodiment 1. Figure 5 is a cross-sectional view of the vicinity of the column circuit in the logic chip of the image sensor according to Embodiment 1. Figure 6 is a schematic plan view showing an example of a planar layout in the logic chip of the image sensor according to a modified example of Embodiment 1. Figure 7 is a cross-sectional view of the vicinity of the column circuit in the logic chip of the image sensor according to a modified example of Embodiment 1. Figure 8 is a block diagram showing an example of the configuration of an imaging device according to Embodiment 2.

[0011] Embodiments of this disclosure will be described in detail below with reference to the drawings. The embodiments described below are either comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. The various embodiments described herein can be combined with each other as long as they do not conflict. Furthermore, components in the following embodiments that are not described in an independent claim will be described as optional components. In each figure, components having substantially the same function are indicated by a common reference numeral, and redundant descriptions may be omitted or simplified.

[0012] Furthermore, the various elements shown in the drawings are for illustrative purposes only, and their dimensional ratios and appearance may differ from those of the actual object. In other words, each drawing is a schematic representation and not necessarily a strictly accurate depiction. Therefore, for example, the scale in each drawing may not necessarily match.

[0013] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather to terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Specifically, the light-incident side of the image sensor is defined as "upper," and the side opposite the light-incident side is defined as "lower." Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0014] Furthermore, in this specification, "plan view" refers to a view taken in a direction perpendicular to the main surface of the chip, in other words, a view taken in the thickness direction of the chip.

[0015] Furthermore, in this specification and the drawings, the X, Y, and Z axes represent the three axes of a three-dimensional Cartesian coordinate system. Below, the Z axis direction is defined as the thickness direction of the chip. Also, the negative side of the Z axis is defined as "downward," and the positive side of the Z axis is defined as "upward."

[0016] Furthermore, in this specification, ordinal numbers such as "first," "second," etc., unless otherwise specified, do not refer to the number or order of constituent elements, etc., but are used for the purpose of avoiding confusion and distinguishing similar constituent elements, etc.

[0017] (Embodiment 1) [Configuration] The configuration of the image sensor according to Embodiment 1 will be described with reference to Figures 1 to 5.

[0018] Figure 1 is a perspective view showing an example of an image sensor 100 according to this embodiment. Figure 2 is a schematic plan view showing an example of a planar layout in the pixel chip 110 of the image sensor 100 according to this embodiment. Figure 3 is a schematic plan view showing an example of a planar layout in the logic chip 120 of the image sensor 100 according to this embodiment. Figure 4 is another schematic plan view showing an example of a planar layout in the logic chip 120 of the image sensor 100 according to this embodiment. Figure 5 is a cross-sectional view of the vicinity of the column circuit 41 in the logic chip 120 of the image sensor 100 according to this embodiment. In Figure 5, the portion corresponding to the size of one pixel 21 in the cross-section at the position indicated by the V-V line in Figures 3 and 4 is shown. Also, in Figures 3 and 4, the positions of the multiple first pads 11 and multiple second pads 12 arranged on the pixel chip 110 in a plan view are shown by dashed lines.

[0019] Note that in Figures 1 to 5, only the circuits and wiring necessary for explanation are shown for clarity, and the image sensor 100 may include components not shown in Figures 1 to 5. For example, the image sensor 100 may include a vertical scanning circuit, power supply circuit, control circuit, frame memory, signal output circuit, and wiring, which are not shown. The vertical scanning circuit, power supply circuit, control circuit, frame memory, and signal output circuit are, for example, located on the logic chip 120, but at least one of these may be located on the pixel chip 110.

[0020] The image sensor 100 may also include one or more chips other than the pixel chip 110 and the logic chip 120. In this case, at least one of the vertical scanning circuit, power supply circuit, control circuit, frame memory, and signal output circuit may be located on one or more other chips. Furthermore, a portion of the pixel 21 circuit, which will be described later, may be located on one or more other chips.

[0021] As shown in Figure 1, the image sensor 100 according to this embodiment comprises a pixel chip 110 and a logic chip 120 located below the pixel chip 110. The logic chip 120 is stacked with the pixel chip 110. The pixel chip 110 and the logic chip 120 are joined together, for example, by hybrid bonding. As long as the pixel chip 110 and the logic chip 120 are stacked, the method of joining the pixel chip 110 and the logic chip 120 is not particularly limited.

[0022] Each of the pixel chip 110 and the logic chip 120 has, for example, a semiconductor substrate and a plurality of wiring layers stacked on the semiconductor substrate. Each of the plurality of wiring layers includes an insulating material and wiring, vias, contacts, etc., provided in the insulating material. The image sensor 100 is, for example, a BSI (Back Side Illumination) type image sensor, and light is incident on the back side of the semiconductor substrate of the pixel chip 110, which is the upper chip in the image sensor 100.

[0023] As shown in Figures 2 to 4, the image sensor 100 includes a pixel array 20 composed of a plurality of pixels 21, a plurality of first vertical signal lines 31, a plurality of second vertical signal lines 32, a plurality of column circuit groups 40 including a plurality of column circuits 41, a plurality of power lines 50, a plurality of first pads 11, a plurality of second pads 12, a connection structure 111, and a load circuit group 121. The connection structure 111 is located below the pixel array 20, and is therefore shown as a dashed line in Figure 2.

[0024] As shown in Figure 2, a pixel array 20 composed of multiple pixels 21, multiple first vertical signal lines 31, multiple first pads 11, and multiple second pads 12 are arranged on a pixel chip 110. The pixel array 20 is formed on the semiconductor substrate of the pixel chip 110. The multiple first vertical signal lines 31 are formed in one or more wiring layers among the multiple wiring layers of the pixel chip 110. The multiple first pads 11 and multiple second pads 12 are formed on the upper surface of the pixel chip 110. Note that in Figure 2, for ease of viewing, only a portion of the multiple pixels 21, only a portion of the multiple first vertical signal lines 31, only a portion of the multiple first pads 11, and only a portion of the multiple second pads 12 are shown. In other words, pixels 21, first vertical signal lines 31, first pads 11, and second pads 12 may also be arranged in positions not shown.

[0025] Furthermore, as shown in Figures 3 and 4, the multiple second vertical signal lines 32, multiple column circuit groups 40, multiple power lines 50, and load circuit group 121 are arranged on the logic chip 120. Each of the multiple column circuit groups 40 and load circuit group 121 is formed on the semiconductor substrate of the logic chip 120. Each of the multiple second vertical signal lines 32 and multiple power lines 50 is formed in one or more wiring layers among the multiple wiring layers of the logic chip 120. Note that in Figure 3, only the multiple second vertical signal lines 32 are shown and the multiple power lines 50 are omitted, and in Figure 4, only the multiple power lines 50 are shown and the multiple second vertical signal lines 32 are omitted. Also, in Figures 3 and 4, for ease of viewing, only a portion of the multiple second vertical signal lines 32, only a portion of the multiple column circuits 41, and only a portion of the multiple power lines 50 are shown. In other words, the second vertical signal line 32, the column circuit 41, and the power line 50 can also be placed in positions not shown in the diagram.

[0026] The details of each component of the image sensor 100 will be described below.

[0027] As shown in Figure 2, the multiple pixels 21 are arranged in a matrix in a plan view. In this specification and in each drawing, the X-axis direction is the row direction of the multiple pixels 21, and the Y-axis direction is the column direction of the multiple pixels 21. Furthermore, below, the row direction of the multiple pixels 21 may be simply referred to as the "row direction," and the column direction of the multiple pixels 21 may be simply referred to as the "column direction." The multiple pixels 21 are arranged at a predetermined pitch along the row direction and the column direction.

[0028] In the example shown in Figure 2, the multiple pixels 21 are arranged in a square grid pattern in a plan view. Alternatively, the multiple pixels 21 may be arranged in a staggered grid pattern in a plan view. In other words, the positions of pixels 21 in adjacent rows in the column direction may be offset in the row direction.

[0029] Each of the multiple pixels 21 has a photoelectric conversion unit that generates an electric charge upon the incidence of light, and a detection circuit that outputs a signal based on the charge generated by the photoelectric conversion unit. Each of the multiple pixels 21 outputs a signal to the first vertical signal line 31 corresponding to the amount of light incident on the photoelectric conversion unit.

[0030] The photoelectric conversion unit is, for example, a photoelectric conversion element such as a photodiode formed on a semiconductor substrate. The detection circuit includes, for example, a plurality of transistors formed on a semiconductor substrate. Each transistor in the detection circuit is connected to a control line (not shown) and operates based on a control signal supplied from the control line.

[0031] The multiple first vertical signal lines 31 are wiring through which signals output from the multiple pixels 21 are transmitted. The multiple first vertical signal lines 31 are provided corresponding to rows of the multiple pixels 21. Each of the multiple first vertical signal lines 31 extends in the row direction. The multiple first vertical signal lines 31 are also arranged along the row direction. In the example shown in Figure 2, eight first vertical signal lines 31 are provided, arranged along the row direction for each row of the multiple pixels 21. Each pixel 21 in each row is electrically connected, for example, to one of the eight first vertical signal lines 31 provided corresponding to the row of pixels 21. Also, in the example shown in Figure 2, the multiple first vertical signal lines 31 are divided into two in the row direction. The number of first vertical signal lines 31 corresponding to a row of pixels 21 is not particularly limited and is designed, for example, according to the number of row circuits 41 corresponding to the row of pixels 21. Furthermore, the multiple first vertical signal lines 31 do not necessarily have to be divided in the row direction.

[0032] The connection structure 111 is electrically connected to a plurality of first vertical signal lines 31. In the example shown in Figure 2, the connection structure 111 is positioned in a location that overlaps with the pixel array 20 in a plan view. The connection structure 111 electrically connects the plurality of first vertical signal lines 31 and a plurality of second vertical signal lines 32. The connection structure 111 includes, for example, a plurality of metal-to-metal bonding portions in hybrid bonding for joining a pixel chip 110 and a logic chip 120. These metal-to-metal bonding portions are connected, for example, to each of the plurality of first vertical signal lines 31. The configuration of the connection structure 111 is not particularly limited as long as it can electrically connect the plurality of first vertical signal lines 31 and a plurality of second vertical signal lines 32. Also, in the example shown in Figure 2, the connection structure 111 is located in the center of the pixel array 20 in a plan view, but it may be located in the area surrounding the pixel array 20. Furthermore, the connection structure 111 does not have to overlap with the pixel array 20 in a plan view.

[0033] The load circuit group 121 includes a plurality of load circuits provided for each of the plurality of first vertical signal lines 31. The load circuits are electrically connected to the first vertical signal lines 31 and function as constant current sources, forming a source follower circuit together with the detection circuit of the pixel 21 and the first vertical signal lines 31. In a plan view, the load circuit group 121 is positioned in a location corresponding to the connection structure 111. For example, in a plan view, the load circuit group 121 overlaps with the connection structure 111. In the example shown in Figures 3 and 4, in a plan view, the load circuit group 121 is sandwiched between the column circuit group 40. Note that since the load circuit group 121 is positioned in a location corresponding to the connection structure 111 in a plan view, it does not have to be sandwiched between the column circuit group 40 depending on the arrangement of the connection structure 111.

[0034] As shown in Figures 3 and 4, the multiple column circuit groups 40 are arranged in the column direction. In addition, two or more column circuit groups 40 are arranged in the column direction on both sides of the load circuit group 121 in the column direction (positive and negative sides in the Y-axis direction). In the example shown in Figures 3 and 4, four column circuit groups 40 are arranged in the column direction. The load circuit group 121 is positioned in the middle of the four column circuit groups 40 arranged in the column direction. Two of the four column circuit groups 40 and the remaining two column circuit groups 40 face each other via the load circuit group 121. The multiple column circuit groups 40 are positioned in a plan view corresponding to the pixel array 20. The multiple column circuit groups 40 overlap the pixel array 20 in a plan view.

[0035] Each column circuit group 40 includes a plurality of column circuits 41 arranged at a predetermined pitch along the row direction. The plurality of column circuits 41 in each column circuit group 40 are provided corresponding to rows of a plurality of pixels 21. In each column circuit group 40, one or more column circuits 41 are provided for each row of a plurality of pixels 21. In the example shown in Figures 3 and 4, two column circuits 41 are provided for each row of a plurality of pixels 21 in each column circuit group 40. In the example shown in Figures 3 and 4, there are four column circuit groups 40, so eight column circuits 41 are provided for each row of a plurality of pixels 21.

[0036] Multiple column circuits 41 receive signals output from multiple pixels 21. Each pixel 21 in each column outputs a signal to one of the column circuits 41 provided, for example, corresponding to the column of pixels 21. Each column circuit 41 receives signals output from the pixels 21 via a first vertical signal line 31 and a second vertical signal line 32.

[0037] Each column circuit 41 includes an A / D conversion circuit that converts the analog signal output from the pixel 21 into a digital signal. In other words, each column circuit 41 performs A / D conversion on the analog signal output from the pixel 21. Each column circuit 41 may also perform processing such as correlated double sampling on the analog signal before A / D conversion. The digital signals converted by each column circuit 41 are output sequentially to the outside of the image sensor 100 via, for example, a signal output circuit (not shown).

[0038] As shown in Figure 3, the multiple second vertical signal lines 32 are wiring through which signals output from multiple pixels 21 are transmitted. Signals output from multiple pixels 21 are input to the multiple second vertical signal lines 32 via the multiple first vertical signal lines 31. The multiple second vertical signal lines 32 are provided corresponding to rows of multiple pixels 21. The multiple second vertical signal lines 32 are electrically connected to multiple column circuits 41 of the multiple column circuit groups 40. Each second vertical signal line 32 electrically connects a column circuit 41 to a first vertical signal line 31 provided corresponding to the same row of pixels 21. For example, each first vertical signal line 31 is electrically connected to one second vertical signal line 32, and each second vertical signal line 32 is electrically connected to one column circuit 41. In the example shown in Figures 2 to 4, the eight first vertical signal lines 31 corresponding to each row of the multiple pixels 21 are electrically connected via the second vertical signal line 32 to two column circuits 41 in each of the four column circuit groups 40 arranged in the column direction, that is, to the eight column circuits 41 corresponding to each row of the multiple pixels 21.

[0039] Each of the multiple second vertical signal lines 32 extends in the column direction. Furthermore, the multiple second vertical signal lines 32 are aligned along the row direction. In the examples shown in Figures 3 and 4, four second vertical signal lines 32 are provided, aligned along the row direction for each column of multiple pixels 21. The second vertical signal lines 32 aligned along the row direction are, for example, of equal length. Also, in the examples shown in Figures 3 and 4, the multiple second vertical signal lines 32 include two or more second vertical signal lines 32 connected to multiple column circuits 41 of a column circuit group 40 located on one side of the column direction of a load circuit group 121 (e.g., the positive side in the Y-axis direction) of two adjacent column circuit groups 40, and two or more other second vertical signal lines 32 connected to multiple column circuits 41 of a column circuit group 40 located on the other side of the column direction of the load circuit group 121 (e.g., the negative side in the Y-axis direction).

[0040] In a plan view, the multiple second vertical signal lines 32 and the multiple column circuits 41 of at least one of the multiple column circuit groups 40 overlap. The multiple second vertical signal lines 32 pass above the multiple column circuits 41 of at least one of the column circuit groups 40. As shown in Figure 3, if two or more column circuit groups 40 are arranged in the column direction on at least one side in the column direction of the load circuit group 121, the multiple second vertical signal lines 32 and the multiple column circuits 41 of at least one of the column circuit groups 40 will overlap. Therefore, the number of column circuit groups 40 provided by the image sensor 100 may be, for example, three or more. Note that in the image sensor 100, two or more column circuit groups 40 may be arranged in the column direction on only one side in the column direction of the load circuit group 121, in which case the number of column circuit groups 40 provided by the image sensor 100 is two or more.

[0041] The number of column circuit groups 40 and the number of first vertical signal lines 31, second vertical signal lines 32, and column circuits 41 corresponding to each column of pixels 21, as shown in Figures 2 to 4 described above, are examples and are not particularly limited. For example, the number of column circuit groups 40 and the number of first vertical signal lines 31, second vertical signal lines 32, and column circuits 41 corresponding to each column of pixels 21 may be one or multiple.

[0042] As shown in FIG. 4, a plurality of power supply lines 50 are electrically connected to a plurality of column circuits 41 of a plurality of column circuit groups 40. The plurality of power supply lines 50 are wirings that supply power necessary for driving the plurality of column circuits 41 of the plurality of column circuit groups 40. The plurality of power supply lines 50 may include power supply lines 50 that supply power with different voltages to the plurality of column circuits 41.

[0043] The plurality of power supply lines 50 are arranged side by side along the row direction. Also, each of the plurality of power supply lines 50 extends in the column direction from the position where the plurality of first pads 11 are arranged in a plan view. In a plan view, from the position where each first pad 11 is arranged, for example, two or more power supply lines 50 extend in the column direction respectively. The positional relationship between each of the plurality of first pads 11 and the two or more power supply lines 50 is unified. The plurality of power supply lines 50 are arranged, for example, on the same wiring layer. In a plan view, the plurality of power supply lines 50 and the plurality of column circuits 41 of the plurality of column circuit groups 40 overlap.

[0044] As shown in FIG. 5, a plurality of second vertical signal lines 32 are arranged between the plurality of power supply lines 50 and the plurality of column circuits 41. The distance D1 between each of the plurality of second vertical signal lines 32 and the nearest power supply line 50 is equal to each other. In the example shown in FIG. 5, in a plan view, each of the plurality of second vertical signal lines 32 overlaps with one of the plurality of power supply lines 50. In any of the plurality of power supply lines 50, the positional relationship between the power supply line 50 and the column circuit 41 closest to the power supply line 50 among the plurality of column circuits 41, and the positional relationship between the power supply line 50 and the second vertical signal line 32 closest to the power supply line 50 among the plurality of second vertical signal lines 32 are, for example, unified. In FIG. 5, illustrations other than the second vertical signal line 32, the power supply line 50, and the column circuit 41 are omitted. For example, an insulating material (not shown) included in the wiring layer of the logic chip 120 is arranged around the second vertical signal line 32 and the power supply line 50.

[0045] As shown in Figure 4, the multiple first pads 11 are electrically connected to the multiple column circuits 41 of the multiple column circuit groups 40 via the multiple power lines 50. The multiple first pads 11 are film-like metal terminals for connecting to a power supply that provides the power necessary to drive the multiple column circuits 41 of the multiple column circuit groups 40. The multiple first pads 11 and the multiple power lines 50 are connected, for example, via through-vias (not shown) that penetrate the semiconductor substrate of the pixel chip 110.

[0046] As shown in Figures 2 to 4, the multiple first pads 11 are arranged at a predetermined pitch along the row direction. In a plan view, the multiple first pads 11 are positioned around the pixel array 20 and the multiple column circuit groups 40. In a plan view, the multiple first pads 11 are aligned in the column direction with the pixel array 20 and the multiple column circuit groups 40. The multiple first pads 11 are positioned in the column circuit region A1 of the image sensor 100 in a plan view, which is the region where the multiple column circuit groups 40 are arranged in the row direction. The column circuit region A1 can also be described as a region that is virtually extended in the column direction with respect to the multiple column circuit groups 40. In the example shown in Figures 2 to 4, in a plan view, the multiple first pads 11 are positioned within the column circuit region A1 on one side (the negative side in the Y-axis direction) of the pixel array 20 and the multiple column circuit groups 40 in the column direction. The image sensor 100 may further include a plurality of first pads 11 arranged within the column circuit region A1 on the other side (the positive side in the Y-axis direction) of the pixel array 20 and the plurality of column circuit groups 40 in the column circuit region A1. In this case, two first pads 11 that are arranged on either side of the plurality of column circuit groups 40 in a plan view and have the same position in the row direction may be connected to the same power line 50.

[0047] The plurality of second pads 12 are film-like metal terminals for connecting to a power supply that supplies power necessary for driving circuits of the image sensor 100 other than the plurality of column circuits 41. The plurality of second pads 12 are not electrically connected to the plurality of power supply lines 50 for supplying power to the plurality of column circuits 41. In a plan view, the plurality of second pads 12 are arranged in a region different from the region where the plurality of first pads 11 are arranged. In the example shown in FIGS. 2 to 4, in a plan view, the plurality of second pads 12 are arranged around the pixel array 20 and the plurality of column circuit groups 40 outside the column circuit region A1.

[0048] The plurality of second pads 12 are arranged at a predetermined pitch along a predetermined direction. In the example shown in FIGS. 2 to 4, the plurality of second pads 12 are arranged along the row direction. Also, in the example shown in FIGS. 2 to 4, the plurality of second pads 12 are arranged side by side in the row direction with the plurality of first pads 11. Note that the positions, arrangement directions, and numbers of the plurality of second pads 12 are not particularly limited. For example, instead of or in addition to the plurality of second pads 12 arranged along the row direction, the image sensor 100 may include the plurality of second pads 12 arranged along the column direction. In this case, the plurality of second pads 12 arranged along the column direction are, for example, arranged side by side in the row direction with the pixel array 20 and the plurality of column circuit groups 40 in a plan view.

[0049] [Relationship of pitches] Next, the relationship of pitches in which the plurality of first pads 11, the plurality of second pads 12, the plurality of pixels 21, and the plurality of column circuits 41 are arranged will be described.

[0050] The pitch P1 of the multiple first pads 11 is an integer multiple of the pitch P2 of the multiple column circuits 41. Here, the integer is 1 or greater. Also, pitch P1 is the distance between the centers of adjacent first pads 11. Pitch P2 is the distance between the centers of adjacent column circuits 41. If pitch P1 is not an integer multiple of pitch P2, the positional relationship between each of the multiple power lines 50 and the column circuits 41 and the second vertical signal lines 32 will not be uniform. As a result, the coupling capacitance with the multiple power lines 50 will not be uniform in the multiple column circuits 41 and the multiple second vertical signal lines 32, and the noise in the signals output from the multiple pixels 21 will vary. By making pitch P1 an integer multiple of pitch P2, the positional relationship between each of the multiple power lines 50 that are electrically connected to the multiple first pads 11 and extend in the column direction and the column circuits 41 and the second vertical signal lines 32 can be unified. Therefore, the coupling capacitance with the multiple power lines 50 is made uniform in the multiple column circuits 41 and the multiple second vertical signal lines 32, and variations in noise in the signals output from the multiple pixels 21 can be suppressed.

[0051] Furthermore, even if the pitch P1 is not an integer multiple of the pitch P2, the positional relationship between each of the multiple power lines 50 and the column circuit 41 and the second vertical signal line 32 can be unified by providing crank-shaped wiring between the multiple first pads 11 and the multiple power lines 50. However, the crank-shaped wiring increases the power impedance and increases the voltage drop. Therefore, it becomes necessary to increase the voltage of the power supply to the multiple column circuits 41, which increases power consumption. Also, in this case, it is necessary to design the shape of the crank-shaped wiring for each of the multiple power lines 50, which increases the design man-hours. Since the pitch P1 is an integer multiple of the pitch P2, the multiple power lines 50 and the multiple first pads 11 can be electrically connected without using crank-shaped wiring, thus reducing the design man-hours.

[0052] From the above, by having the pitch P1 be an integer multiple of the pitch P2, the image sensor 100 can reduce design man-hours while suppressing noise variations in the signals output from multiple pixels 21.

[0053] For example, as shown and explained in Figure 5, by making the distance D1 between each of the multiple second vertical signal lines 32 and the nearest power supply line 50 equal, the uniformity of the coupling capacitance with the power supply line 50 for each of the multiple second vertical signal lines 32 can be improved. With such a configuration, since the pitch P1 is an integer multiple of the pitch P2, the multiple power supply lines 50 and the multiple first pads 11 can be electrically connected without using crank-shaped wiring, thus reducing design man-hours.

[0054] Furthermore, the pitch P1 of multiple first pads 11 is an integer multiple of the pitch P3 of multiple pixels 21 arranged in the row direction. Also, the pitch P3 of multiple pixels 21 arranged in the row direction is an integer multiple of the pitch P2 of multiple column circuits 41 arranged. Here, the integer is 1 or greater. Also, pitch P3 is the distance between the centers of adjacent pixels 21 in the row direction. As a result, the positional relationship between each of the multiple pixels 21 and the column circuits 41 is unified in the row direction, and the multiple pixels 21 and multiple column circuits 41 can be connected with the same wiring length. In addition, the wiring connecting the multiple pixels 21 and multiple column circuits 41 can be shortened. Furthermore, since the positional relationship between the multiple first vertical signal lines 31 and the multiple second vertical signal lines 32 is unified, the design man-hours for wiring connecting the first vertical signal lines 31 and the second vertical signal lines 32 can be reduced.

[0055] Furthermore, the pitch P4 of multiple second pads 12 is smaller than the pitch P1 of multiple first pads 11. Pitch P4 is the distance between the centers of adjacent second pads 12. Multiple second pads 12 are pads that are not electrically connected to multiple power lines 50 that supply power to multiple row circuits 41. Therefore, because pitch P4 is smaller than pitch P1, the efficiency of arranging the second pads 12, which is unrelated to the arrangement of multiple power lines 50 that greatly affects the increase or decrease in design man-hours, can be increased. Note that in Figures 2 to 4, adjacent second pads 12 are shown touching, but this is to illustrate the small pitch P4 in an easy-to-understand way; in reality, adjacent second pads 12 are spaced apart to the extent that they do not short-circuit.

[0056] [Modified Examples] Next, modified examples of Embodiment 1 will be described. In the following, the differences from Embodiment 1 will be the main focus of the explanation, and the similarities will be omitted or simplified.

[0057] Figure 6 is a schematic plan view showing an example of a planar layout in the logic chip 120 of the image sensor according to this modified example. Figure 7 is a cross-sectional view of the vicinity of the column circuit 41 in the logic chip 120 of the image sensor according to this modified example. In Figure 7, the portion of the cross section at the position indicated by the line VII-VII in Figure 6 that corresponds to the size of one pixel 21 is shown. In Figure 6, the positions of the multiple first pads 11, multiple second pads 12, and third pads 13 arranged on the pixel chip 110 are shown by dashed lines in a plan view.

[0058] Note that, as with Figures 1 to 5, in Figures 6 and 7, only the circuits and wiring necessary for the explanation are shown for clarity. Also, in Figure 6, as with Figure 4, only the power lines 50 are shown among the multiple second vertical signal lines 32 and multiple power lines 50, and the illustration of the multiple second vertical signal lines 32 is omitted. Also, in Figure 6, as with Figure 4, only a portion of the multiple second vertical signal lines 32, only a portion of the multiple column circuits 41, and only a portion of the multiple power lines 50 are shown for clarity. Also, in Figure 6, only a portion of the multiple fixed potential wiring 60 is shown with a dotted line. In other words, the second vertical signal lines 32, column circuits 41, power lines 50, and fixed potential wiring 60 may be arranged in positions not shown. Also, in Figure 7, the illustration of anything other than the second vertical signal lines 32, power lines 50, column circuits 41, and fixed potential wiring 60 is omitted. For example, an insulating material (not shown) included in the wiring layer of the logic chip 120 is placed around the second vertical signal line 32, the power line 50, and the fixed potential wiring 60.

[0059] As shown in Figures 6 and 7, the image sensor according to this modified example differs from the image sensor 100 according to Embodiment 1 mainly in that it further includes a plurality of fixed potential wirings 60 and a third pad 13. Although not shown in Figure 6, the image sensor according to this modified example is the same as the image sensor 100 in that it includes a plurality of second vertical signal lines 32 as shown in Figure 3.

[0060] The third pad 13 is a film-like metal terminal for connecting to a fixed potential source such as ground. The third pad 13 is, for example, located on the upper surface of the pixel chip 110. In the example shown in Figure 6, a plurality of first pads 11 are arranged separately in the column circuit region A1, and the third pad 13 is located between the plurality of first pads 11 that are arranged separately. The distance between the center of the third pad 13 and the center of the first pad 11 adjacent to the third pad 13 is, for example, equal to the pitch P1. Power from the plurality of power lines 50 is supplied to the column circuit 41 located at the position where the third pad 13 is located in the row direction, that is, on the positive side in the Y-axis direction of the third pad 13, via wiring that extends in the row direction on a wiring layer different from the wiring layer on which the plurality of power lines 50 are located. In this case, dummy power lines may be located at positions in the wiring layer on which the plurality of power lines 50 are located that overlap with the column circuit 41. The arrangement of the third pad 13 is not particularly limited, and it may be located, for example, outside the column circuit region A1.

[0061] The multiple fixed-potential wires 60 are wires whose potential is fixed to a predetermined potential, such as the ground potential. The multiple fixed-potential wires 60 are arranged on the logic chip 120. As shown in Figure 6, the multiple fixed-potential wires 60 are electrically connected to the third pad 13. In Figure 6, although omitted for clarity, each of the multiple fixed-potential wires 60 extends in the column direction in the region where the multiple column circuit groups 40 are arranged in a plan view.

[0062] As shown in Figure 7, the multiple fixed-potential wirings 60 are arranged, for example, between the multiple power lines 50 and the row circuit 41.

[0063] Some of the fixed potential wiring 60 is located between the multiple second vertical signal lines 32 and the multiple power lines 50. In the example shown in Figure 7, the fixed potential wiring 60 is placed between each second vertical signal line 32 and the power line 50 closest to each second vertical signal line 32. This allows the fixed potential wiring 60 to function as shielding wiring, suppressing coupling between the second vertical signal lines 32 and the power lines 50.

[0064] Furthermore, some of the fixed potential wirings 60 are located between the multiple second vertical signal lines 32 and the multiple row circuits 41 that overlap with the multiple second vertical signal lines 32 in a plan view. In the example shown in Figure 7, the fixed potential wiring 60 is placed between each second vertical signal line 32 and the row circuit 41 that overlaps with each second vertical signal line 32. This allows the fixed potential wiring 60 to function as shielding wiring, suppressing coupling between the second vertical signal lines 32 and the row circuits 41.

[0065] Furthermore, some of the fixed potential wirings 60 are located between adjacent second vertical signal lines 32. This allows the fixed potential wirings 60 to function as shielding wires, suppressing coupling between adjacent second vertical signal lines 32.

[0066] As described above, in the image sensor according to this modified example, fixed potential wiring 60 is adjacent to both sides of each second vertical signal line 32 in the vertical direction (positive and negative sides in the Z-axis direction) and both sides in the row direction (positive and negative sides in the X-axis direction) via an insulating material. Therefore, each second vertical signal line 32 can be shielded by the fixed potential wiring 60, and crosstalk of each second vertical signal line 32 can be reduced. Thus, noise in the signal output from the pixel 21 transmitted by each second vertical signal line 32 can be reduced.

[0067] Furthermore, as explained above, the pitch P1 where multiple first pads 11 are arranged is an integer multiple of the pitch P2 where multiple column circuits 41 are arranged, so the positional relationship with the second vertical signal line 32 can be standardized for each of the multiple power lines 50. Therefore, even when multiple fixed potential wirings 60 are arranged on the logic chip 120 to shield the coupling with multiple power lines 50, the arrangement pattern of the multiple fixed potential wirings 60 can be standardized, reducing design man-hours.

[0068] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 will describe an imaging device equipped with an image sensor according to the present disclosure.

[0069] Figure 8 is a block diagram showing an example of the configuration of the imaging device 300 according to this embodiment.

[0070] As shown in Figure 8, the imaging device 300 according to this embodiment comprises an image sensor 301, an imaging optical system 302, a signal processing unit 303, a drive circuit 304, and a system control unit 305. The imaging device 300 is, for example, a digital still camera, a handy video recorder, etc. The imaging device 300 may also be an electronic device having an imaging function, such as a smartphone. For the image sensor 301, for example, an image sensor according to either Embodiment 1 or a modified version thereof described above is used.

[0071] The imaging optical system 302 includes a lens and focuses light onto the imaging surface of the image sensor 301. The imaging optical system 302 may also include a lens group including an autofocus lens and a zoom lens, and an aperture.

[0072] The signal processing unit 303 is a processing circuit that performs various signal processing on the output signal from the image sensor 301.

[0073] The drive circuit 304 controls the drive of the image sensor 301. For example, the drive circuit 304 receives a control signal corresponding to the drive mode from the system control unit 305 and supplies a drive mode signal to the image sensor 301. When the image sensor 301 receives a drive mode signal, the control circuit generates drive pulses corresponding to the drive mode signal and supplies them to each circuit within the image sensor 301.

[0074] The system control unit 305 controls the entire imaging device 300. The system control unit 305 is, for example, a semiconductor integrated circuit.

[0075] Furthermore, at least a portion of the imaging optical system 302, signal processing unit 303, drive circuit 304, and system control unit 305 may be provided within the image sensor 301, or they may be provided in equipment outside the imaging device 300.

[0076] (Other) The image sensors and imaging devices relating to one or more embodiments of this disclosure have been described above based on embodiments, but this disclosure is not limited to embodiments. Without departing from the spirit of this disclosure, various modifications that a person skilled in the art can conceive of may be applied to each embodiment, and forms constructed by combining components from different embodiments may also be included within the scope of one or more embodiments of this disclosure.

[0077] For example, in the above embodiment, the image sensor is provided with a plurality of second vertical signal lines 32, but it is not limited to this. The image sensor may not be provided with a plurality of second vertical signal lines 32, and a plurality of first vertical signal lines 31 and a plurality of column circuits 41 may be connected via vias or the like corresponding to the positions of the plurality of column circuits 41.

[0078] Furthermore, in the above embodiment, the plurality of first pads 11, the plurality of second pads 12, and the third pad 13 are arranged on the pixel chip 110, but this is not limited to that. The plurality of first pads 11, the plurality of second pads 12, and the third pad 13 may be arranged on the logic chip 120 in the positions in the plan view described above.

[0079] Furthermore, although the image sensor according to this disclosure was used in an imaging device in the above embodiment, it is not limited to this. For example, the image sensor according to this disclosure may be used in a distance measuring device.

[0080] Examples of image sensors and imaging devices relating to this disclosure, as described based on the embodiments above, are shown below. The image sensors and imaging devices relating to this disclosure are not limited to the following examples.

[0081] For example, an image sensor according to a first aspect of the present disclosure comprises: a plurality of pixels arranged in a matrix in a plan view; a plurality of first vertical signal lines through which signals output from the plurality of pixels are transmitted, provided corresponding to the rows of the plurality of pixels and extending in the direction of the rows of the plurality of pixels; a pixel chip on which the plurality of pixels and the plurality of first vertical signal lines are arranged; a group of one or more column circuits provided corresponding to the rows of the plurality of pixels and into which signals output from the plurality of pixels are input, including a group of column circuits arranged along the row direction of the plurality of pixels; a plurality of power lines electrically connected to the plurality of column circuits and extending in the direction of the rows; a logic chip on which the group of one or more column circuits and the plurality of power lines are arranged and stacked with the pixel chip; and a plurality of first pads electrically connected to the plurality of column circuits via the plurality of power lines and arranged along the row direction, wherein in a plan view, the group of one or more column circuits and the plurality of first pads are arranged in the direction of the rows, and the pitch of the arrangement of the plurality of first pads is an integer multiple of the pitch of the arrangement of the plurality of column circuits.

[0082] As a result, the pitch of the multiple first pads is an integer multiple of the pitch of the multiple row circuits. Therefore, even if multiple power lines are arranged according to the pitch of the multiple first pads, the positional relationship with the row circuits can be unified for each of the multiple power lines. Consequently, variations in noise in the signals output from multiple pixels can be suppressed. Furthermore, the need to design for unifying the positional relationship with the row circuits for each of the multiple power lines is eliminated, reducing design man-hours. Thus, in the image sensor according to this embodiment, variations in noise in the signals output from multiple pixels can be suppressed while reducing design man-hours.

[0083] Furthermore, for example, an image sensor according to a second aspect of the present disclosure is an image sensor according to a first aspect, wherein the one or more row circuit groups are a plurality of row circuit groups, the plurality of row circuit groups are arranged in the row direction, and the image sensor is arranged on the logic chip and electrically connected to the plurality of row circuits, and comprises a plurality of second vertical signal lines through which signals output from the plurality of pixels are transmitted, provided corresponding to the rows of the plurality of pixels and extending in the row direction.

[0084] This allows for the unification of the positional relationship between each of the power lines and the second vertical signal line, even when multiple power lines are arranged according to the pitch of the multiple first pads.

[0085] Furthermore, for example, the image sensor according to the third aspect of this disclosure is the image sensor according to the second aspect, wherein the spacing between each of the plurality of second vertical signal lines and the nearest wiring is equal to each other.

[0086] This improves the uniformity of the coupling capacitance with the nearest wiring in each of the multiple second vertical signal lines.

[0087] Furthermore, for example, an image sensor according to a fourth aspect of the present disclosure is an image sensor according to a second or third aspect, wherein in a plan view, the plurality of second vertical signal lines and the plurality of power lines overlap, and the image sensor includes a plurality of fixed potential wirings located between the plurality of second vertical signal lines and the plurality of power lines.

[0088] This allows the fixed-potential wiring to function as shielding wiring, suppressing coupling between the second vertical signal line and the power line. Furthermore, since the pitch of multiple first pads is an integer multiple of the pitch of multiple circuit rows, the positional relationship with the second vertical signal line can be standardized for each of the multiple power lines. Therefore, even when multiple fixed-potential wirings are placed on a logic chip, the arrangement pattern of the multiple fixed-potential wirings is standardized, reducing design effort.

[0089] Furthermore, for example, an image sensor according to a fifth aspect of the present disclosure is an image sensor according to any one of the second to fourth aspects, wherein in a plan view, the plurality of second vertical signal lines and the plurality of column circuits of at least one of the plurality of column circuit groups overlap, and the image sensor comprises a plurality of fixed potential wirings located between the plurality of second vertical signal lines and the plurality of column circuits that overlap with the plurality of second vertical signal lines in a plan view.

[0090] This allows the fixed-potential wiring to function as shielding wiring, suppressing coupling between the second vertical signal line and the column circuit.

[0091] Furthermore, for example, an image sensor according to the sixth aspect of this disclosure is an image sensor according to any one of the second to fifth aspects, and comprises a plurality of fixed potential wirings located between adjacent second vertical signal lines among the plurality of second vertical signal lines.

[0092] This allows the fixed-potential wiring to function as shielding wiring, suppressing coupling between adjacent second vertical signal lines.

[0093] Furthermore, for example, an image sensor according to a seventh aspect of the present disclosure is an image sensor according to any one of the first to sixth aspects, comprising a plurality of second pads arranged in a region different from the region in which the plurality of first pads are arranged in a plan view, and arranged along a predetermined direction, wherein the plurality of second pads are not electrically connected to the plurality of power lines, and the pitch of the plurality of second pads is smaller than the pitch of the plurality of first pads.

[0094] This makes it possible to improve the efficiency of laying out the second pad, which is unrelated to the arrangement of multiple power lines, a factor that significantly impacts the increase or decrease in design man-hours.

[0095] Furthermore, for example, the image sensor according to the eighth aspect of the present disclosure is an image sensor according to any one of the first to seventh aspects, wherein the pitch of the plurality of first pads is an integer multiple of the pitch of the plurality of pixels arranged in the row direction.

[0096] As a result, the pitch of multiple pixels and the pitch of multiple column circuits become integer multiples of the pitch of multiple first pads. Therefore, the positional relationship between each pixel and the column circuits is unified, and multiple pixels and multiple column circuits can be connected with the same wiring length.

[0097] Furthermore, for example, the image sensor according to the ninth aspect of this disclosure is an image sensor according to any one of the first to seventh aspects, wherein the pitch of the plurality of pixels arranged in the row direction is an integer multiple of the pitch of the plurality of column circuits.

[0098] This unifies the positional relationship between each of the multiple pixels and the column circuit, and allows for the connection of multiple pixels and multiple column circuits with the same wiring length.

[0099] Furthermore, for example, an imaging device according to the tenth aspect of this disclosure comprises an image sensor according to any one of the first to ninth aspects.

[0100] As a result, the imaging device according to this embodiment, equipped with the above-mentioned image sensor, can reduce design man-hours while suppressing noise variations in the signals output from multiple pixels.

[0101] This disclosure is widely applicable to image sensors and imaging devices, etc.

[0102] 11 First pad 12 Second pad 13 Third pad 20 Pixel array 21 Pixel 31 First vertical signal line 32 Second vertical signal line 40 Column circuit group 41 Column circuit 50 Power line 60 Fixed potential wiring 100, 301 Image sensor 110 Pixel chip 111 Connection structure 120 Logic chip 121 Load circuit group 300 Imaging device 302 Imaging optical system 303 Signal processing unit 304 Drive circuit 305 System control unit A1 Column circuit area

Claims

1. An image sensor comprising: a plurality of pixels arranged in a matrix in a plan view; a plurality of first vertical signal lines through which signals output from the plurality of pixels are transmitted, provided corresponding to the rows of the plurality of pixels and extending in the direction of the rows of the plurality of pixels; a pixel chip on which the plurality of pixels and the plurality of first vertical signal lines are arranged; a group of one or more column circuits provided corresponding to the rows of the plurality of pixels and into which signals output from the plurality of pixels are input, including a group of column circuits arranged along the row direction of the plurality of pixels; a plurality of power lines electrically connected to the plurality of column circuits and extending in the direction of the rows; a logic chip on which the group of one or more column circuits and the plurality of power lines are arranged and stacked with the pixel chip; and a plurality of first pads electrically connected to the plurality of column circuits via the plurality of power lines and arranged along the row direction, wherein in a plan view, the group of one or more column circuits and the plurality of first pads are arranged in the direction of the rows, and the pitch of the plurality of first pads is an integer multiple of the pitch of the plurality of column circuits.

2. The image sensor according to claim 1, wherein the one or more row circuit groups are a plurality of row circuit groups, the plurality of row circuit groups are arranged in the row direction, and the image sensor is arranged on the logic chip and electrically connected to the plurality of row circuits, and comprises a plurality of second vertical signal lines through which signals output from the plurality of pixels are transmitted, the second vertical signal lines are provided corresponding to the rows of the plurality of pixels and extend in the row direction.

3. The image sensor according to claim 2, wherein the spacing between each of the plurality of second vertical signal lines and the nearest wiring is equal to each other.

4. In the plan view, the plurality of second vertical signal lines and the plurality of power lines overlap, and the image sensor comprises a plurality of fixed potential wirings located between the plurality of second vertical signal lines and the plurality of power lines, the image sensor according to claim 2 or 3.

5. In a plan view, the plurality of second vertical signal lines and the plurality of column circuits of at least one of the plurality of column circuit groups overlap, and the image sensor comprises a plurality of fixed potential wirings located between the plurality of second vertical signal lines and the plurality of column circuits that overlap with the plurality of second vertical signal lines in a plan view, according to any one of claims 2 to 4.

6. The image sensor according to any one of claims 2 to 5, comprising a plurality of fixed potential wirings located between adjacent second vertical signal lines among the plurality of second vertical signal lines.

7. The image sensor according to any one of claims 1 to 6, comprising a plurality of second pads arranged in a region different from the region in which the plurality of first pads are arranged in a plan view, and arranged along a predetermined direction, wherein the plurality of second pads are not electrically connected to the plurality of power lines, and the pitch of the plurality of second pads is smaller than the pitch of the plurality of first pads.

8. The image sensor according to any one of claims 1 to 7, wherein the pitch of the plurality of first pads is an integer multiple of the pitch of the plurality of pixels arranged in the row direction.

9. The image sensor according to any one of claims 1 to 7, wherein the pitch of the plurality of pixels arranged in the row direction is an integer multiple of the pitch of the plurality of column circuits.

10. An imaging device comprising the image sensor described in any one of claims 1 to 9.

Images