GAN HEMT device

Abstract

A GaN HEMT device comprises: an N-type low-resistance substrate (10); a grounded backside grounded metal (32) formed on the backside of the substrate; an epitaxial layer of a P-type SiC material formed on the entire upper surface of the substrate, wherein the upper surface of the epitaxial layer is divided into an epitaxial-layer first region and an epitaxial-layer second region; a first through hole formed downward from the epitaxial-layer first region, wherein the bottom end of the first through hole extends into the substrate; an N-type connection region (20) formed by filling the first through hole with an N-type material, wherein the lower end of the N-type connection region extends into the substrate; and a GaN HEMT front-side structure formed on the epitaxial-layer second region, wherein the backside grounded metal, the N-type substrate, and the N-type connection region are connected, and are connected to the GaN HEMT front-side structure.

Description

A GaN HEMT device Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a GaN HEMT device. Background Technology

[0002] Gallium nitride high electron mobility transistors (GaN HEMTs) are an emerging type of semiconductor device that has found widespread application in various fields due to their superior performance. Compared to traditional silicon-based devices, GaN HEMTs offer higher switching speeds and higher breakdown voltages, enabling them to perform exceptionally well in high-frequency, high-power, and high-temperature environments.

[0003] GaN HEMT devices have applications in multiple fields, including the following:

[0004] Wireless communication: GaN HEMT devices play a crucial role in 5G communication systems. Their high-frequency characteristics enable signals to be transmitted at higher frequencies, improving data transmission rates and network capacity.

[0005] Radar Systems: Due to the high power and efficiency of GaN HEMT devices, many modern radar systems choose to adopt this technology. It can effectively improve the detection range and accuracy of radar.

[0006] Power Conversion: GaN HEMT devices are widely used in power management, especially in high-efficiency power converters and inverters. Their high switching speed and low on-resistance significantly improve power efficiency and help reduce energy consumption.

[0007] Electric Vehicles and Renewable Energy: With the increasing popularity of electric vehicles and renewable energy, GaN HEMT devices are gradually becoming core components of electric vehicle charging stations and inverters, which can improve the efficiency and performance of the overall system.

[0008] In recent years, GaN HEMT device technology has developed rapidly. Many semiconductor companies and research institutions have increased their investment in GaN material research and production. Compared with earlier technologies, today's GaN HEMT devices have made significant progress in cost, stability, and manufacturing processes. With the maturity of manufacturing processes, GaN HEMT devices are finding increasingly wider market applications, and their prices are gradually decreasing, driving their widespread adoption in various fields.

[0009] Common substrates for GaN HEMT devices include SiC and diamond. GaN on SiC HEMT devices specifically refer to GaN HEMT devices fabricated on silicon carbide (SiC) substrates. GaN on SiC HEMT devices typically use high-resistivity SiC substrates. Due to their high thermal conductivity, combined with the excellent transport properties of AlGaN / GaN heterojunctions, SiC substrates enable GaN HEMT devices to exhibit significant performance advantages in high-frequency, broadband, high-efficiency, and high-power applications.

[0010] The main reasons for choosing high-resistivity SiC substrates in GaN on SiC HEMT devices are as follows:

[0011] 1. Reduce leakage current: High-resistivity SiC substrates have high resistivity, which can effectively reduce the leakage current of devices and improve the breakdown voltage and reliability of devices.

[0012] 2. Improved performance: High-resistivity SiC substrates help reduce charge exchange and scattering effects between the SiC substrate and the GaN layer, thereby improving the current collapse effect of HEMT devices and enhancing the overall performance of the devices.

[0013] 3. Reduced thermal effects: High-resistivity SiC substrates can reduce the self-heating effect of devices, which helps to maintain device stability at high power densities.

[0014] 4. Matching: Although high-resistivity SiC substrates have high resistivity, in specific applications, further processing or selection of specific types of high-resistivity SiC substrates can better match the requirements of GaN layers and optimize device performance.

[0015] In summary, the use of high-resistivity SiC substrates in GaN on SiC HEMT devices is to improve the electrical performance, reliability, and stability of the devices.

[0016] Figure 1 is a schematic diagram of a prior art GaN on SiC HEMT device. Figure 1 is from the literature "A Review of GaN on SiC High Electron-Mobility Power Transistors and MMICs". As shown in Figure 1, the substrate via (i.e., substrate via 1-1) extends from the back side of the device to the front side to achieve grounding.

[0017] While existing GaN on SiC HEMT devices are being developed, they also face challenges such as manufacturing difficulties. Figure 2 shows a schematic diagram of another existing GaN on SiC HEMT device. Due to their excellent heat dissipation performance and low SiC substrate defect rate, GaN on SiC HEMT devices have long been used in radio frequency (RF) applications, which place high demands on the device's grounding resistance and inductance. However, due to the wide bandgap characteristics of SiC and GaN, GaN on SiC HEMT devices cannot use a grounding via to conduct electricity to the substrate; instead, they can only be grounded using a TSV via 2-1 as shown in Figure 2.

[0018] Through Silicon Via (TSV) is a vertical interconnect technology that penetrates silicon wafers or chips, and is mainly used in 3D packaging and 3D integrated circuits.

[0019] The TSV via 2-1 exhibits excellent performance, as shown in Figure 2. The TSV via 2-1 has a diameter exceeding 30 μm and a depth exceeding 60 μm, and is filled with gold. Existing TSV via 2-1 processes suffer from complex procedures and high costs.

[0020] The TSV via for grounding in the GaN on SiC HEMT device shown in Figure 2 has the following drawbacks:

[0021] 1. The etching process is complex. Since SiC material is difficult to etch using ordinary processes, ICP (Inductively Coupled Plasma) etching is required. Therefore, a special etching barrier layer is needed, which is then removed using a liftoff process. As shown in Figure 2, ICP etching is performed after the liftoff process. The etching barrier layer on the front side of the device needs to be a difficult-to-etch gold layer.

[0022] 2. The process cost is very high. After etching, metal filling is required, which requires a gold layer of several micrometers. The gold layer is expensive. Furthermore, due to the choice of etching barrier layer on the front side of the device, gold is also chosen, which is also very expensive.

[0023] 3. The etched vias occupy a large area. Because the etching selectivity cannot be very high, the diameter of the TSV vias in the device cannot be reduced to more than 30μm, and the area occupied is larger than that of the active region.

[0024] Therefore, the structure of traditional GaN on SiC HEMT devices leads to complex grounding processes, which is a technical problem that urgently needs to be solved by those skilled in the art.

[0025] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may contain information that is not part of the prior art known to those skilled in the art. Summary of the Invention

[0026] This application provides a GaN HEMT device, and a GaN HEMT device with a novel structure.

[0027] This application provides a GaN HEMT device, comprising:

[0028] N-type low-resistivity substrate;

[0029] A grounded back metal is formed on the back side of the substrate;

[0030] An epitaxial layer of P-type SiC material is formed on the entire upper surface of the substrate, and the upper surface of the epitaxial layer is divided into a first epitaxial layer region and a second epitaxial layer region.

[0031] A first via is formed downward from the first region of the epitaxial layer, and the bottom end of the first via extends into the substrate;

[0032] An N-type connection region is formed by filling the first through-hole with N-type material, and the lower end of the N-type connection region extends into the substrate;

[0033] The GaN HEMT front structure is formed on the second region of the epitaxial layer;

[0034] The back-side ground metal, the N-type substrate, and the N-type connection region are connected and attached to the GaN HEMT device.

[0035] This application, by adopting the above technical solution, has the following technical effects:

[0036] The advantages of the GaN HEMT device in this application are:

[0037] The process is simple: the TSV via is eliminated, and the TSV process is no longer required. Instead, a first via and an N-type interconnect region filled within it, along with a low-resistivity substrate, are needed. Deep via etching is not required; only an epitaxial layer of P-type SiC material needs to be etched, requiring only a few micrometers. Therefore, the etching process for the first via is simple, with fewer steps and lower process difficulty. Attached Figure Description

[0038] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0039] Figure 1 is a schematic diagram of a GaN on SiC HEMT device in the prior art;

[0040] Figure 2 is a schematic diagram of another GaN on SiC HEMT device in the prior art;

[0041] Figure 3 is a schematic diagram of one implementation of the GaN HEMT device of this application;

[0042] Figure 4 is a schematic diagram of another implementation of the GaN HEMT device of this application;

[0043] Figure 5 is a schematic diagram of another implementation of the GaN HEMT device of this application;

[0044] Figure 6 is a schematic diagram of step S1 of the fabrication method of the GaN HEMT device of this application;

[0045] Figure 7 is a schematic diagram illustrating step S2 of the GaN HEMT device fabrication method of this application;

[0046] Figure 8 is a schematic diagram of step S3 in the fabrication method of the GaN HEMT device of this application;

[0047] Figure 9 is a schematic diagram of step S4 in the fabrication method of the GaN HEMT device of this application;

[0048] Figure 10 is a schematic diagram of step S5 in the fabrication method of the GaN HEMT device of this application;

[0049] Figure 11 is a schematic diagram of step S6 in the fabrication method of the GaN HEMT device of this application;

[0050] Figure 12 is a schematic diagram of step S7 in the fabrication method of the GaN HEMT device of this application;

[0051] Figure 13 is a schematic diagram of step S8 in the fabrication method of the GaN HEMT device of this application;

[0052] Figure 14 is a simulation diagram of a traditional GaN HEMT device with a substrate through-hole that extends from the back of the device to the front.

[0053] Figure 15 is a simulation diagram of the GaN HEMT device of this application.

[0054] Figure label:

[0055] In the background art: substrate through-hole 1-1, TSV through-hole 2-1;

[0056] In this application: substrate 10, electric field cutoff layer 11, electric field bearing layer 12, N-type connection region 20, first connection region 21, AlN layer 22, AlN layer base 220, GaN buffer layer 23, GaN buffer layer base 230, GaN layer 24, GaN layer base 240, AlGaN layer 25, AlGaN layer base 250, gate metal 26, SiN layer 27, SiN layer base 270, source 28-1, drain 28-2, metal silicide layer 29, source metal 31, back-side ground metal 32, second connection region 33. Detailed Implementation

[0057] To make the technical solutions and advantages of the embodiments of this application clearer, the exemplary embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0058] Example 1

[0059] As shown in Figures 3, 4, and 5, the GaN HEMT device of this application includes:

[0060] N-type low-resistivity substrate 10;

[0061] A grounded back-side grounding metal 32 is formed on the back side of the substrate 10;

[0062] An epitaxial layer of P-type SiC material is formed on the entire upper surface of the substrate, and the upper surface of the epitaxial layer is divided into a first epitaxial layer region and a second epitaxial layer region.

[0063] The first via is formed by etching downward from the first region of the epitaxial layer, and the bottom end of the first via extends into the substrate 10;

[0064] The N-type connection region 20 is formed by filling the first through hole with N-type material, and the lower end of the N-type connection region 20 extends into the substrate 10.

[0065] The GaN HEMT front structure is formed on the second region of the epitaxial layer;

[0066] The back-side ground metal 32, the N-type substrate 10, and the N-type connection region 20 are connected to the position where zero potential is connected to the GaN HEMT device and the position where zero potential is connected to the upper surface of the N-type connection region 20.

[0067] The GaN HEMT device of this application requires an epitaxial layer of p-type SiC material formed on a substrate 10. The upper surface of the epitaxial layer is divided into a first epitaxial region and a second epitaxial region, and the GaN HEMT front-side structure is formed on the first epitaxial region.

[0068] The first via is formed by etching downwards from the second region of the epitaxial layer, with the bottom end of the first via penetrating into the substrate 10. That is, the etching for forming the first via begins in the second region of the epitaxial layer and ends within the substrate 10. The etching for forming the first via only needs to penetrate the thickness of the SiC epitaxial layer and then slightly deeper into the substrate 10. Since the thickness of the epitaxial layer is typically only a few micrometers, the etching depth for forming the first via is very small.

[0069] The N-type connection region 20 is formed by filling the first through-hole, with its lower end extending into the substrate 10. Therefore, the interface between the N-type substrate 10 and the N-type connection region 20 naturally has no interface resistance. This achieves a low-resistance connection between the back-side ground metal 32, the N-type substrate 10, and the N-type connection region 20.

[0070] The GaN HEMT front-side structure is formed on the second region of the epitaxial layer. The distance between the back-side ground metal 32 and the upper surface of the GaN HEMT front-side structure is the full thickness of the GaN HEMT device of this application. Therefore, the etching to form the first via is performed on the SiC material, which is difficult to etch, and the etching depth is relatively small, and much smaller than the thickness of the GaN HEMT device of this application. Therefore, the etching to form the first via does not require a TSV via process, but only a semi-via etching process is needed, which simplifies the etching process and reduces the difficulty of implementation.

[0071] The first through hole has a smaller depth, and correspondingly, the diameter of the first through hole is also smaller, which in turn makes the area occupied by the first through hole smaller.

[0072] The back-side grounded metal 32 is grounded, and its conductive charge carriers are electrons. The substrate is an N-type low-resistivity substrate 10, meaning that the majority charge carriers of substrate 10 are electrons, and substrate 10 has a relatively large number of electrons. Since both the back-side grounded metal 32 and the N-type low-resistivity substrate 10 have a relatively large number of electrons as conductive charge carriers, the connection between the N-type low-resistivity substrate 10 and the back-side grounded metal 32 has a good electrical connection and low resistance.

[0073] Both the N-type substrate 10 and the N-type connection region 20 are N-type, and the majority carriers are electrons. Thus, by controlling the doping concentration of the N-type substrate 10 and the N-type connection region 20, it is possible to achieve a better electrical connection and lower resistance at the connection point of the N-type substrate 10 and the N-type connection region 20.

[0074] This allows for a good electrical connection between the back-side ground metal 32, the N-type substrate 10, and the N-type connection region 20, resulting in low resistance. Since the back-side ground metal 32 is grounded, the connection between the back-side ground metal 32, the N-type substrate 10, and the N-type connection region 20 connects the zero potential of the grounded back-side ground metal 32 to the upper surface of the N-type connection region 20 (corresponding to the height of the upper surface of the second region of the epitaxial layer). In other words, the zero potential is connected to the interior of the GaN HEMT device of this application and is located in the middle of the thickness direction, providing the conditions for front-side grounding of the GaN HEMT device of this application. Thus, the structure of the GaN HEMT device of this application eliminates the need for front-side grounding to penetrate the entire thickness of the device, and consequently, eliminates the need for TSV via technology.

[0075] The advantages of the GaN HEMT device in this application are:

[0076] (1) Simple process: The TSV via is eliminated, and the TSV process is no longer required. Instead, a first via and an N-type connection region 20 filled in the first via and a low-resistivity substrate are required. Deep holes are not required; only the epitaxial layer of P-type SiC material needs to be etched, which only requires a few micrometers. Therefore, the etching process of the first via is simple, and the process steps are simple and the process difficulty is low.

[0077] (2) Small area of ​​the first through hole: By using a first through hole and an N-type connection area 20 filled in the first through hole, the area occupied by the first through hole is small, and the device area utilization rate is high. Since the depth of the first through hole is only a few micrometers, the diameter of the first through hole only needs to be 1-5μm.

[0078] (3) Low material cost: Since the GaN HEMT device of this application does not require the use of TSV process, it does not require the use of gold as the metal material and TSV filler material, which greatly reduces the material cost. Furthermore, since the GaN HEMT device of this application uses low-resistivity substrates on a large scale, the cost is lower than that of high-resistivity substrates.

[0079] This application uses a low-resistivity substrate 10 and a p-type SiC epitaxial layer to replace the high-resistivity substrate in the prior art. The reason for using the SiC epitaxial layer is that SiC has a high lattice matching degree with GaN, resulting in fewer defects in the grown GaN. In addition, SiC has high thermal conductivity, which can better dissipate heat.

[0080] In this way, the combination of low-resistivity substrate 10 and epitaxial layer of P-type SiC material can also meet the requirements of improving the electrical performance, reliability and stability of the device.

[0081] Using only a low-resistivity substrate can lead to leakage, but a P-type epitaxial layer can prevent electron leakage.

[0082] As a first optional approach, the N-type connection region 20 is an N-type connection region 20 made of Si material, and the substrate 10 is a substrate made of Si material. That is, both the substrate 10 and the N-type connection region 20 are made of Si material.

[0083] As a second alternative, the N-type connection region 20 is an N-type connection region 20 of SiC material, and the substrate 10 is a substrate of SiC material. That is, both the substrate 10 and the N-type connection region 20 are made of SiC material.

[0084] The SiC substrate has a high degree of compatibility with the GaN in GaN HEMT devices. Therefore, the second option is superior. The N-type connection region 20 of the SiC material can be either monocrystalline or polycrystalline. However, polycrystalline SiC material has lower growth requirements and can achieve higher conductivity, making it superior. A monocrystalline SiC substrate is used.

[0085] In practice, the depth at which the lower end of the N-type connection region 20 penetrates into the substrate 10 is greater than or equal to 0.1 μm. This ensures a good connection between the N-type connection region 20 and the substrate 10.

[0086] In practice, the thickness of the substrate 10 is in the range of 5 μm less than or equal to 300 μm;

[0087] The resistivity of the substrate 10 is greater than or equal to 0.1 mol / cm and less than or equal to 1000 ohm / cm.

[0088] The logic behind choosing the substrate resistivity is that the device needs to conduct electricity to the back side through the substrate. With current technology, the back substrate thickness is approximately 100 μm. To achieve lower resistance to ground, for a 10 mm² device, based on a resistivity of 100 ohms*cm, the resistance to ground is 10 ohms. Values ​​greater than this will result in poor device performance. The substrate thickness and resistivity together determine the parasitic resistance.

[0089] In practice, as shown in Figures 3, 4, and 5, the GaN HEMT device of this application also includes:

[0090] A metal silicide layer 29 is formed on the N-type connection region 20;

[0091] A first contact hole 30 is formed on the metal silicide layer 29; the upper end of the first contact hole 30 is connected to the source metal 31 of the GaN HEMT front structure.

[0092] The GaN HEMT front structure includes a source metal 31, a first contact hole 30, a metal silicide layer 29, an N-type connection region 20, an N-type substrate 10, and a grounded back-side ground metal 32.

[0093] In this way, the source metal 31 of the GaN HEMT front structure is grounded from the front of the GaN HEMT device of this application through the first contact hole 30, the metal silicide layer 29, the N-type connection region 20, the N-type substrate 10, and the grounded back ground metal 32. That is, the source of the GaN HEMT device of this application is grounded through the front ground structure.

[0094] The first contact hole 30 is formed using a contact hole process, and the first contact hole 30 is made of tungsten metal. Therefore, the fabrication process of the first contact hole 30 is simple and has low cost.

[0095] Thus, the front-side grounding structure of the GaN HEMT device in this application includes:

[0096] The source metal 31, the first contact hole 30, the metal silicide layer 29, the N-type connection region 20 (filled in the first through hole), the N-type substrate 10, the grounded back-side ground metal 32, and the first connection region 21.

[0097] The adopted two-end structure consists of one section consisting of the metal silicide layer 29 and the structure below it (N-type connection region 20 (filled in the first via), N-type substrate 10, grounded back-side ground metal 32, and first connection region 21), and another section consisting of the structure above the metal silicide layer 29 (source metal 31 and the first contact hole 30). Both the first contact hole 30 and the first via are relatively short, much shorter than the overall thickness of the GaN HEMT device of this application. Moreover, the first contact hole 30 uses a contact hole process, and the first via uses a semi-through-hole process. That is, the fabrication process of the front-side ground structure of the GaN HEMT device of this application does not require the TSV process, and the shortcomings of the TSV process are also absent in this application.

[0098] In practice, as shown in Figures 3, 4, and 5, the GaN HEMT device of this application also includes:

[0099] A P-type connection region is formed downward from the first region of the epitaxial layer within the epitaxial layer, and the P-type connection region is connected to the outer peripheral surface of the N-type connection region 20; and the metal silicide layer 29 is formed on the N-type connection region 20 and the P-type connection region;

[0100] The metal silicide layer 29 connects the N-type connection region 20 and the P-type connection region, respectively.

[0101] This achieves the connection of the back ground metal 32, the N-type substrate 10, the N-type connection region 20, and the metal silicide layer 29; as well as the connection of the P-type epitaxial layer, the P-type connection region, and the metal silicide layer 29.

[0102] The zero potential of the grounded back-side grounding metal 32 is connected to the metal silicide layer 29 via the back-side grounding metal 32, the N-type substrate 10, the N-type connection region 20, and the metal silicide layer 29. The P-type epitaxial layer is connected to the zero potential via the metal silicide layer 29, the P-type connection region, and the P-type epitaxial layer.

[0103] Regarding the structure of the epitaxial layer:

[0104] As a first alternative, the epitaxial layer includes:

[0105] A P-type electric field blocking layer 11 is formed on the substrate 10.

[0106] As a second alternative approach, in implementation, as shown in Figures 3, 4, and 5, the epitaxial layer includes:

[0107] A P-type electric field blocking layer 11 is formed on the substrate 10;

[0108] A P-type electric field bearing layer 12 is formed on the electric field blocking layer 11.

[0109] Simultaneously setting both a P-type electric field blocking layer 11 and a P-type electric field bearing layer 12 is a preferred implementation. In this way, the parameters of the lower-doped P-type electric field bearing layer 12 are used to meet the voltage withstand requirements of the GaN HEMT device, while the parameters of the higher-doped P-type electric field blocking layer 11 are used to meet the electric field blocking requirements of the GaN HEMT device. Therefore, the GaN HEMT device of this application can meet the voltage withstand requirements, while also ensuring that the electric field is blocked within the electric field blocking layer 11, and the overall thickness of the GaN HEMT device remains relatively small.

[0110] In practice, as shown in Figures 3, 4, and 5, the GaN HEMT device also includes:

[0111] The first connection region 21 of type P is formed downward from the upper surface of the epitaxial layer and connected to the outer peripheral surface of the N-type connection region 20. The first connection region 21 occupies a portion of the epitaxial layer in the lateral direction.

[0112] The metal silicide layer 29 is also formed on the first connection region 21, and the metal silicide layer 29 connects the first connection region 21 and the N-type connection region 20 respectively.

[0113] The epitaxial layer of P-type SiC material, the first P-type connection region 21, and the metal silicide layer 29 are connected and electrically well. Since the zero potential has been connected to the metal silicide layer 29, the epitaxial layer is thus connected to zero potential.

[0114] In implementation, as shown in Figures 3, 4, and 5, the P-type connection area includes a P-type first connection area 21, wherein the first connection area 21:

[0115] In the vertical direction, the first connection area 21 is formed downward from the upper surface of the electric field bearing layer 12, and the lower surface of the first connection area 21 is higher than the lower surface of the electric field bearing layer 12.

[0116] In the lateral direction, the first connection area 21 is connected to the outer peripheral surface of the N-type connection area 20, occupying a portion of the electric field bearing layer 12;

[0117] The doping concentration of the first connection region 21 is greater than the doping concentration of the electric field bearing layer 12;

[0118] The metal silicide layer 29 is also formed on the first connection region 21, and the metal silicide layer 29 connects the first connection region 21 and the N-type connection region 20 respectively.

[0119] The doping concentration of the first connection region 21 of the P-type is greater than the doping concentration of the electric field bearing layer 12 of the P-type. Thus, the electric field bearing layer 12 of the P-type and the first connection region 21 of the P-type are electrically connected to the metal silicide layer 29 with zero potential, thereby realizing that the electric field bearing layer 12 of the P-type is connected to zero potential.

[0120] The metal silicide layer 29 connects the first connection region 21 and the N-type connection region 20, respectively. The back-side grounding metal 32, the N-type substrate 10, the N-type N-type connection region 20, and the metal silicide layer 29 are connected to the metal silicide layer 29, thus connecting the grounded back-side grounding metal 32 to zero potential. The P-type electric field bearing layer 12, the P-type first connection region 21, and the metal silicide layer 29, which is connected to zero potential, are electrically connected, thereby connecting the P-type electric field bearing layer 12 to zero potential.

[0121] The first region of the epitaxial layer corresponds to the first region of the electric field bearing layer, and the second region of the epitaxial layer corresponds to the second region of the electric field bearing layer.

[0122] As an alternative approach, as shown in Figure 4, the first connection region 21 is located below the first region of the electric field bearing layer and partially below the second region of the electric field bearing layer. That is, the first connection region 21 extends laterally beneath the GaN HEMT front structure.

[0123] Since the doping concentration of the first connection region 21 is greater than that of the electric field bearing layer 12, the electric field generated by the GaN HEMT front structure is rapidly reduced at the location of the first connection region 21, which plays a role in balancing the electric field.

[0124] As an alternative approach, as shown in Figure 5, the P-type connection region further includes a P-type second connection region 33:

[0125] In the vertical direction, the second connection region 33 is connected below the first connection region 21, and the bottom end of the N-type connection region 20 enters into the electric field cutoff layer 11 or the bottom end of the N-type connection region 20 is connected to the upper surface of the substrate 10.

[0126] In the lateral direction, the second connection area 33 is formed on the outer peripheral surface of the N-type connection area 20;

[0127] The doping concentration of the second connection region 33 is greater than the doping concentration of the electric field cutoff layer 11.

[0128] Because the doping concentration of the second connection region 33 is greater than that of the electric field cutoff layer 11 and the doping concentration of the first connection region 21 is greater than that of the electric field bearing layer 12, the connection of the electric field cutoff layer 11, the second connection region 33, the first connection region 21 and the metal silicide layer 29 of the P-type is better, and the connection of the electric field bearing layer 12, the second connection region 33, the first connection region 21 and the metal silicide layer 29 of the N-type is also better.

[0129] The epitaxial layer of the P-type SiC material, the P-type second connection region 33, and the metal silicide layer 29 are connected and electrically connected, which is also to better connect the epitaxial layer to zero potential.

[0130] The reason why the first connection region 21 and the second connection region 33 are formed using two separate processes is that, due to limitations in the implantation process, the depth of the first connection region 21 cannot be reached too deeply, and the first connection region 21 cannot directly enter the electric field cutoff layer 11. Therefore, the second connection region 33 is formed by ion implantation on the sidewall of the via in a single step.

[0131] The higher the doping concentration of the first connection region 21 and the second connection region 33, the better. In actual fabrication, the doping concentration of the first connection region 21 and the second connection region 33 is limited by the ion implantation process.

[0132] In practice, the doping concentration of the first connection region 21 ranges from greater than or equal to 1 × 10⁻⁶. 17 cm -3 Less than or equal to 1×10 22 cm -3Furthermore, the doping concentration of the first connection region 21 is at least two orders of magnitude higher than the doping concentration of the electric field bearing layer 12;

[0133] The doping concentration of the second connection region 33 ranges from 1×10⁻⁶. 17 cm -3 Less than or equal to 1×10 22 cm -3 Furthermore, the doping concentration of the second connection region 33 is at least two orders of magnitude higher than the doping concentration of the electric field cutoff layer 11.

[0134] Specifically, as shown in Figures 3, 4, and 5, the front-side structure of a GaN HEMT includes:

[0135] AlN layer 22 is formed on the second region of the electric field bearing layer;

[0136] GaN buffer layer 23 is formed on top of AlN layer 22;

[0137] GaN layer 24 is formed on top of GaN buffer layer 23;

[0138] AlGaN layer 25 is formed on top of GaN layer 24;

[0139] SiN layer 27 is formed on top of AlGaN layer 25.

[0140] Gate metal 26 is formed on SiN layer 27 and is connected to AlGaN layer 25 through contact hole through SiN layer 27.

[0141] The source electrode 28-1 and the drain electrode 28-2 each penetrate through the SiN layer 27 and the AlGaN layer 25 into the GaN layer 24, and are respectively connected to the two ends of the GaN layer 24;

[0142] Source metal 31 is connected to source metal 28-1.

[0143] AlN stands for aluminum nitride; GaN for gallium nitride; AlGaN for aluminum gallium nitride; and SiN for silicon nitride.

[0144] AlGaN / GaN form a heterojunction, and the two-dimensional electron gas (2DEG) generated by the heterojunction is the basis for the operation of all GaN HEMT devices. AlGaN layer 25 and GaN layer 24 form a heterojunction, and the two-dimensional electron gas 2DEG generated by the heterojunction is controlled to be turned on and off by gate metal 26.

[0145] Figure 14 is a simulation diagram of a conventional GaN HEMT device with a substrate through-hole that extends from the back side of the device to the front side. Figure 15 is a simulation diagram of the GaN HEMT device of this application.

[0146] The performance comparison between the conventional GaN HEMT device in Figure 14 and the GaN HEMT device of this application in Figure 15 is shown in the table below:

[0147] As can be seen from the table, under similar performance conditions, the GaN HEMT device of this application has a higher breakdown voltage (BV).

[0148] The fabrication process of the GaN HEMT device in this application includes the following steps:

[0149] Step S1: As shown in Figure 6, a back-ground metal 32 is formed on the back side of an N-type low-resistivity substrate 10, and a P-type SiC material epitaxial layer is formed from the upper surface of the substrate 10. The epitaxial layer consists of a P-type electric field cutoff layer 11 and an electric field bearing layer 12 from bottom to top.

[0150] Step S2: As shown in Figure 7, a P-type first connection region base is formed by implantation. A first through-hole is formed by etching from the upper surface of the first connection region base downwards. An N-type polycrystalline SiC is filled in the first through-hole to form an N-type N-type connection region 20. At this time, the first connection region 21 is formed.

[0151] Step S3: As shown in Figure 8, AlN layer foundation 220, GaN buffer layer foundation 230, GaN layer foundation 240, AlGaN layer foundation 250 and SiN layer foundation 270 are formed sequentially from bottom to top above the electric field bearing layer 12, N-type connection region 20 and first connection region 21.

[0152] Step S4: As shown in Figure 9, the first interconnect region 21 and the N-type interconnect region 20 are exposed by etching downwards from the upper surface of the SiN layer base 270.

[0153] Step S5: As shown in Figure 10, a metal silicide layer 29 is formed on the first connection region 21 and the N-type connection region 20;

[0154] Step S6: As shown in Figure 11, a gate metal 26 is formed on the SiN layer base 270;

[0155] Step S7: As shown in Figure 12, a first contact hole 30 is formed on the metal silicide layer 29 to form a source electrode 28-1 and a drain electrode 28-2; thus, an AlN layer 22, a GaN buffer layer 23, a GaN layer 24, an AlGaN layer 25, and a SiN layer 27 are formed.

[0156] Step S8: As shown in Figure 13, source metal 31 and drain metal are formed.

[0157] In the description of this application, it should be understood that the terms "front", "rear", "head", "tail", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0158] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0159] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," etc., should be interpreted broadly; taking connection as an example, it can be a direct connection or an indirect connection through an intermediate medium, and can be the internal connection of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0160] Although some optional embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make further changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including some optional embodiments as well as all changes and modifications falling within the scope of this application.

[0161] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A GaN HEMT device, characterized by, include: N-type low-resistivity substrate (10); A grounded back-side grounding metal (32) is formed on the back side of the substrate (10); An epitaxial layer of P-type SiC material is formed on the substrate, and the upper surface of the epitaxial layer is divided into a first region of the epitaxial layer and a second region of the epitaxial layer. A first through-hole is formed downward from the first region of the epitaxial layer, and the bottom end of the first through-hole enters into the substrate (10); The N-type connection region (20) is formed by filling the first through hole with N-type material, and the lower end of the N-type connection region (20) extends into the substrate (10); The GaN HEMT front structure is formed on the second region of the epitaxial layer; The back-side ground metal (32), the N-type substrate (10), and the N-type connection region (20) are connected and attached to the GaN HEMT device.

2. The GaN HEMT device according to claim 1, characterized in that, Also includes: A metal silicide layer (29) is formed on the N-type connection region (20); A first contact hole (30) is formed on the metal silicide layer (29); the upper end of the first contact hole (30) is connected to the source metal (31) of the GaN HEMT front structure; The source metal (31), the first contact hole (30), and the metal silicide layer (29) of the GaN HEMT front structure are connected.

3. The GaN HEMT device according to claim 2, characterized in that, Also includes: A P-type connection region is formed downward from the first region of the epitaxial layer within the epitaxial layer, and the P-type connection region is connected to the outer peripheral surface of the N-type connection region (20); and the metal silicide layer (29) is also connected and formed on the P-type connection region. The metal silicide layer (29) is connected to the N-type connection region (20) and the P-type connection region, respectively.

4. The GaN HEMT device according to claim 3, characterized in that, The epitaxial layer includes: A P-type electric field blocking layer (11) is formed on the substrate (10).

5. The GaN HEMT device of claim 4, wherein, The epitaxial layer further includes: A P-type electric field bearing layer (12) is formed on the electric field blocking layer (11).

6. The GaN HEMT device of claim 5, wherein, The P-type connection region includes a first P-type connection region (21); the first connection region (21): In the vertical direction, the first connection area (21) is formed downward from the upper surface of the electric field bearing layer (12), and the lower surface of the first connection area (21) is higher than the lower surface of the electric field bearing layer (12). In the lateral direction, the first connection area (21) is connected to the outer peripheral surface of the N-type connection area (20) and occupies a portion of the electric field bearing layer (12); The doping concentration of the first connection region (21) is greater than the doping concentration of the electric field bearing layer (12); The metal silicide layer (29) is also formed on the first connection region (21).

7. The GaN HEMT device of claim 6, wherein, The first region of the epitaxial layer corresponds to the first region of the electric field bearing layer, and the second region of the epitaxial layer corresponds to the second region of the electric field bearing layer; The first connection area (21) is located below the first region of the electric field bearing layer and partially below the second region of the electric field bearing layer.

8. The GaN HEMT device of claim 6, wherein, The P-type connection region further includes a P-type second connection region (33): In the vertical direction, the second connection area (33) is connected below the first connection area (21), and the bottom end of the N-type connection area (20) enters into the electric field cutoff layer (11) or the bottom end of the N-type connection area (20) is connected to the upper surface of the substrate (10); In the lateral direction, the second connection area (33) is formed on the outer peripheral surface of the N-type connection area (20); The doping concentration of the second connection region (33) is greater than the doping concentration of the electric field cutoff layer (11).

9. The GaN HEMT device of claim 1, wherein, The N-type connection region (20) is an N-type connection region (20) of Si material, and the substrate (10) is a substrate of Si material; Alternatively, the N-type connection region (20) is an N-type connection region (20) of SiC material, and the substrate (10) is a substrate of SiC material.

10. The GaN HEMT device of any of claims 1 to 9, wherein, The resistivity of the substrate (10) is greater than or equal to 0.1 mol / cm and less than or equal to 1000 ohm / cm. The thickness of the substrate (10) is greater than or equal to 5 μm and less than or equal to 300 μm.

11. The GaN HEMT device according to claim 8, wherein the doping concentration of the first connection region (21) is greater than or equal to 1 × 10⁻⁶. 17 cm -3 Less than or equal to 1×10 22 cm -3 Furthermore, the doping concentration of the first connection region (21) is at least two orders of magnitude higher than that of the electric field bearing layer (12); The doping concentration of the second connection region (33) is greater than or equal to 1 × 10⁻⁶. 17 cm -3 Less than or equal to 1×10 22 cm -3 Furthermore, the doping concentration of the second connection region (33) is at least two orders of magnitude higher than that of the electric field cutoff layer (11).

12. The GaN HEMT device according to any one of claims 1 to 9, characterized in that, The depth at which the lower end of the N-type connection region (20) enters the substrate (10) is greater than or equal to 0.1 μm.

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